Overlay alignment mark and overlay offset measuring method

Abstract

According to the overlay alignment mark and the overlay offset measuring method provided by the invention, the offset of the central point of the first overlay pattern and the offset of the central point of the second overlay pattern in the X direction and the Y direction are measured, so that the overlay error value of the current layer of the wafer relative to the front layer of the wafer can be obtained; according to the overlay error value, whether the current layer of the wafer deviates relative to the front layer of the wafer is judged, in addition, an overlay alignment mark of a novel structure is provided, and the overlay alignment mark of the novel structure forms an overlay pattern arranged in a regular triangle shape. The overlay alignment mark is small in size and does not occupy a large chip space, so that the overlay alignment mark not only can be placed in a scribing groove to measure the Overlay error value between exposure areas, but also can be placed in a passive area on a wafer substrate to measure the Overlay error value of the exposure areas; therefore, the alignment precision in the semiconductor manufacturing process can be improved, and wider manufacturing process requirements can be met.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a method for measuring an overlay alignment mark and an overlay offset. Background Art

[0002] In the existing semiconductor processing technology, the process from silicon wafer to wafer needs to go through multiple photolithography masks. In order to ensure the final wafer yield, each layer of mask patterns must be accurately aligned, that is, overlay alignment. In order to stack and align during the photolithography process, a series of marks are usually set in the photolithography process. These marks are also called overlay accuracy detection patterns, so that the alignment between the layers of the wafer can be achieved by optically aligning the overlay accuracy detection patterns.

[0003] In the prior art, the structures of overlay accuracy detection patterns are generally advanced image measurement (AIM), bar in bar, and box in BOx. The above types of patterns all use a combination of square positioning patterns, detect the offset through the offset in the X / Y two-dimensional direction, and calculate the Overlay error value. However, it is found during use that the design sizes of the above types of patterns are generally 10 to 40 μm. The larger size design makes it usually placed in the cross-cutting groove, thus occupying a larger chip space, and can only be used to measure the Overlay error value between exposure areas, and cannot achieve the measurement of the Overlay error value inside the exposure area. In addition, the above types of patterns have low recognition, and there is a certain possibility of error in actual production.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0005] In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a method for measuring overlay alignment marks and overlay offsets, so as to solve the problems in the prior art that the overlay alignment marks are large in size, occupy a large chip space, have low recognition and may cause errors, and cannot measure the Overlay error value within the exposure area.

[0006] To achieve the above object, the present invention provides an overlay alignment mark, the overlay alignment mark comprising:

[0007] A front layer marking area is arranged on the front layer of the wafer substrate, and a first mark, a second mark and a third mark are arranged on the front layer marking area, wherein the center points of the first mark, the second mark and the third mark are connected to form a first set engraved pattern in a triangular shape;

[0008] A current layer marking area is arranged on the current layer of the wafer substrate, and a fourth mark, a fifth mark and a sixth mark are arranged on the current layer marking area, wherein the center points of the fourth mark, the fifth mark and the sixth mark are connected to form a second set of engraved patterns in a triangular shape;

[0009] By measuring the offsets of the center points of the first overlay pattern and the second overlay pattern in the X direction and the Y direction, an overlay error value of the current layer of the wafer substrate relative to the front layer of the wafer substrate is obtained.

[0010] Optionally, the first engraved pattern and the second engraved pattern are both arranged in the shape of an equilateral triangle.

[0011] Optionally, the first mark, the second mark, the third mark, the fourth mark, the fifth mark and the sixth mark are arranged in a square shape, and a side length of the square is 1 to 20 μm.

[0012] Optionally, the first mark, the second mark and the third mark have equal side lengths, and the fourth mark, the fifth mark and the sixth mark have equal side lengths.

[0013] Optionally, the second overlay pattern is proportionally reduced relative to the first overlay pattern, and when the overlay error value between the front layer mark area and the current layer mark area is equal to 0, the center of the first overlay pattern and the center of the second overlay pattern coincide with each other.

[0014] Optionally, the overlay alignment mark is disposed in a scribe line on the wafer substrate or in a passive area on the wafer substrate.

[0015] The present invention also provides a method for measuring overlay offset, which is performed using the overlay alignment mark mentioned above and includes the following steps:

[0016] Taking the center point of the first set of engraved patterns as the origin, a rectangular coordinate system is established, and a measuring instrument is used to measure the distance W1 between the center of the third mark and the center of the sixth mark in the X direction, and the distance W2 between the center of the first mark and the center of the fourth mark in the X direction;

[0017] Using a measuring instrument, measure a distance W3 between the center of the third mark and the center of the sixth mark in the Y direction, and measure a distance W4 between the center of the second mark and the center of the fifth mark in the Y direction;

[0018] The offsets between the center of the first overlay pattern and the center of the second overlay pattern in the X direction and the Y direction are calculated to obtain the overlay error value of the current layer of the wafer substrate relative to the previous layer of the wafer substrate, where: OVLX = (W1-W2) / 2, OVLY = (W3-W4) / 2.

[0019] Optionally, the measurement method may be applied to processes of 28 nm and below.

[0020] As described above, the method for measuring the overlay alignment mark and the overlay offset of the present invention has the following beneficial effects compared with the prior art:

[0021] The overlay alignment mark proposed in the present invention is small in size and does not need to occupy a large chip space. In addition, it can not only be placed in the scribe groove to realize the measurement of the overlay error value between the exposure areas, but also can be placed in the passive area on the wafer substrate to realize the measurement of the overlay error value of the exposure area, thereby meeting a wider range of process requirements. Furthermore, by adopting an overlay pattern arranged in an equilateral triangle, the alignment accuracy in the semiconductor manufacturing process is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram showing the structure of the overlay alignment mark in the present invention.

[0023] Figure 2 Shown is a schematic diagram showing the distribution of the overlay alignment marks on the wafer in the present invention.

[0024] Component number description

[0025] 10. First set of engraved patterns; 101. First mark; 102. Second mark; 103. Third mark; 11. Second set of engraved patterns; 111. Fourth mark; 112. Fifth mark; 113. Sixth mark; 12. Slice groove; 13. Inactive area. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0028] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0029] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0030] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0031] Embodiment 1:

[0032] An embodiment of the present invention provides an overlay alignment mark for solving the overlay alignment problem in a photolithography process.

[0033] The overlay alignment mark provided by the present invention is as follows Figure 1 As shown, the specific structure includes:

[0034] A front layer marking area is arranged on the front layer of the wafer substrate, and a first mark 101, a second mark 102 and a third mark 103 are arranged on the front layer marking area, wherein the center points of the first mark 101, the second mark 102 and the third mark 103 are connected to form a first overlay pattern 10 in a triangular shape;

[0035] The current layer marking area is arranged on the current layer of the wafer substrate, and a fourth mark 111, a fifth mark 112 and a sixth mark 113 are arranged on the current layer marking area, wherein the center points of the fourth mark 111, the fifth mark 112 and the sixth mark 113 are connected to each other to form a second set of engraved figures 11 in a triangular shape.

[0036] As an example, the first engraved pattern 10 and the second engraved pattern 11 are both arranged in the form of an equilateral triangle.

[0037] Specifically, Figure 1 As shown, a first mark 101, a second mark 102 and a third mark 103 are arranged on the front layer marking area, wherein the first engraved pattern 10 in which the center points of the first mark 101, the second mark 102 and the third mark 103 are connected to each other can be in a triangular shape, and preferably, the first engraved pattern 10 is an equilateral triangle.

[0038] A fourth mark 111, a fifth mark 112 and a sixth mark 113 are arranged on the current layer marking area, wherein the first set of engraved patterns 10 in which the center points of the fourth mark 111, the fifth mark 112 and the sixth mark 113 are connected to each other can be in a triangular shape, and preferably, the second set of engraved patterns 11 is in a regular triangle shape.

[0039] During the overlay alignment, the first overlay pattern 10 and the second overlay pattern 11 have a default alignment position, for example, the center points can be aligned; a rectangular coordinate system is established with the center point of the first overlay pattern as the origin, and then the offsets of the center points of the first overlay pattern 10 and the second overlay pattern 11 in the X and Y directions are measured, so that the overlay error value of the current layer of the wafer relative to the front layer of the wafer can be obtained, and the overlay error value is used to determine whether the current layer of the wafer is offset relative to the front layer of the wafer. It should be noted that the center mentioned here, for an equilateral triangle, refers to the center of the triangle (the center of gravity, circumcenter, incenter and orthocenter of an equilateral triangle are combined into one); for a non-equilateral triangle, it refers to one of the center of gravity, circumcenter, incenter or orthocenter, and it is only necessary to ensure that the selection of the first overlay pattern 10 and the second overlay pattern 11 is consistent, for example: when the incenter of the first overlay pattern 10 is selected, the incenter of the second overlay pattern 11 should also be selected to calculate the offset of the center point in the X and Y directions.

[0040] When the overlay error value of the current layer of the wafer relative to the front layer of the wafer is equal to 0, that is, the center point of the first overlay pattern 10 and the center point of the second overlay pattern 11 continue to remain aligned, it means that the current layer of the wafer has not shifted relative to the front layer of the wafer.

[0041] As an example, the first mark 101 , the second mark 102 , the third mark 103 , the fourth mark 111 , the fifth mark 112 , and the sixth mark 113 are arranged in a square shape, and the side length of the square is 1 to 20 μm.

[0042] Specifically, Figure 1 and Figure 2As shown, in order to reduce the mark width, the first mark 101, the second mark 102, the third mark 103, the fourth mark 111, the fifth mark 112 and the sixth mark 113 are all arranged in a square shape, and the side length of the square is 1 to 20 μm, for example: 1 μm, 5 μm, 10 μm, 15 μm or 20 μm. When the side length of the square is small, the above marks can be placed not only in the scribe groove 12, but also in the passive area 13 on the wafer substrate, thereby realizing the measurement of the Overlay error value of the exposure area.

[0043] In order to improve the alignment accuracy, the first mark 101, the second mark 102 and the third mark 103 on the front layer marking area have equal side lengths so that the center points of the first mark 101, the second mark 102 and the third mark 103 can be unified, and the fourth mark 111, the fifth mark 112 and the sixth mark 113 on the layer marking area have equal side lengths so that the center points of the fourth mark 111, the fifth mark 112 and the sixth mark 113 can be unified.

[0044] Preferably, the area of ​​the second overlay pattern 11 is proportionally smaller than the area of ​​the first overlay pattern 10. And the three sides of the first overlay pattern 10 are respectively parallel to the three sides of the second overlay pattern 11. Through the above structure, the center position deviation of the first overlay pattern 10 and the second overlay pattern 11 during the photolithography process can reflect the position deviation between the layers of the wafer during the photolithography process.

[0045] Embodiment 2:

[0046] This embodiment further provides a method for measuring overlay offset. Specifically, the overlay offset is measured using the overlay alignment mark described in Embodiment 1. The measurement method includes the following steps:

[0047] A rectangular coordinate system is established with the center point of the first set of engraved patterns as the origin, and a measuring instrument is used to measure the distance W1 between the center of the third mark 103 and the center of the sixth mark 113 in the X direction, and the distance W2 between the center of the first mark 101 and the center of the fourth mark 111 in the X direction;

[0048] Use a measuring instrument to measure a distance W3 between the center of the third mark 103 and the center of the sixth mark 113 in the Y direction, and a distance W4 between the center of the second mark 102 and the center of the fifth mark 112 in the Y direction;

[0049] By calculating the offset OVLX in the X direction and the offset OVLY in the Y direction between the center point of the first overlay pattern 10 and the center point of the second overlay pattern 11, the overlay error value of the current layer of the wafer substrate relative to the front layer of the wafer substrate is obtained, where: OVLX = (W1-W2) / 2, OVLY = (W3-W4) / 2.

[0050] During overlay alignment, the first overlay pattern 10 and the second overlay pattern 11 have a default alignment position, for example, the center points may be aligned; a rectangular coordinate system is established with the center point of the first overlay pattern as the origin, and then the offsets of the center points of the first overlay pattern 10 and the second overlay pattern 11 in the X and Y directions are measured, thereby obtaining the overlay error value of the current layer of the wafer relative to the front layer of the wafer, and using the overlay error value to determine whether the current layer of the wafer is offset relative to the front layer of the wafer.

[0051] Specifically, the area of ​​the second overlay pattern 11 is smaller than that of the first overlay pattern 10. When calculating the overlay error, the measuring instrument is first used to measure the distance W1 between the center of the third mark 103 and the center of the sixth mark 113 in the X direction, and then the distance W2 between the center of the first mark 101 and the center of the fourth mark 111 in the X direction is measured. The offset OVLX in the X direction between the center point of the first overlay pattern 10 and the center point of the second overlay pattern 11 is calculated by the formula OVLX=(W1-W2) / 2; then the measuring instrument is used to measure the distance W2 between the center of the third mark 103 and the center of the fourth mark 111 in the X direction. The distance W3 of the center of the mark 113 in the Y direction, and the distance W4 between the center of the second mark 102 and the center of the fifth mark 112 in the Y direction are measured again, and the offset OVLY in the Y direction between the center point of the first overlay pattern 10 and the center point of the second overlay pattern 11 is calculated by the formula OVLY=(W3-W4) / 2; when OVLX=0 and OVLY=0 calculated by the above formula, it means that the center point of the first overlay pattern 10 and the center point of the second overlay pattern 11 continue to be aligned, that is, the current layer of the wafer has not shifted relative to the front layer of the wafer.

[0052] In addition, the overlay offset measurement method mentioned in this embodiment can be applied to processes of 28 nm and below because the size of the overlay alignment mark used is relatively small.

[0053] In summary, the overlay alignment mark and the overlay offset measurement method of the present invention proposes an overlay alignment mark of a new structure, which forms an overlay pattern arranged in an equilateral triangle. Since the size of the overlay alignment mark is small, it does not need to occupy a large chip space, so that it can not only be placed in the scribe groove to measure the overlay error value between the exposure areas, but also can be placed in the passive area on the wafer substrate to measure the overlay error value of the exposure area, thereby improving the alignment accuracy in the semiconductor manufacturing process and meeting a wider range of process requirements. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An overlay alignment mark, characterized in that: The overlay alignment mark comprises: A front layer marking area is arranged on the front layer of the wafer substrate, and a first mark, a second mark and a third mark are arranged on the front layer marking area, wherein the center points of the first mark, the second mark and the third mark are connected to form a first set engraved pattern in a triangular shape; A current layer marking area is arranged on the current layer of the wafer substrate, and a fourth mark, a fifth mark and a sixth mark are arranged on the current layer marking area, wherein the center points of the fourth mark, the fifth mark and the sixth mark are connected to form a second set of engraved patterns in a triangular shape; By measuring the offsets of the center points of the first overlay pattern and the second overlay pattern in the X direction and the Y direction, an overlay error value of the current layer of the wafer substrate relative to the front layer of the wafer substrate is obtained.

2. The overlay alignment mark according to claim 1, characterized in that: The first engraved pattern and the second engraved pattern are both arranged in the form of an equilateral triangle.

3. The overlay alignment mark according to claim 1, characterized in that: The first mark, the second mark, the third mark, the fourth mark, the fifth mark and the sixth mark are arranged in a square shape, and the side length of the square is 1 to 20 μm.

4. The overlay alignment mark according to claim 3, characterized in that: The first mark, the second mark and the third mark have the same side length, and the fourth mark, the fifth mark and the sixth mark have the same side length.

5. The overlay alignment mark according to claim 1, characterized in that: The second overlay pattern is proportionally reduced relative to the first overlay pattern, and when the overlay error value between the front layer mark area and the current layer mark area is equal to 0, the center of the first overlay pattern coincides with the center of the second overlay pattern.

6. The overlay alignment mark according to claim 1, characterized in that: The overlay alignment mark is arranged on a dicing street on the wafer substrate or in an inactive area on the wafer substrate.

7. A method for measuring overlay offset, characterized in that: Using the overlay alignment mark as claimed in any one of claims 1 to 6, comprising the following steps: Taking the center point of the first set of engraved patterns as the origin, a rectangular coordinate system is established, and a measuring instrument is used to measure the distance W1 between the center of the third mark and the center of the sixth mark in the X direction, and the distance W2 between the center of the first mark and the center of the fourth mark in the X direction; Using a measuring instrument, measure a distance W3 between the center of the third mark and the center of the sixth mark in the Y direction, and measure a distance W4 between the center of the second mark and the center of the fifth mark in the Y direction; The offsets of the center point of the first overlay pattern and the center point of the second overlay pattern in the X direction and the Y direction are obtained by calculation to obtain the overlay error value of the current layer of the wafer substrate relative to the front layer of the wafer substrate, wherein: OVLX=(W1-W2) / 2, OVLY=(W3-W4) / 2.

8. The method for measuring overlay offset according to claim 7, characterized in that: The measuring method can be applied to processes of 28 nm and below.

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