Instruction stream generation method, device, electronic device and storage medium

Abstract

An embodiment of the present invention provides an instruction stream generation method, device, electronic device and storage medium, which relates to the field of computer technology. In this method, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix operation code set corresponding to the register jump instruction is determined; based on the source register encoding and prefix operation code set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. By providing a jump address for the corresponding register jump instruction through the second instruction stream in the target instruction stream, the jump controllability of the register jump instruction in the target instruction stream can be improved, thereby improving the test stability when the CPU is tested through the target instruction stream.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to an instruction stream generation method, device, electronic device, and storage medium. Background Art

[0002] At present, with the continuous development of computer technology, the design of central processing unit (CPU) is becoming more and more complex. How to verify the CPU during the design and development process is becoming more and more important in the CPU development process.

[0003] Typically, an instruction generator generates an instruction stream according to a specific generation rule or randomly. This stream is then fed into a simulated CPU core or a physical CPU core, and the CPU is tested by observing how the CPU processes and responds to the instruction stream. This instruction stream must contain instructions with a variety of opcodes to test the instruction processing capabilities of the simulated CPU core or physical CPU core. However, the generated instruction stream may contain register jump instructions, which often result in unpredictable instruction jumps when executed. This can lead to errors in the instruction stream execution and affect the stability of the instruction stream test on the CPU. Summary of the Invention

[0004] Embodiments of the present invention provide an instruction stream generation method, device, electronic device, and storage medium, which can improve the test stability when testing a CPU through an instruction stream.

[0005] In order to solve the above problems, an embodiment of the present invention discloses an instruction stream generation method, which includes:

[0006] determining a register jump instruction from the first instruction stream;

[0007] Determining a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction;

[0008] generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is used to provide a jump address for the register jump instruction;

[0009] The second instruction stream is inserted into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

[0010] Optionally, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and determining the prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction includes:

[0011] Randomly selecting a first prefix opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction;

[0012] Based on the number of source registers corresponding to the first prefix opcode, a second prefix opcode corresponding to the first prefix opcode is randomly selected from a preset opcode library.

[0013] Optionally, randomly selecting a second prefix opcode corresponding to the first prefix opcode from a preset opcode library based on the number of source registers corresponding to the first prefix opcode includes:

[0014] Based on the input data type corresponding to the first preceding opcode, determining a candidate opcode from the preset opcode library, the candidate opcode having an output data type that is the same as the input data type;

[0015] Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from the candidate operation codes.

[0016] Optionally, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set includes:

[0017] Determining, based on the source register code of the register jump instruction, a destination register code corresponding to each first prefix opcode in the prefix opcode set;

[0018] Determining a second instruction corresponding to each first prefix opcode based on a destination register code corresponding to each first prefix opcode and a randomly generated source register code for each first prefix opcode, and generating a second instruction corresponding to a second prefix opcode of each first prefix opcode based on the source register code corresponding to each first prefix opcode;

[0019] The second instructions are arranged based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0020] Optionally, generating a second instruction corresponding to a second prefix operation code of each first prefix operation code based on a source register code corresponding to each first prefix operation code includes:

[0021] determining a target execution result of each first prefix opcode in the prefix opcode set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction;

[0022] Determining an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code;

[0023] Based on the source register code corresponding to each first prefix operation code and the immediate value, a second instruction corresponding to the second prefix operation code of each first prefix operation code is generated.

[0024] Optionally, the method further includes:

[0025] A jump address of the register jump instruction is selected from an instruction address set corresponding to the target instruction stream.

[0026] Optionally, inserting the second instruction stream into the first instruction stream to obtain a target instruction stream includes:

[0027] Determining an execution order corresponding to each first instruction in the first instruction stream;

[0028] Selecting a target instruction from the first instruction whose execution order is less than or equal to the register jump instruction;

[0029] The second instruction stream is inserted before the target instruction in the first instruction stream to obtain a target instruction stream.

[0030] On the other hand, an embodiment of the present invention discloses an instruction stream generating device, the device comprising:

[0031] an instruction determination module, configured to determine a register jump instruction from the first instruction stream;

[0032] an opcode determination module, configured to determine a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction;

[0033] an instruction stream module, configured to generate a second instruction stream based on a source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is configured to provide a jump address to the register jump instruction;

[0034] An insertion module is used to insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

[0035] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0036] An embodiment of the present invention further discloses a computer-readable storage medium having instructions stored thereon. When executed by one or more processors, the processors are enabled to execute the method described above.

[0037] The embodiment of the present invention includes the following advantages: in the instruction stream generation method provided in the embodiment of the present invention, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, the jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, thereby improving the jump controllability of the register jump instruction in the target instruction stream, thereby improving the test stability when the CPU is tested through the target instruction stream. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 This is a flowchart of a method for generating an instruction stream provided by an embodiment of the present invention;

[0040] Figure 2 This is a block diagram of an instruction stream generating device provided by an embodiment of the present invention;

[0041] Figure 3 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] Reference Figure 1 , shows a flowchart of the steps of an instruction stream generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps:

[0044] Step 101: Determine a register jump instruction from a first instruction stream.

[0045] In an embodiment of the present invention, the first instruction stream may be an instruction stream used to test a CPU or CPU core to be tested. The test environment may include a hardware environment and a simulation environment, i.e., the CPU core to be tested may be a physical core or a simulated core. The first instruction stream may represent an instruction stream generated according to certain rules or may refer to a randomly generated instruction stream. The instructions contained in the first instruction stream may belong to the instruction architecture of the CPU or CPU core to be tested.

[0046] In an embodiment of the present invention, a register jump instruction may represent an instruction that jumps to a specified instruction to continue execution. Register jump instructions may include, but are not limited to, jump instructions that depend on a source register (SourceRegister), such as JUMP_REG, JMP, JR, JALR, and BX. The source register represents the register that provides input data when executing the instruction. For example, a register jump instruction may be "JR rs1," which may indicate a jump to the instruction address specified by the r1 register to continue execution; a register jump instruction may be "JUMP_REG rd rs1 rs2," which may indicate a jump to the instruction address specified by the sum of the rs1 register and the rs2 register to continue execution, and the jump address is stored in the rd register.

[0047] In an embodiment of the present invention, all register jump instructions contained in a first instruction stream can be determined, and the first instruction stream can include one or more register jump instructions. Specifically, the opcode of each first instruction in the first instruction stream can be identified, and the identified opcode of the first instruction can be matched with the opcode corresponding to the register jump instruction to determine whether each instruction in the first instruction stream is a register jump instruction.

[0048] Step 102: Determine a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction.

[0049] In this embodiment of the present invention, for each register jump instruction in the first instruction stream, the corresponding source register number can be determined, and based on the source register number, the corresponding prefix opcode set of the register jump instruction can be determined. That is, for each register jump instruction in the first instruction stream, the corresponding prefix opcode set can be determined. The prefix opcode set represents a set consisting of all prefix opcodes used to write required data to the source register of the corresponding register jump instruction.

[0050] In an embodiment of the present invention, based on the number of source registers of a register jump instruction, an opcode corresponding to the source register number can be selected from a preset opcode library as a set of prefix opcodes corresponding to the register jump instruction. The preset opcode library may include, but is not limited to, opcodes such as ADD, SUB, MUL, DIV, INC, and DEC that can be used to write data to a register. The above-mentioned method of selecting an opcode may include, but is not limited to, random selection, sequential selection, reverse selection, alternating selection, etc., and is not specifically limited in the embodiment of the present invention.

[0051] For example, if the first instruction stream includes a register jump instruction "JUMP_REG rd rs1 rs2", the number of corresponding source registers can be determined to be two, namely registers rs1 and rs2, and a prefix opcode set including two prefix opcodes can be generated, for example, [ADD, SUB]. It should be noted that the prefix opcode set may or may not include repeated opcodes, which is not specifically limited in this embodiment of the present invention.

[0052] Step 103 : Generate a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is used to provide a jump address for the register jump instruction.

[0053] In an embodiment of the present invention, the source register code of the source register corresponding to the register jump instruction can also be obtained, and based on the source register code and the prefix operation code set corresponding to the register jump instruction, the second instruction corresponding to each prefix operation code in the prefix operation code set is generated to obtain a second instruction stream composed of the second instructions.

[0054] In an embodiment of the present invention, different types of prefix operation codes are input in different ways. Some prefix operation codes only use source registers as data sources, some prefix operation codes only use immediate values ​​as operation sources, and other prefix operation codes may use both immediate values ​​and source registers as data sources.

[0055] Specifically, for a pre-opcode in a pre-opcode set, a source register code of a corresponding register jump instruction can be used as its destination register code. When the pre-opcode relies on a source register as a data source, a source register code corresponding to the pre-opcode is randomly generated, and based on the jump address of the register jump instruction, register data is written into the source register corresponding to the pre-opcode. When the pre-opcode relies on an immediate value as a data source, the immediate value is determined according to the jump address of the register jump instruction, so that when the register jump instruction performs an instruction jump according to its source register data, it can jump to the corresponding jump address. The jump address corresponding to the register jump instruction can be generated according to a certain instruction address generation rule, or can be selected from the first instruction stream and / or the second instruction stream, or can be selected from other test instruction streams, and the embodiment of the present invention does not make specific limitations.

[0056] For example, if there is a register jump instruction "JUMP_REG rd rs1 rs2", its corresponding jump address is 60, the source register codes of the source registers rs1 and rs2 of the register jump instruction are 14 and 26 respectively, and the prefix opcode set corresponding to the register jump instruction is [ADD, SUB]. If the prefix opcodes in the prefix opcode set all use only source registers as data sources, then the destination register codes corresponding to the prefix opcodes ADD and SUB can be determined as 14 and 16 respectively (corresponding to the source register code of the register jump instruction), and the corresponding source register codes are randomly generated for the prefix opcodes ADD and SUB. The second instruction corresponding to the prefix opcode ADD can be "ADD 14 17 25" (where 17 and 25 are the randomly generated source register codes corresponding to the prefix opcode ADD), and the second instruction corresponding to the prefix opcode SUB is "SUB 16 19 35". According to the jump address 60 of the register jump instruction, corresponding register data can be generated for the source registers of the preceding operation code ADD (i.e., register 17, register 25) and the source registers corresponding to the preceding operation code SUB (i.e., register 19, register 35), and written into the corresponding registers, so that after the actual execution results obtained by executing the preceding operation codes ADD and SUB are written into their registers 14 and 16, the register jump instruction can jump to the jump address 60 of the register jump instruction based on the register data in registers 14 and register 16 to continue execution.

[0057] It should be noted that, continuing with the above example, since the prefix opcode set corresponding to the register jump instruction includes immediate value loading instructions such as LOAD_IMM, for example, the prefix opcode set can be [LOAD_IMM, LOAD_IMM], the destination register codes corresponding to the two prefix opcodes LOAD_IMM can be determined as 14 and 16 respectively, and the corresponding immediate value can be generated for each prefix opcode according to the jump address 60 of the register jump instruction, so that after the actual execution results obtained by executing the two prefix opcodes LOAD_IMM are written into their destination registers 14 and 16, the register jump instruction can jump to its jump address 60 based on the register data in registers 14 and 16 to continue execution. For example, the second instructions corresponding to each prefix opcode in the prefix opcode set may be "LOAD_IMM 14 7" and "LOAD_IMM 16 8" respectively, where 7 and 8 represent their immediate values, and 14 and 16 represent their destination register codes. After the second instructions corresponding to the above prefix opcodes are executed, 7 and 8 can be written into registers 14 and 16 respectively. Thus, when the register jump instruction is executed, it can jump to the instruction corresponding to the jump address 60 according to the register data of registers 14 and 16 to continue execution. It should be noted that the method of generating the immediate value corresponding to the prefix opcode and the register data of the source register may be different depending on the instruction jump rules of the register jump instruction. For example, if the register jump instruction accumulates the register data of its source register and multiplies the accumulated result by the address step (for example, 4) to obtain the jump address, then the accumulated result of the immediate values ​​corresponding to each prefix opcode generated in the above example is 60 / 4=15.

[0058] Step 104: insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test a central processing unit.

[0059] In an embodiment of the present invention, the second instructions corresponding to all preceding opcodes of a register jump instruction may constitute a second instruction stream corresponding to the register jump instruction. The second instruction stream may be inserted into the first instruction stream to obtain a target instruction stream. Thus, during the execution of the target instruction stream, the first instruction stream therein may prepare and provide input data for the corresponding register jump instruction, ensuring that after executing the register jump instruction, the target instruction stream may correctly jump to the corresponding jump address for continued execution. This not only ensures the correct execution of each instruction in the first instruction stream, but also increases the complexity and randomness of the instruction stream used to test the CPU, thereby helping to improve the test effect.

[0060] Specifically, the second instruction stream can be directly inserted into the sequence position before the corresponding register jump instruction in the first instruction stream to obtain the target instruction stream, so that when the target instruction stream is executed sequentially, its corresponding second instruction stream can be executed first before the register jump instruction is executed, so that the corresponding input data is prepared in its source register before the register jump instruction is executed.

[0061] In summary, in an instruction stream generation method provided by an embodiment of the present invention, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, a jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, thereby improving the jump controllability of the register jump instruction in the target instruction stream, thereby improving the test stability when the CPU is tested through the target instruction stream.

[0062] Optionally, in some embodiments, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode. The step of determining the prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction may specifically include:

[0063] Step 1021 : randomly selecting a first prefix opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction.

[0064] Step 1022: Based on the number of source registers corresponding to the first prefix opcode, randomly select a second prefix opcode corresponding to the first prefix opcode from a preset opcode library.

[0065] In an embodiment of the present invention, a pre-opcode set may include a first pre-opcode that directly generates input data for a corresponding register jump instruction, and a second pre-opcode that generates data input for the first pre-opcode. That is, the pre-opcodes in the pre-opcode set may be divided into multiple levels. The instructions generated by the pre-opcodes at these different levels may pass data level by level, with the first pre-opcode ultimately providing input data for the corresponding register jump instruction.

[0066] Specifically, based on the number of source registers corresponding to the register jump instruction, a first prefix opcode can be randomly selected from a preset opcode library, so that the number of first prefix opcodes is equal to the number of source registers corresponding to the register jump instruction; and for each first prefix opcode, based on the number of source registers corresponding to the first prefix opcode, a second prefix opcode corresponding to the first prefix opcode can be randomly selected from the preset opcode library, so that the number of second prefix opcodes corresponding to the first prefix opcode is equal to the number of source registers corresponding to the first prefix opcode.

[0067] For example, if there is a register jump instruction "JUMP_REG rd rs1 rs2", its corresponding prefix opcode set may include two first prefix opcodes, which are used to write register data to the source registers rs1 and rs2 of the register jump instruction respectively. Each first prefix opcode may also have a corresponding second prefix opcode, and these second prefix opcodes can be used to write register data to the source register of the corresponding first prefix opcode. If the above two first prefix opcodes are ADD and SUM, respectively, the first prefix opcode ADD may correspond to two second prefix opcodes LOAD_IMM, and the first prefix opcode SUM may also correspond to two second prefix opcodes LOAD_IMM. The second prefix opcode LOAD_IMM can be used to write an immediate value to the source register of the first prefix opcode as the input data of the first prefix opcode.

[0068] It should be noted that the above-mentioned first prefix operation code and the second prefix operation code corresponding to the first prefix operation code can be randomly selected from a preset operation code library that can write data to the register. The second prefix operation code corresponding to the first prefix operation code can be an operation code that uses an immediate value as data input, or an operation code that uses a source register as data input. In the case that the second prefix operation code corresponding to the first prefix operation code uses a source register as data input, a corresponding second prefix operation code can be further selected for the second prefix operation code to write data to its source register, thereby forming multiple levels of second prefix operation codes.

[0069] Furthermore, in order to prevent the second prefix opcode level from expanding indefinitely, the maximum level of the second prefix opcode can be limited (for example, 2 levels). Then, when selecting the second prefix opcode of the maximum level, only opcodes that use immediate values ​​as data inputs can be selected from the preset opcode library.

[0070] In an embodiment of the present invention, a first prefix opcode can be randomly selected from a preset opcode library based on the number of source registers corresponding to the register jump instruction; and a second prefix opcode corresponding to the first prefix opcode can be randomly selected from the preset opcode library based on the number of source registers corresponding to the first prefix opcode. This not only allows different types and numbers of prefix opcodes to be generated for different register jump instructions, but also allows the same register jump instruction to correspond to different types and numbers of prefix opcodes. This helps provide a richer set of instruction combinations for register jump instruction input data in the subsequently generated target instruction stream, thereby improving the complexity and test accuracy of the target instruction stream.

[0071] Optionally, in some embodiments, the step of randomly selecting a second prefix opcode corresponding to the first prefix opcode from a preset opcode library based on the number of source registers corresponding to the first prefix opcode may specifically include:

[0072] Step A1: Based on the input data type corresponding to the first preceding operation code, determine a candidate operation code having the same output data type as the input data type from the preset operation code library.

[0073] Step A2: randomly selecting a second prefix operation code corresponding to the first prefix operation code from the candidate operation codes based on the number of source registers corresponding to the first prefix operation code.

[0074] In an embodiment of the present invention, since the input data types required by different first prefix opcodes may be different, when selecting a corresponding second prefix opcode for a first prefix opcode, an opcode with a corresponding output data type may be selected from a preset opcode library as a candidate opcode based on the input data type of the first prefix opcode. Then, based on the number of source registers of the first prefix opcode, a corresponding second prefix opcode may be selected from the candidate opcodes, so that the input data type of the first prefix opcode is the same as the output data type of the corresponding second prefix opcode.

[0075] For example, if the input data type required by the first preceding opcode is an integer type, all integer opcodes whose output data type is an integer can be selected from the preset opcode library as candidate opcodes, and an integer opcode can be selected from these candidate opcodes as the corresponding second preceding opcode.

[0076] Accordingly, since the input data types required by different register jump instructions may be different, when selecting the corresponding first preceding opcode for the register jump instruction, it is also possible to select an opcode of the corresponding output data type from the preset opcode library as its candidate opcode based on the input data type of the register jump instruction, and then select the first preceding opcode of the source register number from the candidate opcodes based on the source register number of the register jump instruction, so that the input data type of the register jump instruction is the same as the output data type of the corresponding first preceding opcode.

[0077] In an embodiment of the present invention, a candidate opcode having the same output data type as the input data type can be determined from a preset opcode library based on the input data type corresponding to the first prefix opcode; and a second prefix opcode corresponding to the first prefix opcode can be randomly selected from the candidate opcodes based on the number of source registers corresponding to the first prefix opcode. The ability to select a second prefix opcode having the same output data type for first prefix opcodes having different input data types helps improve the execution stability of a subsequent second instruction stream generated based on the prefix opcode set.

[0078] Optionally, in some embodiments, the prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and the step of generating the second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set may specifically include:

[0079] Step 1031 : Determine the destination register code corresponding to each first prefix opcode in the prefix opcode set based on the source register code of the register jump instruction.

[0080] In the embodiment of the present invention, since the first prefix operation code is used to write register data to the source register of the corresponding register jump instruction, the source register code of the register jump instruction corresponding to the first prefix operation code can be directly used as the destination register code corresponding to the first prefix operation code.

[0081] Step 1032: Determine a second instruction corresponding to each first prefix opcode based on the destination register code corresponding to each first prefix opcode and the randomly generated source register code for each first prefix opcode; and generate a second instruction corresponding to the second prefix opcode of each first prefix opcode based on the source register code corresponding to each first prefix opcode.

[0082] In the embodiment of the present invention, a source register code may be randomly generated for the first preceding operation code, and a corresponding second instruction may be generated based on the destination register code and the source register code corresponding to the first preceding operation code.

[0083] For example, assume that the randomly generated first instruction stream has a total of 24 instructions, of which the 10th instruction is a register jump instruction JUMP_REG. The register jump instruction JUMP_REG has a destination register JUMP_REG_rd, the encoding of the destination register JUMP_REG_rd is 31, and has two source registers JUMP_REG_rs1 and JUMP_REG_rs2, the encoding of JUMP_REG_rs1 is 10, and the encoding of JUMP_REG_rs2 is 20. For JUMP_REG_rs1 and JUMP_REG_rs2, the corresponding first prefix opcodes ADD and SUB can be randomly selected from the preset opcode library, respectively. If the first prefix operation code ADD has a destination register ADD_rd and two source registers ADD_rs1 and ADD_rs2, then the destination register ADD_rd of the first prefix operation code ADD can be set to 10, and the source registers ADD_rs1 and ADD_rs2 of the first prefix operation code ADD can be set to random values ​​3 and 17 respectively, resulting in the second instruction "ADD 10 3 17" corresponding to the first prefix operation code ADD. If the first prefix operation code SUB has a destination register SUB_rd and two source registers SUB_rs1 and SUB_rs2, then the destination register SUB_rd of the first prefix operation code SUB can be set to 20, and the source registers SUB_rs1 and SUB_rs2 of the first prefix operation code SUB can be set to random values ​​14 and 26 respectively, resulting in the second instruction "SUB 2014 26" corresponding to the first prefix operation code SUB.

[0084] In an embodiment of the present invention, the prefix operation code set may further include a second prefix operation code corresponding to the first prefix operation code, and each second prefix operation code may correspond to a source register of a first prefix operation code. Then, for each second prefix operation code, the source register code of the corresponding first prefix operation code may be used as the destination register code of the second prefix operation code, and a source register code may be randomly generated for the second prefix operation code, thereby generating a second instruction corresponding to the second prefix operation code based on the destination register code and source register code corresponding to the second prefix operation code.

[0085] Optionally, when the second prefix opcode is an immediate value load opcode, the immediate value of the second prefix opcode can be calculated based on the target execution result and operation mode of the corresponding first prefix opcode, and the corresponding second instruction can be generated based on the immediate value and destination register encoding corresponding to the second prefix opcode. The target execution result of the first prefix opcode represents the value expected to be written to the destination register of the second instruction after the second instruction generated by the first prefix opcode is executed.

[0086] Continuing with the above example, the prefix opcode set may further include a second prefix opcode corresponding to each first prefix opcode. Assuming that the source register of each first prefix opcode corresponds to a second prefix opcode, and these second prefix opcodes are all immediate load opcodes LOAD_IMM, then the destination registers of the second prefix opcodes LOAD_IMM1 to 4 can be set to 3, 17, 14, and 26, respectively, corresponding to a source register of a first prefix opcode. If the jump address of the register jump instruction JUMP_REG is 60, and the instruction jump rule of the register jump instruction JUMP_REG is to accumulate the register data of JUMP_REG_rs1 and the register data of JUMP_REG_rs2, and use the product of the accumulated result and the address step 4 as the jump address, then the sum of the target execution result of the second instruction "ADD 10 3 17" and the target execution result of the second instruction "SUB 2014 26" can be 60 / 4=15 as a condition, and the target execution result of the second instruction "ADD 10 3 17" = 30 and the target execution result of the second instruction "SUB 2014 26" can be randomly generated. 26". The target execution result = -15. The sum of the immediate values ​​of the two second pre-opcodes LOAD_IMM1 to 2 corresponding to the first pre-opcode ADD is further taken as 30 as a condition, and the immediate values ​​of the second pre-opcodes LOAD_IMM1 to 2 are randomly generated as 12 and 18 respectively, so that the sum of the two immediate values ​​is 30; the difference between the immediate values ​​of the two second pre-opcodes LOAD_IMM3 to 4 corresponding to the first pre-opcode SUB is -15 as a condition, and the immediate values ​​of the second pre-opcodes LOAD_IMM3 to 4 are randomly generated as 37 and 52 respectively, so that the difference between the two immediate values ​​is equal to -15. Therefore, according to the destination register codes and immediate values ​​corresponding to the second pre-opcodes LOAD_IMM1 to 4, four second instructions can be generated, namely "LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 1437", and "LOAD_IMM 26 52".

[0087] Step 1033: Arrange the second instructions based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0088] In an embodiment of the present invention, since the source register of the second instruction corresponding to the first pre-opcode serves as the destination register of the second instruction corresponding to the second pre-opcode, and the source register of the second instruction corresponding to the second pre-opcode can also serve as the destination register of the second instructions corresponding to other second pre-opcodes, these second instructions can form different instruction hierarchies, and the instructions of adjacent instruction hierarchies can have a read-after-write dependency relationship. The second instructions can be arranged according to the read-after-write dependency relationship between the second instructions, so that in a second instruction pair with a read-after-write dependency relationship (a pair of second instructions with the same destination register code and source register code), the second instruction that writes data to the same register is located before the second instruction that reads data from the same register, thereby obtaining a second instruction stream. It should be noted that the second instructions can be randomly arranged while satisfying the above-mentioned constraints to obtain a second instruction stream, thereby improving the complexity and randomness of the second instruction stream and improving the test accuracy of the target instruction stream subsequently obtained based on the second instruction stream.

[0089] Continuing with the above example, the second instruction may include "SUB 20 14 26", "ADD 10 3 17", "LOAD_IMM 312", "LOAD_IMM 17 18", "LOAD_IMM 14 37", and "LOAD_IMM 26 52". If the source register code 14 of "SUB 20 14 26" is the same as the destination register code 14 of "LOAD_IMM 14 37", then "SUB 20 14 26" and "LOAD_IMM 14 37" may constitute a second instruction pair with a read-after-write dependency relationship; if the source register code 26 of "SUB 20 14 26" is the same as the destination register code 26 of "LOAD_IMM 26 52", then "SUB 20 14 26" and "LOAD_IMM26 52" may constitute a second instruction pair with a read-after-write dependency relationship, and so on. According to the read-after-write dependency relationship between the second instructions, the above-mentioned six second instructions may generate the second instruction stream ["LOAD_IMM 26 52", "LOAD_IMM 1437", "SUB 20 14 26", "LOAD_IMM 3 12", "LOAD_IMM 17 18", "ADD 10 3 17"]; may also generate the second instruction stream ["LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 26 52", "LOAD_IMM 1437", "ADD 10 3 17", "SUB 20 14 26"]; may also generate the second instruction stream in other arrangement orders, which is not specifically limited in the embodiment of the present invention.

[0090] In an embodiment of the present invention, a second instruction corresponding to each first pre-opcode is determined based on a destination register code corresponding to each first pre-opcode and a randomly generated source register code for each first pre-opcode; a second instruction corresponding to a second pre-opcode of each first pre-opcode is generated based on the source register code corresponding to each first pre-opcode; and each second instruction is arranged based on a read-after-write dependency relationship between the second instructions to obtain a second instruction stream. This enables the second instructions in the second instruction stream to be executed sequentially according to the read-after-write dependency relationship, thereby helping to improve the execution stability of the instruction stream.

[0091] Optionally, in some embodiments, the step of generating a second instruction corresponding to a second prefix opcode of each first prefix opcode based on a source register code corresponding to each first prefix opcode may specifically include:

[0092] Step B1: determining a target execution result of each first prefix operation code in the prefix operation code set based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction.

[0093] In an embodiment of the present invention, a target execution result of each first prefix opcode in a corresponding prefix opcode set can be determined based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction. The target execution result of the first prefix opcode of the register jump instruction is the input data of the register jump instruction, and the instruction jump rule is used to describe how the register jump instruction calculates and jumps to its corresponding jump address based on the input data.

[0094] For example, if the instruction jump rule for a register jump instruction is to add the register data of the two source registers of the register jump instruction and use the product of the added result and 4 as the jump address, then if the jump address corresponding to the register jump instruction is 60, the target execution results of the two first prefix opcodes corresponding to the register jump instruction can be randomly generated as -15 and 30, respectively. Therefore, the calculation result of ((-15) + 30) × 4 equals the jump address 60.

[0095] Step B2: determining the immediate value corresponding to the second preceding operation code of each first preceding operation code based on the target execution result of each first preceding operation code and the operation rule of each first preceding operation code.

[0096] In an embodiment of the present invention, each first pre-opcode may correspond to a second pre-opcode for providing input data therefor, and the second pre-opcode may be an immediate load opcode and a non-immediate load opcode. In the case where the second pre-opcode is an immediate load opcode, an immediate value may be generated for the second pre-opcode corresponding to the first pre-opcode based on the target execution result of the first pre-opcode, so that the calculation result obtained by calculating the immediate values ​​of all second pre-opcodes corresponding to the first pre-opcode using the calculation rule corresponding to the first pre-opcode is equal to the target execution result corresponding to the first pre-opcode. Different pre-opcodes may correspond to different calculation rules. For example, the calculation rule of the ADD opcode is register data addition, and the calculation rule of the SUB opcode is register data subtraction. The above calculation rules may include but are not limited to addition, subtraction, multiplication, division, etc., and are not specifically limited in the embodiment of the present invention.

[0097] For example, if the target execution results of the first prefix operation code SUB and the first prefix operation code ADD are -15 and 30 respectively, the sum of the immediate values ​​of the two second prefix operation codes LOAD_IMM1 and LOAD_IMM2 corresponding to the first prefix operation code ADD can be used as a condition to randomly generate the immediate values ​​of the second prefix operation codes LOAD_IMM1 and LOAD_IMM2 as 12 and 18 respectively, so that the sum of the two immediate values ​​is 30; the difference between the immediate values ​​of the two second prefix operation codes LOAD_IMM3 and LOAD_IMM4 corresponding to the first prefix operation code SUB is -15 as a condition to randomly generate the immediate values ​​of the second prefix operation codes LOAD_IMM3 and LOAD_IMM4 as 37 and 52 respectively, so that the difference between the two immediate values ​​is equal to -15.

[0098] Step B3: generating a second instruction corresponding to a second prefix operation code of each first prefix operation code based on the source register code corresponding to each first prefix operation code and the immediate value.

[0099] In an embodiment of the present invention, the target execution result of each first prefix opcode in the prefix opcode set can be determined based on the jump address of the register jump instruction and the instruction jump rule corresponding to the register jump instruction; the immediate value corresponding to the second prefix opcode of each first prefix opcode is determined based on the target execution result of each first prefix opcode and the operation rule of each first prefix opcode; and the second instruction corresponding to the second prefix opcode of each first prefix opcode is generated based on the source register code and the immediate value corresponding to each first prefix opcode. By configuring the immediate value in the second instruction, the jump address of the corresponding register jump instruction can be controlled, so that the register jump instruction can jump to the correct instruction for continued execution, which helps to improve the execution stability of the target instruction stream generated subsequently.

[0100] Optionally, in some embodiments, the jump address of the register jump instruction may be selected from a set of instruction addresses corresponding to the target instruction stream.

[0101] In an embodiment of the present invention, each instruction in the target instruction stream has a corresponding instruction address. In order to improve the operational stability of the target instruction stream and avoid jumping to an unreasonable address during the execution of the target instruction stream, the jump address of the register jump instruction can be selected from the instruction address set corresponding to the target instruction stream. The above-mentioned instruction address set may include the instruction addresses corresponding to all instructions in the target instruction stream, and the above-mentioned selection method may include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., which are not specifically limited in the embodiment of the present invention.

[0102] It should be noted that the jump address corresponding to the register jump instruction may also be selected from some instruction addresses in the instruction address set of the target instruction stream. For example, the jump address of the register jump instruction may be selected from the instruction addresses corresponding to the first instructions in the first instruction stream of the instruction address set.

[0103] For example, if the instruction starting address of the first instruction stream is 0, and the address difference between adjacent instructions is 4, and the first instruction stream contains 24 instructions, then the corresponding instruction address set can be {0, 4, 8, ..., 92, 96}. If the instruction address of a register jump instruction included in the first instruction stream is 40, and the second instruction stream corresponding to the register jump instruction contains 8 instructions, which are inserted before the above-mentioned register jump instruction, the instruction address set corresponding to the obtained second instruction stream can be {0, 4, 8, ..., 124, 128}. The jump address of the register jump instruction can be randomly selected from the instruction address set corresponding to the second instruction stream, for example, a jump address of 60 can be selected. After determining the corresponding jump address for the register jump instruction, the immediate value or source register data corresponding to the second instruction in the corresponding second instruction set can be determined based on its jump address.

[0104] In an embodiment of the present invention, by selecting a jump address for a register jump instruction from a set of instruction addresses corresponding to a target instruction stream, the target instruction stream can always jump between instructions within the instruction stream during re-execution, thereby avoiding instruction jump errors and helping to improve the operational stability of the target instruction stream.

[0105] For example, if a register jump instruction is "JUMP_REG 48 10 20", its corresponding second instruction stream can be ["LOAD_IMM 3 12", "LOAD_IMM 17 18", "LOAD_IMM 26 52", "LOAD_IMM 14 37", "ADD10 3 17", "SUB 20 14 26"]. By executing the above second instruction stream, -15 can be written to register 20 and 30 can be written to register 10. As a result, after the above register jump instruction is executed, the register jumps to the jump address ((-15) + 30) × 4 = 60, and the result of adding registers 10 and 20 is written to register 48 to record the instruction number corresponding to the jump address. The instruction sequence numbers of the register jump instruction and the corresponding second instruction stream in the target instruction stream may be continuous, so that the second instruction stream prepares data in the source register corresponding to the register jump instruction before the corresponding register jump instruction is executed. For example, the instruction sequence numbers of the second instruction stream and the corresponding register jump instruction in the above example may be as shown in Table 1 below:

[0106] Table 1

[0107]

[0108] Optionally, in some embodiments, the step of inserting the second instruction stream into the first instruction stream to obtain a target instruction stream may specifically include:

[0109] Step 1041: Determine the execution order corresponding to each first instruction in the first instruction stream.

[0110] In embodiments of the present invention, due to the presence of register jump instructions or other jump instructions in a first instruction stream, the actual execution order of the first instructions in the first instruction stream may differ from their order in the first instruction stream. To ensure that the second instruction stream can execute before the corresponding register jump instruction and to improve the accuracy and stability of providing jump addresses to the corresponding register jump instructions via the second instruction stream, the execution order corresponding to the first instructions in the first instruction stream can be determined.

[0111] Specifically, the first instruction stream may be simulated and the execution order of each first instruction in the first instruction stream may be recorded during the simulation. Alternatively, the opcode and operand of each first instruction in the first instruction stream may be analyzed to determine the execution order of each first instruction in the first instruction stream, which is not specifically limited in the embodiment of the present invention.

[0112] Step 1042 : Select a target instruction from the first instructions whose execution order is less than or equal to the register jump instruction.

[0113] In an embodiment of the present invention, a first instruction whose execution order is less than or equal to the register jump instruction can be determined from the first instruction stream. That is, the first instruction whose execution order is less than or equal to the register jump instruction can include the first instruction whose execution order is less than the register jump instruction, as well as the register jump instruction itself. Then, from the first instructions whose execution order is less than or equal to the register jump instruction, a first instruction is selected as the target instruction corresponding to the register jump instruction. The above selection method may include, but is not limited to, random selection, rule selection, etc., and is not specifically limited in the embodiment of the present invention.

[0114] Step 1043: Insert the second instruction stream before the target instruction in the first instruction stream to obtain a target instruction stream.

[0115] In an embodiment of the present invention, a second instruction stream of register jump instructions may be inserted before a target instruction corresponding to the register jump instruction in a first instruction stream, thereby obtaining a target instruction stream consisting of the first instruction stream and the second instruction stream. It should be noted that "before the target instruction" in the first instruction stream may refer to a position adjacent to the target instruction or to a position separated from the target instruction by one or more instructions, and this is not specifically limited in the embodiment of the present invention.

[0116] In an embodiment of the present invention, since the first instruction stream may include multiple register jump instructions, each register jump instruction may generate a corresponding second instruction stream. Therefore, the target instruction stream generated based on the first instruction stream and the second instruction stream may include second instruction streams corresponding to multiple register jump instructions.

[0117] In an embodiment of the present invention, a target instruction stream is obtained by determining the execution order corresponding to each first instruction in a first instruction stream; selecting a target instruction from first instructions whose execution order is less than or equal to a register jump instruction; and inserting a second instruction stream before the target instruction in the first instruction stream. While ensuring stable and accurate execution of the target instruction stream, the randomness of the insertion of the second instruction stream into the first instruction stream can be improved, thereby increasing the diversity and variability of the resulting target instruction stream, thereby improving the accuracy and efficiency of testing a CPU core using the target instruction stream.

[0118] Reference Figure 2 , shows a block diagram of an instruction stream generating device provided by an embodiment of the present invention, such as Figure 2 As shown, the device may specifically include:

[0119] An instruction determination module 201 is configured to determine a register jump instruction from a first instruction stream;

[0120] An opcode determination module 202 is configured to determine a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction;

[0121] An instruction stream module 203 is configured to generate a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is configured to provide a jump address for the register jump instruction;

[0122] The inserting module 204 is used to insert the second instruction stream into the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test the central processing unit.

[0123] Optionally, the pre-opcode set includes a first pre-opcode and a second pre-opcode corresponding to the first pre-opcode, and the opcode determination module includes:

[0124] A first pre-opcode submodule is configured to randomly select a first pre-opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction;

[0125] The second pre-opcode sub-module is configured to randomly select a second pre-opcode corresponding to the first pre-opcode from a preset opcode library based on the number of source registers corresponding to the first pre-opcode.

[0126] Optionally, the second pre-opcode submodule includes:

[0127] a candidate operation code unit, configured to determine, from the preset operation code library, a candidate operation code having an output data type that is the same as the input data type, based on the input data type corresponding to the first preceding operation code;

[0128] The second preceding operation code selection unit is configured to randomly select a second preceding operation code corresponding to the first preceding operation code from the candidate operation codes based on the number of source registers corresponding to the first preceding operation code.

[0129] Optionally, the prefix operation code set includes a first prefix operation code and a second prefix operation code corresponding to the first prefix operation code, and the instruction stream module includes:

[0130] a destination register encoding submodule, configured to determine, based on the source register encoding of the register jump instruction, a destination register encoding corresponding to each first prefix opcode in the prefix opcode set;

[0131] an instruction determination submodule, configured to determine a second instruction corresponding to each first prefix opcode based on a destination register code corresponding to each first prefix opcode and a source register code randomly generated for each first prefix opcode, and to generate a second instruction corresponding to a second prefix opcode of each first prefix opcode based on the source register code corresponding to each first prefix opcode;

[0132] The instruction stream determination submodule is used to arrange the second instructions based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

[0133] Optionally, the instruction determination submodule includes:

[0134] a target execution result unit, configured to determine a target execution result of each first prefix operation code in the prefix operation code set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction;

[0135] an immediate value unit, configured to determine an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code;

[0136] The instruction generation unit is configured to generate a second instruction corresponding to a second prefix operation code of each first prefix operation code based on a source register code corresponding to each first prefix operation code and the immediate value.

[0137] Optionally, the device further includes:

[0138] The jump address module is used to select the jump address of the register jump instruction from the instruction address set corresponding to the target instruction stream.

[0139] Optionally, the insertion module includes:

[0140] An execution order submodule, configured to determine an execution order corresponding to each first instruction in the first instruction stream;

[0141] a target instruction submodule, configured to select a target instruction from a first instruction whose execution order is less than or equal to the register jump instruction;

[0142] The instruction stream insertion submodule is used to insert the second instruction stream before the target instruction in the first instruction stream to obtain a target instruction stream.

[0143] In summary, in the instruction stream generation device provided by the embodiment of the present invention, a register jump instruction is determined from a first instruction stream; based on the number of source registers corresponding to the register jump instruction, a prefix opcode set corresponding to the register jump instruction is determined; based on the source register encoding and prefix opcode set of the register jump instruction, a second instruction stream is generated; wherein the second instruction stream is used to provide a jump address to the register jump instruction; and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream. A corresponding second instruction stream can be generated for the register jump instruction in the first instruction stream, and the second instruction stream is inserted into the first instruction stream to obtain a target instruction stream, so that when the CPU is tested through the target instruction stream, a jump address can be provided for the corresponding register jump instruction through the second instruction stream in the target instruction stream, thereby improving the jump controllability of the register jump instruction in the target instruction stream, thereby improving the test stability when the CPU is tested through the target instruction stream.

[0144] Reference Figure 3 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction, which enables the processor to execute the instruction stream generation method of the aforementioned embodiment. The executable instructions can constitute a program.

[0145] An embodiment of the present invention provides a computer-readable storage medium having instructions stored thereon. When executed by one or more processors, the processors are enabled to execute the instruction stream generation method of the aforementioned embodiment.

[0146] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0147] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code. It should be noted that all actions in the present invention to obtain signals, information, or data are performed in compliance with the relevant data protection laws and policies of the country of residence and with authorization from the owner of the corresponding device. Embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0148] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0149] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0150] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0151] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0152] The above is a detailed introduction to an instruction stream generation method, an instruction stream generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for generating an instruction stream, characterized in that: The method comprises: determining a register jump instruction from the first instruction stream; Determining a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is used to provide a jump address for the register jump instruction; The second instruction stream is inserted before the target instruction in the first instruction stream to obtain a target instruction stream; wherein the target instruction stream is used to test the central processing unit, and the target instruction is selected from the first instruction in the first instruction stream whose execution order is less than or equal to the register jump instruction.

2. The instruction stream generation method according to claim 1, wherein: The prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and determining the prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction includes: Randomly selecting a first prefix opcode from a preset opcode library based on the number of source registers corresponding to the register jump instruction; Based on the number of source registers corresponding to the first prefix opcode, a second prefix opcode corresponding to the first prefix opcode is randomly selected from a preset opcode library.

3. The instruction stream generation method according to claim 2, wherein: The randomly selecting a second prefix opcode corresponding to the first prefix opcode from a preset opcode library based on the number of source registers corresponding to the first prefix opcode includes: Based on the input data type corresponding to the first preceding opcode, determining a candidate opcode from the preset opcode library, the candidate opcode having an output data type that is the same as the input data type; Based on the number of source registers corresponding to the first preceding operation code, a second preceding operation code corresponding to the first preceding operation code is randomly selected from the candidate operation codes.

4. The instruction stream generation method according to claim 1, wherein: The prefix opcode set includes a first prefix opcode and a second prefix opcode corresponding to the first prefix opcode, and generating a second instruction stream based on the source register encoding of the register jump instruction and the prefix opcode set includes: Determining, based on the source register code of the register jump instruction, a destination register code corresponding to each first prefix opcode in the prefix opcode set; Determining a second instruction corresponding to each first prefix opcode based on a destination register code corresponding to each first prefix opcode and a randomly generated source register code for each first prefix opcode, and generating a second instruction corresponding to a second prefix opcode of each first prefix opcode based on the source register code corresponding to each first prefix opcode; The second instructions are arranged based on the read-after-write dependency relationship between the second instructions to obtain the second instruction stream.

5. The instruction stream generation method according to claim 4, wherein: The generating, based on the source register code corresponding to each first preceding operation code, a second instruction corresponding to the second preceding operation code of each first preceding operation code includes: determining a target execution result of each first prefix opcode in the prefix opcode set based on a jump address of the register jump instruction and an instruction jump rule corresponding to the register jump instruction; Determining an immediate value corresponding to a second preceding operation code of each first preceding operation code based on a target execution result of each first preceding operation code and an operation rule of each first preceding operation code; Based on the source register code corresponding to each first prefix operation code and the immediate value, a second instruction corresponding to the second prefix operation code of each first prefix operation code is generated.

6. The instruction stream generation method according to claim 5, characterized in that: The method further comprises: A jump address of the register jump instruction is selected from an instruction address set corresponding to the target instruction stream.

7. The instruction stream generation method according to claim 1, wherein: Before inserting the second instruction stream before the target instruction in the first instruction stream to obtain the target instruction stream, the method further includes: Determining an execution order corresponding to each first instruction in the first instruction stream; The target instruction is selected from the first instruction whose execution order is less than or equal to the register jump instruction.

8. An instruction stream generating device, characterized in that: The device comprises: an instruction determination module, configured to determine a register jump instruction from the first instruction stream; an opcode determination module, configured to determine a prefix opcode set corresponding to the register jump instruction based on the number of source registers corresponding to the register jump instruction; an instruction stream module, configured to generate a second instruction stream based on a source register encoding of the register jump instruction and the prefix opcode set; wherein the second instruction stream is configured to provide a jump address to the register jump instruction; An insertion module is used to insert the second instruction stream before the target instruction in the first instruction stream to obtain a target instruction stream; wherein, the target instruction stream is used to test the central processing unit, and the target instruction is selected from the first instruction in the first instruction stream whose execution order is less than or equal to the register jump instruction.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction stream generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that Instructions are stored thereon, which, when executed by one or more processors, cause the processors to execute the instruction stream generation method according to any one of claims 1 to 7.

Images