Multi-channel flash memory array controller hardware system and implementation method thereof

Abstract

The invention provides a multi-channel flash memory array controller hardware system and an implementation method thereof in order to solve the multi-channel memory array management problem of a memory system in the fields of high-performance computing, cloud storage, embedded systems and the like. According to the system, hardware design and a management mechanism are optimized, and a parallel expansion DMA technology, a multi-path logic channel design and an optimized bus architecture are adopted, so that the data transmission efficiency is improved, and the resource allocation flexibility is improved. Through hardware level management of the command buffer area and the state processing mechanism, the efficiency bottleneck of a traditional storage array management scheme in large-scale data transmission is solved, and the overall performance and reliability of the system are improved. According to the scheme, the requirements of efficient and high-reliability storage arrays can be met, and the method is particularly suitable for scenes of large-scale data storage and processing.

Description

Technical Field

[0002] The invention relates to a multi-channel flash memory array controller hardware system and an implementation method thereof, belonging to the technical field of high-speed storage. Background Art

[0004] At present, with the rapid development of information technology and the popularization of big data applications, the requirements for storage systems in terms of capacity, speed and reliability are increasing. Especially in the fields of high-performance computing, cloud storage and embedded systems, how to efficiently manage multi-channel storage arrays has become a key issue in technological development. NAND flash memory is widely used in storage array systems due to its high storage density, low power consumption and high read and write speed. However, limited by the characteristics of NAND flash memory itself, such as limited erase and write times and low random write performance, traditional storage array management solutions face problems such as low efficiency and insufficient resource utilization when processing large-scale data transmission. In addition, the single channel or low-bit width DMA transmission method used in the prior art, as well as the complexity of command and status entry management, lead to obvious performance bottlenecks in the system when processing high-concurrency tasks, low bus utilization, and difficulty in meeting high-bandwidth and high-frequency storage requirements. Summary of the invention

[0006] In view of the above problems, the present invention provides a multi-channel flash array controller hardware system and its implementation method to solve the deficiencies in the prior art by optimizing the hardware design and management mechanism. Through parallel extension DMA technology, multi-path logic channel design and optimized bus architecture, data transmission efficiency can be significantly improved and resource allocation flexibility can be improved. In addition, an efficient command buffer and status processing mechanism are adopted to achieve hardware-level management of command and status entries, which helps to improve the overall performance and reliability of the system. This improvement can meet the requirements of current storage array systems for efficiency and reliability, and provides a better solution for large-scale data storage and processing.

[0007] The multi-channel flash array controller hardware system and its implementation method described in the present invention, the system architecture includes a PCIE controller 1, a DMA controller 2, a message control unit 3, four flash array controllers 5 and an MCU 7.

[0008] In terms of storage array management, the system is designed with 4 logical channels corresponding to NAC0 5-1, NAC1 5-2, NAC2 5-3, and NAC3 5-4, corresponding to 8 NAND Flash chips 6-1 of NAC0, 8 NAND Flash chips 6-2 of NAC1, 8 NAND Flash chips 6-3 of NAC2, and 8 NAND Flash chips 6-4 of NAC3. Each flash array has 8 independent flash channels, labeled CH0 to CH7, working in parallel. All channels of a flash array always perform the same operation unless one or more channels are shielded by certain operations. The control signals they receive are the same, but their block and page addresses can be different.

[0009] Equipped with a DMA controller 2 for data transfer in DMA mode. By expanding the number of channels and bit width of the DMA controller, efficient matching with the flash configuration is achieved, thereby improving the transfer rate. The DMA controller receives outbound read / write requests from the on-chip DMA source. Receives inbound read / write requests from the PCE EP interface and converts them into read / write operations of on-chip memory or registers.

[0010] The message and control unit uses a 32-bit wide AHB data bus as the transmission channel for core data and commands. The bus is responsible for connecting various functional modules and efficiently completing the distribution and processing of commands to ensure the continuity and stability of data flow.

[0011] The command buffer is a dual-port SRAM with a total of 96 command slots, a total size of 18KB, and each command slot can only accommodate one command entry. It also supports the writing of message units and the reading operations of the MCU.

[0012] The command buffer is used in a circular manner, and the management of NAC command slot FIFO and empty command FIFO is implemented to ensure efficient processing and fast response of commands. The command pool of NAC 0-3 is managed by two FIFOs: free slot FIFO and completion slot FIFO, and both are 12 levels deep to avoid overflow and ensure smooth processing of commands.

[0013] The array controller state processing method of the present invention comprises: the NAND array controller executes the commands in the command pool, converts them into flash operations, notifies the DMAC to transmit data, and finally reports the state to the MCU.

[0014] On each physical channel, about 40KB of on-chip dual-port SRAM is integrated and used as a flash page buffer. Both ports can read and write. One port is connected to the DMAC interface with a clock frequency of 62.5MHz. The other port is connected to NAC, NFI and ECC. When contention occurs, the priority is NFI, ECC and NAC from high to low.

[0015] CSI is used to manage the exchange of command table entries and status table entries between MCU and NAC. A 12-level command pool is implemented, which is written by MCU and read by NAC. The command queue is used to specify the exact order of command entries from MCU, and the status entry exchange is completed by the status FIFO. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a hardware system architecture diagram of a multi-channel flash array controller;

[0018] Figure 2 is a structural diagram of the array controller and flash array;

[0019] Figure 3 It is the MCU command allocation flow chart;

[0020] Figure 4 It is the flow chart of command pool writing data;

[0021] Figure 5 It is a state frame combination flow chart; DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0025] Specific implementation method 1: The following is combined Figures 1 to 5 Description of this embodiment

[0026] like Figure 1As shown in the figure, in this system, the controller consists of a flash memory controller, RAM, and PCIE and AHB bus architecture. The controller design supports multi-channel data transmission, uses direct memory access (DMA) to efficiently move data, and expands the bit width and number of channels of the DMA controller in parallel to adapt to the existing flash memory configuration.

[0027] In terms of storage array management, the system is designed with 4 logical channels corresponding to NAC0 5-1, NAC1 5-2, NAC2 5-3, and NAC3 5-4, corresponding to 8 NAND Flash chips 6-1 of NAC0, 8 NAND Flash chips 6-2 of NAC1, 8 NAND Flash chips 6-3 of NAC2, and 8 NAND Flash chips 6-4 of NAC3. A DMA controller 2 is provided for data transmission in DMA mode.

[0028] The system architecture includes a PCIE controller 1 , a DMA controller 2 , a message control unit 3 , four flash array controllers 5 and an MCU 7 .

[0029] The system uses a 32-bit AHB bus as the main data and command transmission channel to connect various modules and implement command distribution. In addition, the system is equipped with DDR storage for FPGA use. In terms of data transmission, the system uses a 256-bit bus with a frequency of 78.125MHz and uses DMA for efficient data transfer.

[0030] Each flash array has 8 independent flash channels, labeled CH0 to CH7, working in parallel. All channels of a flash array always perform the same operation unless one or more channels are masked by certain operations.

[0031] The host sends commands through the message unit and stores these commands in a dedicated command buffer. Figure 3 As shown, after receiving the command, the MCU distributes it to NAC 0-3 and stores the data in the registers and SRAM of the corresponding NAC as required.

[0032] The command buffer is designed with 96 command slots with a total size of 18KB and occupies the full slot regardless of the actual command entry size. The buffer is built on a dual-port SRAM, supporting parallel writing of message units and synchronous reading of CPU0. Since host commands may arrive continuously, the command buffer is managed in a cyclic manner and efficient scheduling is achieved through two FIFOs:

[0033] NAC command slot FIFO: The slot index where management commands are distributed to the NAC.

[0034] Empty command FIFO: Maintains the index of free slots for use by subsequent commands.

[0035] Considering that there are four NACs in the system, four independent NAC command slot FIFOs are set.

[0036] CSI is used to manage the exchange of command table entries and status table entries between MCU and NAC. A 12-level command pool is implemented, which is written by MCU and read by NAC. The command queue is used to specify the exact order of command entries from MCU, and the status entry exchange is completed by the status FIFO.

[0037] The main loop function monitors the hardware status and calls the dispatch function when a new command is detected, executing the following steps:

[0038] Pop CSI: New commands are written into the buffer by the message unit, and the firmware extracts the command information through the read interface of NAC 0-3, processing one request in the FIFO at a time.

[0039] Copy data: Determine the target slot for storing command data based on CSI information, and write the data to the corresponding NAC command pool.

[0040] Distribution to NAC: Command data needs to be coordinated with the hardware and firmware of NAC and stored in registers and SRAM.

[0041] Release CSI: After command distribution is completed, the occupied slot is released, and the register of the empty command FIFO is written to mark the slot as idle.

[0042] Optimize command processing delay

[0043] In order to reduce the processing delay of the MCU, the command dispatch process optimizes the processing of host address (HA) data. Each HA occupies 8 bytes, and each command is associated with up to 14 HAs, requiring a total of 112 bytes of space. When these data are transferred to the SRAM of NAC 0-3, the upper limit of a single transfer is 64 bytes, which needs to be processed in batches.

[0044] In order to improve efficiency, a table lookup method is introduced, which presets the access table through 14 tags (each 8 bytes) and combines the length parameter of the R2 register to achieve fast retrieval. Compared with traditional loop control, this method is more efficient when processing small data blocks (within 112 bytes).

[0045] The NAC command pool consists of two parts: registers and SRAM:

[0046] Register section: holds the main parameters of command entry (excluding HA0-HA14 and OOBA).

[0047] SRAM part: stores HA0-HA14 and OOBA data.

[0048] The command pool is managed by free slot FIFO and completion slot FIFO, both of which are 12 levels deep to ensure no overflow risk in high concurrency situations.

[0049] Ultimately, the collaborative design of the command buffer, FIFO mechanism, and command pool ensures efficient command distribution and stable system operation.

[0050] like Figure 4 As shown in the figure, when using the NAC 0-3 command pool, the first step for the firmware to process a command is to confirm the currently available command slot. By querying the NAC's empty command slot FIFO and reading the specified register, the firmware obtains the index information of the command slot to determine the storage location of the new command data. After completing the data copy, the firmware sends a signal to the NAC through a specific register to indicate that it is ready to execute the command. Each time this register is written, the corresponding slot is locked by the FIFO to ensure that the command enters the execution phase smoothly. After the command execution is completed, the firmware writes the slot index to the completed command pool index register to unlock the slot.

[0051] The operation of the NAC firmware is the opposite of the above process: first, the CPI (command slot index) is popped out from the completion slot FIFO, and then the corresponding command is processed. After the command is executed, the relevant command slot is released by writing the CPI to the empty slot FIFO to free up resources for subsequent command processing.

[0052] Return status processing Figure 5 As shown in the figure, after NAC completes the command execution, it will generate corresponding status information, each status information occupies 8 bytes. This information is first transmitted to the MCU, and then sent to the host by the MCU through DMA. To implement this process, NAC, MCU and host need to configure dedicated storage space for the management of status entries.

[0053] The MCU has a 1KB status buffer inside, which can hold up to 128 status entries. The buffer is designed with dual-port SRAM to support CPU0 write operations and DMAC read operations in parallel. The MCU firmware ensures that the buffer stores status information efficiently in a circular manner to avoid wasting space.

[0054] There is also a state buffer in the host memory, usually located in DRAM, with sufficient capacity to prevent overflow. This buffer is also managed in a circular manner to receive and store state entries.

[0055] The MCU firmware is responsible for extracting status entries from the NAC status FIFO and storing them in the MCU's status buffer. Each time data is read from the NAC status FIFO, a status entry is popped out. When the accumulated number of status entries reaches a preset value, the firmware starts preparing for the transmission of the status frame.

[0056] The length of the status frame is variable, and the request FIFO mechanism is used for efficient management. A maximum of 128 status frames can be accommodated in a 1KB buffer, and the offset address does not need to be stored in the FIFO. By controlling the FIFO head pointer and counter, the status FIFO can be used cyclically, fully optimizing the storage resource utilization and effectively avoiding buffer overflow.

[0057] After the status entries are extracted through the read port registers of the NAC, they are stored in the MCU buffer and assembled into status frames for further transmission to the host.

[0058] Status DMA control: The status frame is transferred to the host via DMA. When starting a DMA transfer, the following three key parameters need to be provided: frame address, frame length, and host status buffer index (HSBI). These parameters are written to the write port register of the status frame request FIFO to trigger the DMA transfer operation.

[0059] When the DMA transfer is completed, the DMA operation status can be checked by reading the read port register of the status frame completion FIFO. If no error occurs, the pop operation of the request FIFO is performed to release the corresponding resources.

[0060] During the push operation of the FIFO, the counter is incremented by 1. When the frame parameters are written to the DMA register and the DMA transfer is started, the frame length is pushed to the end of the array. At the same time, to ensure that the status buffer does not overflow, the system dynamically calculates the available space of the 1KB buffer by subtracting the frame length. The maximum value of the FIFO counter is 128 to ensure the stability of the buffer management.

[0061] In the pop operation of the FIFO, the head pointer moves to the next position and the counter is decremented by 1. When the DMA transfer is completed, the system pops the stored frame length from the array and recalculates the number of bytes available in the buffer. If the head pointer reaches the maximum value of 128, the pop operation will return the head pointer to the starting position, realizing the recycling of the FIFO.

[0062] After the status entry is sent to the host, the MCU generates an interrupt signal to notify the host CPU by writing 0x80000000 to the message signal interrupt (MSI) control and status register. The triggering of this interrupt signal can adopt two merge processing strategies:

[0063] Triggered when the number of status entries reaches the count threshold set by the register;

[0064] Triggered when the time since the latest status entry was added to the status FIFO exceeds the time threshold set by the register.

[0065] The DMA controller handles various transfer types, including inbound and outbound memory read and write requests and the processing of completion packets.

[0066] First, inbound memory read requests are for PCIE memory mapped registers, which are converted by DMAC into completion requests and sent to the arbiter inside DMAC. DMAC TX logic reads register data through DMAC read bus, then encapsulates it in PCIE completion data packet with data, and finally sends it to PCIE EP interface. Inbound memory write requests are directly for memory mapped registers, and DMAC will write data to the target register directly through DMAC write bus.

[0067] For inbound Completion packets with data packets, which are the host's response to outbound memory read requests, the Completion packets must match the pending request or they will be discarded. The destinations of these packets can be NAC0 to NAC3 and the MSG unit command frame FIFOs. The DMAC writes data to these destination locations directly over the DMAC write bus.

[0068] The outbound memory write request is sent to DMAC by NAC0 to NAC3 and MSG unit. A request can process up to 4KB of data, which is called source memory write request. DMAC will read the data sent by the requester through DMAC read bus, and then pack the data into one or more PCIE memory write request packets according to the maximum load size of PCIE, and send these packets to PCIE EP interface. After the transmission is completed, DMAC will return the status to the requester.

[0069] Similarly, NAC0 to NAC3 and MSG units can also send outbound memory read requests to DMAC. These requests are called source memory read requests. DMAC packages these source requests into PCIE memory read request packets, sends them to the PCIE EP interface, and finally returns the request status to the requester. DMAC also manages the number of memory read request packets to avoid PCIE receive buffer overflow. Each pending memory read request will start a timer.

[0070] Finally, after receiving the completion data packet, DMAC will write the returned data to the requester through the DMAC write bus. Since the host may split a read request into multiple completion data packets, DMAC will return the completion status to the requester only after all data of the source request is completed.

[0071] The DMAC is responsible for handling multiple types of transfers, including inbound and outbound memory read and write requests and completing data packet processing. Its specific operations are as follows:

[0072] Inbound memory read request: Inbound memory read requests are for PCIE memory mapped registers. The DMAC converts these requests into completion requests and sends them to the arbiter inside the DMAC. Subsequently, the DMAC TX logic reads the register data through the DMAC read bus, encapsulates it into a PCIE completion packet containing the data, and finally sends it to the PCIE EP interface.

[0073] Inbound memory write request: Inbound memory write request is directly for PCIE memory mapped register. DMAC writes data directly to the target register through DMAC write bus without additional encapsulation processing.

[0074] Inbound Completion Packets: Inbound Completion Packets are the host's response data for outbound memory read requests. These Completion Packets must match the pending memory read request, otherwise they are discarded. The destination may be the command frame FIFO of NAC0 to NAC3 or the MSG unit, and the DMAC writes the data to the specified location through the DMAC write bus.

[0075] Outbound memory write request: Outbound memory write request is issued by NAC0 to NAC3 or MSG unit. Each request processes up to 4KB of data and is called source memory write request. DMAC reads the data of the requester through DMAC read bus, and packages the data into one or more PCIE memory write request packets according to the maximum load size of PCIE, and transmits it to PCIE EP interface. After the transmission is completed, DMAC returns the transmission status to the requester.

[0076] Outbound memory read request: NAC0 to NAC3 or MSG units can also issue source memory read requests, which DMAC encapsulates into PCIE memory read request packets and sends to the PCIE EP interface. DMAC is responsible for managing the number of pending memory read requests to prevent the PCIE receive buffer from overflowing. At the same time, each pending memory read request starts a timer to ensure timely completion.

[0077] Completion Packet Processing: When the DMAC receives a completion packet, it writes the data to the requester through the DMAC write bus. If the host splits a read request into multiple completion packets, the DMAC needs to wait until all packets are transmitted before returning a complete completion status to the requester to ensure data consistency and integrity.

[0078] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A multi-channel flash array controller hardware system and implementation method thereof, characterized in that: The hardware structure of the array controller includes: a. It integrates flash memory controller, random access memory (RAM), PCIE and advanced high-performance bus (AHB) architecture, and can support multi-channel parallel data transmission. The flash array controller converts the formatting command from the host into flash operation, then sends / receives data to the host, and finally reports the status to the host. It contains four flash arrays connected to the flash array controller, and each array has 8 flash channels; b. The message and control unit performs the transmission of command entries and status entries, temperature detection, non-volatile memory (NVM) management, and exception handling. The NAND array controller (NAC) converts the command received from the message and control unit into a flash operation, executes the operation, sends a request to the direct memory access controller (DMAC), and returns the status to the message and control unit; c. Data transmission uses direct memory access (DMA) technology. By expanding the number of channels and bit width of the DMA controller, efficient matching with the flash memory configuration is achieved, thereby improving the transmission rate. The DMA controller receives outbound read / write requests from the on-chip DMA source, receives inbound read / write requests from the PCE EP interface, and converts them into read / write operations of on-chip memory or registers.

2. The message and control unit according to claim 1, characterized in that The message and control unit uses a 32-bit wide AHB data bus inside the system as a transmission channel for core data and commands. The bus is responsible for connecting various functional modules and efficiently completing the distribution and processing of commands to ensure the continuity and stability of data flow.

3. The flash memory array according to claim 1, characterized in that: Each flash array has 8 independent flash channels, labeled CH0 to CH7, working in parallel. All channels of a flash array always perform the same operation unless one or more channels are masked by certain operations. The control signals they receive are the same, but their block and page addresses can be different.

4. The transmission of command items and status items according to claim 2, characterized in that: The command buffer is a dual-port static random access memory (SRAM) with a total of 96 command slots, a total size of 18KB, and each command slot can only accommodate one command entry. It supports the writing of the message unit and the reading of the microcontroller unit (MCU). The command buffer is used in a circular manner and implements the management of the NAC command slot first-in-first-out queue (FIFO) and the empty command FIFO to ensure efficient processing and fast response of commands. The command pool of NAC 0-3 is managed by two FIFOs: the free slot FIFO and the completion slot FIFO, and both are 12 levels deep to avoid overflow and ensure smooth processing of commands.

5. A method for processing array controller status, characterized in that: The following steps are involved: a. The NAND array controller executes the commands in the command pool, converts them into flash operations, notifies the DMAC to transfer data, and finally reports the status to the MCU; b. About 40KB of on-chip dual-port SRAM is integrated on each physical channel and used as a flash page buffer. Both ports can read and write. One port is connected to the DMAC interface with a clock frequency of 62.5MHz, and the other port is connected to the NAC, NAND Flash interface (NFI) and error checking and correction (ECC). When contention occurs, the priority is NFI, ECC and NAC from high to low; c. The Command / Status Interface (CSI) is used to manage the exchange of command table entries and status table entries between the MCU and the NAC. It implements a 12-level command pool, which is written by the MCU and read by the NAC. The command queue is used to specify the exact order of command entries from the MCU. The status entry exchange is completed by the status FIFO.

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