Communication method, device and equipment of FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) in high-voltage direct-hanging energy storage system and medium

Abstract

The invention discloses a communication method, device and equipment for an FPGA and a DSP in a high-voltage direct-hanging energy storage system and a medium, relates to the technical field of energy storage, is applied to an FPAG, the FPGA and the DSP establish communication connection through an external memory interface, and comprises the following steps: determining a target communication state according to a pin signal sent by the DSP; the target communication state is a data reading state or a data writing state; determining a target address according to an address signal sent by the DSP; if the target communication state is a data reading state, transmitting first target data acquired from a local memory based on the target address to the DSP; if the target communication state is a data writing state, writing second target data sent by the DSP into a local target address; in the communication process of the FPGA and the DSP, the communication time sequence is controlled through a state switching mode which is configured by the target state machine and corresponds to the current communication mode; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

Description

Technical Field

[0001] The present invention relates to the field of energy storage technology, and in particular to a communication method, device, equipment and medium between FPGA and DSP in a high-voltage direct-mounted energy storage system. Background Art

[0002] The high-voltage direct-mounted energy storage system is an advanced energy storage technology that allows the battery energy storage system to be directly connected to the grid at a high-voltage level, thereby reducing the steps and associated losses of energy conversion. This technology typically involves the use of high-voltage switchgear and battery modules that are directly connected to the grid without the need for a traditional step-up transformer. By eliminating the step-up transformer, the structure of the high-voltage direct-mounted energy storage system is simpler, which helps to improve the overall efficiency and reliability of the system. Operating directly at the high-voltage level allows for faster charging and discharging responses, which is very important for real-time regulation of the grid. The high-voltage direct-mounted energy storage system is able to provide fast charging and discharging capabilities and is suitable for a variety of application scenarios such as peak shaving, frequency regulation, and backup power supply for the grid. Due to the reduction in energy conversion steps, the operating efficiency of the system is improved, which can reduce operation and maintenance costs in the long run.

[0003] FPGA (Field-Programmable Gate Array) is a programmable logic device that allows users to reconfigure its internal logic structure at the hardware level. In high-voltage direct-mounted energy storage systems, the parallel processing capabilities of FPGAs make them very suitable for fast data processing tasks in high-voltage direct-mounted energy storage systems, such as power quality control, status monitoring, and protection functions.

[0004] At present, in high-voltage direct-mounted energy storage systems, FPGA and DSP (Digital Signal Processor) are often needed to form a control board, and the communication between the two also faces many technical difficulties. FPGA and DSP usually need to exchange data and transmit control instructions in high-voltage direct-mounted energy storage systems. Due to its programmability and high-speed processing capabilities, FPGA is often used to execute complex control algorithms and real-time data processing, while DSP is good at performing digital signal processing tasks. The communication between the two is crucial to the performance of the entire system. At present, DSP and FPGA are mostly connected through high-speed serial bus protocols (Serial RapidIO, SRIO) or general purpose input / output ports (General Purpose Input / Output, GPIO).

[0005] However, since the energy storage system needs to process a large amount of data, the communication interface between FPGA and DSP is required to support high-speed and large-scale data transmission to avoid the bottleneck effect existing in existing solutions.

[0006] In summary, in high-voltage direct-mounted energy storage systems, how to achieve high-speed and large-volume data transmission between FPGA and DSP is a problem that needs to be solved. Summary of the invention

[0007] In view of this, the purpose of the present invention is to provide a communication method, device, equipment and medium between FPGA and DSP in a high-voltage direct-mounted energy storage system, which can realize high-speed and large-volume data transmission between the FPGA and DSP in the high-voltage direct-mounted energy storage system. The specific scheme is as follows:

[0008] In the first aspect, the present application discloses a communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system, which is applied to FPAG, wherein a communication connection is established between the FPGA and DSP via an external memory interface, and the method comprises:

[0009] Acquire the pin signal sent by the DSP, and determine the target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state;

[0010] Acquire the address signal sent by the DSP, and determine the target address according to the address signal;

[0011] If the target communication state is a data reading state, obtaining pre-stored first target data from a local memory based on the target address, and transmitting the first target data to the DSP;

[0012] If the target communication state is a data writing state, obtaining the second target data sent by the DSP, and writing the second target data into the local target address;

[0013] Wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

[0014] Optionally, the communication method between FPGA and DSP in the high-voltage direct-mounted energy storage system further includes:

[0015] If the current communication mode is asynchronous parallel communication, the target state machine is used to configure a first state switching mode corresponding to the asynchronous parallel communication; the state types in the first state switching mode include a read state, a write state and an idle state;

[0016] If the current communication mode is synchronous parallel communication, the target state machine is used to configure a second state switching mode corresponding to the synchronous parallel communication; the state types in the second state switching mode include idle state, read row address state, read column address state, read state, write row address state, write column address state and write state.

[0017] Optionally, determining the target communication state according to the pin signal includes:

[0018] If the pin signal is used to indicate that the read enable pin is at a low level, the target communication state is determined to be a data read state; if the pin signal is used to indicate that the write enable pin is at a low level, the target communication state is determined to be a data write state.

[0019] Optionally, if the current communication mode is asynchronous parallel communication, the communication method between FPGA and DSP in the high-voltage direct-mounted energy storage system further includes:

[0020] After determining that the target communication state is a data reading state, switching the current state from an idle state to a reading state, and after transmitting the first target data to the DSP, switching the current state from the reading state to an idle state;

[0021] After determining that the target communication state is the data writing state, the current state is switched from the idle state to the writing state, and after writing the second target data to the local target address, the current state is switched from the writing state to the idle state.

[0022] Optionally, if the current communication mode is synchronous parallel communication, the address signal includes a first address signal for indicating that the row address enable pin is at a low level and a second address signal for indicating that the column address enable pin signal is at a low level;

[0023] Accordingly, the step of acquiring the address signal sent by the DSP and determining the target address according to the address signal includes:

[0024] Acquire the first address signal sent by the DSP, and determine the target row address according to the first address signal, acquire the second address signal sent by the DSP, and determine the target column address according to the second address signal;

[0025] A target address is determined based on the target row address and the target column address.

[0026] Optionally, if the current communication mode is asynchronous parallel communication, the communication method between FPGA and DSP in the high-voltage direct-mounted energy storage system further includes:

[0027] If it is determined that the target communication state is a data reading state, then after determining the target row address according to the first address signal, the current state is switched from the idle state to the read row address state, and after determining the target column address according to the second address signal, the current state is switched from the read row address state to the read column address state, and then the current state is switched from the read column address state to the read state, so as to perform the step of transmitting the first target data to the DSP, and after the transmission is completed, the current state is switched from the read state to the idle state;

[0028] If the target communication state is determined to be a data writing state, then after the target row address is determined according to the first address signal, the current state is switched from the idle state to the write row address state, and after the target column address is determined according to the second address signal, the current state is switched from the write row address state to the write column address state, and then the current state is switched from the write column address state to the write state, so as to execute the step of writing the second target data to the local target address, and after the writing is completed, the current state is switched from the write state to the idle state.

[0029] Optionally, the communication method between FPGA and DSP in the high-voltage direct-mounted energy storage system further includes:

[0030] Acquire data to be transmitted in advance; wherein the data to be transmitted includes phase current of the three-phase circuit and voltage, charge state and fault signal of each energy storage unit;

[0031] The data to be transmitted is converted into binary data, and the binary data is stored in a local memory.

[0032] In the second aspect, the present application discloses a communication device between FPGA and DSP in a high-voltage direct-mounted energy storage system, which is applied to FPAG. The FPGA and DSP establish a communication connection through an external memory interface. The device includes:

[0033] A pin signal acquisition module, used to acquire the pin signal sent by the DSP, and determine the target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state;

[0034] An address signal acquisition module, used to acquire the address signal sent by the DSP and determine the target address according to the address signal;

[0035] A data reading module, configured to obtain pre-stored first target data from a local memory based on the target address if the target communication state is a data reading state, and transmit the first target data to the DSP;

[0036] A data writing module, used for obtaining the second target data sent by the DSP and writing the second target data into the local target address if the target communication state is the data writing state;

[0037] Wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

[0038] In a third aspect, the present application discloses an electronic device, comprising:

[0039] Memory, used to store computer programs;

[0040] The processor is used to execute the computer program to implement the steps of the communication method between FPGA and DSP in the above-mentioned high-voltage direct-mounted energy storage system.

[0041] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the communication method between FPGA and DSP in the aforementioned high-voltage direct-mounted energy storage system are implemented.

[0042] It can be seen that the present application discloses a communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system, which is applied to FPAG, and a communication connection is established between the FPGA and the DSP through an external memory interface. The method includes: obtaining a pin signal sent by the DSP, and determining a target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state; obtaining an address signal sent by the DSP, and determining a target address according to the address signal; if the target communication state is a data reading state, obtaining a pre-stored first target data from a local memory based on the target address, and transmitting the first target data to the DSP; if the target communication state is a data writing state, obtaining a second target data sent by the DSP, and writing the second target data to the local target address; wherein, in the communication process between the FPGA and the DSP, the communication timing is controlled by using a state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

[0043] Beneficial effect: In this application, an external memory interface is used to establish a communication connection between the FPGA and the DSP to realize parallel communication transmission between the FPGA and the DSP, and the external memory interface supports high-speed data transmission, which is more suitable for the rapid transmission of large amounts of data. At the same time, the EMIF interface allows the timing parameters to be adjusted according to different external devices to optimize performance and compatibility. First, according to the pin signal sent by the DSP, it is determined whether the target communication state is a data read state or a data write state, and then the target address is determined according to the address signal sent by the DSP. If the target communication state is a data read state, the first target data pre-stored from the local memory based on the target address is transmitted to the DSP, that is, the local memory pre-stores the data that needs to be sent to the DSP, which can avoid the complex frame structure and function code in the communication protocol, that is, it can bypass the communication protocol to achieve rapid data transmission. If the target communication state is a data write state, the second target data sent by the DSP is obtained, and the second target data is written to the local target address. It should be pointed out that in the communication process between the above-mentioned FPGA and DSP, the state switching mode corresponding to the current communication mode configured by the target state machine needs to be used to control the communication timing. By using the state machine in the communication process between the FPGA and DSP, it is helpful to reduce errors and improve the robustness of the system. In addition, the present application supports both asynchronous parallel communication and synchronous parallel communication. For different communication modes, the state switching mode configured by the state machine is also different. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0045] Figure 1 A flow chart of a communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system disclosed in this application;

[0046] Figure 2 This is a schematic diagram of the structure of a communication device between FPGA and DSP in a high-voltage direct-mounted energy storage system disclosed in this application;

[0047] Figure 3 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] At present, in high-voltage direct-mounted energy storage systems, FPGA and DSP are often required to form control boards, and the communication between the two also faces many technical difficulties. FPGA and DSP usually need to exchange data and transmit control instructions in high-voltage direct-mounted energy storage systems. Due to its programmability and high-speed processing capabilities, FPGA is often used to execute complex control algorithms and real-time data processing, while DSP is good at performing digital signal processing tasks. The communication between the two is crucial to the performance of the entire system. At present, DSP and FPGA are mostly connected through high-speed serial bus protocols or general input and output ports. However, since the energy storage system needs to process a large amount of data, this requires that the communication interface between FPGA and DSP can support high-speed and large-scale data transmission to avoid the bottleneck effect existing in existing solutions.

[0050] To this end, the embodiments of the present application disclose a communication method, device, equipment and medium between FPGA and DSP in a high-voltage direct-mounted energy storage system, which can realize high-speed and large-scale data transmission between the FPGA and DSP in the high-voltage direct-mounted energy storage system.

[0051] See also Figure 1 As shown, the embodiment of the present application discloses a communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system, which is applied to FPAG. The FPGA and DSP establish a communication connection through an external memory interface. The method includes:

[0052] Step S11: acquiring a pin signal sent by the DSP, and determining a target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state.

[0053] In this embodiment, FPGA and DSP are used as the communication parties to build a basic high-voltage direct hanging system. Among them, FPGA is good at realizing highly parallel processing tasks and is suitable for executing data-intensive and computation-intensive algorithms, which enables FPGA to quickly process large amounts of data and is suitable for key applications such as high-speed data transmission and signal processing. In addition, FPGA provides reconfigurable hardware logic, which means that they can be customized according to different application requirements, providing extremely high flexibility and reconfigurability. DSP usually has efficient floating-point computing capabilities and is suitable for processing tasks that require high-precision calculations, such as fast Fourier transforms, digital filters, modulation and demodulation, etc. The power consumption of DSP chips is relatively low, which is suitable for portable or battery-powered applications, and helps to extend the battery life of the system.

[0054] By combining the advantages of FPGA and DSP, resource usage can be optimized at different processing stages. For example, FPGA can handle low-level signal preprocessing with large data volume and simple structure, while DSP can handle high-level algorithms with complex control structure. The current connection method between FPGA and DSP can vary according to specific application requirements and hardware platforms. In the connection between DSP and FPGA, the following types of physical interfaces are usually used to achieve data communication, including but not limited to: General Purpose Input / Output (GPIO), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), High-speed Serial Bus Protocol (Serial RapidIO, SRIO), etc. In this application, an external memory interface is used to establish a communication connection between FPGA and DSP to realize parallel communication transmission between FPGA and DSP. Compared with GPIO, SPI, and UART interfaces, EMIF interface supports high-speed data transmission and is more suitable for the rapid transmission of large amounts of data. At the same time, EMIF interface allows timing parameters to be adjusted according to different external devices to optimize performance and compatibility.

[0055] It should be pointed out that in the high-voltage direct-mounted energy storage system, the contents that need to be transmitted between the FPGA and the DSP include: the phase current of the three-phase circuit, the voltage of each energy storage unit, the state of charge SOC of each energy storage unit, the modulation wave associated with controlling the thyristor switch of each energy storage unit, and various fault signals and control parameters. The DSP reads the three-phase phase current, fault signal, voltage of each energy storage unit and the state of charge SOC of each energy storage unit from the FPGA, and then generates the modulation wave based on this information, and then sends the modulation wave and other control parameters to the FPGA. In addition, due to its programmability and high-speed processing capabilities, FPGA is often used to execute complex control algorithms and real-time data processing, while DSP is good at executing digital signal processing tasks. Therefore, for digital signal processing tasks involving FPGA local, the execution speed of "using FPGA to perform digital signal processing and output results" and "transmitting digital signal processing tasks to DSP, and outputting results after DSP processing" can be measured, and the solution with faster actual execution speed is finally taken. Similarly, if the DSP local involves executing complex control algorithms and real-time data processing, the same decision is made. In this way, in high-voltage direct-mounted energy storage systems, the combination of FPGA and DSP can give full play to their respective advantages and provide high-performance, low-power, flexible and programmable communication solutions that are suitable for a variety of complex communication and signal processing application scenarios.

[0056] In this embodiment, when the DSP needs these data to generate a modulated wave, the DSP will send a pin signal to enable the FPGA to send data to the DSP. After the DSP generates a modulated wave, it will also send a corresponding pin signal to enable the FPGA to receive the modulated wave data sent by the DSP. Therefore, in this embodiment, the FPGA will first determine whether the target communication state is a data reading state or a data writing state according to the pin signal sent by the DSP.

[0057] In a specific implementation, the above-mentioned determination of the target communication state according to the pin signal includes: if the pin signal is used to characterize that the read enable pin is at a low level, then the target communication state is determined to be a data reading state, and if the pin signal is used to characterize that the write enable pin is at a low level, then the target communication state is determined to be a data writing state. First of all, it should be pointed out that a read enable pin and a write enable pin are connected between the DSP and the FPGA. If the DSP sets the read enable pin connected to the FPGA to a low level and the write enable pin to a high level, the current target communication state of the FPGA is a data reading state. If the DSP sets the write enable pin connected to the FPGA to a low level and the read enable pin to a high level, the current target communication state of the FPGA is a data writing state.

[0058] Step S12: Acquire the address signal sent by the DSP, and determine the target address according to the address signal.

[0059] In this embodiment, the FPGA will further determine the target address according to the address signal sent by the DSP. It is understandable that there are 11-bit address lines and 16-bit data lines connected between the DSP and the FPGA, and the FPGA will determine the target address according to the address signal given by the 11-bit address line of the DSP.

[0060] In addition, if the current communication mode is synchronous parallel communication, the address signal includes a first address signal for characterizing that the row address enable pin is at a low level and a second address signal for characterizing that the column address enable pin signal is at a low level; accordingly, obtaining the address signal sent by the DSP and determining the target address based on the address signal includes: obtaining the first address signal sent by the DSP and determining the target row address based on the first address signal, obtaining the second address signal sent by the DSP and determining the target column address based on the second address signal; determining the target address based on the target row address and the target column address.

[0061] It should be pointed out that if the communication mode between DSP and FPGA is synchronous parallel communication, there are row address enable pins and column address enable pins connected between DSP and FPGA. Therefore, in synchronous parallel communication mode, DSP will first pull down the row address enable pin and give the target row address on the 11-bit address line. At the next clock rising edge, DSP will pull down the column address enable pin and give the target column address on the 11-bit address line. FPGA thus determines the target address based on the target row address and target column address.

[0062] Step S13: If the target communication state is a data reading state, first target data stored in advance is acquired from a local memory based on the target address, and the first target data is transmitted to the DSP.

[0063] In this embodiment, if the target communication state is a data reading state, the pre-stored first target data obtained from the local memory based on the target address is sent to the pin connected to the 16-bit data line for the DSP to read, thereby realizing data transmission. That is, the local memory pre-stores data that needs to be sent to the DSP, which can avoid the complex frame structure and function code in the communication protocol, that is, it can bypass the communication protocol to realize fast data transmission.

[0064] Further, the above method also includes: pre-acquiring data to be transmitted; wherein the data to be transmitted includes the phase current of the three-phase circuit and the voltage, state of charge and fault signal of each energy storage unit; converting the data to be transmitted into binary data, and storing the binary data in local memory. That is, the embodiment of the present application will pre-acquire the data to be transmitted to the DSP, which may specifically include but is not limited to the phase current of the three-phase circuit and the voltage, state of charge and fault signal of each energy storage unit, and then the present application will convert these data into binary data first, and temporarily store the high and low levels of the converted binary data in the form of signals in the local memory, so that the FPGA acts as a transfer station in the energy storage system. In this way, when the corresponding signal is received, the internal temporarily stored level signal is directly assigned to the corresponding output pin, and this construction method can avoid the complex frame structure and function code in the communication protocol. And because the DSP and FPGA are close to each other in the control board of the energy storage system and are not easily affected by interference signals, it meets the requirements of the energy storage system for real-time control of a large amount of data, immediate storage and use, and no need for long-term storage.

[0065] Step S14: If the target communication state is a data writing state, the second target data sent by the DSP is obtained, and the second target data is written into the local target address; wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

[0066] In this embodiment, if the target communication state is the data writing state, the second target data sent by the DSP to the 16-bit data line is acquired, and the second target data is written into the local target address.

[0067] It should be pointed out that in the communication process between the above-mentioned FPGA and DSP, the state switching mode corresponding to the current communication mode configured by the target state machine needs to be used to control the communication timing. By using the state machine in the communication process between the FPGA and DSP, it is helpful to reduce errors and improve the robustness of the system. In addition, the present application supports both asynchronous parallel communication and synchronous parallel communication. For different communication modes, the state switching mode configured by the state machine is also different.

[0068] In FPGA design, state machine is a commonly used control logic structure that describes and manages the behavior of the system through discrete states. The state is the core of the state machine, which represents the condition or behavior of the system at a certain point in time. The state can be explicit or implicit, depending on the type of state machine. State transition defines the rules for the state machine to move from the current state to the next state under certain conditions, which are usually triggered by input signals or internal timing events. The input signal is an external event or data that triggers the state transition. In the design of the state machine, the input signal is closely related to the state transition and output. The output is the signal generated by the state machine based on the current state or state transition. The output can be a direct product of combinational logic or a signal based on timing. The state register is used to store the current state and update it to the next state at the appropriate edge of each clock cycle. State encoding is a numerical representation of the state. Common encoding methods include binary encoding, Gray code encoding, and one-hot encoding. The encoding method will affect the design complexity and performance of the state machine. In the implementation of the state machine, the state transition logic is usually combinational logic, while the update of the state register is sequential logic. The basic function of a state machine is to control and coordinate the behavior of a system to ensure that the system operates in a predetermined order and logic. Specifically, a state machine can decompose a complex control process into a series of simple states, each of which performs a specific task or operation. Based on the input signal and the current state, the state machine can make decisions and change the state accordingly to adapt to changes in the external environment or internal conditions. The state machine is usually synchronized with the clock signal to ensure the consistency of the state and the timing accuracy of the system. Through reasonable state encoding and design, the state machine can effectively utilize the logic resources inside the FPGA, such as lookup tables (LUTs) and flip-flops (FFs).

[0069] For example, when the state machine is in a certain state, LUTs can determine the next state based on the current state and input signals, which is usually achieved by writing a truth table that lists all possible input combinations and their corresponding outputs. Then, the FPGA development tool automatically maps this truth table into LUTs. In the state machine, FFs are used to store the current state. Each state machine has one or more state registers, which are usually composed of FFs. At the rising or falling edge of the clock signal, the FFs update their stored values ​​to achieve state switching. For example, in a simple two-state machine, one FF can be used to store the current state (0 or 1), while the other FF can be used to store the next state. This helps to implement complex communication functions under resource constraints. The design of state machines usually follows a structured approach, which makes the design easy to understand and maintain. The clear separation of state machines can simplify the debugging process and facilitate subsequent functional expansion or modification. In FPGA design, state machines can integrate error detection logic to ensure the reliability of the communication process. When an error is detected, the state machine can take recovery measures, such as resetting to a safe state, to ensure the stable operation of the system. State machines are particularly suitable for implementing complex control logic, such as communication protocol state management, data packet processing and forwarding, etc., which is particularly important for building high-performance communication systems.

[0070] In a specific embodiment, the above method also includes: if the current communication mode is asynchronous parallel communication, the target state machine is used to configure a first state switching mode corresponding to the asynchronous parallel communication; the state types in the first state switching mode include a read state, a write state, and an idle state; if the current communication mode is synchronous parallel communication, the target state machine is used to configure a second state switching mode corresponding to the synchronous parallel communication; the state types in the second state switching mode include an idle state, a read row address state, a read column address state, a read state, a write row address state, a write column address state, and a write state.

[0071] That is, for asynchronous parallel communication, FPGA only needs to set three states: read state, write state and idle state. For synchronous parallel communication, FPGA needs to set seven states: idle state, read row address state, read column address state, read state, write row address state, write column address state and write state.

[0072] Among them, the design and implementation of the state machine usually follows the "three-segment" structure. The three parts of the segment state machine usually include: 1. State Register: This part uses sequential logic to describe the state update. 2. Next State Logic: This part uses combinational logic to describe the state transfer. Usually in a separate process block, the next state is calculated based on the current state and the input signal. 3. Output Logic: This part uses combinational logic or sequential logic to describe the output of the state machine. Usually in a separate process block, the output signal is calculated based on the current state. For example, in the asynchronous parallel communication method mainly used in high-voltage direct-mounted energy storage systems, the state register refreshes the current state at each clock rising edge, and selects a state from read, write, and idle to assign to the current state. The next state logic will determine what the state should be when the next clock rising edge arrives. For example, when the FPGA is in the idle state, if the read and write enable pins are not active, the next state logic will determine that the next state is still idle. If there is an enable pin action, the next state logic will determine whether to read or write in the next state according to the pin that is active. The output logic is used to calculate the output signal, for example, output the corresponding data according to the content of the address line. This structure separates the state register, state transfer logic and output logic, which helps to improve the readability of the code and the optimization ability of the synthesizer.

[0073] In addition, the parallel processing capability of FPGA allows the state machine to process multiple input events in a single clock cycle, which can significantly improve the processing speed and throughput of the communication system. Specifically, FPGA can burn multiple program modules at one time and set whether the program modules need to be associated. If you want to transmit information between program modules, you can do so by setting intermediate signals. If you do not want multiple input programs to interfere with each other, just do not set intermediate signals. For example, there are three different communication methods in the high-voltage direct-mounted energy storage system. When the intermediate signals are not set, they can be executed simultaneously in the same FPGA without interfering with each other. The state machine can be designed as a hard real-time system to ensure that state transitions and data processing are completed within strict time constraints, which is crucial for the correct execution of the communication protocol. The programmability provided by FPGA allows designers to quickly adjust the logic of the state machine according to different communication standards or protocols, which improves the flexibility and reusability of the design. Through the state machine logic optimized specifically for communication tasks, unnecessary calculations and resource usage can be reduced, thereby reducing the power consumption of the system.

[0074] In a specific implementation, if the current communication mode is asynchronous parallel communication, the above method also includes: after determining that the target communication state is a data reading state, switching the current state from an idle state to a reading state, and after transmitting the first target data to the DSP, switching the current state from a reading state to an idle state; after determining that the target communication state is a data writing state, switching the current state from an idle state to a writing state, and after writing the second target data to the local target address, switching the current state from a writing state to an idle state.

[0075] That is, the FPGA is initially in an idle state. When the DSP enable pin is activated, the FPGA chooses to switch to the read state or the write state according to whether the pin set low by the DSP is a read enable pin or a write enable pin. When entering the read state, the FPGA will take out the data of the corresponding address according to the address given by the 11-bit address line of the DSP and put it on the pin connected to the 16 data lines for the DSP to read; when entering the write state, the FPGA will write the data on the 16 data lines to the address given by the 11-bit address line of the DSP. After the read or write is completed, the FPGA returns to the idle state. In this process, the FPGA can only enter the other two states from the idle state, and return to the idle state after completing the read and write operations. It cannot enter the write state from the read state, or enter the read state from the write state. For the DSP, the idle state corresponds to the setup time and hold time when the DSP transmits data, and the read and write states correspond to the effective time of the DSP. In this application, the setup time set by the DSP: effective time: hold time = 1:5:1.

[0076] In a specific embodiment, if the current communication mode is asynchronous parallel communication, it also includes: if the target communication state is determined to be a data read state, then after the target row address is determined according to the first address signal, the current state is switched from an idle state to a read row address state, and after the target column address is determined according to the second address signal, the current state is switched from a read row address state to a read column address state, and then the current state is switched from a read column address state to a read state, so as to execute the step of transmitting the first target data to the DSP, and after the transmission is completed, the current state is switched from a read state to an idle state; if the target communication state is determined to be a data write state, then after the target row address is determined according to the first address signal, the current state is switched from an idle state to a write row address state, and after the target column address is determined according to the second address signal, the current state is switched from a write row address state to a write column address state, and then the current state is switched from a write column address state to a write state, so as to execute the step of writing the second target data to the local target address, and after the writing is completed, the current state is switched from a write state to an idle state.

[0077] That is, the FPGA is initially set to the idle state. When the first clock rising edge arrives, the DSP enables the pin, and the FPGA determines whether the current target communication state is the data reading state or the data writing state according to whether the pin set low by the DSP is the read enable or the write enable; when the second clock rising edge arrives, the DSP will pull down the row address enable line, and the FPGA switches to the read / write row address state, and the address on the 11 address lines is read / written as the row address; when the third clock rising edge arrives, the DSP will pull down the column address enable line, and the FPGA switches to the read / write column address state, and the address on the 11 address lines is read / written as the column address; when the fourth clock rising edge arrives, the FPGA switches to the read / write state to put the data of the corresponding address on the pin connected to the 16 data lines for the DSP to read, or write the data on the 16 data lines to the corresponding address, and switches to the idle state after the reading / sending is completed. Similarly, the state of the FPGA can only change in the order of "idle-read row address-read column address-read data-idle" or "idle-write row address-write column address-write data-idle".

[0078] It can be seen that in this application, an external memory interface is used to establish a communication connection between the FPGA and the DSP to realize parallel communication transmission between the FPGA and the DSP, and the external memory interface supports high-speed data transmission, which is more suitable for the rapid transmission of large amounts of data. At the same time, the EMIF interface allows the timing parameters to be adjusted according to different external devices to optimize performance and compatibility. First, according to the pin signal sent by the DSP, it is determined whether the target communication state is a data read state or a data write state, and then the target address is determined according to the address signal sent by the DSP. If the target communication state is a data read state, the first target data pre-stored from the local memory based on the target address is transmitted to the DSP, that is, the local memory pre-stores the data that needs to be sent to the DSP, which can avoid the complex frame structure and function code in the communication protocol, that is, it can bypass the communication protocol to achieve rapid data transmission. If the target communication state is a data write state, the second target data sent by the DSP is obtained, and the second target data is written to the local target address. It should be pointed out that in the communication process between the above-mentioned FPGA and DSP, the state switching mode corresponding to the current communication mode configured by the target state machine needs to be used to control the communication timing. By using the state machine in the communication process between the FPGA and DSP, it is helpful to reduce errors and improve the robustness of the system. In addition, the present application supports both asynchronous parallel communication and synchronous parallel communication. For different communication modes, the state switching mode configured by the state machine is also different.

[0079] In addition, although FPGA and DSP in the energy storage system mainly use asynchronous parallel communication and synchronous parallel communication, there is also an asynchronous serial communication part.

[0080] For asynchronous serial communication, FPGA needs to set five states: idle, start, receive / send, stop, and clear. FPGA is initially set to idle state. At the same time, it is necessary to define the data frame structure and set the frequency division number according to the UART communication protocol. The transmission time of each bit of data = frequency division number * time of one clock cycle. When no data is transmitted, a single data line is always at a high level; when data needs to be transmitted, if FPGA is the sender, FPGA will start to output a low level as the start bit. The frame structure specified by UART in this application is 1 start bit, 8 data bits, and 1 stop bit, and no check bit is set in the transmission data frame.

[0081] If the FPGA is used as the receiver of asynchronous serial communication, when the receiving end receives a low-level signal, the FPGA switches from the idle state to the start state; in the start state, the FPGA detects the start bit of the transmitted data. When the low-level signal is maintained for a sufficiently long number of clocks, it is considered that the start bit is correct and the FPGA switches to the receiving state; in the receiving state, the FPGA counts each rising edge of the clock. When the count is equal to the division number -1, the FPGA stores one bit of data on the current data line in the internal signal, then clears the counter and starts counting from 0 again, repeating the cycle until all 8 bits of data are received. After receiving all the data bits, the FPGA switches to the stop state; in the stop state, the FPGA clears the previous count, transmits the received data to where it is needed, and switches to the idle state when the next rising edge of the clock arrives.

[0082] If the FPGA is used as the sender of asynchronous serial communication, when data needs to be sent, the FPGA switches from the idle state to the start state; in the start state, the FPGA sends the start bit, allowing the low-level signal to continue for the transmission time of one bit of data, and then the FPGA switches to the sending state; in the sending state, the FPGA will send the first bit of data and count each rising edge of the clock. When the count is equal to the division number -1, the FPGA will send the next bit of data, then clear the counter, and start counting from 0 again, repeating the cycle until all 8 bits of data are sent. After the FPGA has sent all the data bits, it switches to the stop state; in the stop state, the FPGA sends a high-level signal that continues for the transmission time of one bit of data, forming a stop bit in a frame of data, and switches to the idle state when the next rising edge of the clock arrives.

[0083] In addition, in addition to high-speed data transmission, the challenges faced by FPGA and DSP communication also include real-time requirements: the control algorithm of the energy storage system often requires real-time response, which means that the communication between the FPGA and DSP must have low latency characteristics; electromagnetic compatibility: in a high-voltage environment, electromagnetic interference may affect the integrity of the communication signal, so measures need to be taken to ensure the robustness of the communication; system complexity: a high-voltage direct-mounted energy storage system may contain multiple FPGAs and DSPs, as well as other electronic components, which increases the complexity of system design, especially in terms of communication protocols and interface design; thermal management: high-speed communication may cause the equipment to heat up, and an effective thermal management strategy is required to maintain the stable operation of the system; synchronization of software and hardware: the programmability of FPGA requires that the software configuration be closely synchronized with the hardware logic, which is a challenge when designing the communication interface.

[0084] For real-time requirements, in order to achieve low latency in the energy storage system, a phase-locked loop (PLL) can be used in the FPGA and DSP communication modules to increase the clock frequency of this module to 100MHz, thereby reducing latency while keeping the number of clocks required unchanged. For electromagnetic compatibility, in order to cope with electromagnetic interference in high-voltage environments, the DSP and FPGA are placed on the same circuit board, and the connection distance between the two is shortened as much as possible to minimize the electromagnetic interference received by the communication between the two. For system complexity, the board is currently determined to be an FPGA with two DSPs, one of which is used to process various calculations and digital signals, and the other is used for observation via an external network port; for thermal management, in order to prevent local overheating of the system from affecting performance or even causing safety hazards, we have equipped the energy storage system with an air conditioning system to keep the internal temperature constant; for software and hardware synchronization, in order to solve the problem of software and hardware synchronization, all components on the control board use the control board's master clock uniformly, and when the software calls the phase-locked loop for frequency multiplication and frequency division operations, no phase difference is allowed.

[0085] See also Figure 2 As shown, the embodiment of the present application discloses a communication device between FPGA and DSP in a high-voltage direct-mounted energy storage system, which is applied to FPAG. The FPGA and DSP establish a communication connection through an external memory interface. The device includes:

[0086] The pin signal acquisition module 11 is used to acquire the pin signal sent by the DSP and determine the target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state;

[0087] An address signal acquisition module 12, used to acquire the address signal sent by the DSP and determine the target address according to the address signal;

[0088] A data reading module 13, configured to obtain pre-stored first target data from a local memory based on the target address if the target communication state is a data reading state, and transmit the first target data to the DSP;

[0089] A data writing module 14 is used for acquiring the second target data sent by the DSP and writing the second target data into the local target address if the target communication state is a data writing state;

[0090] Wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

[0091] It can be seen that in this application, an external memory interface is used to establish a communication connection between the FPGA and the DSP to realize parallel communication transmission between the FPGA and the DSP, and the external memory interface supports high-speed data transmission, which is more suitable for the rapid transmission of large amounts of data. At the same time, the EMIF interface allows the timing parameters to be adjusted according to different external devices to optimize performance and compatibility. First, according to the pin signal sent by the DSP, it is determined whether the target communication state is a data read state or a data write state, and then the target address is determined according to the address signal sent by the DSP. If the target communication state is a data read state, the first target data pre-stored from the local memory based on the target address is transmitted to the DSP, that is, the local memory pre-stores the data that needs to be sent to the DSP, which can avoid the complex frame structure and function code in the communication protocol, that is, it can bypass the communication protocol to achieve rapid data transmission. If the target communication state is a data write state, the second target data sent by the DSP is obtained, and the second target data is written to the local target address. It should be pointed out that in the communication process between the above-mentioned FPGA and DSP, the state switching mode corresponding to the current communication mode configured by the target state machine needs to be used to control the communication timing. By using the state machine in the communication process between the FPGA and DSP, it is helpful to reduce errors and improve the robustness of the system. In addition, the present application supports both asynchronous parallel communication and synchronous parallel communication. For different communication modes, the state switching mode configured by the state machine is also different.

[0092] Figure 3A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system performed by an electronic device disclosed in any of the aforementioned embodiments.

[0093] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0094] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0095] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0096] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the communication method between FPGA and DSP in the high-voltage direct-mounted energy storage system executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0097] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the communication method steps between FPGA and DSP in a high-voltage direct-mounted energy storage system disclosed in any of the aforementioned embodiments are implemented.

[0098] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0099] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0100] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0101] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0102] The above is a detailed introduction to the communication method, device, equipment and storage medium between FPGA and DSP in a high-voltage direct-mounted energy storage system provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system, characterized in that: Applied to FPAG, the FPGA and DSP establish a communication connection through an external memory interface, and the method includes: Acquire the pin signal sent by the DSP, and determine the target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state; Acquire the address signal sent by the DSP, and determine the target address according to the address signal; If the target communication state is a data reading state, obtaining pre-stored first target data from a local memory based on the target address, and transmitting the first target data to the DSP; If the target communication state is a data writing state, obtaining the second target data sent by the DSP, and writing the second target data into the local target address; Wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

2. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to claim 1, characterized in that: Also includes: If the current communication mode is asynchronous parallel communication, configuring a first state switching mode corresponding to the asynchronous parallel communication using the target state machine; The state types in the first state switching mode include a read state, a write state and an idle state; If the current communication mode is synchronous parallel communication, the target state machine is used to configure a second state switching mode corresponding to the synchronous parallel communication; the state types in the second state switching mode include idle state, read row address state, read column address state, read state, write row address state, write column address state and write state.

3. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to claim 2, characterized in that: The determining the target communication state according to the pin signal comprises: If the pin signal is used to indicate that the read enable pin is at a low level, the target communication state is determined to be a data read state; if the pin signal is used to indicate that the write enable pin is at a low level, the target communication state is determined to be a data write state.

4. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to claim 3 is characterized in that: If the current communication mode is asynchronous parallel communication, it also includes: After determining that the target communication state is a data reading state, switching the current state from an idle state to a reading state, and after transmitting the first target data to the DSP, switching the current state from the reading state to an idle state; After determining that the target communication state is the data writing state, the current state is switched from the idle state to the writing state, and after writing the second target data to the local target address, the current state is switched from the writing state to the idle state.

5. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to claim 3, characterized in that: If the current communication mode is synchronous parallel communication, the address signal includes a first address signal for indicating that the row address enable pin is at a low level and a second address signal for indicating that the column address enable pin signal is at a low level; Accordingly, the step of acquiring the address signal sent by the DSP and determining the target address according to the address signal includes: Acquire the first address signal sent by the DSP, and determine the target row address according to the first address signal, acquire the second address signal sent by the DSP, and determine the target column address according to the second address signal; A target address is determined based on the target row address and the target column address.

6. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to claim 5, characterized in that: If the current communication mode is asynchronous parallel communication, it also includes: If it is determined that the target communication state is a data reading state, then after determining the target row address according to the first address signal, the current state is switched from the idle state to the read row address state, and after determining the target column address according to the second address signal, the current state is switched from the read row address state to the read column address state, and then the current state is switched from the read column address state to the read state, so as to perform the step of transmitting the first target data to the DSP, and after the transmission is completed, the current state is switched from the read state to the idle state; If the target communication state is determined to be a data writing state, then after the target row address is determined according to the first address signal, the current state is switched from the idle state to the write row address state, and after the target column address is determined according to the second address signal, the current state is switched from the write row address state to the write column address state, and then the current state is switched from the write column address state to the write state, so as to execute the step of writing the second target data to the local target address, and after the writing is completed, the current state is switched from the write state to the idle state.

7. The communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system according to any one of claims 1 to 6, characterized in that: Also includes: Acquire data to be transmitted in advance; wherein the data to be transmitted includes phase current of the three-phase circuit and voltage, charge state and fault signal of each energy storage unit; The data to be transmitted is converted into binary data, and the binary data is stored in a local memory.

8. A communication device between FPGA and DSP in a high-voltage direct-mounted energy storage system, characterized in that: Applied to FPAG, the FPGA and DSP establish a communication connection through an external memory interface, and the device includes: A pin signal acquisition module, used to acquire the pin signal sent by the DSP, and determine the target communication state according to the pin signal; wherein the target communication state is a data reading state or a data writing state; An address signal acquisition module, used to acquire the address signal sent by the DSP and determine the target address according to the address signal; A data reading module, configured to obtain pre-stored first target data from a local memory based on the target address if the target communication state is a data reading state, and transmit the first target data to the DSP; A data writing module, used for obtaining the second target data sent by the DSP and writing the second target data into the local target address if the target communication state is the data writing state; Wherein, during the communication process between the FPGA and the DSP, the communication timing is controlled by using the state switching mode corresponding to the current communication mode configured by the target state machine; the current communication mode is asynchronous parallel communication or synchronous parallel communication.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the communication method between FPGA and DSP in a high-voltage direct-mounted energy storage system as described in any one of claims 1 to 7 are implemented.

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