Reliable loading method for DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) under distributed heterogeneous system

Abstract

The invention discloses a reliable loading method for a digital signal processor (DSP) and a field programmable gate array (FPGA) under a distributed heterogeneous system, and relates to the technical field of industrial control, the reliable loading method comprises an MSU module, the FPGA, the DSP, a related bus and a storage unit, and is characterized in that the MSU module is connected with the FPGA through a SelectMAP bus or is connected with the DSP through an EMIF bus, according to the reliable loading method for the DSP and the FPGA under the distributed heterogeneous system, the MSU module is added on the basis of the FPGA + DSP scheme, and the reliable loading of the DSP and the FPGA under the distributed heterogeneous system is achieved. According to the method, the limitation that equipment is bound with an algorithm component is broken through, an MSU module stores the algorithm component to be loaded in an eMMC storage unit in advance or through a network control port of the MSU module, then the algorithm component is remotely loaded to an FPGA or a DSP through an FPGA ASSelectMAP bus or a DSPEMIF bus, and dynamic remote loading of the algorithm component is achieved; through the mode, the limitation of binding of equipment algorithm components is broken through, so that the maintenance cost of the equipment is reduced, the reliability and stability of the equipment are improved, and the complexity of system design is simplified.

Description

Technical Field

[0001] The present invention relates to the field of industrial control technology, and in particular to a method for reliably loading DSP and FPGA in a distributed heterogeneous system. Background Art

[0002] In the fields of aerospace, industrial control, radar, etc., the field programmable gate array (FPGA) + digital signal processor (DSP) combination design has been widely used due to its advantages in signal processing. For example, in radar signal processing, FPGA can perform high-speed data acquisition and preprocessing, while DSP is used for complex algorithm calculations.

[0003] Based on the scenario requirements of the industrial radio control end, it is necessary to load and unload the algorithm components running on the FPGA and DSP. However, current equipment has many limitations in this regard. Taking the update of algorithm components through the JTAG interface as an example, it takes several minutes on average to update an algorithm component, and only one algorithm component can be run on a set of devices. When there are multiple devices in the system, this update method is not only time-consuming and labor-intensive, but also cannot meet the needs of fast switching and loading of algorithm components with different frequency bands and different modulation methods, resulting in the reliability of equipment updates cannot be guaranteed, which is not conducive to the maintenance and management of equipment. Therefore, a reliable loading method for DSP and FPGA in a distributed heterogeneous system is proposed to solve the above problems. Summary of the invention

[0004] The present invention provides a method for reliably loading DSP and FPGA in a distributed heterogeneous system to solve the problems in the background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a method for reliably loading DSP and FPGA in a distributed heterogeneous system, comprising an MSU module, an FPGA, a DSP and related buses and a storage unit, characterized in that: the MSU module is connected to the FPGA via a SelectMAP bus or to the DSP via an EMIF bus, comprising the following steps:

[0006] S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls internal program to ensure accurate selection of loading mode;

[0007] S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module.

[0008] S3, the MSU module control program reads the algorithm component from the eMMC and writes it into the DDR. The algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the FPGA according to the selectMAP timing.

[0009] Furthermore, the MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port for storing the algorithm components. The MSU module can realize remote loading of the FPGA.

[0010] Furthermore, the MSU module implements remote loading of the DSP, or the specific steps are as follows:

[0011] S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls internal program to ensure accurate selection of loading mode;

[0012] S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module.

[0013] S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the DSP according to the EMIF timing.

[0014] Furthermore, the eMMC storage unit is an embedded storage structure, including an MMC packaging interface and a main controller including a control chip.

[0015] Furthermore, when DDSP is loaded for operation, it is used for filtering and denoising in signal processing. The convolution formula used is as follows:

[0016]

[0017] Among them: x[k] is the input signal; h[nk] is the impulse response of the filter; through calculation, the output signal y[n] can be obtained.

[0018] Furthermore, the update process of the MSU module includes reading the algorithm component from the eMMC storage unit and loading it into the FPGA or DSP through the relevant bus.

[0019] Furthermore, the hardware implementation process of the MSU module for remote loading of the FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to the timing.

[0020] Furthermore, the hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to the timing.

[0021] Furthermore, it also includes a loading failure processing module. If the first remote loading fails, the FPGA or DSP is remotely reset through the MSU module before remote loading. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can call the underlying driver through the network window control program to pull down and release the FPGA and DSP reset function to achieve remote reset.

[0022] Furthermore, at least two algorithm components are stored in the eMMC storage unit, and the stored algorithm components are remotely loaded into the FPGA or DSP via the FPGASelectMAP bus or the DSPEMIF bus.

[0023] Compared with the prior art, the present invention provides a method for reliable loading of DSP and FPGA in a distributed heterogeneous system, which has the following beneficial effects:

[0024] The reliable loading method of DSP and FPGA in the distributed heterogeneous system adds an MSU module to the FPGA+DSP solution to break the limitation of device binding algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP through the FPGASelectMAP bus or the DSPEMIF bus to realize dynamic remote loading of the algorithm components. In this way, the present invention breaks through the limitation of device algorithm component binding, thereby reducing the equipment maintenance cost, while improving the reliability and stability of the equipment and simplifying the complexity of system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A block diagram of the module support unit design of a DSP and FPGA reliable loading method in a distributed heterogeneous system of the present invention;

[0027] Figure 2 A schematic diagram of an MSU module update process of a DSP and FPGA reliable loading method in a distributed heterogeneous system of the present invention;

[0028] Figure 3 A flowchart of hardware implementation of remote loading of FPGA by an MSU module in a distributed heterogeneous system DSP and FPGA reliable loading method of the present invention;

[0029] Figure 4 The present invention is a method for reliably loading DSP and FPGA in a distributed heterogeneous system Figure 4 Flowchart of the MSU module’s remote loading hardware implementation for DSP. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0032] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

[0033] The present invention aims to solve the problems existing in the prior art. The proposed MSU module is used as a module support unit. The MSU module is added to the FPGA+DSP solution to break the limitation of device binding algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port. The eMMC storage unit stores multiple algorithm components. The stored algorithm components remotely load the algorithm components to the FPGA or DSP through the FPGASelectMAP bus or the DSPEMIF bus to realize dynamic remote loading of the algorithm components. In this way, the present invention breaks through the limitation of device algorithm component binding, thereby reducing the equipment maintenance cost, while improving the reliability and stability of the equipment, and simplifying the complexity of system design.

[0034] The innovation of the present invention is to realize the hardware design scheme of remote loading of DSP and FPGA based on MSU module. Because the equipment needs to remotely load both FPGA and DSP, MSU can realize remote loading of SelectMAP and EMIF respectively through MSU module pin multiplexing when designing the overall hardware architecture. MSU module design simplifies the complexity of system design and greatly improves the reliability and stability of the equipment. FPGA or DSP can be remotely loaded and unloaded in real time through the control bus respectively. The design also considers the scenario that if the first remote loading fails, the FPGA or DSP can be remotely reset through MSU before remote loading.

[0035] See also Figure 1-4 The present invention discloses a reliable loading method of DSP and FPGA in a distributed heterogeneous system.

[0036] Overall hardware architecture: The innovation of the present invention is to implement a hardware design scheme for remote loading of DSP and FPGA based on the MSU module. The overall hardware architecture includes the MSU module, FPGA, DSP, and related buses and storage units; the MSU module is connected to the FPGA through the SelectMAP bus or to the DSP through the EMIF bus; at the same time, the MSU module integrates an eMMC storage component for storing algorithm components.

[0037] The multiplexing of SelectMAP bus and EMIF bus pins is a key feature of this design. Through multiplexing, the number of hardware pins is reduced, the hardware cost is reduced, and the remote loading requirements for FPGA and DSP are met at the same time.

[0038] Remote loading process: Through the above hardware architecture, the MSU module can realize remote loading of FPGA, including the following steps:

[0039] S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls internal program to ensure accurate selection of loading mode;

[0040] S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module.

[0041] S3, the MSU module control program reads the algorithm component from the eMMC and writes it into the DDR. The algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the FPGA according to the selectMAP timing.

[0042] Specifically, the MSU module implements remote loading of the DSP, or the specific steps are as follows:

[0043] S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls internal program to ensure accurate selection of loading mode;

[0044] S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module.

[0045] S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the DSP according to the EMIF timing.

[0046] Loading failure processing: also includes a loading failure processing module. If the first remote loading fails, the FPGA or DSP is remotely reset through the MSU module before remote loading. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can call the underlying driver through the network window control program to pull down and release the FPGA and DSP reset function to achieve remote reset.

[0047] The reliable loading method of DSP and FPGA in the distributed heterogeneous system adds an MSU module to the FPGA+DSP solution to break the limitation of device binding algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP through the FPGASelectMAP bus or the DSPEMIF bus to realize dynamic remote loading of the algorithm components. In this way, the present invention breaks through the limitation of device algorithm component binding, thereby reducing the equipment maintenance cost, while improving the reliability and stability of the equipment and simplifying the complexity of system design.

[0048] Specifically, the MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port, which is used to store the algorithm components. The MSU module can realize remote loading of the FPGA.

[0049] Specifically, the eMMC storage unit is an embedded storage structure, including an MMC packaging interface and a main controller including a control chip.

[0050] Specifically, when DDSP loads operations, it is used for filtering and denoising in signal processing. The convolution formula used is as follows:

[0051]

[0052] Among them: x[k] is the input signal; h[nk] is the impulse response of the filter; through calculation, the output signal y[n] can be obtained.

[0053] refer to Figure 2 As shown, the update process of the MSU module includes reading the algorithm component from the eMMC storage unit and loading it to the FPGA or DSP through the relevant bus.

[0054] refer to Figure 3 As shown, the hardware implementation process of the MSU module for remote loading of FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to timing.

[0055] refer to Figure 4 As shown, the hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to the timing.

[0056] In digital signal processing (DSP) and field programmable gate array (FPGA) systems, remote loading technology enables flexible software and hardware updates without physical access to the device, which is particularly important in distributed control systems, communication equipment, and embedded systems.

[0057] The DSP and FPGA remote loading application algorithm is as follows:

[0058] Remote loading is divided into three main stages: data transmission, verification, and configuration. The algorithm needs to meet the following requirements:

[0059] Reliability: integrity and correctness of transmitted data.

[0060] Security: Prevent illegal updates and malicious tampering.

[0061] Efficiency: Minimize the time required for updates.

[0062] Flexibility: Compatible with different protocols and hardware.

[0063] Step 1: System Initialization

[0064] The algorithm steps are as follows:

[0065] 1. Check the network connection status to ensure that communication with the remote server is normal.

[0066] 2. Or, initialize the communication protocol stack (e.g. TCP / IP, UDP, CAN, RS-485) and store the algorithm components to be loaded in the eMMC storage unit through the network control port.

[0067] 3. Check the current system operation status and confirm whether the update operation can be performed:

[0068] oDSP is in idle mode;

[0069] Or, oFPGA is in erasable state (make sure it is not locked).

[0070] pseudocode:

[0071] pseudo

[0072] Copy code

[0073]

[0074]

[0075] Step 2: Data Transfer

[0076] Core Requirements:

[0077] 1. Data block: prevent memory overflow caused by transmitting too much data at one time.

[0078] 2. Reliable transport protocol: ensures that data is received correctly (for example, using TCP).

[0079] 3. Encryption and authentication: AES encryption and SHA verification are used to prevent data tampering.

[0080] The algorithm steps are as follows:

[0081] 1. Request the update package from the server and obtain meta information (such as size, version, checksum).

[0082] 2. Download data in chunks, each chunk is N bytes in size.

[0083] 3. Each block of data passes CRC check, and if it fails, retransmission is requested.

[0084] After the data download is completed, SHA-256 verification is performed on the entire data packet.

[0085] pseudocode

[0086] pseudo

[0087] Copy code

[0088]

[0089]

[0090] Step 3: Load the configuration

[0091] Core Requirements:

[0092] 1. Ensure that the DSP and FPGA configuration processes do not interfere with each other.

[0093] 2. Ensure configuration security and success rate.

[0094] 3. Automatic rollback mechanism after update (to prevent the system from being unable to run due to update failure).

[0095] The algorithm steps are as follows:

[0096] 1. Use the internal logic of CPLD to select the appropriate bus for data transmission, and implement the loading operation of FPGA / DSP on the PL side through the AXI-GP protocol.

[0097] 2. Send an erase command to the FPGA to ensure that the old configuration is cleared.

[0098] 3. Load the new configuration to the FPGA block by block.

[0099] 4. DSP restarts and loads the new program.

[0100] pseudocode

[0101] pseudo

[0102] Copy code

[0103]

[0104] Step 4: Failure recovery mechanism

[0105] Design points:

[0106] 1. Use a dual partition mechanism: the current partition saves the old configuration, and the new partition saves the new configuration.

[0107] 2. When verification fails or runs abnormally, switch back to the old partition.

[0108] pseudocode

[0109] pseudo

[0110] Copy code

[0111]

[0112] At least two algorithm components are stored in the eMMC storage unit, and the stored algorithm components are remotely loaded into the FPGA or DSP via the FPGASelectMAP bus or the DSPEMIF bus.

[0113] DSP is the abbreviation of Digital Signal Processing. A digital signal processor represents a signal in digital form, and uses a computer or signal processing device to collect, transform, filter, compress, enhance, identify, and process the signal to extract useful components and forms. DSP (digital signal processor) is a programmable chip dedicated to digital signal processing. Its main features: high real-time performance, predictable running time; Harvard architecture, separate instruction and data buses; RISC instruction set, predictable instruction time; special architecture, suitable for calculation-intensive applications; internal hardware multiplier, short multiplication time and high speed; high integration, with a variety of memory interfaces and 1 / 0 interconnect interfaces; generally with DMA channel controller to ensure parallel data transmission and calculation processing.

[0114] The biggest feature of the DSP+FPGA structure is its flexible structure, strong versatility, and suitability for modular design, which can improve algorithm efficiency. At the same time, its development cycle is short, the system is easy to maintain and expand, and it is suitable for real-time signal processing. In real-time signal processing systems, low-level signal preprocessing algorithms process a large amount of data and have high requirements for processing speed, but the calculation structure is relatively simple, which is suitable for hardware implementation using FPGA, so that both speed and flexibility can be taken into account. The characteristic of high-level processing algorithms is that the amount of data processed is less than that of low-level algorithms, but the control structure of the algorithm is complex, which is suitable for implementation using DSP chips with high calculation speed, flexible addressing method, and powerful communication mechanism.

[0115] This application uses a design scheme based on the MSU module to achieve remote loading of FPGA and DSP, simplify hardware design, and improve system reliability and stability. This application uses the pin multiplexing of the MSU module to control the CPLD to achieve time-sharing multiplexing of SelectMAP and EMIF, thereby supporting the remote loading requirements of FPGA and DSP at the same time.

[0116] Instructions for use: First, the user needs to store the file containing the FPGA / DSP loading data in the eMMC device of the MSU module; secondly, control the MSU module interface through the program to complete the data reading and transmission to the FPGA or DSP; control the BYPASS logic and CPLD inside the MSU module to realize the shared use of SelectMAP and EMIF to complete the remote loading task of the FPGA and DSP.

[0117] Working process: First, select the FPGA remote loading mode, and the SelectMAP bus is activated; second, the CPLD detects and selects the correct bus connection path; third, the loading data is read from the DDR through the program in the eMMC and transmitted through the AXI-GP protocol; finally, remote loading is realized according to the SelectMAP timing of the FPGA.

[0118] When the user sends a loading instruction remotely, the relevant chips and logic circuits in the MSU module start to move and begin to process data transmission, verification, loading and other tasks in sequence. The process is equivalent to the gradual implementation of the D / A conversion task.

[0119] The technical solution of this application is to design a system based on the MSU module that can load the operating program of FPGA and DSP in a remote environment. The system adopts pin multiplexing technology, that is, one interface supports Alternate functions at the same time, such as the switching of SelectMAP and EMIF, so that the same module can have at least two interfaces with completely different functions and realize at least two highly different loading tasks.

[0120] This application mainly includes MSU module, FPGA, DSP, CPLD (programmable logic device), eMMC storage device and related bus and storage unit, among which:

[0121] MSU module: As the core control unit, it implements selection logic, interface multiplexing and reset control.

[0122] FPGA: Field Programmable Gate Array that users need to load.

[0123] DSP: Digital signal processor, new programs need to be loaded later.

[0124] CPLD: configures the logic device and selects the bus connection path by detecting GPIO signals.

[0125] eMMC: storage device that stores the algorithm components required for loading.

[0126] Bus and storage unit: responsible for data transmission and cache operations.

[0127] Technical effect: Simplify the design, improve the flexibility and reliability of hardware, use the pin multiplexing technology of the MSU module to simplify the design, optimize the hardware interface, reduce costs, and control the selection logic through CPLD processing to achieve remote loading of FPGA and DSP.

[0128] The algorithm components are stored in the eMMC storage device of the MSU module, the internal logic of the CPLD is used to select the appropriate bus for data transmission, and the loading operation of the FPGA and DSP is implemented on the PL side through the AXI-GP protocol. The SelectMAP and EMIF buses are used to efficiently implement remote loading while maintaining the system's response speed and accuracy. When loading fails, the FPGA or DSP is remotely reset through the MSU module to ensure that the loading task can be successfully completed, thereby enhancing the stability of the system.

[0129] To sum up, the reliable loading method of DSP and FPGA in the distributed heterogeneous system adds an MSU module to the FPGA+DSP solution, breaking the limitation of device binding algorithm components. The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network port, and then remotely loads the algorithm components to the FPGA or DSP through the FPGASelectMAP bus or the DSPEMIF bus, thereby realizing dynamic remote loading of the algorithm components. In this way, the present invention breaks through the limitation of device algorithm component binding, thereby reducing the equipment maintenance cost, while improving the reliability and stability of the equipment, and simplifying the complexity of system design.

[0130] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0131] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0132] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0133] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for reliable loading of DSP and FPGA in a distributed heterogeneous system, comprising an MSU module, an FPGA, a DSP and related buses and storage units, characterized in that: The MSU module is connected to the FPGA via a SelectMAP bus or to the DSP via an EMIF bus, including the following steps: S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls internal program to ensure accurate selection of loading mode; S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module. S3, the MSU module control program reads the algorithm component from the eMMC and writes it into the DDR. The algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the FPGA according to the selectMAP timing.

2. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The MSU module stores the algorithm components to be loaded in the eMMC storage unit in advance or through its network control port, which is used to store the algorithm components. The MSU module can realize remote loading of the FPGA.

3. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The MSU module implements remote loading of the DSP, or the specific steps are as follows: S1, MSU module selects SelectMAP bus remote loading mode through chip select signal; the generation of chip select signal is based on the loading of IP core that calls the internal program to ensure accurate selection of loading mode; S2. Since the data bus of the MSU module is a multiplexed pin, the BYPASS logic inside the CPLD must be used in the program control SelectMAP or EMIF signal. The CPLD detects the high and low levels of the pins of the bus chip select GPIO signal to internally select and connect the selectMAP signal link between the FPGA and the MSU module. S3: The MSU module control program reads the algorithm component from the eMMC and writes it into the DDR; the algorithm component transparently transmits the data from the PS side to the PL side through the AXI-GP protocol. After the PL side receives the GP protocol data, it implements remote loading of the DSP according to the EMIF timing.

4. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 2, characterized in that: The eMMC storage unit is an embedded storage structure, including an MMC packaging interface and a main controller including a control chip.

5. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 3, characterized in that: When DDSP is loaded for operation, it is used for filtering and denoising in signal processing. The convolution formula used is as follows: Among them: x[k] is the input signal; h[nk] is the impulse response of the filter; through calculation, the output signal y[n] can be obtained.

6. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The update process of the MSU module includes reading the algorithm component from the eMMC storage unit and loading it into the FPGA or DSP through the relevant bus.

7. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The hardware implementation process of the MSU module for remote loading of FPGA includes chip select signal selection, logic switching, data reading and writing, and loading according to timing.

8. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: The hardware implementation process of the MSU module for remote loading of the DSP includes chip select signal selection, logic switching, data reading and writing, and loading according to the timing.

9. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 1, characterized in that: It also includes a loading failure processing module. If the first remote loading fails, the FPGA or DSP is remotely reset through the MSU module before remote loading. The reset pins on the FPGA and DSP chips are connected to the MSU module. The MSU module can call the underlying driver through the network window control program to pull down and release the FPGA and DSP reset function to achieve remote reset.

10. The method for reliable loading of DSP and FPGA in a distributed heterogeneous system according to claim 2, characterized in that: At least two algorithm components are stored in the eMMC storage unit, and the stored algorithm components are remotely loaded into the FPGA or DSP via the FPGASelectMAP bus or the DSPEMIF bus.

Images