Processing unit, systolic array, data processing method, and electronic device

Abstract

The invention provides a processing unit in a systolic array, the systolic array, a data processing method and electronic equipment, and the processing unit is provided with a first group of data transmission paths used for transmitting data in a first dimension and a second group of data transmission paths used for transmitting data in a second dimension. The first group of data transmission paths is used for transmitting first data, and the second group of data transmission paths is used for transmitting second data; wherein the first group of data transmission paths comprises a first data transmission path for transmitting data along a first direction and a second data transmission path for transmitting data along a second direction; and the second group of data transmission paths comprises a third data transmission path for transmitting data along a third direction and a fourth data transmission path for transmitting data along a fourth direction.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a processing unit in a systolic array, a systolic array, a data processing method and an electronic device. Background Art

[0002] A systolic array is a parallel computing architecture that can be implemented through hardware circuits. Specifically, a systolic array consists of multiple identical processing elements (PEs) connected according to certain interconnection rules. Each processing element can communicate with adjacent processing elements and perform certain computing tasks to efficiently perform matrix operations and other linear algebra operations.

[0003] The core idea of ​​the systolic array is to allow data to flow in the array of processing units to reduce the number of memory accesses, thereby increasing the computing frequency. Therefore, how to improve the operating speed and pipeline operating efficiency in the systolic array has become a research direction for those skilled in the art. Summary of the invention

[0004] A processing unit in a systolic array, the processing unit having a first set of data transmission paths for transmitting data in a first dimension and a second set of data transmission paths for transmitting data in a second dimension, the first set of data transmission paths being used to transmit first data and the second set of data transmission paths being used to transmit second data; wherein

[0005] The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction;

[0006] The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction.

[0007] Optionally, the first group of data transmission paths includes a first selection module, and the first selection module is used to select the first data transmission path to transmit the first data, or select the second data transmission path to transmit the first data based on a selection signal;

[0008] The second group of data transmission paths includes a second selection module, and the second selection module selects the third data transmission path to transmit the second data, or selects the fourth data transmission path to transmit the second data based on the selection signal;

[0009] The processing unit also includes: a data processing module, which includes a computing unit, and the computing unit is located on the data transmission path of the first group of data transmission paths and the second group of data transmission paths, and is used to process the first data and the second data to generate third data, and store the third data.

[0010] Optionally, the first group of data transmission paths further includes a first group of output ports located on the first dimension, and the second group of data transmission paths further includes a second group of output ports located on the second dimension;

[0011] The first group of output ports includes a first output port and a second output port, the first output port and the second output port are used to output the first data; the second group of output ports includes a third output port and a fourth output port, the third output port and the fourth output port are used to output the second data;

[0012] A first data output terminal of the computing unit is connected to the first group of output ports;

[0013] The second data output terminal of the computing unit is connected to the second group of output ports.

[0014] Optionally, the first group of data transmission paths further includes a first group of input ports located on the first dimension, and the second group of data transmission paths further includes a second group of input ports located on the second dimension; wherein the first group of input ports includes a first input port and a second input port, and the first input port and the second input port are used to input the first data; the second group of input ports includes a third input port and a fourth input port, and the third input port and the fourth input port are used to input the second data;

[0015] The two input terminals of the first selection module are connected to the first input port and the second input port respectively, and the output terminal is connected to the first data input terminal of the calculation unit;

[0016] The two input terminals of the second selection module are connected to the third input port and the fourth input port respectively, and the output terminal is connected to the second data input terminal of the calculation unit;

[0017] The control ends of the first selection module and the second selection module are used to input selection signals.

[0018] Optionally, the processing unit further includes:

[0019] A selection signal generating module, configured to generate a corresponding selection signal based on the signal input states of the two input terminals of the first selection module or the two input terminals of the second selection module; a selection signal output terminal of the selection signal generating module is connected to the control terminals of the first selection module and the second selection module;

[0020] The selection signal generating module is used to generate a first selection signal when the first input port first receives the first data or the third input port first receives the second data, so that the first selection module selects the first data transmission path to transmit the first data, and the second selection module selects the third data transmission path to transmit the second data;

[0021] The selection signal generating module is also used to generate a second selection signal when the second input port first receives the first data or the fourth input port first receives the second data, so that the first selection module selects the second data transmission path to transmit the first data, and the second selection module selects the fourth data transmission path to transmit the second data.

[0022] Optionally, also include:

[0023] A first delay module, wherein two input ends of the first delay module are respectively connected to the first input port and the second input port, and two output ends are respectively connected to the two input ends of the first selection module, and is used for delaying the first data by one cycle and outputting it to the first selection module;

[0024] A second delay module, wherein two input terminals of the second delay module are respectively connected to the third input port and the fourth input port, and two output terminals are respectively connected to two input terminals of the second selection module, and is used for delaying the second data by one cycle and outputting it to the second selection module;

[0025] The two input ends of the selection generation module are respectively connected to the two input ends of the first delay module, or are respectively connected to the two input ends of the second delay module.

[0026] A systolic array comprises m×n processing units, wherein the processing units have a first group of data transmission paths for transmitting data in a first dimension and a second group of data transmission paths for transmitting data in a second dimension, wherein the first group of data transmission paths is used to transmit first data, and the second group of data transmission paths is used to transmit second data; wherein

[0027] The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction;

[0028] The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction.

[0029] Optionally, the processing units in the first row and the processing units in the nth column of the m×n processing units are first processing units, and the other processing units are second processing units; or, the processing units in the mth row and the processing units in the first column of the m×n processing units are first processing units, and the other processing units are second processing units; wherein m is greater than 1 and / or n is greater than 1;

[0030] The first processing unit generates a selection signal based on the input status of the data input port of the first data transmission path and / or the second data transmission path, and selects the first data transmitted by the first data transmission path and the second data transmitted by the third data transmission path based on the selection signal, and outputs the data to the downstream processing unit through the first data transmission path and the second data transmission path;

[0031] The second processing unit is used to receive data output by the processing unit of the upstream node, and select the first data transmitted by the first data transmission path and the second data transmitted by the third data transmission path based on the selection signal received from the upstream processing unit, and output the data to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths;

[0032] or,

[0033] The first processing unit generates a selection signal based on the input status of the data input port of the first data transmission path and / or the second data transmission path, and selects the first data transmitted by the second data transmission path and the second data transmitted by the fourth data transmission path based on the selection signal, and outputs the data to the downstream processing unit through the first data transmission path and the second data transmission path;

[0034] The second processing unit is used to receive data output by the processing unit of the upstream node, and based on the selection signal received from the output of the upstream processing unit, select the first data transmitted by the second data transmission path and the second data transmitted by the fourth data transmission path, and output them to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths.

[0035] Optionally, the systolic array includes a first processing unit and a second processing unit adjacent to each other in a first dimension, a first output port of the first processing unit is connected to a first input port of the second processing unit, and a second input port of the first processing unit is connected to a second output port of the second processing unit;

[0036] The systolic array includes a first processing unit and a second processing unit adjacent to each other in a second dimension, a third output port of the first processing unit is connected to a third input port of the second processing unit, and a fourth input port of the first processing unit is connected to a fourth output port of the second processing unit.

[0037] Optionally, the second processing units located in a plurality of diagonal directions parallel to the diagonal direction of the array are connected to the selection signal output ends of the first processing units in the diagonal directions.

[0038] An electronic device comprises any one of the systolic arrays described above or a systolic array formed by processing units in any one of the systolic arrays described above.

[0039] A data processing method is applied to a systolic array, the systolic array comprising m×n processing units, the processing units having a first group of data transmission paths for transmitting data in a row direction and a second group of data transmission paths for transmitting data in a column direction, the first group of data transmission paths transmitting first data, the second group of data transmission paths transmitting second data; each group comprising two data transmission directions;

[0040] If m=n, the data processing method includes:

[0041] At the same time, the processing unit in the i-th row and the j-th column is controlled to transmit the first data through the first data transmission path and the second data through the third data transmission path, and the processing unit in the m+1-i-th row and the n+1-j-th column is controlled to transmit the first data through the second data transmission path and the second data through the fourth data transmission path;

[0042] The processing unit in the i-th row and j-th column and the processing unit in the r-th row and s-th column transmit data simultaneously; i+j=r+s, i and r are integers not less than 1 and not greater than m, and j and s are integers not less than 1 and not greater than n.

[0043] Optionally, in the row direction, starting from the first column, the second data of each column in the second data matrix starting from the first column is input to the first row processing units of the subsequent columns one cycle later, and each second data in the second data array of each column is transferred to the processing units of the next row row by row according to the data transmission cycle; at the same time, starting from the last column, the second data of each column in the second data matrix starting from the last column is input to the last row processing units of the previous columns one cycle later, and each second data in the second data array of each column is transferred to the processing units of the previous row row by row according to the data transmission cycle;

[0044] In the column direction, starting from the first row, the first data of each row in the first data matrix starting from the first row is input to the first column processing units of each subsequent row one cycle later, and each first data in the first data array of each row is transferred to the processing units of the next column column by column according to the data transmission cycle; at the same time, starting from the last row, the first data of each row in the first data matrix starting from the last row is input to the last column processing units of the previous rows one cycle later, and each first data in the first data array of each row is transferred to the processing units of the previous column column by column according to the data transmission cycle.

[0045] Optionally, according to the data input status of the first row processing unit and the last column processing unit, or the first column processing unit and the last row processing unit in the systolic array, a data transmission path in a corresponding direction is selected so that the processing units in the diagonal direction at the same moment select the same data transmission direction.

[0046] Optionally, also include:

[0047] After the processing unit in the first row and the nth column outputs the third signal, the third data stored in the processing units in each row are synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the first row and the nth column is completed; or,

[0048] After the processing unit in the mth row and the first column outputs the third signal, the third data stored in the processing units in each row are synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the mth row and the first column is completed.

[0049] An electronic device comprises: a systolic array, a processor and a memory, wherein the systolic array is the systolic array described in any one of the above items; the memory is used to store a computer program; and the processor is used to execute the computer program so that the electronic device can implement any one of the data processing methods described in the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0051] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0052] Figure 1 A schematic diagram of a processing unit provided in the present application;

[0053] Figure 2 A schematic diagram of another processing unit provided for the present application;

[0054] Figure 3 for Figure 2 A schematic diagram of the structure of the corresponding processing unit;

[0055] Figure 4 for Figure 1 A structural schematic diagram of a corresponding processing unit;

[0056] Figure 5 for Figure 1 Another structural schematic diagram of the corresponding processing unit;

[0057] Figure 6 for Figure 1 Another structural schematic diagram of a corresponding processing unit;

[0058] Figure 7 A schematic diagram of a data transmission path of a first delay module in a processing unit provided by the present application;

[0059] Figure 8 A schematic diagram of another data transmission path of a first delay module in a processing unit provided by the present application;

[0060] Fig. 9 A schematic diagram of a data processing process of a computing unit in a processing unit provided in the present application;

[0061] Fig.10 A schematic diagram of a systolic array provided for this application;

[0062] Fig.11 A schematic diagram of another systolic array provided for this application;

[0063] Fig.12 A partial schematic diagram of a pulsating array provided in this application;

[0064] Fig.13 A schematic diagram of a data transmission method in a systolic array in a data processing method provided in the present application;

[0065] Fig.14 A schematic diagram of a data transmission method in a systolic array in another data processing method provided in the present application; a schematic diagram;

[0066] Figure 15-Figure 24 A schematic diagram of the data input process when the systolic array uses a bidirectional input data matrix of the same dimension in another data processing method provided by the present application;

[0067] Fig.25 A schematic diagram of selecting a propagation direction of a signal in another data processing method provided by the present application;

[0068] Fig.26 A schematic diagram of selecting another propagation direction of a signal in another data processing method provided by the present application;

[0069] Fig. 27 A schematic diagram of an output result after the third data stored in each processing unit in the same row of processing units is outputted sequentially from the left side of the systolic matrix when the systolic array adopts a bidirectional input data matrix in the same dimension, and the third data stored in the processing units in different rows are outputted synchronously;

[0070] Fig.28 A schematic diagram of an output result after the third data stored in each processing unit in the same row of processing units is sequentially output from the left side of the systolic matrix when the systolic array adopts a unidirectional input data matrix in the same dimension, and the third data stored in the processing units in different rows are sequentially output based on the completion time of the data processing process of the corresponding processing units;

[0071] Fig.29 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0073] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0074] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0075] As described in the background technology section, how to improve the operating speed and pipeline operating efficiency in the systolic array has become a research direction for those skilled in the art.

[0076] In view of this, an embodiment of the present application provides a processing unit in a systolic array, such as Figure 1 As shown, the processing unit PE has a first group of data transmission paths a for transmitting data in a first dimension X and a second group of data transmission paths b for transmitting data in a second dimension Y. The first group of data transmission paths a is used to transmit first data, and the second group of data transmission paths b is used to transmit second data, thereby realizing the transmission of data in the data array. The first dimension X and the second dimension Y are different.

[0077] In this embodiment, continue as Figure 1 As shown, the first group of data transmission paths a includes a first data transmission path a1 for transmitting data along a first direction and a second data transmission path a2 for transmitting data along a second direction; the second group of data transmission paths includes a third data transmission path b1 for transmitting data along a third direction and a fourth data transmission path b2 for transmitting data along a fourth direction, wherein the first direction is different from the second direction, and the third direction is different from the fourth direction, so that the processing unit PE can transmit data bidirectionally in the same dimension, and further, when the processing unit PE is applied to a systolic array, it can simultaneously receive data matrices in two directions, thereby improving the operating speed of the systolic array and the pipeline operating efficiency.

[0078] Optionally, in one embodiment of the present application, the first direction is opposite to the second direction, and the third direction is opposite to the fourth direction.

[0079] like Figure 2 and Figure 3As shown, in one embodiment of the present application, the first group of data transmission paths of the processing unit includes a first selection module 10, and the first selection module 10 is used to select the first data transmission path a1 to transmit the first data based on the selection signal select, or select the second data transmission path a2 to transmit the first data, so that the processing unit PE only selects one data transmission path to transmit the first data at the same time in the first dimension, thereby avoiding the data processing process of the processing unit PE from being disordered; the second group of data transmission paths includes a second selection module 20, and the second selection module 20 selects the third data transmission path b1 to transmit the second data, or selects the fourth data transmission path b2 to transmit the second data based on the selection signal select, thereby allowing the processing unit PE to only select one data transmission path to transmit the second data at the same time in the second dimension, thereby avoiding the data processing process of the processing unit PE from being disordered.

[0080] Optionally, in one embodiment of the present application, continue as Figure 3 As shown, the selection module 10 and the selection module 20 can be implemented by a MUX selector. When the selection signal select is 1, the first selection module 10 selects the first data transmission path a1 to transmit the first data, and the second selection module 20 selects the third data transmission path b1 to transmit the second data; when the selection signal select is 0, the first selection module 10 selects the second data transmission path a2 to transmit the first data, and the second selection module 20 selects the fourth data transmission path b2 to transmit the second data.

[0081] In this embodiment, continue as Figure 3 As shown, the processing unit PE also includes a data processing module, which includes a computing unit 30. The computing unit 30 is located on the data transmission path of the first group of data transmission paths a and the second group of data transmission paths b, and is used to process the first data and the second data to generate third data, and store the third data.

[0082] Based on the above embodiment, in one embodiment of the present application, continue as follows Figure 1-Figure 3 As shown, the first group of data transmission paths a of the processing unit PE includes a first group of input ports located on the first dimension X, and the second group of data transmission paths b includes a second group of input ports located on the second dimension Y; wherein the first group of input ports includes a first input port a1i and a second input port a2i, and the first input port a1i and the second input port a2i are used to input the first data; the second group of input ports includes a third input port b1i and a fourth input port b2i, and the third input port b1i and the fourth input port b2i are used to input the second data.

[0083] Optionally, in one embodiment of the present application, the first group of data transmission paths of the processing unit PE further includes a first group of output ports located on the first dimension, and the second group of data transmission paths further includes a second group of output ports located on the second dimension; Figure 2 and Figure 3 As shown, the first group of output ports of the processing unit PE includes a first output port a1o and a second output port a2o. When the first data is transmitted in the first data transmission path a1, the first output port a1o outputs the first data transmitted in the first data transmission path a1; when the first data is transmitted in the second data transmission path a2, the second output port a2o outputs the first data transmitted in the second data transmission path a2; the second group of output ports includes a third output port b1o and a fourth output port b2o. When the third output port b1o transmits second data in the third data transmission path b1, the third output port b1o outputs the second data transmitted in the third data transmission path b1; when the fourth output port b2o transmits second data in the fourth data transmission path b2, the fourth data transmitted in the fourth data transmission path b2.

[0084] Continue as Figure 3 As shown, in this embodiment, the first data output end of the computing unit 30 is connected to the first group of output ports to facilitate the transmission of first data to the outside through the first group of output ports; the second data output end of the computing unit 30 is connected to the second group of output ports to facilitate the transmission of second data to the outside through the second group of output ports.

[0085] In this embodiment, the signal transmission path between the first input port a1i and the first output port a1o is the signal transmission path of the first data transmission path a1, that is, when the first data transmission path a1 transmits the first data, the first data is input from the first input port a1i, and is transmitted along the first data transmission path a1 to the first output port a1o for output;

[0086] The signal transmission path between the second input port a2i and the second output port a2o is the signal transmission path of the second data transmission path a2, that is, when the second data transmission path a2 transmits the first data, the first data is input from the second input port a2i, transmitted along the second data transmission path a2 to the second output port a2o for output;

[0087] The signal transmission path between the third input port b1i and the third output port b1o is the signal transmission path of the third data transmission path b1, that is, when the third data transmission path b1 transmits the second data, the second data is input from the third input port b1i, transmitted along the third data transmission path b1 to the third output port b1o for output;

[0088] The signal transmission path between the fourth input port b2i and the fourth output port b2o is the signal transmission path of the fourth data transmission path b2, that is, when the fourth data transmission path b2 transmits the second data, the second data is input from the fourth input port b2i, transmitted along the fourth data transmission path b2 to the fourth output port b2o for output.

[0089] On the basis of the above embodiments, in one embodiment of the present application, the two input ends of the first selection module 10 are respectively connected to the first input port a1i and the second input port a2i, the output end is connected to the first data input end of the calculation unit 30, and the control end is used to input a selection signal select, and based on the selection signal select, it is selected to input the data output by the first input port a1i or the data input by the second input port a2i. For example, when the selection signal is 1, the first data input end of the calculation unit 30 inputs the data output by the first input port a1i, and when the selection signal is 0, the first data input end of the calculation unit 30 inputs the data output by the second input port a2i;

[0090] The two input ends of the second selection module 20 are respectively connected to the third input port b1i and the fourth input port b2i, and the output end is connected to the second data input end of the calculation unit 30. The control end is used to input a selection signal select; based on the selection signal select, it is selected to input the data output by the third input port b1i or the data input by the fourth input port b2i. For example, when the selection signal is 1, the second data input end of the calculation unit 30 inputs the data output by the third input port b1i, and when the selection signal is 0, the second data input end of the calculation unit 30 inputs the data output by the fourth input port b2i.

[0091] Optionally, in one embodiment of the present application, Figure 4 As shown, the processing unit also includes: a selection signal generating module 40, which is used to generate a corresponding selection signal select based on the signal input status of the two input ends of the first selection module 10 or the two input ends of the second selection module 20; the selection signal output end of the selection signal generating module 40 is connected to the control end of the first selection module 10 and the second selection module 20, so as to generate a corresponding selection signal select based on the signal input status of the two input ends of the first selection module 10 or the two input ends of the second selection module 20 and output it to the control end of the first selection module and the second selection module.

[0092] Specifically, in this embodiment, the selection signal generating module 40 is used to generate a first selection signal when the first input port a1i first receives the first data or the third input port b1i first receives the second data, so that the first selection module 10 selects the first data transmission path a1 to transmit the first data, and the second selection module 20 selects the third data transmission path b1 to transmit the second data;

[0093] The selection signal generating module 40 is also used to generate a second selection signal when the second input port a2i first receives the first data or the fourth input port b2i first receives the second data, so that the first selection module 10 selects the second data transmission path a2 to transmit the first data, and the second selection module 20 selects the fourth data transmission path b2 to transmit the second data.

[0094] It can be seen from the above description that in this embodiment, the processing unit includes two data transmission channels in different directions on the same dimension. When selecting data input, the data transmitted by the first data transmission path and the third data transmission path can be selected, or the data transmitted by the first data transmission path and the third data transmission path can be selected. Specifically, it depends on whether the first input port a1i and the third input port b1i receive the valid data first, or the second input port a2i and the fourth input port b2i receive the valid data first. If the first input port a1i and the second input port a2i receive valid data at the same time, the processing unit can choose to arbitrarily select the data input by the first input port a1i or the data input by the second input port a2i. Similarly, if the third input port b1i and the fourth input port b2i receive valid data at the same time, the processing unit can choose to arbitrarily select / or select the data input by the third input port b1i or the data input by the fourth input port b2i based on the default configuration.

[0095] Optionally, in one embodiment of the present application, Figure 4 and Figure 5 As shown, the selection signal generating module 40 includes:

[0096] a logic element 41, wherein the logic element 41 has a fifth input port, a sixth input port and a fifth output port;

[0097] The trigger module 42 , the register group 42 includes a seventh input port D1 , an eighth input port D2 and a sixth output port Q2 , the seventh input port D1 is connected to the fifth output port of the logic element 41 , the eighth input port D2 is connected to the fifth output port of the logic element 41 .

[0098] On the basis of the above embodiments, in one embodiment of the present application, when the fifth input port of the logic element 41 inputs the first signal a1_pre, the eighth input port D2 outputs the first selection signal, such as the first selection signal is 1, and when the fifth input port of the logic element 41 inputs the second signal a2_pre, the eighth input port D2 outputs the second selection signal, such as the first selection signal is 0; wherein, the first signal a1_pre represents that the first input port a1i of the first data transmission path a1 inputs the first data, and the second signal a2_pre represents that the second input port a2i of the second data transmission path a2 inputs the first data.

[0099] In another embodiment of the present application, Figure 5 As shown, when the fifth input port of the logic element 41 inputs the first signal b1_pre, the eighth input port D2 outputs the first selection signal, such as the first selection signal is 1; when the fifth input port of the logic element 41 inputs the second signal b2_pre, the eighth input port D2 outputs the second selection signal, such as the first selection signal is 0; wherein, the first signal b1_pre represents that the third input port b1i of the third data transmission path b1 inputs the second data, and the second signal b2_pre represents that the fourth input port b2i of the fourth data transmission path b2 inputs the second data.

[0100] The following describes the processing unit of the systolic array provided in an embodiment of the present application by taking the first signal a1_pre representing that the first data is input into the first input port a1i of the first data transmission path a1 and the second signal a2_pre representing that the first data is input into the second input port a2i of the second data transmission path a2 as an example.

[0101] Specifically, in one embodiment of the present application, the trigger module 42 includes a first trigger unit 421 and a second trigger unit 422, wherein the first trigger unit 421 includes a D1 input terminal, an E1 input terminal, a Q1 output terminal and a Qn1 output terminal, and the second trigger unit 422 includes a D2 input terminal, an E2 input terminal, a Q2 output terminal and a Qn2 output terminal; wherein the first trigger unit 421 includes a D1 input terminal as the seventh input port of the trigger module, the E1 input terminal is connected to the Qn1 output terminal, the Qn1 output terminal is connected to the E2 input terminal of the second trigger unit 422, the D2 input terminal of the second trigger unit 422 is connected to the fifth input port of the logic element 41, and the Q2 output terminal is the sixth output port of the trigger module, which is used to output a selection signal.

[0102] It should be noted that, in the above embodiment, the first trigger unit 421 also has a first reset terminal RST1 for inputting a reset signal, and the second trigger unit 422 has a second reset terminal RST2 for inputting a reset signal. Before the pulsating array starts working, the first reset terminal and the second reset terminal input a reset signal, so that E1 is 1 and E2 is 1. It should be noted that if E1 is 1, the signal input to the D1 input terminal can be delayed by one cycle and output from Q1. Similarly, if E2 is 1, the signal input to the D2 input terminal can be delayed by one cycle and output from Q2. If E1 is 0, the signal input to the D1 input terminal is not transmitted to Q1. Similarly, if E2 is 0, the signal input to the D2 input terminal is not transmitted to Q2. When Q1 is 1, Qn1 is 0. When Q1 is 0, Qn1 is 0. Similarly, when Q2 is 1, Qn2 is 0. When Q2 is 0, Qn2 is 1.

[0103] Optionally, in one embodiment of the present application, the logic element is an OR gate. In this embodiment, the working process of the selection generation module includes:

[0104] In the initial state, E1 is 1, E2 is 1, if a1_pre is 1, a2_pre is 0, then the logic element 41 outputs 1, D1 is 1, D2 is 1, in the next cycle, Q1 is 1, Q2 is 1, Qn1 is 0, E2 is 0, Q2 keeps outputting 1, the first selection module 10 selects the signal input to the first input port a1i, the second selection module 20 selects the signal input to the third input port b1i, at the same time, the second flip-flop unit 422 will save the value of a1_pre (i.e., the output signal of the logic element) until the next reset signal arrives;

[0105] In the initial state, E1 is 1, E2 is 1, if a1_pre is 0, a2_pre is 1, then the logic element 41 outputs 1, D1 is 1, D2 is 0, in the next cycle, Q1 is 1, Q2 is 0, Qn1 is 0, E2 is 0, Q2 keeps outputting 0, the first selection module 10 selects the signal input to the second input port a2i, the second selection module 20 selects the signal input to the fourth input port b2i, at the same time, the second flip-flop unit 422 will save the value of a1_pre (i.e., the output signal of the logic element) until the next reset signal arrives;

[0106] If a1_pre is 1 and a2_pre is 1, the logic element 41 outputs 1, D1 is 1, D2 is 1, and in the next cycle, Q1 is 1, Q2 is 1, Qn1 is 0, E2 is 0, Q2 keeps outputting 1, the first selection module 10 selects the signal input to the first input port a1i, and the second selection module 20 selects the signal input to the third input port b1i. At the same time, the second trigger unit 422 will save the value of a1_pre (i.e., the output signal of the logic element) until the next reset signal arrives.

[0107] It should be noted that, in the above embodiment, the output signal a_pre of the logic element may also be output to a downstream processing unit of the processing unit to inform the downstream processing unit that the data in the processing unit is valid data.

[0108] In another embodiment of the present application, the processing unit may not include a selection signal generating module, and may only include a logic element, such as Figure 2 As shown, the processing unit does not generate a selection signal, but receives a selection signal output by its upstream processing unit; Figure 3 As shown, the processing unit will select the first data input from the first input port a1i and the second data input from the third input port b1i, or the first data input from the second input port a2i and the second data input from the fourth input port b2i according to the input select signal, and at the same time, the corresponding first signal a1_pre and the second signal a2_pre are ORed together and output as a new a_pre value, and passed to the downstream processing unit.

[0109] Optionally, in one embodiment of the present application, Figure 6 As shown, the first data transmission path a1 includes two signal transmission paths, which transmit the first data a1_data and the first valid signal a1_valid indicating that the first data is valid; the second data transmission path a2 includes two signal transmission paths, which transmit the first data a2_data and the second valid signal a2_valid indicating that the second data is valid. For example, a1_valid is 1 and a2_valid is 0, indicating that the first data a1_data transmitted by the first data transmission path is valid data; a1_valid is 0 and a2_valid is 1, indicating that the first data a2_data transmitted by the second data transmission path is valid data.

[0110] As can be seen from the foregoing, since the time when the Q2 output terminal of the second trigger unit outputs the selection signal select is one cycle later than the time when the D2 input terminal inputs the signal, the time when the selection generation module outputs the selection signal is one cycle later than the time when the input terminal of the logic element inputs the signal. If the two input terminals of the logic element directly input a1_valid and a2_valid, the time when the control terminal of the first selection module inputs the selection signal will be one cycle later than the time when the two input terminals of the first selection module input the signal, and the time when the control terminal of the second selection module inputs the selection signal will be one cycle later than the time when the two input terminals of the second selection module input the signal.

[0111] Therefore, based on the above embodiment, in one embodiment of the present application, the processing unit further includes:

[0112] a first delay module, wherein two input ends of the first delay module are respectively connected to the first input port and the second input port, and two output ends are respectively connected to the two input ends of the first selection module, and is used to delay the first data by one cycle and output it to the first selection module, so that the signals input to the two input ends of the first selection module and the selection signal input to the control end thereof are simultaneously input to the first selection module;

[0113] The second delay module, the two input ends of the second delay module are respectively connected to the third input port and the fourth input port, and the two output ends are respectively connected to the two input ends of the second selection module, for delaying the second data by one cycle and outputting it to the second selection module, so that the signals input to the two input ends of the second selection module and the selection signal input to its control end are simultaneously input to the second selection module. It should be noted that, in the above embodiment, the two input ends of the selection generation module are respectively connected to the two input ends of the first delay module, or respectively connected to the two input ends of the second delay module.

[0114] Optionally, in an embodiment of the present application, the first delay module and the second delay module may be implemented by registers, but the present application does not limit this and it depends on the specific circumstances.

[0115] The following describes the working principle of the first delay module by taking the example that the two input terminals of the selection generation module are respectively connected to the two input terminals of the first delay module.

[0116] Specifically, Figure 7As shown, the first valid signal a1_valid0 indicating whether the first data a1_data0 is valid is directly input as the first signal a1_pre to the fifth input port of the logic element 41, that is, an input end of the selection generation module 40; the first valid signal a1_valid0 indicating whether the first data a1_data0 is valid and the first data a1_data0 are input to the input end of the first delay module REG1, and after being delayed by one cycle by the first delay module REG1, are output to the first input port a1i of the first selection module 10, so that the first data a1_data and the first valid signal a1_valid input to the first input port a1i of the first selection module 10 and the selection signal input to its control end are simultaneously input to the first selection module 10;

[0117] Similarly, if Figure 8 As shown, the second valid signal a2_valid0 indicating whether the first data a2_data0 is valid is directly input as the second signal a2_pre to the sixth input port of the logic element 41, that is, another input end of the selection generation module 40; the second valid signal a2_valid0 indicating whether the first data a2_data0 is valid and the first data a2_data0 are input to the input end of the first delay module REG1, and after being delayed for one cycle by the first delay module REG1, are output to the second input port a2i of the first selection module 10, so that the first data a2_data in the second input port a2i of the first selection module 10 and the first valid signal a2_valid indicating that the first data a2_data is valid and the selection signal input at its control end are simultaneously input to the first selection module 10.

[0118] Optionally, in the above embodiment, the first delay module can implement the delay of the data input by the first input port and the delay of the data input by the second input port through different delay units (such as registers), or can implement the delay of the data input by the first input port and the delay of the data input by the second input port through the same delay unit (such as register). The present application does not limit this and it depends on the specific circumstances.

[0119] On the basis of any of the above embodiments, in one embodiment of the present application, taking a computing unit implementing a convolution operation as an example, Fig. 9 As shown, the calculation unit 30 performs a convolution operation (corresponding to Fig. 9 mul), and the third data stored in the previous cycle (corresponding to Fig. 9 psum in the calculation (corresponding to Fig. 9 acc) to get the third data at the current moment (corresponding to Fig. 9 psum sel in), store the third data at the current moment (corresponding to Fig. 9 psum reg in) and output (corresponding to Fig. 9 psumo in the above), and the first data output by the first selection module 10 is output through the first output port a1o and the second output port a2o in the next cycle after passing through a delay unit reg, and the second data output by the second selection module 20 is output through the third output port b1o and the fourth output port b2o in the next cycle after passing through a delay unit reg. Optionally, the delay unit can be implemented by a register, which is not limited in the present application and depends on the specific situation.

[0120] Optionally, in one embodiment of the present application, the processing unit PE also has a third data input terminal and a third data output terminal. The third data input terminal of the processing unit PE is connected to the third data output terminal of the upstream processing unit PE, and is used to receive the third data output by the third data output terminal of the processing unit of its upstream node; the third data output terminal of the processing unit PE is connected to the third data input terminal of the downstream processing unit PE, and is used to transmit the third data to the processing unit PE of its downstream node.

[0121] Accordingly, the embodiment of the present application also provides a systolic array, such as Fig.10 As shown, the systolic array includes m×n processing units PE (including a first processing unit PE_1 and a second processing unit PE_2), and the processing unit PE has a first group of data transmission paths a for transmitting data in a first dimension X and a second group of data transmission paths b for transmitting data in a second dimension Y, wherein the first group of data transmission paths a is used to transmit first data, and the second group of data transmission paths b is used to transmit second data; wherein,

[0122] The first group of data transmission paths a includes a first data transmission path a1 that transmits data along a first direction and a second data transmission path a2 that transmits data along a second direction, wherein the first direction and the second direction are different;

[0123] The second group of data transmission paths b includes a third data transmission path b1 that transmits data along a third direction and a fourth data transmission path b2 that transmits data along a fourth direction, wherein the third direction is different from the fourth direction.

[0124] Optionally, in one embodiment of the present application, the first direction is opposite to the second direction, and the third direction is opposite to the fourth direction.

[0125] In the systolic array provided in the embodiment of the present application, the processing unit PE can transmit data bidirectionally in the same dimension, so that when the processing unit PE is applied to the systolic array, it can simultaneously receive data matrices in two directions, thereby improving the operating speed of the systolic array and the pipeline operating efficiency.

[0126] Optionally, in one embodiment of the present application, continue as Fig.10 As shown, the processing units in the first row and the processing units in the nth column among the m×n processing units are the first processing units PE_1, and the other processing units are the second processing units PE_2; in another embodiment of the present application, the processing units in the mth row and the processing units in the 1st column among the m×n processing units are the first processing units, and the other processing units are the second processing units; wherein, m is greater than 1 and / or n is greater than 1; the present application does not impose any limitation on this, and it depends on the specific circumstances.

[0127] The following describes the systolic array provided in the embodiment of the present application by taking the processing units in the first row and the processing units in the nth column of the m×n processing units as the first processing unit PE_1 and the other processing units as the second processing unit PE_2 as an example.

[0128] In this embodiment, the first processing unit PE_1 generates a selection signal select based on the input status of the data input port of its first group of data transmission paths a and / or the second group of data transmission paths b, such as the selection signal is a first selection signal, and selects the first data transmitted by the first data transmission path a1 and the second data transmitted by the third data transmission path b1 based on the selection signal select, and outputs them to the downstream processing unit through the first group of data transmission paths a and the second group of data transmission paths b; the second processing unit PE_2 is used to receive the data output by the processing unit of the upstream node, and selects the first data transmitted by the first data transmission path a1 and the second data transmitted by the third data transmission path b1 based on the selection signal select received from the upstream processing unit, and outputs them to the downstream processing unit through the first group of data transmission paths a and the second group of data transmission paths b;

[0129] or,

[0130] The first processing unit PE_1 generates a selection signal select based on the input status of the data input port of the first group of data transmission paths a and / or the second group of data transmission paths b, such as the selection signal is a second selection signal, and selects the first data transmitted by the second data transmission path a2 and the second data transmitted by the fourth data transmission path b2 based on the selection signal select, and outputs the data to the downstream processing unit through the first group of data transmission paths a and the second group of data transmission paths b;

[0131] The second processing unit PE_2 is used to receive data output by the processing unit of the upstream node, and based on the selection signal select received from the output of the upstream processing unit, select the first data transmitted by the second data transmission path a2 and the second data transmitted by the fourth data transmission path b2, and output them to the downstream processing unit through the first group of data transmission paths a and the second group of data transmission paths b.

[0132] It can be seen from the above description that the first processing unit needs to generate a selection signal, and the second processing unit does not need to generate a selection signal, but only needs to receive the selection signal. Therefore, the first processing unit can be a processing unit provided by any of the above embodiments, such as Figure 1 and Figure 4 As shown, the structure includes: a first selection module, a second selection module, a data processing module, a selection signal generation module, a first delay module or a second delay module; compared with the first processing unit, the second processing unit does not need to include a selection signal generation module, such as Figure 2 and Figure 3 As shown, it may include: a first selection module, a second selection module, a data processing module, etc. It should be noted that in this embodiment, the second processing unit may include a first delay module or a second delay module, or may not include the first delay module and the second delay module, depending on the specific situation.

[0133] Since the structures and working principles of the first selection module, the second selection module, the data processing module, the selection signal generating module, the first delay module and the second delay module have been described in the various embodiments of the processing unit, they will not be repeated here.

[0134] Optionally, in one embodiment of the present application, Fig.11 As shown, the first column processing unit PE and the last column processing unit PE of each row processing unit in the m×n processing units PE are provided with a first delay module Input REG1, and the first row processing unit PE and the last row processing unit PE of each column processing unit PE are provided with a second delay module Input REG2. However, this application does not limit this, and it depends on the specific situation.

[0135] Based on the above embodiments, in one embodiment of the present application, Fig.12 As shown, Fig.12 for Fig.11A partial enlarged view of the systolic array, wherein the systolic array includes a first processing unit 101 and a second processing unit 102 that are adjacent to each other in a first dimension X, wherein a first output port a1o of the first processing unit 101 is connected to a first input port a1i of the second processing unit 102, and a second input port a2i of the first processing unit 101 is connected to a second output port a2o of the second processing unit 102. It should be noted that the first processing unit 101 and the second processing unit 102 may be any two adjacent processing units in the systolic array in the first dimension X;

[0136] The systolic array includes a first processing unit 103 and a second processing unit 104 that are adjacent to each other in the second dimension Y. The third output port b1o of the first processing unit 103 is connected to the third input port b1i of the second processing unit 104. The fourth input port b2i of the first processing unit 103 is connected to the fourth output port b2o of the second processing unit 104. It should be noted that the first processing unit 103 and the second processing unit 104 can be any two adjacent processing units in the systolic array in the second dimension Y.

[0137] It should be noted that, in the above embodiment, Fig.12 As shown, in the row direction, any processing unit also receives the third data psumo output by its upstream processing unit, and outputs the third data psumo generated by it to its downstream processing unit.

[0138] Optionally, in one embodiment of the present application, continue as Fig.11 As shown, the second processing unit PE_2 located in several diagonal directions parallel to the diagonal direction of the array is connected to the selection signal output end of the first processing unit PE_1 in the diagonal direction, so that the selection signals input to the control ends of all processing units located in the same diagonal direction in the systolic array are the same.

[0139] For ease of description, the i-th row and j-th column is represented by PE(i, j). For example, the processing unit in the first row and first column is represented by PE(1, 1), the processing unit in the first row and second column is represented by PE(1, 2), the processing unit in the second row and first column is represented by PE(2, 1), the processing unit in the first row and second column is represented by PE(2, 2), and so on. Fig.13 As shown, Fig.13 The coordinates of each processing unit when the systolic array includes 5×5 processing units are shown. In this embodiment, PE (1, 1) is the first processing unit, which generates a selection signal as its own selection signal;

[0140] PE (1, 2) is a first processing unit, generating and outputting a selection signal; PE (2, 1) is a second processing unit, whose selection signal input terminal is connected to the selection signal output terminal of PE (1, 2) and inputs the selection signal output by PE (1, 2);

[0141] PE (1, 3) is a first processing unit, generating and outputting a selection signal; PE (2, 2) and PE (3, 1) are second processing units, whose selection signal input terminals are connected to the selection signal output terminals of PE (1, 3) and input the selection signal output by PE (1, 3);

[0142] PE (1, 4) is a first processing unit, generating and outputting a selection signal; PE (2, 3) and PE (3, 2) and PE (4, 1) are second processing units, whose selection signal input terminals are connected to the selection signal output terminals of PE (1, 4) and input the selection signal output by PE (1, 4);

[0143] PE (1, 5) is a first processing unit, generating and outputting a selection signal; PE (2, 4) and PE (3, 3), PE (4, 2), and PE (5, 1) are second processing units, whose selection signal input terminals are connected to the selection signal output terminals of PE (1, 5) and input the selection signal output by PE (1, 5);

[0144] PE (2, 5) is a first processing unit, generating and outputting a selection signal; PE (3, 4) and PE (4, 3) and PE (5, 2) are second processing units, whose selection signal input terminals are connected to the selection signal output terminals of PE (2, 5) and input the selection signal output by PE (2, 5);

[0145] And so on. That is, in the systolic array, the selection signals corresponding to the processing unit in the i-th row and j-th column and the processing unit in the r-th row and s-th column are the same, where i+j=r+s, i and r are integers not less than 1 and not greater than m, and j and s are integers not less than 1 and not greater than n.

[0146] Optionally, based on any of the above embodiments, in one embodiment of the present application, m=n, so that the systolic array can input the data matrix in two different directions on the same dimension, thereby improving the operation speed of the systolic array and the pipeline operation efficiency. However, the present application is not limited to this. In other embodiments of the present application, m may not be equal to n. If m is not equal to n, the systolic array can input the data matrix in one direction on the same dimension.

[0147] Accordingly, an embodiment of the present application further provides an electronic device, which may include the systolic array provided in any of the above embodiments, or may include a systolic array composed of processing units in the systolic array provided in any of the above embodiments, and the present application does not limit this, and the specific situation depends on the specific situation. It should be noted that since the relevant content about the systolic array and the relevant content about the processing unit in the systolic array have been described in the above embodiments, they will not be repeated here.

[0148] In addition, an embodiment of the present application further provides a data processing method, which is applied to the systolic array provided in any of the above embodiments, wherein the systolic array includes m×n processing units, and the processing units have a first group of data transmission paths for transmitting data in the row direction and a second group of data transmission paths for transmitting data in the column direction, wherein the first group of data transmission paths transmits first data, and the second group of data transmission paths transmits second data; each group includes two data transmission directions, specifically, the first group of data transmission paths includes a first data transmission path for transmitting data along a first direction and a second data transmission path for transmitting data along a second direction, and the second group of data transmission paths includes a third data transmission path for transmitting data along a third direction and a fourth data transmission path for transmitting data along a fourth direction. Since the relevant description of the systolic array has been described in the above embodiments, the present application will not repeat it here.

[0149] Specifically, in one embodiment of the present application, if m=n, the data processing method includes: at the same time, controlling the processing unit in the i-th row and j-th column to transmit the first data through the first data transmission path, and transmitting the second data through the third data transmission path, and controlling the processing unit in the m+1-i-th row and n+1-j-th column to transmit the first data through the second data transmission path, and transmitting the second data through the fourth data transmission path; and the processing unit in the i-th row and j-th column and the processing unit in the r-th row and s-th column transmit data at the same time; wherein, i+j=r+s, i and r are integers not less than 1 and not greater than m respectively, and j and s are integers not less than 1 and not greater than n respectively.

[0150] Taking the example that the systolic array includes 5×5 processing units, the data matrix input process in the systolic array is described. Fig.13 As shown, PE (1, 1) transmits first data through the first data transmission path a1 and transmits second data through the third data transmission path b1, while PE (5, 5) transmits first data through the second data transmission path a2 and transmits second data through the fourth data transmission path b2;

[0151] PE (1, 2) receives and transmits the first data transmitted by PE (1, 1) through the first data transmission path a1 and receives and transmits the second data transmitted by PE (1, 1) through the third data transmission path b1, while PE (5, 4) receives and transmits the first data transmitted by PE (5, 5) through the second data transmission path a2 and receives and transmits the second data transmitted by PE (5, 5) through the fourth data transmission path b2; PE (2, 1) receives and transmits the first data transmitted by PE (1, 1) through the first data transmission path a1 and receives and transmits the second data transmitted by PE (1, 1) through the third data transmission path b1, while PE (4, 5) receives and transmits the first data transmitted by PE (5, 5) through the second data transmission path a2 and receives and transmits the second data transmitted by PE (5, 5) through the fourth data transmission path b2; and PE (1, 2) and PE (2, 1) transmit data simultaneously;

[0152] Similarly, PE(1,3) and PE(5,3) transmit data simultaneously, PE(3,1) and PE(3,5) transmit data simultaneously, PE(2,2) and PE(4,4) transmit data simultaneously, PE(1,3), PE(3,1) and PE(2,2) transmit data simultaneously; PE(5,3), PE(3,5) and PE(4,4) transmit data simultaneously;

[0153] PE(1,4) and PE(5,2) transmit data simultaneously, PE(4,1) and PE(2,5) transmit data simultaneously, PE(2,3) and PE(4,3) transmit data simultaneously, PE(3,2) and PE(3,4) transmit data simultaneously, PE(1,4), PE(2,3), PE(3,2) and PE(4,1) transmit data simultaneously, PE(5,2), PE(4,3), PE(3,4) and PE(2,5) transmit data simultaneously;

[0154] PE(1,5), PE(2,4), PE(3,3), PE(4,2), and PE(5,1) transmit data simultaneously.

[0155] It can be seen that the systolic array provided in the embodiment of the present application uses a plurality of processing units to input data from different directions at the same time to input a data matrix, thereby improving the operating speed and pipeline operating efficiency of the systolic array.

[0156] Optionally, in one embodiment of the present application, in the row direction, starting from the first column, the second data of each column in the second data matrix starting from the first column is input to the first row processing unit of each subsequent column one cycle later, and each second data in the second data array of each column is transferred to the processing unit of the next row row by row according to the data transmission cycle; at the same time, starting from the last column, the second data of each column in the second data matrix starting from the last column is input to the last row processing unit of each previous column one cycle later, and each second data in the second data array of each column is transferred to the processing unit of the previous row row by row according to the data transmission cycle;

[0157] In the column direction, starting from the first row, the first data of each row in the first data matrix starting from the first row is input to the first column processing units of each subsequent row one cycle later, and each first data in the first data array of each row is transferred to the processing units of the next column column by column according to the data transmission cycle; at the same time, starting from the last row, the first data of each row in the first data matrix starting from the last row is input to the last column processing units of the previous rows one cycle later, and each first data in the first data array of each row is transferred to the processing units of the previous column column by column according to the data transmission cycle.

[0158] It should be noted that the first data matrix is ​​a data matrix composed of a plurality of first data, and the second data matrix is ​​a data matrix composed of a plurality of second data.

[0159] Taking the systolic array including 5×5 processing units as an example, the data matrix input process in the systolic array is described. Optionally, in this embodiment, when the systolic array includes 5×5 processing units, the first data matrix is: The second data matrix is:

[0160] In this embodiment, if Figure 14-Figure 24 As shown, when the first data matrix and the second data matrix are input into the systolic array including 5×5 processing units, the data matrix input process of the systolic array includes:

[0161] In the first data transmission cycle T1, PE(1,1) inputs data a0,0 and b0,0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0*b0,0, and transmits a0,0 and b0,0 to the two downstream processing units PE(1,2) and PE(2,1) according to the transmission direction; at the same time, PE(5,5) inputs data a4,0 and b0,4 through the second data transmission path a2 and the fourth data transmission path b2, and transmits a4,0 and b0,4 to the two downstream processing units PE(4,5) and PE(5,4) according to the transmission direction, and generates third data a4,0*b0,4, so that the systolic matrix is ​​changed from Fig.15 Transformed to Fig.16 It should be noted that, in addition to processing data, the processing unit also needs to transmit the received first data and second data to the downstream processing unit PE according to the input transmission direction, which will not be repeated below.

[0162] In the second data transmission cycle T2, if Fig.17 As shown, PE (1, 1) inputs data a0,1 and b1,0 through the first data transmission path a1 and the third data transmission path b1, and the generated third data is a0,0*b0,0+a0,1*b1,0;

[0163] PE (1, 2) inputs data a0,0 and b0,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,1;

[0164] PE (2, 1) inputs data a1, 0 and b0, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a1, 0 × b0, 0;

[0165] At the same time, PE (5, 5) inputs data a4,1 and b1,4 through the second data transmission path a2 and the fourth data transmission path b2, and the generated third data is a4,0*b0,4+a4,1*b1,4;

[0166] PE (5, 4) inputs data a4,0 and b0,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,3;

[0167] PE (4, 5) inputs data a3,0 and b0,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,4;

[0168] In the third data transmission cycle T3, if Fig.18 As shown, PE (1, 1) inputs data a0, 2 and b2, 0 through the first data transmission path a1 and the third data transmission path b1, and the generated third data is: a0, 0*b0, 0+a0, 1*b1, 0+a0, 2*b2, 0;

[0169] PE (1, 2) inputs data a0,1 and b1,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,1+a0,1×b1,1;

[0170] PE (1, 3) inputs data a0,0 and b0,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,2;

[0171] PE(2,1) inputs data a1,1 and b1,0 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,0+a1,1×b1,0;

[0172] PE (3, 1) inputs data a2, 0 and b0, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2, 0 × b0, 0;

[0173] PE (2, 2) inputs data a1,0 and b0,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a1,0×b0,1;

[0174] At the same time, PE (5, 5) inputs data a4,2 and b2,4 through the second data transmission path a2 and the fourth data transmission path b2, and the generated third data is a4,0*b0,4+a4,1*b1,4+a4,2*b2,4;

[0175] PE (5, 4) inputs data a4,1 and b1,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,3+a4,1×b1,3;

[0176] PE (5, 3) inputs data a4, 0 and b0, 2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4, 0 × b0, 2;

[0177] PE (4, 5) inputs data a3,1 and b1,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,4+a3,1×b1,4;

[0178] PE (3, 5) inputs data a2,0 and b0,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,4;

[0179] PE (4, 4) inputs data a3,0 and b0,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,3;

[0180] In the fourth data transmission cycle T4, Fig.19 As shown, PE (1, 1) inputs data a0,3 and b3,0 through the first data transmission path a1 and the third data transmission path b1, and the generated third data is: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0;

[0181] PE(1,2) inputs data a0,2 and b2,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,1+a0,1×b1,1+a0,2×b2,1;

[0182] PE(1,3) inputs data a0,1 and b1,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,2+a0,1×b1,2;

[0183] PE (1, 4) inputs data a0,0 and b0,3 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,3;

[0184] PE(2,1) inputs data a1,2 and b2,0 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0;

[0185] PE (2, 2) inputs data a1,1 and b1,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,1+a1,1×b1,1;

[0186] PE (2, 3) inputs data a1,0 and b0,2 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,2;

[0187] PE (3, 1) inputs data a2, 1 and b1, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0, 0+a2.1×b1, 0;

[0188] PE (3, 2) inputs data a2,0 and b0,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,1;

[0189] PE (4, 1) inputs data a3, 0 and b0, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0, 0;

[0190] At the same time, PE (5, 5) inputs data a4,3 and b3,4 through the second data transmission path a2 and the fourth data transmission path b2, and the generated third data is a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4;

[0191] PE(5,4) inputs data a4,2 and b2,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,3+a4,1×b1,3+a4,2×b2,3;

[0192] PE (5, 3) inputs data a4,1 and b1,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,2+a4,1×b1,2;

[0193] PE (5, 2) inputs data a4, 0 and b0, 1 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4, 0 × b0, 1;

[0194] PE (4, 5) inputs data a3, 2 and b2, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3, 0 × b0, 4 + a3, 1 × b1, 4 + a3, 2 × b2, 4;

[0195] PE(4,4) inputs data a3,1 and b1,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,3+a3,1×b1,3;

[0196] PE (4, 3) inputs data a3, 0 and b0, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3, 0 × b0, 2;

[0197] PE (3, 5) inputs data a2,1 and b1,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,4+a2,1×b1,4;

[0198] PE (3, 4) inputs data a2,0 and b0,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,3;

[0199] PE (2, 5) inputs data a1, 0 and b0, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a1, 0 × b0, 4;

[0200] In the fifth data transmission cycle T5, if Fig. 20As shown, PE (1, 1) inputs data a0,4 and b4,0 through the first data transmission path a1 and the third data transmission path b1, and the generated third data is: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0+a0,4×b4,0;

[0201] PE(1,2) inputs data a0,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,1+a0,1×b1,1+a0,2×b2,1+a0,3 and b3,1;

[0202] PE(1,3) inputs data a0,2 and b2,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,2+a0,1×b1,2+a0,2×b2,2;

[0203] PE (1, 4) inputs data a0, 1 ​​and b1, 3 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0 × b0, 3 + a0, 1 ​​× b1, 3;

[0204] PE (1, 5) inputs data a0, 0 and b0, 4 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0 × b0, 4;

[0205] PE(2,1) inputs data a1,3 and b3,0 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0+a1,3×b3,0;

[0206] PE(2,2) inputs data a1,2 and b2,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,1+a1,1×b1,1+a1,2×b2,1;

[0207] PE (2, 3) inputs data a1,1 and b1,2 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,2+a1,1×b1,2;

[0208] PE (2, 4) inputs data a1,0 and b0.3 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,3;

[0209] PE (3, 1) inputs data a2, 2 and b2, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0, 0+a2.1×b1, 0+a2, 2×b2, 0;

[0210] PE (3, 2) inputs data a2,1 and b1,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,1a2,1×b1,1;

[0211] PE (3, 3) inputs data a2,0 and b0,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,2;

[0212] PE (4, 1) inputs data a3, 1 and b1, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0, 0+a3, 1×b1, 0;

[0213] PE (4, 2) inputs data a3,0 and b0,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0,1;

[0214] PE (5, 1) inputs data a4, 0 and b0, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a4.0×b0, 0;

[0215] At the same time, PE (5, 5) inputs data a4,4 and b4,4 through the second data transmission path a2 and the fourth data transmission path b2, and the generated third data is a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4+a4,4×b4,4;

[0216] PE(5,4) inputs data a4,3 and b3,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,3+a4,1×b1,3+a4,2×b2,3+a4,3×b3,3;

[0217] PE(5,3) inputs data a4,2 and b2,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,2+a4,1×b1,2+a4,2×b2,2;

[0218] PE (5, 2) inputs data a4,1 and b1,1 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,1+a4,1×b1,1;

[0219] PE (4, 5) inputs data a3,3 and b3,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,4+a3,1×b1,4+a3,2×b2,4+a3,3×b3,4;

[0220] PE(4,4) inputs data a3,2 and b2,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,3+a3,1×b1,3+a3,2×b2,4;

[0221] PE (4, 3) inputs data a3,1 and b1,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,2+a3,1×b1,2;

[0222] PE (3, 5) inputs data a2,2 and b2,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,4+a2,1×b1,4+a2,2×b2,4;

[0223] PE (3, 4) inputs data a2,1 and b1,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,3+a2,1×b1,3;

[0224] PE (2, 5) inputs data a1, 1 and b1, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a1, 0×b0, 4+a1, 1×b1, 4;

[0225] In the sixth data transmission cycle T6, if Fig.21 As shown, PE (1, 1) no longer inputs data, and the third data is maintained as: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0+a0,4×b4,0;

[0226] PE(1,2) inputs data a0,4 and b4,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,1+a0,1×b1,1+a0,2×b2,1+a0,3 and b3,1+a0,4×b4,1;

[0227] PE(1,3) inputs data a0,3 and b3,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,2+a0,1×b1,2+a0,2×b2,2+a0,3×b3,2;

[0228] PE (1, 4) inputs data a0, 2 and b2, 3 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0×b0, 3+a0, 1×b1, 3+a0, 2×b2, 3;

[0229] PE (1, 5) inputs data a0, 1 ​​and b1, 4 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0×b0, 4+a0, 1×b1, 4;

[0230] PE(2,1) inputs data a1,4 and b4,0 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0+a1,3×b3,0+a1,4×b4,0;

[0231] PE(2,2) inputs data a1,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,1+a1,1×b1,1+a1,2×b2,1+a1,3×b3,1;

[0232] PE (2, 3) inputs data a1, 2 and b2, 2 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1, 0 × b0, 2 + a1, 1 × b1, 2 + a1, 2 × b2, 2;

[0233] PE (2, 4) inputs data a1,1 and b1.3 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,3+a1,1×b1.3;

[0234] PE (3, 1) inputs data a2, 3 and b3, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0, 0+a2.1×b1, 0+a2, 2×b2, 0+a2, 3×b3, 0;

[0235] PE (3, 2) inputs data a2,2 and b2,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,1+a2,1×b1,1+a2,2×b2,1;

[0236] PE (3, 3) inputs data a2,1 and b1,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,2+a2.1×b1,2;

[0237] PE (4, 1) inputs data a3, 2 and b2, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0, 0+a3, 1×b1, 0+a3, 2×b2, 0;

[0238] PE (4, 2) inputs data a3,1 and b1,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0,1+a3,1×b1,1;

[0239] PE (5, 1) inputs data a4, 1 and b1, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a4.0×b0, 0+a4, 1×b1, 0;

[0240] At the same time, PE(5,5) no longer inputs data and maintains the third data as a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4+a4,4×b4,4;

[0241] PE(5,4) inputs data a4,4 and b4,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,3+a4,1×b1,3+a4,2×b2,3+a4,3×b3,3+a4,4×b4,3;

[0242] PE(5,3) inputs data a4,3 and b3,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,2+a4,1×b1,2+a4,2×b2,2+a4,3×b3,2;

[0243] PE(5,2) inputs data a4,2 and b2,1 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,1+a4,1×b1,1+a4,2×b2,1;

[0244] PE (4, 5) inputs data a3, 4 and b4, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3, 0 × b0, 4 + a3, 1 × b1, 4 + a3, 2 × b2, 4 + a3, 3 × b3, 4 + a3, 4 × b4, 4;

[0245] PE(4,4) inputs data a3,3 and b2,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,3+a3,1×b1,3+a3,2×b2,4+a3,3×b3,4;

[0246] PE(4,3) inputs data a3,2 and b2,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,2+a3,1×b1,2+a3,2×b2,2;

[0247] PE (3, 5) inputs data a2, 3 and b3, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2, 0 × b0, 4 + a2, 1 × b1, 4 + a2, 2 × b2, 4 + a2, 3 × b3, 4;

[0248] PE (3, 4) inputs data a2,2 and b2,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,3+a2,1×b1,3+a2,2×b2,3;

[0249] PE (2, 5) inputs data a1, 2 and b2, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a1, 0 × b0, 4 + a1, 1 × b1, 4 + a1, 2 × b2, 4;

[0250] In the seventh data transmission cycle T7, if Fig. 22 As shown, PE (1, 1) no longer inputs data, and the third data is maintained as: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0+a0,4×b4,0;

[0251] PE(1,2) no longer inputs data and keeps the third data as a0,0×b0,1+a0,1×b1,1+a0,2×b2,1+a0,3 and b3,1+a0,4×b4,1;

[0252] PE(1,3) inputs data a0,4 and b4,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,2+a0,1×b1,2+a0,2×b2,2+a0,3×b3,2+a0,4×b4,2;

[0253] PE(1,4) inputs data a0,3 and b3,3 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,3+a0,1×b1,3+a0,2×b2,3+a0,3×b3,3;

[0254] PE (1, 5) inputs data a0, 2 and b2, 4 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0×b0, 4+a0, 1×b1, 4+a0, 2×b2, 4;

[0255] PE(2,1) no longer inputs data and keeps the third data as: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0+a1,3×b3,0+a1,4×b4,0;

[0256] PE(2,2) inputs data a1,4 and b4,1 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,1+a1,1×b1,1+a1,2×b2,1+a1,3×b3,1+a1,4×b4,1;

[0257] PE(2,3) inputs data a1,3 and b3,2 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,2+a1,1×b1,2+a1,2×b2,2+a1,3×b3,2;

[0258] PE (2, 4) inputs data a1,2 and b2.3 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,3+a1,1×b1.3+a1,2×b2.3;

[0259] PE(3,1) inputs data a2,4 and b4,0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,0+a2.1×b1,0+a2,2×b2,0+a2,3×b3,0+a2,4×b4,0;

[0260] PE(3,2) inputs data a2,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,1+a2,1×b1,1+a2,2×b2,1+a2,3×b3,1;

[0261] PE (3, 3) inputs data a2,2 and b2,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,2+a2.1×b1,2+a2,2×b2,2;

[0262] PE (4, 1) inputs data a3, 3 and b3, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0, 0+a3, 1×b1, 0+a3, 2×b2, 0+a3, 3×b3, 0;

[0263] PE (4, 2) inputs data a3, 2 and b2, 1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0, 1+a3, 1×b1, 1+a3, 2×b2, 1;

[0264] PE (5, 1) inputs data a4, 2 and b2, 0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a4.0×b0, 0+a4, 1×b1, 0+a4, 2×b2, 0;

[0265] At the same time, PE(5,5) no longer inputs data and maintains the third data as a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4+a4,4×b4,4;

[0266] PE(5,4) no longer inputs data and keeps the third data as a4,0×b0,3+a4,1×b1,3+a4,2×b2,3+a4,3×b3,3+a4,4×b4,3;

[0267] PE(5,3) inputs data a4,4 and b4,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,2+a4,1×b1,2+a4,2×b2,2+a4,3×b3,2+a4,4×b4,2;

[0268] PE(5,2) inputs data a4,3 and b3,1 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,1+a4,1×b1,1+a4,2×b2,1+a4,3×b3,1;

[0269] PE(4,5) no longer inputs data and keeps the third data as a3,0×b0,4+a3,1×b1,4+a3,2×b2,4+a3,3×b3,4+a3,4×b4,4;

[0270] PE(4,4) inputs data a3,4 and b4,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,3+a3,1×b1,3+a3,2×b2,4+a3,3×b3,4+a3,4×b4,3;

[0271] PE(4,3) inputs data a3,3 and b3,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,2+a3,1×b1,2+a3,2×b2,2+a3,3×b3,2;

[0272] PE (3, 5) inputs data a2,4 and b4,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,4+a2,1×b1,4+a2,2×b2,4+a2,3×b3,4+a2,4×b4,4;

[0273] PE (3, 4) inputs data a2,3 and b3,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,3+a2,1×b1,3+a2,2×b2,3+a2,3×b3,3;

[0274] PE (2, 5) inputs data a1, 3 and b3, 4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a1, 0 × b0, 4 + a1, 1 × b1, 4 + a1, 2 × b2, 4 + a1, 3 × b3, 4;

[0275] In the eighth data transmission cycle T8, if Fig.23 As shown, PE (1, 1) no longer inputs data, and the third data is maintained as: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0+a0,4×b4,0;

[0276] PE(1,2) no longer inputs data and keeps the third data as a0,0×b0,1+a0,1×b1,1+a0,2×b2,1+a0,3 and b3,1+a0,4×b4,1;

[0277] PE(1,3) no longer inputs data and keeps the third data as a0,0×b0,2+a0,1×b1,2+a0,2×b2,2+a0,3×b3,2+a0,4×b4,2;

[0278] PE(1,4) inputs data a0,4 and b4,3 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,3+a0,1×b1,3+a0,2×b2,3+a0,3×b3,3+a0,4×b4,3;

[0279] PE (1, 5) inputs data a0, 3 and b3, 4 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0, 0×b0, 4+a0, 1×b1, 4+a0, 2×b2, 4+a0, 3×b3, 4;

[0280] PE(2,1) no longer inputs data and keeps the third data as: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0+a1,3×b3,0+a1,4×b4,0;

[0281] PE(2,2) no longer inputs data and keeps the third data as: a1,0×b0,1+a1,1×b1,1+a1,2×b2,1+a1,3×b3,1+a1,4×b4,1;

[0282] PE(2,3) inputs data a1,4 and b4,2 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,2+a1,1×b1,2+a1,2×b2,2+a1,3×b3,2+a1,4×b4,2;

[0283] PE (2, 4) inputs data a1,3 and b3.3 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,3+a1,1×b1.3+a1,2×b2.3+a1,3×b3.3;

[0284] PE(3,1) no longer inputs data and keeps the third data as a2.0×b0,0+a2.1×b1,0+a2,2×b2,0+a2,3×b3,0+a2,4×b4,0;

[0285] PE(3,2) inputs data a2,4 and b4,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,1+a2,1×b1,1+a2,2×b2,1+a2,3×b3,1+a2,4×b4,1;

[0286] PE(3,3) inputs data a2,3 and b3,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,2+a2.1×b1,2+a2,2×b2,2+a2,3×b3,2;

[0287] PE(4,1) inputs data a3,4 and b4,0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0,0+a3,1×b1,0+a3,2×b2,0+a3,3×b3,0+a3,4×b4,0;

[0288] PE (4, 2) inputs data a3,3 and b3,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0,1+a3,1×b1,1+a3,2×b2,1+a3,3×b3,1;

[0289] PE(5,1) inputs data a4,3 and b3,0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a4.0×b0,0+a4,1×b1,0+a4,2×b2,0+a4,3×b3,0;

[0290] At the same time, PE(5,5) no longer inputs data and maintains the third data as a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4+a4,4×b4,4;

[0291] PE(5,4) no longer inputs data and keeps the third data as a4,0×b0,3+a4,1×b1,3+a4,2×b2,3+a4,3×b3,3+a4,4×b4,3;

[0292] PE(5,3) no longer inputs data and keeps the third data as a4,0×b0,2+a4,1×b1,2+a4,2×b2,2+a4,3×b3,2+a4,4×b4,2;

[0293] PE(5,2) inputs data a4,4 and b4,1 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a4,0×b0,1+a4,1×b1,1+a4,2×b2,1+a4,3×b3,1+a4,4×b4,1;

[0294] PE(4,5) no longer inputs data and keeps the third data as a3,0×b0,4+a3,1×b1,4+a3,2×b2,4+a3,3×b3,4+a3,4×b4,4;

[0295] PE(4,4) no longer inputs data and keeps the third data as a3,0×b0,3+a3,1×b1,3+a3,2×b2,4+a3,3×b3,4+a3,4×b4,3;

[0296] PE(4,3) inputs data a3,4 and b4,2 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a3,0×b0,2+a3,1×b1,2+a3,2×b2,2+a3,2×b3,2+a3,4×b4,2;

[0297] PE(3,5) no longer inputs data and keeps the third data as a2,0×b0,4+a2,1×b1,4+a2,2×b2,4+a2,3×b3,4+a2,4×b4,4;

[0298] PE(3,4) inputs data a2,4 and b4,3 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a2,0×b0,3+a2,1×b1,3+a2,2×b2,3+a2,3×b3,3+a2,4×b4,3;

[0299] PE(2,5) inputs data a1,4 and b4,4 through the second data transmission path a2 and the fourth data transmission path b2, and generates third data a1,0×b0,4+a1,1×b1,4+a1,2×b2,4+a1,3×b3,4+a1,4×b4,4;

[0300] In the ninth data transmission cycle T9, if Fig.24 As shown, PE (1, 1) no longer inputs data, and the third data is maintained as: a0,0*b0,0+a0,1*b1,0+a0,2*b2,0+a0,3×b3,0+a0,4×b4,0;

[0301] PE(1,2) no longer inputs data and keeps the third data as a0,0×b0,1+a0,1×b1,1+a0,2×b2,1+a0,3 and b3,1+a0,4×b4,1;

[0302] PE(1,3) no longer inputs data and keeps the third data as a0,0×b0,2+a0,1×b1,2+a0,2×b2,2+a0,3×b3,2+a0,4×b4,2;

[0303] PE(1,4) no longer inputs data and keeps the third data as a0,0×b0,3+a0,1×b1,3+a0,2×b2,3+a0,3×b3,3+a0,4×b4,3;

[0304] PE(1,5) inputs data a0,4 and b4,4 through the first data transmission path a1 and the third data transmission path b1, and generates third data a0,0×b0,4+a0,1×b1,4+a0,2×b2,4+a0,3×b3,4+a0,4×b4,4;

[0305] PE(2,1) no longer inputs data and keeps the third data as: a1,0×b0,0+a1,1×b1,0+a1,2×b2,0+a1,3×b3,0+a1,4×b4,0;

[0306] PE(2,2) no longer inputs data and keeps the third data as: a1,0×b0,1+a1,1×b1,1+a1,2×b2,1+a1,3×b3,1+a1,4×b4,1;

[0307] PE(2,3) no longer inputs data and keeps the third data as: a1,0×b0,2+a1,1×b1,2+a1,2×b2,2+a1,3×b3,2+a1,4×b4,2;

[0308] PE(2,4) inputs data a1,4 and b4.3 through the first data transmission path a1 and the third data transmission path b1, and generates the third data: a1,0×b0,3+a1,1×b1.3+a1,2×b2.3+a1,3×b3.3+a1,4×b4.3;

[0309] PE(3,1) no longer inputs data and keeps the third data as a2.0×b0,0+a2.1×b1,0+a2,2×b2,0+a2,3×b3,0+a2,4×b4,0;

[0310] PE(3,2) no longer inputs data and keeps the third data as a2.0×b0,1+a2,1×b1,1+a2,2×b2,1+a2,3×b3,1+a2,4×b4,1;

[0311] PE(3,3) inputs data a2,4 and b4,2 through the first data transmission path a1 and the third data transmission path b1, and generates third data a2.0×b0,2+a2.1×b1,2+a2,2×b2,2+a2,3×b3,2+a2,4×b4,2;

[0312] PE(4,1) no longer inputs data and keeps the third data as a3.0×b0,0+a3,1×b1,0+a3,2×b2,0+a3,3×b3,0+a3,4×b4,0;

[0313] PE(4,2) inputs data a3,4 and b4,1 through the first data transmission path a1 and the third data transmission path b1, and generates third data a3.0×b0,1+a3,1×b1,1+a3,2×b2,1+a3,3×b3,1+a3,4×b4,1;

[0314] PE(5,1) inputs data a4,4 and b4,0 through the first data transmission path a1 and the third data transmission path b1, and generates third data a4.0×b0,0+a4,1×b1,0+a4,2×b2,0+a4,3×b3,0+a4,4×b4,0;

[0315] At the same time, PE(5,5) no longer inputs data and maintains the third data as a4,0*b0,4+a4,1*b1,4+a4,2*b2,4+a4,3×b3,4+a4,4×b4,4;

[0316] PE(5,4) no longer inputs data and keeps the third data as a4,0×b0,3+a4,1×b1,3+a4,2×b2,3+a4,3×b3,3+a4,4×b4,3;

[0317] PE(5,3) no longer inputs data and keeps the third data as a4,0×b0,2+a4,1×b1,2+a4,2×b2,2+a4,3×b3,2+a4,4×b4,2;

[0318] PE(5,2) no longer inputs data and keeps the third data as a4,0×b0,1+a4,1×b1,1+a4,2×b2,1+a4,3×b3,1+a4,4×b4,1;

[0319] PE(4,5) no longer inputs data and keeps the third data as a3,0×b0,4+a3,1×b1,4+a3,2×b2,4+a3,3×b3,4+a3,4×b4,4;

[0320] PE(4,4) no longer inputs data and keeps the third data as a3,0×b0,3+a3,1×b1,3+a3,2×b2,4+a3,3×b3,4+a3,4×b4,3;

[0321] PE(4,3) no longer inputs data and keeps the third data as a3,0×b0,2+a3,1×b1,2+a3,2×b2,2+a3,2×b3,2+a3,4×b4,2;

[0322] PE(3,5) no longer inputs data and keeps the third data as a2,0×b0,4+a2,1×b1,4+a2,2×b2,4+a2,3×b3,4+a2,4×b4,4;

[0323] PE(3,4) no longer inputs data and keeps the third data as a2,0×b0,3+a2,1×b1,3+a2,2×b2,3+a2,3×b3,3+a2,4×b4,3;

[0324] PE(2,5) no longer inputs data and keeps the third data as a1,0×b0,4+a1,1×b1,4+a1,2×b2,4+a1,3×b3,4+a1,4×b4,4.

[0325] After the above nine cycles, the input and calculation of the data matrix in the systolic array are completed.

[0326] Optionally, in one embodiment of the present application, according to the data input state of the first row processing unit and the last column processing unit, or the first column processing unit and the last row processing unit in the systolic array, a data transmission path in a corresponding direction is selected so that the processing units in the diagonal direction at the same moment select the same data transmission direction.

[0327] Specifically, in one embodiment of the present application, the systolic array may start to input data from the first row of processing units and the last column of processing units, and the transmission direction of the selection signal thereof is from PE(1, n) to PE(m, 1), referring to Fig.10 , its data transmission path refers to Figure 15-Figure 24 In other embodiments of the present application, the systolic array may also start inputting data from the first column processing unit and the last row processing unit, and the transmission direction of the selection signal is from PE(m, 1) to PE(1, n), referring to Fig.25 This application does not limit this and it depends on the specific circumstances.

[0328] Optionally, in one embodiment of the present application, when the systolic array starts to input data from the first row of processing units and the last column of processing units, the data processing method further includes: after the processing unit in the 1st row and the nth column outputs a third signal, synchronously outputting third data stored in the processing units in each row, wherein the third signal indicates that the data processing process in the processing unit in the 1st row and the nth column is completed.

[0329] In another embodiment of the present application, the data processing method also includes: after the processing unit in the mth row and the first column outputs a third signal, synchronously outputting the third data stored in the processing units in each row, wherein the third signal indicates that the data processing process in the processing unit in the mth row and the first column is completed.

[0330] In other embodiments of the present application, the data processing method may further include: after the other processing units located diagonally opposite to the processing unit in the mth row and the first column or the processing unit in the 1st row and the nth column output the third signal, synchronously outputting the third data stored in the processing units in each row, wherein the third signal indicates that the data processing process in the other processing units located diagonally opposite to the processing unit in the mth row and the first column or the processing unit in the 1st row and the nth column is completed. The present application does not limit this, and the specific situation depends on the situation. Taking m=n=5 as an example, in this embodiment, the data processing method can synchronously output the third data stored in the processing units in each row after any processing unit among PE(1,5), PE(2,4), PE(3,3), PE(4,2) and PE(5,1) outputs the third signal.

[0331] It should be noted that the above embodiments all describe the data processing method by taking the systolic array as an example of using a bidirectional input method on the same dimension when inputting a data matrix, but the present application is not limited to this. In other embodiments of the present application, the systolic array can also use a unidirectional input data matrix method on the same dimension to process data.

[0332] Optionally, in one embodiment of the present application, if the systolic array adopts a unidirectional input data matrix in the same dimension, the data processing method includes:

[0333] In the row direction, starting from the first column, the second data of each column in the second data matrix starting from the first column is input to the first row processing unit of each subsequent column one cycle later, and each second data in the second data array of each column is transmitted to the processing unit of the next row row by row according to the data transmission cycle;

[0334] In the column direction, starting from the first row, the first data of each row in the first data matrix starting from the first row are input to the first column processing units of each subsequent row one cycle later, and each first data in the first data array of each row is transmitted to the processing units of the next column column by column according to the data transmission cycle.

[0335] Since data transmission is performed in only one direction, in this embodiment, the first selection module of each processing unit PE in the systolic array selects the data transmission channel in the same direction for transmission in the row direction, and the second selection module of each processing unit PE in the systolic array selects the data transmission channel in the same direction for transmission in the column direction.

[0336] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the method further comprises: after the processing unit in the i-th row and the n-th column outputs the third signal, the data stored in the processing unit in the i-th row is output; the third signal indicates that the data processing process in the processing unit in the i-th row and the n-th column is completely completed. That is, when the data processing method adopts a bidirectional input data matrix on the same dimension, since the data processing process of each row will end at the same time, the third data stored in the processing units in each row can be output synchronously at one time after the data processing processes in all processing units are completely completed; and when the data processing method adopts a unidirectional input data matrix on the same dimension, since the data calculation of each row ends at different times, it is necessary to output the third data stored in each processing unit in the row after the data processing process in the processing unit in each row is completely completed.

[0337] It should be noted that, although the above embodiments are described by taking the systolic array outputting the third data along the row direction as an example, the present application is not limited to this. In other embodiments of the present application, the systolic array may also output the third data along the column direction, depending on the specific situation. If the systolic array outputs the third data along the column direction, taking the systolic array using bidirectional input data in the same dimension as an example, the data processing method includes:

[0338] After the processing unit in the first row and the nth column outputs the third signal, the third data stored in the processing unit in each column is synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the first row and the nth column is completed; or,

[0339] After the processing unit in the mth row and the first column outputs the third signal, the third data stored in the processing units in each column are synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the mth row and the first column is completed.

[0340] In another embodiment of the present application, if the systolic array adopts a unidirectional input data matrix in the same dimension, the data processing method includes:

[0341] Starting from the last column, one cycle is delayed in sequence, and the second data of each column in the second data matrix starting from the last column is respectively input to the last row processing units of the previous columns, and each second data in the second data array of each column is transmitted row by row to the processing units of the previous row according to the data transmission cycle;

[0342] Starting from the last row, the first data of each row in the first data matrix starting from the last row is input to the last column processing units of the previous rows one cycle later, and each first data in the first data array of each row is transmitted to the processing units of the previous columns column by column according to the data transmission cycle.

[0343] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the method further comprises: after the processing unit in the ith row and the first column outputs the third signal, the data stored in the processing unit in the ith row is output; the third signal indicates that the data processing process in the processing unit in the ith row and the first column is completely completed. That is, when the data processing method adopts a bidirectional input data matrix on the same dimension, the third data stored in the processing units in each row are synchronously output after the data processing processes in all processing units are completely completed; and when the data processing method adopts a unidirectional input data matrix on the same dimension, the third data stored in each processing unit in the row is output after the data processing processes in the processing units in each row are completely completed.

[0344] Optionally, in one embodiment of the present application, Fig.26 As shown, the data processing method sequentially outputs the third data psum stored in each processing unit in the same row of processing units from one side of the pulsation matrix. Optionally, regardless of whether the data processing method adopts a unidirectional data matrix input or a bidirectional data matrix input, the data processing method can sequentially transfer the third data psum stored in each processing unit from one side of the pulsation matrix to the output direction, so as to sequentially output the third data stored in each processing unit in the same row of processing units to the cache, thereby realizing the output and storage of the third data in each processing unit. This application does not limit this, and it depends on the specific situation. Fig. 27 and Fig.28 As shown, Fig. 27 A schematic diagram of an output result after the third data stored in each processing unit in the same row of processing units is outputted row by row from the systolic matrix when the systolic array adopts a bidirectional input data matrix in the same dimension, and the third data stored in the processing units in different rows are outputted synchronously; Fig.28 A schematic diagram of an output result after the third data stored in each processing unit in the same row of processing units is output in sequence from one side of the systolic matrix when the systolic array adopts a unidirectional input data matrix in the same dimension, and the third data stored in the processing units in different rows are output in sequence based on the completion time of the data processing process of the corresponding processing units.

[0345] It should be noted that, in the embodiment of the present application, if m=n in the systolic array, the systolic array can use a bidirectional input data matrix on the same dimension to perform data processing, or can use a unidirectional input data matrix on the same dimension to perform data processing; if m≠n in the systolic array, the systolic array uses a unidirectional input data matrix on the same dimension to perform data processing, or only enables part of the d*d systolic array to realize the bidirectional input function, that is, the other processing units except the d*d processing unit in each m*n processing unit are bypassed or only perform data transmission without performing data processing.

[0346] Since the data processing process of the systolic array using a unidirectional input data matrix is ​​well known to those skilled in the art, this application will not describe it in detail.

[0347] It should be noted that, for both the first data matrix and the second data matrix, which are n×n matrices, when the data processing method uses one direction on the same dimension to input the data matrix, the data processing method is to load the parameters of the first data matrix and the second data matrix in sequence from the horizontal direction (i.e., the first dimension) and the vertical direction (i.e., the second dimension), respectively. When using this calculation method, there will be a large number of idle PE units at the beginning and end of the calculation. The entire data processing requires (3n-2) data transmission cycles, the calculation time is long, and the design difficulty is relatively high. When the data matrix is ​​input in two directions on the same dimension, the entire data processing process can reduce the number of data transmission cycles from (3n-2) to (2n-1), which greatly improves the data processing speed and pipeline operation efficiency of the systolic array.

[0348] Optionally, based on any of the above embodiments, in one embodiment of the present application, the data processing method can be implemented by a hardware circuit and used for data processing of regular algorithms, such as matrix operations, convolution and other algorithms, but the present application does not limit this and it depends on the specific circumstances.

[0349] Optionally, in one embodiment of the present application, the data processing method can be applied to the calculation of a neural network unit, such as the calculation of an AI model, etc. The present application does not limit this and the specific application will depend on the circumstances.

[0350] In addition, the present application also provides an electronic device, such as Fig.29 As shown, the electronic device includes: a systolic array 100, a processor 200 and a memory 300, wherein the systolic array 100 may be the systolic array provided in any of the above embodiments; the memory 300 is used to store a computer program; the processor 200 is used to execute the computer program, so that the electronic device can implement the data processing method provided in any of the above embodiments. Since the relevant contents of the systolic array and the relevant contents of the data processing method have been described in the above embodiments, they will not be repeated again.

[0351] In summary, the electronic device, systolic array and data processing method thereof provided in the embodiments of the present application can input a data matrix into the systolic array by bidirectionally inputting a data matrix in the same dimension, thereby improving the data processing speed and pipeline operation efficiency of the systolic array.

[0352] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0353] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the article or equipment including the above elements.

[0354] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A processing unit in a systolic array, the processing unit having a first set of data transmission paths for transmitting data in a first dimension and a second set of data transmission paths for transmitting data in a second dimension, the first set of data transmission paths being used to transmit first data and the second set of data transmission paths being used to transmit second data; wherein The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction; The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction.

2. A processing unit in a systolic array according to claim 1, The first group of data transmission paths includes a first selection module, the first selection module is used to select the first data transmission path to transmit the first data, or select the second data transmission path to transmit the first data based on a selection signal; The second group of data transmission paths includes a second selection module, and the second selection module selects the third data transmission path to transmit the second data, or selects the fourth data transmission path to transmit the second data based on the selection signal; The processing unit also includes: A data processing module, wherein the data processing module includes a computing unit, wherein the computing unit is located on the data transmission path of the first group of data transmission paths and the second group of data transmission paths, and is used to process the first data and the second data to generate third data, and store the third data.

3. The processing unit in a systolic array of claim 2, wherein the first set of data transmission paths further comprises a first set of output ports located in the first dimension, and the second set of data transmission paths further comprises a second set of output ports located in the second dimension; in, The first group of output ports includes a first output port and a second output port, the first output port and the second output port are used to output the first data; the second group of output ports includes a third output port and a fourth output port, the third output port and the fourth output port are used to output the second data; A first data output terminal of the computing unit is connected to the first group of output ports; The second data output terminal of the computing unit is connected to the second group of output ports.

4. The processing unit in a systolic array of claim 2, wherein the first set of data transmission paths further comprises a first set of input ports located in the first dimension, and the second set of data transmission paths further comprises a second set of input ports located in the second dimension; wherein The first group of input ports includes a first input port and a second input port, the first input port and the second input port are used to input the first data; the second group of input ports includes a third input port and a fourth input port, the third input port and the fourth input port are used to input the second data; The two input terminals of the first selection module are connected to the first input port and the second input port respectively, and the output terminal is connected to the first data input terminal of the calculation unit; The two input terminals of the second selection module are connected to the third input port and the fourth input port respectively, and the output terminal is connected to the second data input terminal of the calculation unit; The control ends of the first selection module and the second selection module are used to input selection signals.

5. The processing unit in a systolic array according to claim 4, further comprising: A selection signal generating module, configured to generate a corresponding selection signal based on the signal input states of the two input terminals of the first selection module or the two input terminals of the second selection module; a selection signal output terminal of the selection signal generating module is connected to the control terminals of the first selection module and the second selection module; The selection signal generating module is used to generate a first selection signal when the first input port first receives the first data or the third input port first receives the second data, so that the first selection module selects the first data transmission path to transmit the first data, and the second selection module selects the third data transmission path to transmit the second data; The selection signal generating module is also used to generate a second selection signal when the second input port first receives the first data or the fourth input port first receives the second data, so that the first selection module selects the second data transmission path to transmit the first data, and the second selection module selects the fourth data transmission path to transmit the second data.

6. The processing unit according to claim 5, further comprising: A first delay module, wherein two input ends of the first delay module are respectively connected to the first input port and the second input port, and two output ends are respectively connected to the two input ends of the first selection module, and is used for delaying the first data by one cycle and outputting it to the first selection module; A second delay module, wherein two input terminals of the second delay module are respectively connected to the third input port and the fourth input port, and two output terminals are respectively connected to two input terminals of the second selection module, and is used for delaying the second data by one cycle and outputting it to the second selection module; The two input ends of the selection generation module are respectively connected to the two input ends of the first delay module, or are respectively connected to the two input ends of the second delay module.

7. A systolic array comprising m×n processing units, wherein the processing units have a first set of data transmission paths for transmitting data in a first dimension and a second set of data transmission paths for transmitting data in a second dimension, wherein the first set of data transmission paths is used to transmit first data and the second set of data transmission paths is used to transmit second data; wherein The first group of data transmission paths includes a first data transmission path for transmitting data in a first direction and a second data transmission path for transmitting data in a second direction; The second group of data transmission paths includes a third data transmission path that transmits data along a third direction and a fourth data transmission path that transmits data along a fourth direction.

8. The systolic array according to claim 7, wherein the processing units in the first row and the processing units in the nth column of the m×n processing units are first processing units, and the other processing units are second processing units; or, the processing units in the mth row and the processing units in the first column of the m×n processing units are first processing units, and the other processing units are second processing units; wherein, m is greater than 1 and / or n is greater than 1; The first processing unit generates a selection signal based on the input status of the data input port of the first data transmission path and / or the second data transmission path, and selects the first data transmitted by the first data transmission path and the second data transmitted by the third data transmission path based on the selection signal, and outputs the data to the downstream processing unit through the first data transmission path and the second data transmission path; The second processing unit is used to receive data output by the processing unit of the upstream node, and select the first data transmitted by the first data transmission path and the second data transmitted by the third data transmission path based on the selection signal received from the upstream processing unit, and output the data to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths; or, The first processing unit generates a selection signal based on the input status of the data input port of the first data transmission path and / or the second data transmission path, and selects the first data transmitted by the second data transmission path and the second data transmitted by the fourth data transmission path based on the selection signal, and outputs the data to the downstream processing unit through the first data transmission path and the second data transmission path; The second processing unit is used to receive data output by the processing unit of the upstream node, and based on the selection signal received from the output of the upstream processing unit, select the first data transmitted by the second data transmission path and the second data transmitted by the fourth data transmission path, and output them to the downstream processing unit through the first group of data transmission paths and the second group of data transmission paths.

9. The systolic array of claim 8, comprising a first processing unit and a second processing unit adjacent to each other in a first dimension, wherein a first output port of the first processing unit is connected to a first input port of the second processing unit, and a second input port of the first processing unit is connected to a second output port of the second processing unit; The systolic array includes a first processing unit and a second processing unit adjacent to each other in a second dimension, a third output port of the first processing unit is connected to a third input port of the second processing unit, and a fourth input port of the first processing unit is connected to a fourth output port of the second processing unit.

10. The systolic array of claim 7, wherein the second processing units located in a plurality of diagonal directions parallel to the diagonal direction of the array are connected to the selection signal output terminals of the first processing units in the diagonal directions.

11. An electronic device comprising a systolic array according to any one of claims 7 to 10 or a systolic array consisting of processing units in a systolic array according to any one of claims 1 to 6.

12. A data processing method, applied to a systolic array, the systolic array comprising m×n processing units, the processing units having a first group of data transmission paths for transmitting data in a row direction and a second group of data transmission paths for transmitting data in a column direction, the first group of data transmission paths transmitting first data, the second group of data transmission paths transmitting second data; each group comprising two data transmission directions; If m=n, the data processing method includes: At the same time, the processing unit in the i-th row and the j-th column is controlled to transmit the first data through the first data transmission path and the second data through the third data transmission path, and the processing unit in the m+1-i-th row and the n+1-j-th column is controlled to transmit the first data through the second data transmission path and the second data through the fourth data transmission path; Among them, the processing unit in the i-th row and j-th column and the processing unit in the r-th row and s-th column transmit data simultaneously; i+j=r+s, i and r are integers not less than 1 and not greater than m respectively, and j and s are integers not less than 1 and not greater than n respectively.

13. The data processing method according to claim 12, in the row direction, starting from the first column, the second data of each column in the second data matrix starting from the first column is input to the first row processing unit of each subsequent column one cycle later, and each second data in the second data array of each column is transferred to the processing unit of the next row row by row according to the data transmission cycle; at the same time, starting from the last column, the second data of each column in the second data matrix starting from the last column is input to the last row processing unit of each previous column one cycle later, and each second data in the second data array of each column is transferred to the processing unit of the previous row row by row according to the data transmission cycle; In the column direction, starting from the first row, the first data of each row in the first data matrix starting from the first row is input to the first column processing units of each subsequent row one cycle later, and each first data in the first data array of each row is transferred to the processing units of the next column column by column according to the data transmission cycle; at the same time, starting from the last row, the first data of each row in the first data matrix starting from the last row is input to the last column processing units of the previous rows one cycle later, and each first data in the first data array of each row is transferred to the processing units of the previous column column by column according to the data transmission cycle.

14. The data processing method according to claim 12, selects a data transmission path in a corresponding direction according to the data input state of the first row processing unit and the last column processing unit, or the first column processing unit and the last row processing unit in the systolic array, so that the processing units in the diagonal direction at the same time select the same data transmission direction.

15. The data processing method according to claim 13, further comprising: After the processing unit in the first row and the nth column outputs the third signal, the third data stored in the processing units in each row are synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the first row and the nth column is completed; or, After the processing unit in the mth row and the first column outputs the third signal, the third data stored in the processing units in each row are synchronously output, wherein the third signal indicates that the data processing process in the processing unit in the mth row and the first column is completed.

16. An electronic device, comprising: A systolic array, a processor and a memory, wherein the systolic array is the systolic array described in any one of claims 7 to 10; the memory is used to store a computer program; and the processor is used to execute the computer program so that the electronic device can implement the data processing method described in any one of claims 12 to 15.

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