System-on-chip design for high performance computing

Abstract

Systems, methods, and apparatus are provided for distributing code images via an update controller. In one or more examples, systems, methods, and apparatuses include sending a hold command via a serial interface to hold a first node in a reset mode, the first node connected to an update controller via the serial interface; a memory that writes the code image to the first node via the serial interface, the memory connected to the serial interface; upon determining that the code image is written to the memory, sending a release command to the first node via the serial interface to release the first node from the reset mode; and upon detecting that the first node is restarted, removing the code image from the memory via the serial interface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 543,510, filed on October 10, 2023, which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to memory systems and, more particularly, to system-on-chip designs for high performance computing. Background Art

[0004] This Background section is intended to provide context only, and the disclosure of any concepts in this section does not constitute an admission that the concepts are prior art.

[0005] The following relates to high performance computing (HPC). HPC uses parallel data processing to improve computing performance. HPC involves aggregating computing power to perform complex calculations and simulations, so that advanced applications can run efficiently, reliably and quickly. HPC can use groups of servers (e.g., clusters) to process complex calculations at high speeds. A cluster can consist of hundreds or thousands of computing servers connected by a network.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] In various embodiments, described herein include systems, methods, and apparatus for system-on-chip designs for high-performance computing. In some aspects, the technology described herein relates to a method for distributing a code image via an update controller, the method comprising: sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to the update controller via the serial interface; writing the code image to a memory of the first node via the serial interface, the memory being connected to the serial interface; upon determining that the code image is written to the memory, sending a release command to the first node via the serial interface to release the first node from the reset mode; and upon detecting that the first node is rebooted, removing the code image from the memory of the first node via the serial interface.

[0008] In some aspects, the technology described herein relates to a method in which writing a code image to a memory of a first node is based on a serial interface host of an update controller issuing a write request to a serial interface target of the first node.

[0009] In some aspects, the technology described herein relates to a method in which sending a hold command is based on updating a controller to send a restart command to a first node.

[0010] In some aspects, the technology described herein relates to a method in which sending a reboot command includes sending the reboot command to a group of nodes including a first node.

[0011] In some aspects, the technology described herein relates to a method, further comprising: selecting the set of nodes via a select line of a serial interface; and simultaneously writing the code image to the set of nodes via a broadcast mode of the serial interface.

[0012] In some aspects, the technology described herein relates to a method in which sending a hold command is based on an update controller detecting that a first node is rebooting.

[0013] In some aspects, the techniques described herein relate to a method in which the serial interface is a serial peripheral interface or a quad serial peripheral interface.

[0014] In some aspects, the techniques described herein relate to a method in which the update controller is a baseboard management controller (BMC).

[0015] In some aspects, the technology described herein relates to a method of receiving a code image from an update controller at a first node, the method comprising: receiving a hold command via a serial interface to hold the first node in a reset mode, the first node being connected to the update controller via the serial interface; receiving the code image at a memory of the first node via the serial interface, the memory being connected to the serial interface; receiving a release command from the update controller via the serial interface to release the first node from the reset mode; and based on the release command, restarting the first node and executing the code image.

[0016] In some aspects, the technology described herein relates to a method in which a first node receives a code image at a memory of the first node based on a serial interface target of the first node receiving a write request from a serial interface host of an update controller.

[0017] In some aspects, the technology described herein relates to a method in which executing a code image initiates execution of an executable file (executable) included in the code image stored in a memory based on a masked read-only memory of a first node.

[0018] In some aspects, the techniques described herein relate to a method of determining, after a reboot, that a state of a memory indicates that a code image was removed from the memory.

[0019] In some aspects, the technology described herein relates to a method, wherein receiving a hold command is based on a first node receiving a restart command from an update controller, and receiving the restart command is based on the restart command being received by a group of nodes including the first node.

[0020] In some aspects, the technology described herein relates to a method in which: a group of nodes including a first node are selected to receive a code image via a selection line of a serial interface, and the code image is received by the first node simultaneously with the group of nodes based on a broadcast mode of the serial interface.

[0021] In some aspects, the techniques described herein relate to a method in which the serial interface is a serial peripheral interface or a quad serial peripheral interface.

[0022] In some aspects, the technology described herein relates to a method in which the memory of the first node is an on-chip volatile memory communicatively connected to a serial interface as a writable target.

[0023] In some aspects, the technology described herein relates to a method in which a first node is a first system-on-chip of a solid-state drive.

[0024] In some aspects, the technology described herein relates to a non-transitory computer-readable medium storing code, the code including instructions executable by a processor of an update controller to perform the following operations: sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to the update controller via the serial interface; writing a code image to a memory of the first node via the serial interface, the memory being connected to the serial interface; upon determining that the code image is written to the memory, sending a release command to the first node via the serial interface to release the first node from the reset mode; and upon detecting that the first node is restarted, removing the code image from the memory of the first node via the serial interface.

[0025] In some aspects, the technology described herein relates to a non-transitory computer-readable medium in which writing a code image to a memory of a first node is based on a serial interface host of an update controller issuing a write request to a serial interface target of the first node.

[0026] In some aspects, the technology described herein relates to a non-transitory computer-readable medium, wherein sending the hold command is based on updating the controller to send a restart command to the first node.

[0027] A computer-readable medium is disclosed. The computer-readable medium may store instructions that, when executed by a computer, cause the computer to perform operations substantially the same or similar to those described herein. Similarly, non-transitory computer-readable media, devices, and systems for performing operations substantially the same or similar to those described herein are also disclosed.

[0028] Therefore, specific embodiments of the subject matter described herein can be implemented to achieve one or more of the following advantages: optimizing application processing efficiency, reducing latency, and minimizing security risks. Based on the described technology, persistent firmware will not remain on an untrusted system. Therefore, malware is prevented from attacking the persistent firmware portion on a given device (e.g., a system on chip (SoC)) because there is nothing to attack (e.g., the persistent firmware is removed). In an example system with 32 SoCs, the cost of the system is reduced based on the removal of 32 read-only memories (ROMs) and 32 silicon trust roots (Silicon Root of Trust, SRoT), which would otherwise be associated with each SoC based on conventional methods. In addition, based on the described technology, code (e.g., a trusted code image) can be updated in less time (e.g., 1 / 1000 of the time) via a baseboard management controller (BMC) compared to conventional methods. In addition, based on the technology described herein, because the SoC firmware does not persist, security risks are minimized. Therefore, persistent threats are removed or minimized based on the described technology. Therefore, the described technology provides reduced computing latency, improves the efficient use of system resources, and increases system security. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above aspects and other aspects of the present technology will be better understood when reading this application in light of the following drawings, in which the same reference numerals represent similar or identical elements. In addition, the drawings provided herein are only for the purpose of illustrating certain embodiments; other embodiments that may not be explicitly shown are not excluded from the scope of the present disclosure.

[0030] These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims and drawings.

[0031] Figure 1 An example system is shown according to one or more implementations as described herein.

[0032] Figure 2 According to one or more embodiments described herein, Figure 1 Details of the machine.

[0033] Figure 3 An example system-on-chip configuration is illustrated.

[0034] Figure 4 An example system-on-chip configuration is illustrated.

[0035] Figure 5 An example system is shown according to one or more implementations as described herein.

[0036] Figure 6 An example system is shown according to one or more implementations as described herein.

[0037] Figure 7 An example system is shown according to one or more implementations as described herein.

[0038] Figure 8 An example system is shown according to one or more implementations as described herein.

[0039] Fig. 9 An example system is shown according to one or more implementations as described herein.

[0040] Fig.10 Depicted is a flow chart illustrating an example method associated with the disclosed system according to example implementations described herein.

[0041] Fig.11 Depicted is a flow chart illustrating an example method associated with the disclosed system according to example implementations described herein.

[0042] Fig.12 Depicted is a flow chart illustrating an example method associated with the disclosed system according to example implementations described herein.

[0043] While the present technology is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described herein. The drawings may not be drawn to scale. However, it should be understood that the drawings and their detailed description are not intended to limit the present technology to the particular form disclosed, but on the contrary, the present invention is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present technology as defined by the appended claims. DETAILED DESCRIPTION

[0044] The details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0045] Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments are shown. In fact, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. Unless otherwise stated, the term "or" is used herein in an alternative and connecting sense. The terms "illustrative" and "example" are used as examples without indication of quality levels. The same reference numerals always refer to the same elements. The arrows in each figure depict bidirectional data flow and / or bidirectional data flow capabilities. The terms "path," "pathway," and "route" are used interchangeably herein.

[0046] Embodiments of the present disclosure may be implemented in various ways, including as a computer program product including a product. A computer program product may include a non-transitory computer-readable storage medium storing an application, a program, a program component, a script, a source code, a program code, an object code, a byte code, a compiled code, an interpreted code, a machine code, an executable instruction, etc. (also referred to herein as an executable instruction, an instruction for execution, a computer program product, a program code, and / or similar terms used interchangeably herein). Such non-transitory computer-readable storage medium includes all computer-readable media (including volatile and non-volatile media).

[0047] In one embodiment, the non-volatile computer-readable storage medium may include a floppy disk, a flexible disk, a hard disk, a solid-state storage device (SSS) (e.g., a solid-state drive (SSD)), a solid-state card (SSC), a solid-state module (SSM), an enterprise flash drive, a magnetic tape, or any other non-transitory magnetic medium, etc. The non-volatile computer-readable storage medium may also include a punch card, a paper tape, an optical mark sheet (or any other physical medium having a hole pattern or other optically recognizable mark), a compact disk read-only memory (CD-ROM), a rewritable compact disk (CD-RW), a digital versatile disk (DVD), a Blu-ray disk (BD), any other non-transitory optical medium, etc. Such non-volatile computer-readable storage medium may also include a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (e.g., serial, NAND, NOR, etc.), a multimedia memory card (MMC), a secure digital (SD) memory card, a smart media card, a CompactFlash (CF) card, a memory stick, etc. In addition, the non-volatile computer-readable storage medium may also include conductive bridging random access memory (CBRAM), phase change random access memory (PRAM), ferroelectric random access memory (FeRAM), non-volatile random access memory (NVRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), floating junction gate random access memory (FJG RAM), millipede memory, racetrack memory, etc.

[0048] In one embodiment, the volatile computer-readable storage medium may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate type 2 synchronous dynamic random access memory (DDR2 SDRAM), double data rate type 3 synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), two-transistor RAM (TTRAM), thyristor RAM (T-RAM), zero capacitor (Z-RAM), Rambus in-line memory module (RIMM), dual in-line memory module (DIMM), single in-line memory module (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, etc. It should be appreciated that where embodiments are described as using computer-readable storage media, other types of computer-readable storage media may be used in place of or in addition to the computer-readable storage media described above.

[0049] It should be understood that various embodiments of the present disclosure may also be implemented as methods, apparatuses, systems, computing devices, computing entities, etc. Thus, embodiments of the present disclosure may take the form of apparatuses, systems, computing devices, computing entities, etc. that execute instructions stored on a computer-readable storage medium to perform certain steps or operations. Therefore, embodiments of the present disclosure may also take the form of a complete hardware embodiment, a complete computer program product embodiment, and / or an embodiment that includes a combination of a computer program product and hardware that performs certain steps or operations.

[0050] The embodiments of the present disclosure are described below with reference to block diagrams and flow charts. Therefore, it should be understood that each box illustrated in the block diagram and flow chart can be implemented in the form of a computer program product, a complete hardware embodiment, a combination of hardware and computer program products, and / or an apparatus, system, computing device, computing entity, etc. that executes instructions, operations, steps, and similar words (e.g., executable instructions, instructions for execution, program codes, etc.) on a computer-readable storage medium. For example, the retrieval, loading, and execution of the code can be performed sequentially so that one instruction is retrieved, loaded, and executed at a time. In some example embodiments, retrieval, loading, and / or execution can be performed in parallel so that multiple instructions are retrieved, loaded, and / or executed together. Therefore, such an embodiment can produce a specially configured machine that performs the steps or operations specified in the block diagram and flow chart illustration. Therefore, the block diagram and flow chart illustration support various combinations of embodiments for executing specified instructions, operations, or steps.

[0051] The following description is presented to enable one of ordinary skill in the art to make and use the subject matter disclosed herein and to incorporate it in the context of a particular application.While the following is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof.

[0052] A baseboard management controller (BMC) is a dedicated service processor that monitors the physical state of a computer, server, system (e.g., system on chip, multiple systems on chip) and / or other hardware devices (e.g., monitored devices). The BMC can use one or more sensors to monitor the physical state of the monitored device, and can transmit monitoring data based on an independent connection (e.g., to a system administrator). The BMC can be powered (e.g., via an independent power line on the host power supply) even when the host is powered off. In some cases, the BMC can be part of an intelligent platform management interface (e.g., part of the Intelligent Platform Management Interface (IPMI) standard). In some examples, the BMC can be integrated on a motherboard and / or a main circuit board of the monitored device. The BMC may include a processor or microcontroller integrated into a motherboard (e.g., in a server motherboard). The BMC may include an embedded computer system (e.g., an ARM-based system on chip (SoC)) configured to provide out-of-band (OOB) management. Additionally or alternatively, the BMC may be located on a central device and configured to monitor one or more nodes outside the central device and / or the central device. In some cases, the BMC is a SoC BMC configured to monitor one or more SoC nodes.

[0053] In the device monitored by the BMC, the sensors of the BMC can be configured to measure internal physical variables, such as temperature, humidity, power supply voltage, fan speed, remote access, communication parameters and / or operating system (OS) functions. If it is determined that any of these variables deviate from specified limits, the BMC can generate and transmit a notification indicating the condition. The BMC can be configured to remotely diagnose, shut down, power cycle and / or restart the monitored device. Therefore, the BMC can enable an administrator to remotely manage one or more monitored devices (e.g., simultaneously or concurrently), thereby saving the overall operating cost of the network and helping to ensure system reliability.

[0054] The communication of BMC can be based on bus interface. In some examples, BMC can communicate via serial peripheral interface (SPI) and / or quad serial peripheral interface (QSPI). QSPI is a serial communication interface that allows communication between a host and an external quad SPI memory. The QSPI host includes software, firmware and / or hardware configured to issue QSPI read and write requests to the QSPI target. The QSPI target includes software, firmware and / or hardware configured to respond to QSPI read and write requests. QSPI is an enhanced version of SPI (serial peripheral interface). QSPI provides higher speed and additional features than SPI, but QSPI can use more hardware or more complex hardware than SPI. QSPI supports SPI and dual SPI communication modes. In quad channel mode, QSPI can use up to six lines. The throughput of quad SPI is four times higher than SPI. The QSPI mode reduces protocol overhead by using four channels to transmit operation codes. QSPI is a full-duplex synchronous bus that facilitates communication between a control node and one or more slave nodes.

[0055] The QSPI target may include data registers that allow the QSPI host to transfer data back and forth via data registers. The QSPI host may include a device that controls when communication is triggered and which node or nodes receive messages (e.g., data, code images). The QSPI host controller (e.g., BMC SoC) may include a full-duplex synchronous serial input / output data connection for communicating with one or more nodes (e.g., SoC nodes, SSD nodes, processor nodes, input / output peripheral nodes, analog-to-digital converters (ADCs), etc.). During QSPI communication, data may be sent (data is sent serially from the controller to the node) and received (data is sent serially from the node to the controller) simultaneously or concurrently. The serial clock edge synchronizes the shifting and sampling of data. The QSPI may include one or more clock lines, one or more chip select lines for selecting which nodes receive and do not receive messages, one or more data lines for transmitting data from the controller to the node (e.g., from the BMC SoC to the SoC node), and one or more data lines for transmitting data from the node to the controller (e.g., from the SoC node to the BMC SoC). In some cases, the QSPI interface includes four data lines.

[0056] Based on the techniques and mechanisms described herein, a BMC (e.g., a BMC SoC) is configured to control one or more aspects of a given SoC and / or the operation of a given SoC. The SoC is configured for subordinate operations or dependent operations (e.g., a given SoC is not configured for independent operations). The subordinate SoC depends on the BMC (e.g., for firmware, computer code, etc.). The BMC can provide firmware updates to the subordinate SoC. Firmware updates help keep devices (e.g., SoC nodes, SSDs, etc.) up to date. Firmware updates can include bug fixes, new features, security updates, program changes, patches for vulnerabilities, etc. Firmware updates can include critical firmware updates and / or non-critical firmware updates. In some cases, the BMC can restart the device (e.g., reset the SoC node, SSD, etc.) and provide critical firmware updates without delay. Additionally or alternatively, when the firmware update is non-critical, the BMC can delay restarting the device. For example, the BMC can wait until it detects that the device is restarting and provide non-critical firmware updates based on the device restart.

[0057] The slave SoC is not configured as a QSPI host, but as a QSPI target. Unlike conventional SoCs (e.g., independent SoCs), slave SoCs are configured for high-performance computing. A slave SoC or a high-performance computing SoC depends on a trusted component (e.g., an update controller, a BMC). For a slave SoC, the SoC code is controlled (e.g., fully controlled) by a BMC or a trusted component (e.g., a central trusted component) of a given system. Based on the technology described herein, the QSPI interface is configured with a broadcast mode that enables communication with up to 64 targets (e.g., 64 daisy chained SoC nodes). For example, the present technology configures the SPI / QSPI interface in a manner that provides a broadcast mode for distributing trusted code. Therefore, the present technology enables the BMC to write software code to up to 64 targets (e.g., concurrently or simultaneously write firmware to 64 SoC nodes). In an example system with 64 SoCs, the cost of the system is reduced based on the removal of 64 read-only memories (ROMs) and 64 silicon trust roots (SRoTs), which would otherwise be associated with each SoC based on conventional methods. Thus, implementing the described techniques reduces the attack points from 130 devices (e.g., 64 SRoTs, 64 ROMs, BMC SoCs, and BMC QSPIs) to only 2 devices (e.g., BMC SoCs and BMC QSPIs). In addition, the BMC does not run or is not allowed to run untrusted code (e.g., based on administrator policy, based on monitoring). For example, the BMC is configured to be accessed only by an administrator and / or controlled and actively monitored by an administrator, etc.

[0058] Figure 1 An example system is shown according to one or more embodiments as described herein. Figure 1 , a machine 105 is shown, which may also be referred to as a host, a system (eg, a system on a chip), or a server. Figure 1 The machine 105 is depicted as a tower computer, but embodiments of the present disclosure may extend to any form factor or type of machine. For example, the machine 105 may be a rack server, a blade server, a desktop computer, a tower computer, a mini-tower computer, a desktop server, a laptop computer, a notebook computer, a tablet computer, etc.

[0059] The machine 105 may include a processor 110, a memory 115, and a storage device 135. The processor 110 may be any type of processor. Note that for ease of illustration, the processor 110 and other components discussed below are shown external to the machine: embodiments of the present disclosure may include these components within the machine. Figure 1A single processor 110 is shown, but machine 105 may include any number of processors, each of which may be a single-core or multi-core processor, each of which may implement a reduced instruction set computer (RISC) architecture or a complex instruction set computer (CISC) architecture (among other possibilities), and which may be mixed in any desired combination.

[0060] The processor 110 may be coupled to a memory 115. The memory 115 may be any kind of memory, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM), such as magnetoresistive random access memory (MRAM), phase change memory (PCM), or resistive random access memory (ReRAM). The memory 115 may include volatile and / or non-volatile memory. The memory 115 may use any desired form factor: for example, a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a non-volatile DIMM (NVDIMM), etc. The memory 115 may also be any desired combination of different memory types and may be managed by a memory controller 125. The memory 115 may be used to store what may be referred to as "short-term" data: that is, data that is not expected to be stored for a long time. Examples of short-term data may include temporary files, data used locally by an application (which may have been copied from other storage locations), etc.

[0061] The processor 110 and the memory 115 may also support an operating system under which various applications may run. These applications may issue requests (also referred to as commands) to read data from or write data to the memory 115 or storage device 135. When the storage device 135 is used to support applications to read or write data via a certain file system, the device driver 130 may be used to access the storage device 135. Figure 1One storage device 135 is shown, but any number (one or more) of storage devices may be present in the machine 105. The storage device 135 may support any desired one or more protocols, including, for example, a non-volatile memory express (NVMe) protocol, a serial attached small computer system interface (SCSI) (SAS) protocol, or a serial AT attachment (SATA) protocol. The storage device 135 may also include any desired interface, including, for example, a peripheral component interconnect express (PCIe) interface or a computing express link (CXL) interface. The storage device 135 may also adopt any desired form factor, including, for example, a U.2 form factor, a U.3 form factor, an M.2 form factor, an enterprise and data center standard form factor (EDSFF) (including all its variants, such as E1 short, E1 long, and E3 variants) or an add-in card (AIC).

[0062] Although Figure 1 The term "storage device" is used, but embodiments of the present disclosure may include any storage device format that can benefit from the use of a computational storage unit, examples of which may include a hard drive, a solid-state drive (SSD), or a persistent memory device such as PCM, ReRAM, or MRAM. Any reference to "storage device," "SSD," below should be understood to include such other embodiments of the present disclosure and other kinds of storage devices. In some cases, the term "storage unit" may cover both storage device 135 and memory 115.

[0063] Machine 105 may also include power supply 155. Power supply 155 may provide power to machine 105 and its components. Power supply 155 may have a maximum amount of power that may be used (before exceeding the specifications of power supply 155): this information may be known to machine 105 and may be used, for example, by update controller 140 when monitoring machine 105. The operating level of power supply 155 may be regulated by update controller 140. In some cases, update controller 140 is a BMC (e.g., a BMC SoC).

[0064] The machine 105 may also include a transmitter 145 and a receiver 150. The transmitter 145 or the receiver 150 may be used to send or receive data, respectively. In some cases, the transmitter 145 and / or the receiver 150 may be used to communicate with the memory 115 and / or the storage device 135.

[0065] In one or more examples, the machine 105 may be implemented with any type of device. The machine 105 may be configured as one or more of (e.g., as a host for) servers, such as a computing server, a storage server, a storage node, a network server, a supercomputer, a data center system, etc., or any combination thereof. Additionally or alternatively, the machine 105 may be configured as (e.g., as a host for) one or more computers, such as a workstation, a personal computer, a tablet computer, a smart phone, etc., or any combination thereof. The machine 105 may be implemented with any type of device, which may be configured to include, for example, an accelerator device, a storage device, a network device, a memory expansion and / or buffer device, a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), etc., or any combination thereof.

[0066] Any communication between devices including machine 105 (e.g., a host, a computational storage device, and / or any intermediate device) may occur through one or more interfaces (e.g., communication interface 120), which may be implemented using any type of wired and / or wireless communication medium, interface, protocol, etc., including PCIe, NVMe, Ethernet, NVMe-oF, Compute Express Link (CXL) and / or coherent protocols (such as CXL.mem, CXL.cache, CXL.IO, etc.), Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), Advanced Extensible Interface (AXI), etc. or any combination thereof, Transmission Control Protocol / Internet Protocol (TCP / IP), Fibre Channel, Infiniband, Serial AT Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, any generation of wireless network including 2G, 3G, 4G, 5G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc. or any combination thereof. In some embodiments, the communication interface 120 may include a communication structure including one or more links, buses, switches, hubs, nodes, routers, switches, repeaters, etc. In some embodiments, the systems described herein may include one or more additional devices having one or more additional communication interfaces.

[0067] Any functionality described herein, including any functionality in the host functionality, device functionality, update controller 140 functionality, etc., may be implemented in hardware, software, firmware, or any combination thereof, including, for example, hardware and / or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as dynamic random access memory (DRAM) and / or static random access memory (SRAM)), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory), memory with body resistance change, phase change memory (PCM), etc., and / or any combination thereof, complex programmable logic device (CPLD), field programmable gate array (FPGA), application specific integrated circuit (ASIC), CPU (including complex instruction set computer (CISC) processor (such as x86 processor) and / or reduced instruction set computer (RISC) processor (such as RISC-V and / or ARM processor), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), etc., executing instructions stored in any type of memory. In some embodiments, one or more components may be implemented as a system on chip (SoC).

[0068] As shown, components of the machine 105 may include an update controller 140 having a processor 110, a memory 115, a power supply 155, etc. As shown, the communication interface 120 may include an internal interface of the illustrated components of the machine 105. Additionally or alternatively, the communication interface 120 may be an external interface between the machine 105 and the update controller 140. In one or more examples, the communication interface 120 may include a serial peripheral interface (SPI) and / or a quad serial peripheral interface (QSPI).

[0069] In some examples, the update controller 140 may include any combination of logic (e.g., logic circuits), hardware (e.g., processing units, memory, storage devices), software, firmware, etc. In some cases, the update controller 140 may perform one or more functions in conjunction with the processor 110. In some cases, at least a portion of the update controller 140 may be implemented in or by the processor 110 and / or the memory 115. In some cases, the update controller 140 may perform one or more operations described herein in conjunction with the communication interface 120. The update controller 140 may improve application processing efficiency, reduce latency, and minimize security risks to the machine 105. The update controller 140 may be configured to remove firmware from an untrusted system (e.g., the machine 105). Thus, the update controller 140 ensures that the firmware does not remain on the untrusted system. Thus, the update controller 140 prevents malware from attacking the persistent firmware portion of a given device (e.g., the machine 105) because there is nothing to attack (e.g., the persistent firmware is removed). The update controller 140 may include a baseboard management controller (BMC). In some cases, the update controller 140 updates the code (e.g., a trusted code image) via the BMC. Based on the update controller 140, security risks are minimized because the firmware (e.g., SoC firmware) does not persist. Therefore, persistent threats are eliminated or minimized. Therefore, the update controller 140 provides reduced computing latency, improves efficient use of system resources, and increases system security.

[0070] Figure 2 The example described herein is shown Figure 1 Details of the machine 105. Figure 2 In general, machine 105 includes processor 110, which may include memory controller 125 and clock 205, which may be used to coordinate the operation of components of machine 105. Figure 2 A single processor 110 is shown, but the machine 105 may include any number of processors, such as Figure 1 The processor 110 may also be coupled to a memory 115, which may include, for example, a random access memory (RAM), a read-only memory (ROM), or other state preservation medium. The processor 110 may also be coupled to a storage device 135 and a network connector 210, which may be, for example, an Ethernet connector or a wireless connector. The processor 110 may also be connected to a bus 220, to which a user interface 215 and input / output (I / O) interface ports may be attached, and an I / O engine 225 and other components may be used to manage the I / O interface ports. As shown, the processor 110 may be coupled to an update controller 230, which may be Figure 1Additionally or alternatively, processor 110 can be connected to bus 220 and update controller 230 can be attached to bus 220. In one or more examples, at least a portion of bus 220 can be an example of communication interface 120. In some cases, bus 220 can include a serial peripheral interface (SPI) and / or a quad serial peripheral interface (QSPI).

[0071] Figure 3 An example SoC configuration 300 is shown. In the example shown, the SoC configuration 300 includes a SoC 305, a read-only memory (ROM) 310, a QSPI target 315, and a communication interface 320 (e.g., an SPI communication interface, a QSPI communication interface). As shown, the SoC 305 includes a QSPI host 325, a memory 330 (e.g., an SRAM or other type of memory), a mask ROM 335, and a communication interface 320. As shown, the communication interface 320 enables the QSPI target 315 to communicate with the QSPI host 325. As shown, the communication interface 320 enables the QSPI host 325 to communicate with the memory 330.

[0072] In some examples, the mask ROM 335 can be configured to copy data to the memory 330 via the communication interface 320 (e.g., via QSPI). The ROM 310 can be a non-volatile memory that stores power-on software code. The memory 330 can be a volatile memory in which the data is lost when power is removed. The QSPI target 315 includes software and / or hardware (e.g., logic circuits) configured to process and / or respond to QSPI read and QSPI write requests (e.g., from the QSPI host 325). The QSPI host 325 includes software and / or hardware (e.g., logic circuits) configured to issue QSPI read requests and / or QSPI write requests to the QSPI target 315. The mask ROM 335 includes a first program that is executed by the SoC 305 after power-on / reset. In some cases, the mask ROM 335 may include computer code that is "baked in" (e.g., unchangeable).

[0073] At reset, mask ROM 335 writes code (e.g., program) from ROM 310 to memory 330 via communication interface 320 (e.g., via QSPI). SoC 305 then runs the code (e.g., program) in memory 330. For example, at reset, SoC 305 executes boot code on mask ROM 335, which causes SoC 305 to issue a QSPI read request for the code on ROM 310 via QSPI master 325. QSPI target 315 receives the QSPI read request, retrieves the requested code from ROM 310, and sends the requested code to SoC 305 via communication interface 320. SoC 305 writes the retrieved code to memory 330, and then executes the retrieved code written to memory 330.

[0074] Based on conventional methods, SoC can be configured as an independent system, wherein each SoC includes one or more cores. Conventional SoC is designed as an independent independent unit. For example, SoC can be designed for a single SoC system used independently. However, some systems use SoC in a dependent non-independent configuration. For example, a supercomputer may include multiple printed circuit boards, wherein each circuit board includes one or more SoCs. However, using independent SoCs in such a dependent configuration may result in increased computing latency, inefficient use of system resources, and reduced system security.

[0075] Figure 4 An example SoC configuration 400 (e.g., a configuration of a supercomputer system) is shown. In the example shown, the SoC configuration 400 includes a baseboard management controller (BMC) ROM 405, a BMC SoC 410, a SoC 415 (e.g., SoC 415a, SoC 415b, SoC 415c), and a communication interface 420 (e.g., SPI communication interface, QSPI communication interface). As shown, each of the SoCs 415 includes a silicon root of trust (SRoT) (e.g., SRoT 430a, SRoT 430b, SRoT 430c) and a ROM (e.g., ROM 425a, ROM 425b, ROM 425c). Each of the SRoTs 430 can be configured as a gatekeeper between the BMC SoC 410 and a given SoC.

[0076] Each of the SRoTs 430 is placed between the BMC SoC 410 and the ROM of a given SoC (e.g., via the QSPI target of the communication interface 420) to avoid corruption of the ROM (e.g., based on untrusted code, malware, etc.). For example, the SRoT (430a) is placed between the BMC SoC 410 and the ROM (425a) of the SoC (415a). In some systems, each of the SRoTs 430 verifies the contents of the ROM of a given SoC before the given SoC uses or executes the contents. Each of the SRoTs 430 controls whether the BMC SoC 410 is allowed to update the ROM of a given SoC. Each of the SRoTs 430 includes firmware technology that protects system hardware. Each of the SRoTs 430 creates a chain of trust that verifies that the system firmware is legitimate. Therefore, each of the SRoTs 430 prevents firmware attacks and can detect malware or damaged firmware.

[0077] In the example shown, the SoC configuration 400 includes 32 SoCs (e.g., Node 0 to Node 31). The SoC configuration 400 includes 33 QSPI parts (e.g., 32 SoCs 415 and one BMC SoC 410). As shown, the SoC configuration 400 includes 32 SRoTs 430 (e.g., one SRoT for each SoC 415).

[0078] Based on conventional methods, SoCs may be prone to running untrusted code, posing security risks to the system. In such systems, firmware updates are expensive in terms of time and system resources. In order to complete firmware updates, each SoC in the system is updated individually, taking up considerable time and resources and making the system vulnerable to malware attacks. In addition, because each SRoT has a unique serial number, supply chain management is relatively complex in such a system. The assumption that traditional SoCs are stand-alone devices (e.g., stand-alone devices in high-performance computing, data center systems, supercomputers, etc.) leads to unnecessary hardware, complexity, and risk for a given system.

[0079] Figure 5 An example system 500 is shown according to one or more embodiments as described herein. System 500 shows a schematic diagram of a system-on-chip configuration (e.g., a device such as an SSD). As shown, system 500 includes SoC 505. In the example shown, SoC 505 is configured to include a mask ROM 510, a target 515 (e.g., a QSPI target), and a memory 520 (e.g., an SRAM or other type of memory).

[0080] In some examples, SoC 505 is configured for use in a data center and / or high-performance environment. Target 515 includes software and / or hardware that responds to read and write requests (e.g., QSPI read requests and QSPI write requests). When power on / reset occurs, SoC 505 can remain in reset (e.g., in reset mode) until memory 520 is filled (e.g., until memory 520 receives executable code or a trusted code image). The code image or trusted code image can include a software package (e.g., a software package including an executable file, a firmware update, an updated version of firmware, etc.).

[0081] In some cases, SoC 505 may be based on a trusted component (e.g., Figure 1 The update controller 140, Figure 2 SoC 505 may be released from reset based on a communication received from a BMC indicating that memory 520 has received a trusted code image. In some cases, SoC 505 monitors memory 520 and releases itself from reset when SoC 505 determines that memory 520 has received executable code (e.g., completed receiving a trusted code image from a trusted component). Mask ROM 510 may include a first program executed by SoC 505 after power on / reset. Therefore, when SoC 505 is released from reset, mask ROM 510 initiates execution of code in memory 520 via a processor of SoC 505.

[0082] In one or more examples, upon reset, the QSPI target 515 receives a QSPI write request from a QSPI master of a trusted component (e.g., a BMC SoC). The trusted component then writes the trusted code from the ROM of the trusted component to the memory 520 via the target 515 (e.g., based on the QSPI communication protocol). The SoC 505 then executes the code written to the memory 330 (e.g., via one or more processors of the SoC 505).

[0083] Figure 6 An example system 600 is shown according to one or more embodiments as described herein. System 600 shows a schematic diagram of a system-on-chip configuration. As shown, system 600 includes SoC 605, BMC SoC 610, target 615 (e.g., QSPI target), communication interface 620 (e.g., SPI communication interface, QSPI communication interface, QSPI bus), and QSPI 625. SoC 605 can be Figure 5 An example of SoC 505.

[0084] In the example shown, SoC 605 includes mask ROM 630, memory 635 (e.g., on-chip memory, on-chip SRAM, etc.), and target 640 (e.g., QSPI target). As shown, BMC SoC 610 (e.g., BMC QSPI target) includes input / output (I / O) ports 645, memory 650, and host 655 (e.g., QSPI host). In some examples, SoC 605 is configured for high-performance computing environments (e.g., for data center systems, supercomputers, as slave SoCs, etc.).

[0085] In the example shown, the host 655 of the BMC is attached to the target 615 of the QSPI 625 via the communication interface 620. In the example shown, the I / O ports of the BMC are communicatively connected to the target 640 of the SoC 605 via the communication interface 620 (eg, via the QSPI bus).

[0086] As shown, memory 635 is connected to communication interface 620 as a writable target via target 640. This enables BMC SoC 610 to write to memory 635 (e.g., to write to on-chip memory of SoC 605). Thus, a trusted code image (e.g., a single central trusted code image) can be distributed by BMC SoC 610 to one or more SoCs (e.g., simultaneously or concurrently to multiple SoCs, including SoC 605) based on one or more SoCs being configured as slave SoCs (e.g., as QSPI targets having on-chip memory connected to BMC SoC 610 via a QSPI bus).

[0087] In one or more examples, the BMC SoC 610 is a trusted component. Because the BMC SoC 610 is a trusted component, the BMC SoC 610 does not run third-party code. For example, the BMC SoC 610 can be configured not to execute third-party code, can be configured to block third-party code, or can be designed to be unreachable or undetectable by third-party code. The BMC SoC 610 is a trusted component that is controlled and monitored based on access to the BMC SoC 610. The BMC SoC 610 is a trusted component that determines which SoC 605 is allowed to run and / or which SoC 605 is not allowed to run based on the BMC SoC 610. Therefore, the BMC SoC 610 is a trusted component (e.g., an SoC having on-chip SoC SRAM and configured as a QSPI target) associated with one or more SoCs (e.g., SoC 605) designed for high-performance computing.

[0088] Figure 7An example system 700 is shown according to one or more embodiments as described herein. System 700 shows a schematic diagram of a system-on-chip configuration. As shown, system 700 includes BMC SoC 705, BMC QSPI 710, SoC 715 (e.g., SoC 715a, SoC 715b, and SoC 715c). Any SoC in SoC 715 can be Figure 5 SoC 505 and / or Figure 6 BMC SoC 705 may be an example of a SoC 605. Figure 6 An example of a BMC SoC 610.

[0089] The set of SoCs 715 may be configured for use in a high performance computing environment (eg, a supercomputer system, a data center system, a system of slave SoCs). In the example shown, the set of SoCs 715 may include 32 SoC nodes (eg, of a data center system).

[0090] In the example shown, BMC SoC 705 can be configured as a host SoC of system 700, and SoC 715 (e.g., an SSD node) can be configured as a target SoC of system 700. In some cases, at least one of SoCs 715 includes a QSPI target (e.g., software, hardware, and / or firmware that responds to QSPI read and write requests from a QSPI host (such as the QSPI host of BMC SoC 705)). Target 640 can be an example of a QSPI target of SoC 715a and / or a QSPI target of another SoC in SoC 715.

[0091] In some cases, BMC QSPI 710 (e.g., BMC QSPI bus interface, BMC QSPI controller) allows multiple targets (e.g., up to 64 SoC targets) to be daisy-chained (e.g., based on a broadcast mode of the QSPI communication protocol). BMC QSPI 710 may be Figure 6 As an example of QSPI 625 , BMC QSPI 710 may include a microcontroller to control communication (eg, QSPI communication) between BMC SoC 705 and SoC 715 .

[0092] As shown, SoC 715a is connected to SoC 715b via communication interface 725 (e.g., SPI communication interface, QSPI communication interface). In some cases, communication interface 720 and communication interface 725 are part of the same bus interface (e.g., the same QSPI bus or a connected QSPI bus). In some cases, communication interface 720 and communication interface 725 are different communication interfaces (e.g., based on different protocols).

[0093] In the illustrated example, based on the SoC 715 being designed for high-performance computing (e.g., each SoC is configured with an on-chip SoC SRAM that is communicatively connected to the BMC QSPI 710 via a QSPI bus interface, and each SoC 715 is daisy-chained), the BMC SoC 705 is able to distribute a trusted code image to one or more SoCs in the SoC 715 (e.g., concurrently, simultaneously, or in any configured order or sequence to distribute the trusted code image to each SoC 715). In some cases, the BMC QSPI 710 includes a QSPI target. Additionally or alternatively, the BMC SoC 705 includes a QSPI master (e.g., software, hardware, and / or firmware that issues QSPI read and write requests to a QSPI target (such as target 640, a QSPI target of SoC 715a, etc.)

[0094] In one or more examples, the BMC SoC 705 may send a hold command via the communication interface 720 (e.g., via a serial interface) to hold the SoC 715a in reset mode, wherein the SoC 715a is connected to the BMC SoC 705 via the communication interface 720. The BMC SoC 705 may write a code image to a memory of the SoC 715a via the communication interface 720, which is connected to the communication interface 720. In some cases, the BMC SoC 705 may restart the device (e.g., reset the SoC 715a) and provide a critical firmware update without delay. Additionally or alternatively, when the firmware update is non-critical, the BMC SoC 705 may delay restarting the device. For example, the BMC SoC 705 may wait until it detects that the device is restarting, and provide a non-critical firmware update based on determining that the device is restarting.

[0095] When determining that the code image is written to the memory of SoC 715a, BMC SoC 705 may send a release command to SoC 715a via communication interface 720 to release SoC 715a from reset mode. In some cases, BMC SoC 705 may remove the code image from the memory of SoC 715a via communication interface 720 when detecting that SoC 715a is restarted.

[0096] In one or more examples, the BMC SoC 705 writes the code image to the memory of the SoC 715a based on the serial interface host of the BMC SoC 705 issuing a write request to the serial interface target of the SoC 715a via the communication interface 720. In some cases, the BMC SoC 705 sends the hold command based on the BMC SoC 705 sending a restart command to the SoC 715a. In some examples, sending the restart command includes sending the restart command to a group of nodes including the SoC 715a.

[0097] In one or more examples, the BMC SoC 705 can select the group of nodes via a select line (e.g., a chip select line) of the communication interface 720. The BMC SoC 705 can concurrently (e.g., simultaneously) write the code image to the group of nodes via a broadcast mode of the communication interface 720. In some cases, the BMC SoC 705 sends the hold command based on the BMC SoC 705 detecting that the SoC 715a is restarting. In some examples, the communication interface 720 is SPI or QSPI.

[0098] In one or more examples, the SoC 715a may receive a hold command via the serial interface to hold the SoC 715a in the reset mode, the SoC 715a being connected to the BMC SoC 705 via the communication interface 720. The SoC 715a may receive the code image via the communication interface 720 at a memory (e.g., the memory 635) of the SoC 715a, the memory being connected to the communication interface 720. The SoC 715a may receive a release command from the BMC SoC 705 via the communication interface 720 to release the SoC 715a from the reset mode. Based on the release command, the SoC 715a may restart and execute the code image.

[0099] In one or more examples, the SoC 715a receives a code image at a memory of the SoC 715a based on a serial interface target of the SoC 715a receiving a write request from a serial interface host of the BMC SoC 705. In some cases, the SoC 715a executes the code image based on a mask read-only memory (e.g., mask ROM 630) of the SoC 715a to initiate execution of an executable file included in the code image stored in the memory. The SoC 715a may determine after a reboot that the state of the memory indicates that the code image is removed from the memory.

[0100] In one or more examples, the SoC 715a receives the hold command based on the SoC 715a receiving the restart command from the BMC SoC 705. In some cases, the SoC 715a receives the restart command based on a group of nodes (e.g., group 715 of SoCs) including the SoC 715a receiving the restart command. In some cases, the group of nodes including the SoC 715a is selected to receive the code image via a selection line of the communication interface 720. In some cases, the code image is received by the SoC 715a concurrently (e.g., simultaneously) with the group of nodes based on a broadcast mode of the communication interface 720.

[0101] In one or more examples, the communication interface 720 may be SPI or QSPI. In some cases, the memory of the SoC 715a may be an on-chip volatile memory communicatively connected to the communication interface 720 as a writable target. In some cases, the SoC 715a may be a system on chip of a solid state drive.

[0102] Figure 8 An example system 800 is shown according to one or more implementations as described herein. System 800 depicts example components for high performance computing (e.g., storage such as SSDs, networking, processing units, parallel processing units, etc.). As shown, system 800 includes a BMC 805, a SoC 810 (e.g., an SoC node), a serial peripheral interface (SPI) target 815 of the SoC 810, and an SPI bus 820 (e.g., a QSPI bus). The SoC 810 may be Figure 5 SoC 505, Figure 6 SoC 605 and / or Figure 7 The BMC 805 may be an example of an SoC 715. Figure 6 BMC SoC 610 and / or Figure 7 830 , a BMC SoC 705. As depicted, the SoC 810 includes an SPI target 815, a memory 825 (e.g., a volatile memory, a dual-port SRAM), an SoC interconnect network 830, a processor 835 (e.g., a parallel processor such as CPU 835a, CPU 835b, CPU 835c, etc.), an input-output (I / O) peripheral 840 (e.g., I / O peripheral device 840a, I / O peripheral device 840b, etc.), and an on-chip network (NoC) 845. In some cases, the I / O peripheral 840 includes or depicts at least one I / O port. As shown, the SoC interconnect network 830 links the memory 825 to the processor 835, the I / O peripheral 840, and the NoC 845 via a high-bandwidth interconnect (e.g., 10 Gigabit Ethernet, InfiniBand, etc.). Although Figure 8Three processors, two I / O peripherals, and one NoC are shown, but SoC 810 may include any number of processors, I / O peripherals, and / or NoCs.

[0103] In the example shown, the SPI bus 820 runs between the BMC 805 and the SoC 810. As shown, the SPI target 815 is connected to the memory 825, and the memory 825 is located between the SPI target 815 and the SoC interconnect network 830. In the example shown, the BMC 805 writes code (e.g., firmware, firmware update, trusted code image, etc.) directly to the memory 825 via the SPI bus 820 and the SPI target 815. In some cases, the BMC 805 includes an SPI host (e.g., a QSPI host). In one or more examples, a given processor (e.g., CPU 835a) reads the memory 825. For example, the CPU 835a can read the contents of the memory 825 (e.g., firmware update or trusted code image) via the SoC interconnect network 830. In some cases, the CPU 835a can read the status of the firmware update or trusted code image loaded on the memory 825 by the BMC 805. Additionally or alternatively, the CPU 835a may write status to the memory 825 (e.g., updating firmware on the memory 825, launching firmware on the memory 825, executing firmware on the memory 825, the result of comparing data to a calculated hash, setting an information block, etc.).

[0104] Fig. 9 An example system 900 is shown according to one or more embodiments as described herein. System 900 depicts example components for high performance computing (e.g., storage devices such as SSDs, networking, processing units, parallel processing units, etc.). As shown, system 900 includes BMC 905, SoC 910 (e.g., SoC node), serial peripheral interface (SPI) target 915 of SoC 910, and SPI bus 920 (e.g., QSPI bus). SoC 910 may be Figure 5 SoC 505, Figure 6 SoC605, Figure 7 SoC 715 and / or Figure 8 An example of a SoC 810. The BMC 905 may be Figure 6 BMC SoC610, Figure 7 BMC SoC 705 and / or Figure 8805 . As depicted, the SoC 910 includes an SPI target 915, a memory 925 (e.g., volatile memory, SRAM), an SoC interconnect network 930, a processor 935 (e.g., a parallel processor such as CPU 935a, CPU 935b, CPU 935c, etc.), an input / output (I / O) peripheral 940 (e.g., I / O peripheral 940a, I / O peripheral 940b, etc.), and an on-chip network (NoC) 945. In some cases, the I / O peripheral 940 includes or depicts at least one I / O port. As shown, the SoC interconnect network 930 links the memory 925 to the set of processors 935, I / O peripherals 940, and NoC 945 via a high-bandwidth interconnect (e.g., 10 Gigabit Ethernet, InfiniBand, etc.). Although Fig. 9 Three processors, two I / O peripherals, and one NoC are shown, but SoC 910 may include any number of processors, I / O peripherals, and / or NoCs.

[0105] In the illustrated example, the SPI bus 920 runs between the BMC 905 and the SoC 910. As shown, the memory 925 is connected to the SoC interconnect network 930, and the SPI target 915 is connected to the memory 925 via the SoC interconnect network 930. Thus, the BMC 905 accesses the memory 925 via the SPI target 915 and the SoC interconnect network 930. For example, the BMC 805 writes code (e.g., firmware, firmware updates, trusted code images, etc.) to the memory 925 via the SoC interconnect network 930.

[0106] Fig.10 A flowchart illustrating an example method 1000 associated with the disclosed system according to example implementations described herein is depicted. In some configurations, the method 1000 may be performed by Figure 1 The update controller 140, Figure 2 The update controller 230, Figure 6 BMC SoC 610, Figure 7 BMC SoC 705 and / or Figure 8 The method 1000 may be implemented in conjunction with the BMC 805 of the machine 105. In some configurations, the method 1000 may be implemented in conjunction with the machine 105, components of the machine 105, or any combination thereof. The method 1000 is only one embodiment, and one or more operations of the method 1000 may be rearranged, reordered, omitted, and / or otherwise modified, such that others are possible and contemplated.

[0107] At 1005, method 1000 may include sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to an update controller via the serial interface. For example, BMC SoC 705 may send a hold command via communication interface 720 to hold SoC 715a in a reset mode, SoC 715a being connected to BMC SoC 705 via communication interface 720.

[0108] At 1010 , method 1000 may include writing the code image to a memory of the first node via the serial interface, the memory being connected to the serial interface. For example, BMC SoC 705 may write the code image to a memory of SoC 715 a via communication interface 720 , the memory being connected to communication interface 720 .

[0109] At 1015, method 1000 may include sending a release command to the first node via the serial interface to release the first node from the reset mode when it is determined that the code image is written to the memory. For example, BMC SoC 705 may send a release command to SoC 715a via the communication interface 720 to release SoC 715a from the reset mode when it is determined that the code image is written to the memory.

[0110] At 1020, method 1000 may include removing the code image from the memory of the first node via the serial interface upon detecting that the first node is rebooted. For example, BMC SoC 705 may remove the code image from the memory of SoC 715a via communication interface 720 upon detecting that SoC 715a is rebooted.

[0111] Fig.11 A flowchart illustrating an example method 1100 associated with the disclosed system according to example implementations described herein is depicted. In some configurations, the method 1100 may be performed by Figure 1 The update controller 140, Figure 2 The update controller 230, Figure 6 BMC SoC 610, Figure 7 BMC SoC 705 and / or Figure 8 The method 1100 may be implemented in conjunction with the BMC 805 of the machine 105. In some configurations, the method 1100 may be implemented in conjunction with the machine 105, components of the machine 105, or any combination thereof. The method 1100 is only one embodiment, and one or more operations of the method 1100 may be rearranged, reordered, omitted, and / or otherwise modified, such that others are possible and contemplated.

[0112] At 1105, method 1100 may include receiving a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to an update controller via the serial interface. For example, a SoC of SoC 715 (e.g., SoC 715a) may receive a hold command via a communication interface 720 to hold the SoC of SoC 715 in a reset mode, the SoC of SoC 715 being connected to BMC SoC 705 via the communication interface 720.

[0113] At 1110, method 1100 may include receiving a code image at a memory of the first node via a serial interface, the memory connected to the serial interface. For example, the SoC of SoC 715 may receive the code image at a memory of the SoC of SoC 715 via a communication interface 720, the memory connected to the communication interface 720.

[0114] At 1115, method 1100 may include receiving a release command from the update controller via the serial interface to release the first node from the reset mode. For example, SoC 715 may receive a release command from BMC SoC 705 via communication interface 720 to release SoC 715 from the reset mode.

[0115] At 1120, method 1100 may include restarting the first node based on the release command and executing the code image. For example, the SoC of SoC 715 may restart the SoC of SoC 715 based on the release command and execute the code image.

[0116] Fig.12 A flowchart illustrating an example method 1200 associated with the disclosed system according to example implementations described herein is depicted. In some configurations, the method 1200 may be performed by Figure 1 The update controller 140, Figure 2 The update controller 230, Figure 6 BMC SoC 610, Figure 7 BMC SoC 705 and / or Figure 8 The method 1200 may be implemented in conjunction with the BMC 805 of the machine 105. In some configurations, the method 1200 may be implemented in conjunction with the machine 105, components of the machine 105, or any combination thereof. The method 1200 is only one embodiment, and one or more operations of the method 1200 may be rearranged, reordered, omitted, and / or otherwise modified, such that others are possible and contemplated.

[0117] At 1205, method 1200 may include selecting a set of nodes via select lines of a serial interface (eg, chip select lines of SPI or QSPI). For example, BMC SoC 705 may select SoC 715 via select lines of a serial interface.

[0118] At 1210, method 1200 may include sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to an update controller via the serial interface. For example, BMC SoC 705 may send a hold command via a communication interface 720 to hold SoC 715a in a reset mode, SoC 715a being connected to an update controller via the communication interface 720.

[0119] At 1215, method 1200 may include concurrently writing the code image to the memory of each node in the group of nodes via the serial interface based on the broadcast mode of the serial interface. For example, BMC SoC 705 may concurrently write the code image to the memory of each SoC in SoC 715 via communication interface 720 based on the broadcast mode of communication interface 720.

[0120] At 1220, the method 1200 may include sending a release command to each node in the group of nodes via a serial interface to release the group of nodes from the reset mode when it is determined that the code image is written to each corresponding memory. For example, the BMC SoC 705 may send a release command to each SoC in the SoC 715 via the communication interface 720 to release the SoC 715 from the reset mode when it is determined that the code image is written to each corresponding memory.

[0121] At 1225, method 1200 may include removing the code image from the memory of each node in the group of nodes via the serial interface when detecting that the group of nodes is restarted. For example, BMC SoC 705 may remove the code image from the memory of each SoC of SoC 715 via communication interface 720 when detecting that SoC 715 is restarted.

[0122] In the examples described herein, configurations and operations are example configurations and operations, and may relate to various additional configurations and operations that are not explicitly shown. In some examples, one or more aspects of the configurations and / or operations shown may be omitted. In some embodiments, one or more of the operations may be performed by components other than those shown herein. Additionally or alternatively, the order and / or chronological order of the operations may be changed.

[0123] Certain embodiments may be implemented in one or a combination of hardware, firmware, and software. Other embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any non-transitory memory mechanism for storing information in a machine (e.g., computer) readable form. For example, a computer-readable storage device may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, and other storage devices and media.

[0124] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The terms "computing device," "user device," "communication station," "station," "handheld device," "mobile device," "wireless device," and "user equipment" (UE) as used herein refer to a wireless communication device such as a cellular phone, smart phone, tablet, netbook, wireless terminal, laptop, femtocell, high data rate (HDR) subscriber station, access point, printer, point of sale device, access terminal, or other personal communication system (PCS) device. The device may be mobile or fixed.

[0125] As used within this document, the term "communication" is intended to include sending, or receiving, or both sending and receiving. This may be particularly useful in a claim when describing the organization of data sent by one device and received by another device, but only the functionality of one of these devices is required to infringe the claim. Similarly, a two-way data exchange between two devices (both devices send and receive during the exchange) may be described as "communication" when only the functionality of one of these devices is claimed. The term "transmit" as used herein with respect to wireless communication signals includes sending wireless communication signals and / or receiving wireless communication signals. For example, a wireless communication unit capable of transmitting wireless communication signals may include a wireless transmitter for sending wireless communication signals to at least one other wireless communication unit, and / or a wireless communication receiver for receiving wireless communication signals from at least one other wireless communication unit.

[0126] Some embodiments may be used in conjunction with various devices and systems, such as personal computers (PCs), desktop computers, mobile computers, laptop computers, notebook computers, tablet computers, server computers, handheld computers, handheld devices, personal digital assistant (PDA) devices, handheld PDA devices, vehicle-mounted devices, non-vehicle-mounted devices, hybrid devices, vehicle devices, non-vehicle devices, mobile or portable devices, consumer devices, non-mobile or non-portable devices, wireless communication stations, wireless communication devices, wireless access points (APs), wired or wireless routers, wired or wireless modems, video devices, audio devices, audio-video (A / V) devices, wired or wireless networks, wireless area networks, wireless video area networks (WVANs), local area networks (LANs), wireless LANs (WLANs), personal area networks (PANs), wireless PANs (WPANs), and the like.

[0127] Some embodiments may be used with one-way and / or two-way radio communication systems, cellular radiotelephone communication systems, mobile phones, cellular phones, wireless phones, personal communication system (PCS) devices, PDA devices containing wireless communication devices, mobile or portable global positioning system (GPS) devices, devices containing GPS receivers or transceivers or chips, devices containing RFID elements or chips, multiple-input multiple-output (MIMO) transceivers or devices, single-input multiple-output (SIMO) transceivers or devices, multiple-input single-output (MISO) transceivers or devices, devices with one or more internal antennas and / or external antennas, digital video broadcasting (DVB) devices or systems, multi-standard radio devices or systems, wired or wireless handheld devices such as smart phones, wireless application protocol (WAP) devices, etc.

[0128] Some embodiments may be used in conjunction with one or more types of wireless communication signals and / or systems that follow one or more wireless communication protocols, such as radio frequency (RF), infrared (IR), frequency division multiplexing (FDM), orthogonal FDM (OFDM), time division multiplexing (TDM), time division multiple access (TDMA), extended TDMA (E-TDMA), general packet radio service (GPRS), extended GPRS, code division multiple access (CDMA), wideband CDMA (WCDMA), CDMA 2000, single carrier CDMA, multi-carrier CDMA, multi-carrier modulation (MDM), discrete multi-tone (DMT), Bluetooth TM , Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee TM, Ultra Wideband (UWB), Global System for Mobile Communications (GSM), 2G, 2.5G, 3G, 3.5G, 4G, fifth generation (5G) mobile networks, 3GPP, Long Term Evolution (LTE), Advanced LTE, Enhanced Data Rates for GSM Evolution (EDGE), etc. Other embodiments may be used in various other devices, systems and / or networks.

[0129] Although an example processing system has been described above, embodiments of the subject matter and functional operations described herein may be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them.

[0130] The embodiments of the subject matter and operations described herein may be implemented in digital electronic circuits, or in computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described herein may be implemented as one or more computer programs, i.e., one or more components of computer program instructions, which are encoded on a computer storage medium for execution by an information / data processing device or for controlling the operation of an information / data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information / data for transmission to a suitable receiver device for execution by an information / data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them, or may be included therein. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage media may also be, or be included in, one or more separate physical components or media (eg, multiple CDs, disks, or other storage devices).

[0131] The operations described herein may be implemented as operations performed by an information / data processing apparatus on information / data stored on one or more computer-readable storage devices or received from other sources.

[0132] The term "data processing apparatus" encompasses all kinds of apparatus, devices and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or multiple or combinations of the foregoing. The apparatus may include dedicated logic circuits, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them. The apparatus and execution environment may implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0133] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a component, assembly, subroutine, object, or other unit suitable for a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or information / data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more components, subroutines, or portions of code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed over multiple sites and interconnected by a communications network.

[0134] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input information / data and generating output. As an example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital computer. Typically, the processor will receive instructions and information / data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for performing actions according to instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more large-capacity storage devices (such as disks, magneto-optical disks, or optical disks) for storing data, or operably coupled to receive information / data from it or transmit information / data to it or both. However, a computer does not need to have such a device. Devices suitable for storing computer program instructions and information / data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by or incorporated into a dedicated logic circuit.

[0135] To provide interaction with a user, embodiments of the subject matter described herein may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information / data to the user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input. In addition, the computer may interact with the user by sending documents to and receiving documents from a device used by the user; for example, by sending a web page to a web browser on a user's client device in response to a request received from the web browser.

[0136] Embodiments of the subject matter described herein may be implemented in a computing system that includes a back-end component, such as an information / data server, or includes a middleware component, such as an application server, or includes a front-end component, such as a client computer with a graphical user interface or a web browser, through which a user can interact with an embodiment of the subject matter described herein, or any combination of one or more such back-end, middleware, or front-end components. The components of the system may be interconnected by digital information / data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), interconnected networks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0137] The computing system may include a client and a server. The client and the server are usually remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by means of computer programs running on the respective computers and having a client-server relationship with each other. In some embodiments, the server sends information / data (e.g., an HTML page) to the client device (e.g., for the purpose of displaying information / data to a user interacting with the client device and receiving user input from the user interacting with the client device). Information / data generated at the client device (e.g., the result of user interaction) can be received from the client device at the server.

[0138] Although this specification contains many specific embodiment details, these should not be interpreted as limitations on any embodiment or the scope that may be claimed, but as descriptions of features specific to a particular embodiment. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0139] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0140] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0141] Many modifications and other examples of the present invention described herein will occur to those skilled in the art having the benefit of the foregoing description and the teachings presented in the associated drawings. Therefore, it should be understood that the embodiments are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A method for distributing a code image via an update controller, the method comprising: sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to the update controller via the serial interface; writing a code image into a memory of the first node via the serial interface, the memory being connected to the serial interface; When it is determined that the code image is written into the memory, sending a release command to the first node via the serial interface to release the first node from the reset mode; as well as Upon detecting that the first node is rebooted, removing the code image from the memory via the serial interface.

2. The method according to claim 1, wherein: Writing the code image into the memory is based on a serial interface host of the update controller issuing a write request to a serial interface target of the first node.

3. The method according to claim 1, wherein: Sending the hold command is based on the update controller sending a restart command to the first node.

4. The method according to claim 3, wherein: Sending the restart command includes sending the restart command to a group of nodes including the first node.

5. The method according to claim 4, further comprising: selecting the set of nodes via a select line of the serial interface; as well as The code image is concurrently written to the set of nodes via a broadcast mode of the serial interface.

6. The method according to claim 1, wherein: Sending the hold command is based on the update controller detecting that the first node is rebooting.

7. The method according to claim 1, wherein: The serial interface is a serial peripheral interface or a quad serial peripheral interface.

8. The method according to claim 1, wherein: The update controller is a baseboard management controller (BMC).

9. A method of receiving a code image from an update controller at a first node, the method comprising: receiving a hold command via a serial interface to hold the first node in a reset mode, the first node being connected to the update controller via the serial interface; receiving a code image at a memory of the first node via the serial interface, the memory being connected to the serial interface; receiving a release command from the update controller via the serial interface to release the first node from the reset mode; as well as Based on the release command, the first node is restarted and the code image is executed.

10. The method according to claim 9, wherein: The first node receiving the code image at the memory is based on a serial interface target of the first node receiving a write request from a serial interface host of the update controller.

11. The method according to claim 9, wherein: Executing the code image initiates execution of an executable file included in the code image stored in the memory based on the mask read-only memory of the first node.

12. The method according to claim 9, further comprising: After rebooting, it is determined that a state of the memory indicates that the code image is removed from the memory.

13. The method according to claim 9, wherein: Receiving the hold command is based on the first node receiving a restart command from the update controller, and Receiving the restart command is based on the restart command being received by a group of nodes including the first node.

14. The method according to claim 13, wherein: The group of nodes including the first node are selected to receive the code image via a select line of the serial interface, and The code image is received by the first node concurrently with the group of nodes based on a broadcast mode of the serial interface.

15. The method according to claim 9, wherein: The serial interface is a serial peripheral interface or a quad serial peripheral interface.

16. The method according to claim 9, wherein: The memory is an on-chip volatile memory communicatively connected to the serial interface as a writable target.

17. The method according to claim 9, wherein: The first node is a first system on chip of a solid state drive.

18. A non-transitory computer readable medium storing code, the code comprising instructions executable by a processor of an update controller to: sending a hold command via a serial interface to hold a first node in a reset mode, the first node being connected to the update controller via the serial interface; writing a code image into a memory of the first node via the serial interface, the memory being connected to the serial interface; When it is determined that the code image is written into the memory, sending a release command to the first node via the serial interface to release the first node from the reset mode; as well as Upon detecting that the first node is rebooted, removing the code image from the memory of the first node via the serial interface.

19. The non-transitory computer readable medium of claim 18, wherein: Writing the code image into the memory is based on a serial interface host of the update controller issuing a write request to a serial interface target of the first node.

20. The non-transitory computer readable medium of claim 18, wherein: Sending the hold command is based on the update controller sending a restart command to the first node.

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