Reliability evaluation method applied to internal interconnection welding spots of laminated packaging chip

Abstract

The invention belongs to the technical field of welding spot reliability evaluation, and particularly relates to a reliability evaluation method applied to interconnection welding spots in a laminated packaging chip. Comprising the following steps: carrying out basic performance characterization and structure and material parameter extraction on the interconnection welding spot of the laminated packaging chip; carrying out simulation analysis and simulation verification on the reliability of interconnection welding spots in the laminated packaging chip; testing and analyzing the reliability stress of the interconnection welding spots in the laminated packaging chip; carrying out reliability performance degradation and defect characterization on interconnection welding spots in the laminated packaging chip; and constructing a quantitative index of the reliability of the interconnection welding spots of the laminated packaging chip. According to the method, a failure mechanism, microstructure evolution and performance degradation rules of the internal interconnection welding spots of the laminated packaging chip are disclosed, key factors and structural parameters influencing the reliability level of the internal interconnection welding spots are analyzed, optimal structural combination parameters are obtained through reliability simulation analysis and simulation verification and reliability stress test assessment analysis, and the reliability of the internal interconnection welding spots is improved. And forming a reliability quantitative index.

Description

Technical Field

[0001] The invention belongs to the technical field of solder joint reliability evaluation, and in particular relates to a reliability evaluation method for internal interconnect solder joints of a stacked package chip. Background Art

[0002] As electronic components continue to develop towards high density, miniaturization and integration, the packaging form is also constantly advancing from two-dimensional packaging to 3D stacked packaging chips. 3D stacked packaging chips are different from traditional packaging technology. This technology enables the component package to have an interconnected structure of multi-layer solder ball arrays inside.

[0003] The internal interconnect solder joints of the stacked packaged chip will easily lead to reliability loss of the solder joints due to the mismatch in thermal expansion coefficients between the chip, solder joints and PCB materials when the external ambient temperature changes, multiple reflow processes during the packaging process will cause the internal interconnect solder joints to remelt, and the deformation of the upper and lower substrates under mechanical stress will cause uneven stress on the solder joints.

[0004] As the key component of mechanical connection and electrical signal transmission channel in the structure, internal interconnect solder joints largely determine the reliability of stacked package chips. However, the deep mechanism of interface phase, defect formation and evolution of internal interconnect solder joints in stacked package chips is not clear at present, and the lack of assessment and evaluation methods has greatly hindered the development of stacked package chip packaging technology and terminal applications.

[0005] Therefore, it is an indispensable technical reserve to establish a reliability evaluation method for the internal interconnect solder joints of stacked package chips, reveal the failure mechanism and microstructure evolution law of the internal interconnect solder joints of stacked package chips, establish quantitative reliability indicators for product quality control and screening assessment of the internal interconnect solder joints of stacked package chips, achieve product reliability optimization, and ensure the final application of the product. Summary of the invention

[0006] The purpose of the present invention is to provide a reliability evaluation method for internal interconnect solder joints of stacked package chips, which is used for reliability evaluation of internal interconnect solder joints of stacked package chips and for constructing reliability quantitative indicators for quality control and screening assessment.

[0007] In order to solve the above technical problems, the present invention provides a reliability evaluation method for internal interconnect solder joints of a stacked package chip, comprising the following steps:

[0008] Step S1: characterization of basic performance of interconnect solder joints of stacked package chips, and extraction of structure and material parameters;

[0009] The basic performance parameter characterization includes but is not limited to the flatness, bonding strength and electrical properties of the internal interconnect solder joints; the structural parameters include the outer dimensions, the upper and lower substrate dimensions, the pad dimensions, the solder ball diameter and spacing, the interface morphology and IMC thickness, the assembly process parameters and other structural parameters necessary for the establishment of the simulation model; the structural parameter extraction can be achieved through 3D-X-ray analysis, longitudinal section and scanning electron microscope or transmission electron microscope characterization structure analysis methods; the material parameters include the chip package cover, outer frame, upper and lower substrates, solder balls and package bottom plate structure, specifically including the density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity physical parameters of the materials involved in the structure;

[0010] Step S2: reliability simulation analysis and simulation verification of the internal interconnect solder joints of the stacked package chip; that is, based on the basic performance characterization, structure and material parameter results of the interconnect solder joints in step S1, an interconnect structure model for simulation analysis is established; by changing the structural parameters that affect the reliability level of the internal interconnect solder joints, such as the thickness of the upper and lower substrates and the size of the solder ball pads, the reliability differences under corresponding different stress conditions are simulated and analyzed; the structural parameters that affect the reliability level of the internal interconnect solder joints can be determined by the structural characteristics of the product itself, design evaluation and engineering verification data;

[0011] Step S3: reliability stress test assessment and analysis of the internal interconnect solder joints of the stacked package chip; the stress test assessment and analysis object should be based on the simulation analysis and simulation verification results, select the top three structural parameter combinations in reliability level, and conduct reliability stress test assessment and analysis simultaneously;

[0012] Step S4: reliability performance degradation and defect characterization of interconnect solder joints within the stacked package chip; the reliability performance degradation results can be extracted by using flatness test, electrical performance test, bonding strength and shear strength test methods in different reliability stress test assessment time periods, and further by data analysis, the reliability performance degradation law is obtained;

[0013] Step S5: constructing reliability quantitative indicators of interconnect solder joints of stacked package chips; based on reliability simulation analysis and simulation verification as well as reliability test assessment analysis results, combined with interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained as reliability quantitative indicators.

[0014] Preferably, the simulation analysis of reliability under different stress conditions in step S2 includes combinations of all different structural parameters.

[0015] Preferably, the corresponding different stress conditions should be determined by the environmental profile during the manufacturing, assembly and application of the product or the sensitive stress existing in the product design itself.

[0016] Preferably, the object of the reliability stress test assessment analysis can be increased or selected according to the actual application requirements or other requirements, and a specific combination of structural parameters can be added to conduct reliability stress test assessment analysis.

[0017] Preferably, the object of the reliability stress test assessment analysis can be designed and prepared with the structurally consistent engineering samples for reliability stress test assessment analysis in combination with the extraction results of the structural parameters in step S1 and the simulation analysis and simulation verification results.

[0018] Preferably, the stress conditions for reliability test assessment analysis include stress conditions used in reliability simulation analysis and simulation verification.

[0019] Preferably, the stress test assessment and analysis of the reliability of the internal interconnect solder joints of the stacked package chip is terminated based on the failure or obvious performance degradation of the object of the stress test assessment and analysis.

[0020] Preferably, in step S4, the reliability performance degradation and defect characterization of the interconnect solder joints inside the stacked package chip requires monitoring the growth thickness and micromorphology changes of the intermetallic compound IMC layer at the interconnect interface.

[0021] Preferably, in step S4, the reliability performance degradation and defect characterization of the internal interconnect solder joints of the stacked package chip, and the interconnect solder joint defect characterization are characterized and identified by 3D-X-ray, red ink staining test, and SEM analysis technology after longitudinal sectioning.

[0022] Preferably, the reliability quantitative index of the interconnect solder joints of the stacked package chip can be used as a control index for quality control and screening assessment of mass-produced products.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] (1) In the present invention, through parameter extraction, simulation analysis and simulation verification, stress test assessment analysis, reliability performance degradation and defect characterization, and the construction of reliability quantification indicators, a complete reliability assessment process is established, which helps to improve the accuracy of the reliability assessment of the internal interconnect solder joints of the stacked package chip.

[0025] (2) In the present invention, by means of reliability simulation analysis and simulation verification and reliability stress test assessment analysis, various structural parameters and combinations that affect the reliability level of internal interconnect solder joints are evaluated, which helps to comprehensively evaluate the reliability of internal interconnect solder joints of stacked packaging chips.

[0026] (3) In the present invention, the extraction results of structural parameters can be combined with the simulation analysis and simulation verification results to design and prepare engineering samples with consistent structures for reliability stress test assessment and analysis, which is helpful for targeted verification of influencing factors and cost control during the implementation process.

[0027] (4) In the present invention, the reliability stress test conditions are determined by the environmental profile during the manufacturing, assembly and application of the product or the sensitive stress existing in the product design itself, taking into account the actual application environment, and the evaluation results are more accurate and reliable.

[0028] (5) In the present invention, it is proposed to establish a reliability quantitative index for product quality control and screening assessment based on reliability simulation analysis and simulation verification as well as reliability test assessment analysis results, which is beneficial to the long-term stability monitoring of product quality and reliability improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The figure is a flow chart of a typical method for evaluating the reliability of internal interconnect solder joints of a stacked package chip according to the present invention.

[0030] Figure 2 It is a schematic diagram of the typical stacked package chip interconnection structure of the present invention.

[0031] Figure 3 It is a schematic diagram of the cross-sectional microstructure of the internal interconnect solder joints of a typical stacked package chip of the present invention.

[0032] Figure 4 It is a schematic diagram of the typical reliability stress test assessment, reliability performance degradation monitoring and defect characterization process of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] like Figures 1 to 4As shown, an embodiment of the present invention specifically provides a reliability evaluation method for internal interconnect solder joints of stacked packaged chips, the method comprising: characterizing and extracting basic performance, structure and material parameters of interconnect solder joints of specific stacked packaged chips; establishing an interconnect structure model for simulation analysis based on the characterization of basic performance, structure and material parameter results of interconnect solder joints; using the simulation structure model, changing the structural parameters that affect the reliability level of the internal interconnect solder joints, simulating and analyzing the differences in reliability under corresponding different stress conditions when different structural parameter combinations are combined; selecting the top three structural parameter combinations in reliability level after simulation analysis and simulation verification, and simultaneously conducting reliability stress test assessment analysis; further analyzing the reliability performance degradation law and defect mechanism of the interconnect solder joints during the stress test assessment process to obtain the optimal structural combination parameters; obtaining and establishing product quality control and screening assessment reliability quantitative indicators based on the reliability simulation analysis and simulation verification as well as the reliability test assessment analysis results.

[0035] The technical solution of the embodiment of the present invention specifically includes the following steps:

[0036] Step 1: Characterization of basic performance, structure and material parameter extraction of interconnect solder joints of stacked package chips;

[0037] Step 2: Simulation analysis and verification of reliability of internal interconnect solder joints of stacked package chips;

[0038] Step 3: Reliability stress test assessment and analysis of the internal interconnect solder joints of the stacked package chip;

[0039] Step 4: Reliability performance degradation and defect characterization of interconnect solder joints within stacked package chips;

[0040] Step 5: Construction of quantitative indicators of reliability of interconnect solder joints of stacked package chips.

[0041] like Figure 2 As shown, the typical stacked package chip interconnection structure mainly includes a cover plate, an outer frame, an inner chip, an upper organic substrate, internal interconnection solder joints, a lower organic substrate, a package base plate, and external interconnection solder joints;

[0042] The present invention is mainly used for reliability evaluation of internal interconnect solder joints in a stacked package chip interconnect structure.

[0043] Specifically, in step 1, structural parameters can be extracted by optical microscopy, X-ray, 3D-X-ray, visual inspection inside the package, cross-sectional analysis, SEM / EDS analysis, TEM analysis and other technical means;

[0044] like Figure 3As shown, the thickness of the upper and lower organic substrates, the diameter of the upper and lower pads of the internal solder joints, the coating material and thickness, the diameter and spacing of the internal and external solder balls, the material composition, the IMC interface morphology and thickness and other parameters can be obtained.

[0045] The extraction of basic performance parameters can be achieved through test methods such as flatness test, bonding strength test and electrical performance test.

[0046] Physical material parameters such as density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity can be extracted by consulting formal literature or conducting material performance analysis.

[0047] In step 2, the establishment of the reliability simulation analysis model should be based on the basic performance characterization, structure and material parameter extraction results of the interconnect solder joints of the stacked package chip to ensure the accuracy of the model establishment;

[0048] Reliability simulation analysis and simulation verification: Before implementation, the structural parameters that affect the reliability level of internal interconnect solder joints should be fully analyzed;

[0049] Reliability simulation analysis and simulation verification: Before implementation, the environmental profile during product manufacturing, assembly and application or the sensitive stress in the product design itself should be investigated and analyzed;

[0050] Based on the research and analysis results, determine the stress type and conditions to be applied in simulation analysis and simulation verification;

[0051] In step 2, simulation analysis and simulation verification should be carried out to simulate the reliability of all combinations of different structural parameters under different stress conditions;

[0052] Evaluate the top three structural parameter combinations in terms of reliability level, or the structural parameter combinations that meet specific application requirements.

[0053] like Figure 4 As shown, the object of reliability stress test assessment and analysis can be the top three structural parameter combinations, or special products with structural parameter combinations that meet specific application requirements, or engineering samples with the same structure designed and prepared for reliability stress testing;

[0054] The assessment and analysis is mainly carried out through tests such as reflow soldering, temperature cycling, random vibration and other stress tests, and should include the stress conditions used in reliability simulation analysis and simulation verification.

[0055] In step 4, reliability performance degradation and defect characterization are performed using 3D X-ray characterization, flatness test, electrical performance test, IMC microanalysis, bonding strength and other test characterization methods at different reliability stress test assessment time periods;

[0056] Through further data analysis, the quantitative correspondence between different structural parameter combinations and solder joint reliability is analyzed to obtain the reliability performance degradation law.

[0057] In step 5, based on the reliability simulation analysis and simulation verification and the reliability test assessment analysis results, combined with the interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained to form a reliability quantitative index;

[0058] A quantitative indicator of the reliability of the interconnect solder joints of stacked package chips, used as a control indicator for quality control and screening assessment of mass-produced products.

[0059] In summary, the evaluation method of the present invention includes the steps of basic performance test and structural parameter extraction of interconnect solder joints, simulation analysis and simulation verification of reliability indicators, reliability stress test assessment analysis, reliability performance degradation and defect characterization, and construction of reliability quantitative indicators. The method extracts the basic performance and structural parameters of the interconnect solder joints of the stacked package chip, establishes a simulation analysis model, simulates stress fields such as reflow soldering, random vibration, and temperature cycling to simulate and verify the reliability of the internal interconnect solder joints of the stacked package chip, and screens the structural parameter combination with the top reliability level. Based on the simulation analysis results, the sensitive stress reliability test assessment is further designed and implemented, and with the help of 3D-X-ray non-destructive defect positioning; dyeing microcrack defect characterization; bonding strength mechanical measurement and intermetallic compound (IMC) microscopic characterization and other technologies, the reliability degradation evaluation and defect characterization of the internal interconnect solder joints of the stacked package chip are realized, and the failure mechanism, microstructure evolution and performance degradation law of the internal interconnect solder joints of the stacked package chip are revealed, and the optimal structural combination parameters are obtained to form reliability quantitative indicators; It provides support for the reliability evaluation of the internal interconnect solder joints of the stacked package chip and the control of product quality control and screening assessment.

[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A reliability evaluation method for internal interconnect solder joints of stacked package chips, characterized in that: The steps include: Step S1: characterization of basic performance of interconnect solder joints of stacked package chips, and extraction of structure and material parameters; The basic performance parameter characterization includes but is not limited to the flatness, bonding strength and electrical properties of the internal interconnect solder joints; the structural parameters include the outer dimensions, the upper and lower substrate dimensions, the pad dimensions, the solder ball diameter and spacing, the interface morphology and IMC thickness, the assembly process parameters and other structural parameters necessary for the establishment of the simulation model; the structural parameter extraction can be achieved through 3D-X-ray analysis, longitudinal section and scanning electron microscope or transmission electron microscope characterization structure analysis methods; the material parameter extraction objects include the chip packaging cover plate, outer frame, upper and lower substrates, solder balls and packaging bottom plate, specifically including the density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity physical property parameters involved in the structural material; Step S2: reliability simulation analysis and simulation verification of the internal interconnect solder joints of the stacked package chip; that is, based on the basic performance characterization, structure and material parameter results of the interconnect solder joints in step S1, an interconnect structure model for simulation analysis is established; by changing the thickness of the upper and lower substrates and the solder ball-to-pad size ratio, the structural parameters that will affect the reliability level of the internal interconnect solder joints are simulated and analyzed, and the differences in reliability under corresponding different stress conditions are analyzed; the structural parameters that affect the reliability level of the internal interconnect solder joints can be determined by the structural characteristics of the product itself, design evaluation and engineering verification data; Step S3: reliability stress test assessment and analysis of the interconnect solder joints inside the stacked package chip; the stress test assessment and analysis object should be based on the simulation analysis and simulation verification results, and the top three structural parameter combinations ranked by the reliability level of the simulation verification results should be selected for reliability stress test assessment and analysis; Step S4: reliability performance degradation and defect characterization of interconnect solder joints within the stacked package chip; the reliability performance degradation results can be extracted by using flatness test, electrical performance test, bonding strength and shear strength test methods in different reliability stress test assessment time periods, and further by data analysis, the reliability performance degradation law is obtained; Step S5: constructing reliability quantitative indicators of interconnect solder joints of stacked package chips; based on reliability simulation analysis and simulation verification as well as reliability test assessment analysis results, combined with interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained as reliability quantitative indicators.

2. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 1, characterized in that: The simulation analysis of reliability under different stress conditions in step S2 includes all combinations of different structural parameters.

3. A reliability evaluation method for internal interconnect solder joints of a stacked package chip as claimed in claim 2, characterized in that: Different stress conditions should be determined by the environmental profile during the product's manufacturing, assembly and application process or the sensitive stresses existing in the product design itself.

4. A reliability evaluation method for internal interconnect solder joints of a stacked package chip as claimed in claim 1, characterized in that: The object of reliability stress test assessment and analysis can be increased or selected according to the actual application requirements or other requirements, and a specific combination of structural parameters can be added to carry out reliability stress test assessment and analysis.

5. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 4, characterized in that: The object of the reliability stress test assessment analysis can be designed and prepared with the structurally consistent engineering samples for reliability stress test assessment analysis in combination with the extraction results of the structural parameters in step S1 and the simulation analysis and simulation verification results.

6. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 4, characterized in that: The stress conditions for reliability test assessment and analysis include the stress conditions used in reliability simulation analysis and simulation verification.

7. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 4, characterized in that: The stress test assessment and analysis of the reliability of the internal interconnect solder joints of the stacked package chip has a deadline for the stress test assessment based on the failure or obvious performance degradation of the object of the stress test assessment and analysis.

8. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 1, characterized in that: In the step S4, the reliability performance degradation and defect characterization of the interconnection solder joints inside the stacked package chip requires monitoring the growth thickness and micromorphology changes of the intermetallic compound IMC layer at the interconnection interface.

9. A reliability evaluation method for internal interconnect solder joints of stacked package chips as claimed in claim 1, characterized in that: In the step S4, the reliability performance degradation and defect characterization of the internal interconnect solder joints of the stacked package chip are performed, and the interconnect solder joint defect characterization is performed by 3D-X-ray, red ink staining test, and SEM analysis after longitudinal section.

10. The reliability evaluation method for internal interconnect solder joints of stacked package chips according to claim 1, characterized in that: The reliability quantitative index of the interconnect solder joints of the stacked package chip can be used as a control index for quality control and screening assessment of mass-produced products.

Images