State Tracking and Location Method and System during FPGA Simulation of Processor Cores

Abstract

The present invention discloses a method and system for state tracking and positioning during the FPGA simulation of a processor core, belonging to the field of computer technology. The method includes: monitoring the key states of the processor core to be verified to obtain tracking data; restoring the tracking data into tracking data frames, and obtaining the change sequence of the abnormal states of the processor core after processing and analyzing the tracking data frames. The system includes: a target system to be tested, which is internally provided with a processor core to be verified and a key state tracker implemented by FPGA, and is connected to a host computer. A receiving program module and a positioning and analysis module are run on the host computer; after the key state tracker monitors the key states of the processor core to obtain tracking data, it outputs the tracking data to the host computer; the receiving program module restores the tracking data into tracking data frames, and the positioning and analysis module obtains the change sequence of the abnormal states of the processor core after processing and analyzing the tracking data frames. The present invention does not require tracking the program execution flow, greatly reducing the amount of tracking data.

Description

Technical Field

[0001] The invention belongs to the field of computer technology, and in particular relates to a state tracking and positioning method and system in a processor core FPGA simulation process. Background Art

[0002] Processor cores, especially high-performance processor cores, have a huge number of logic gates. In order to avoid design defects, they must undergo a large number of tests before tape-out. These tests include directional tests in a bare metal environment and tests based on some benchmark data sets under the operating system, such as SPEC CPU 2006. Since the number of logic gates of the processor is extremely large, complex tests are almost impossible to complete in a software simulation environment. In addition to software simulation, simulation can also be performed through FPGA (Field-Programmable Gate Array) or using a dedicated hardware simulation accelerator. Generally, a dedicated hardware simulation accelerator can achieve a simulation speed of about 0.5~10MHz, which is a huge improvement in simulation speed compared to software simulation. However, hardware simulation accelerators are extremely expensive, and the waveform window for observation is limited. For complex use cases, it takes several days to run to get simulation results.

[0003] Compared with simulation accelerators, FPGA simulation is low-cost and runs faster, usually reaching around 50~100MHz. Using FPGA to debug processor cores can be done through the software path of GDB (GNU Debugger) + OpenOCD (Open On-Chip Debugger) + JTAG (Joint Test Action Group) + Debug (debugging) kernel, or through waveform debugging. Using software path debugging faces the problem of slow debugging response and the inability to grasp the overall picture of the entire program flow, which makes it difficult for debuggers to track and analyze the program execution flow based on GDB. Using waveform debugging, it is impossible to track signals for a long time. At the same time, when changing the debug signal, the FPGA layout and wiring needs to be re-performed, which is a very time-consuming process. These two problems make it difficult to debug complex problems when using FPGA to simulate processor cores.

[0004] Tracing the program execution flow is a very effective method to grasp the overall running situation. Currently, many tracing methods are based on tracing the program counter (PC). Tracing is carried out through branch instructions and the number of consecutive instructions executed after a jump, and then these information flows are subjected to real-time hardware compression and sent to the host computer through the output port. There are mainly two problems with this method: First, the amount of data traced based on branches far exceeds the communication speed of general low-speed peripherals, such as JTAG and UART (Universal Asynchronous Receiver Transmitter). If additional information is to be provided, such as changes in the values of general registers, this problem will become even more severe. Second, to solve the problem of tracing such large amounts of data, a large amount of complex compression logic needs to be introduced or more complex high-speed communication ports need to be used, such as network ports and PCIE (Peripheral Component Interconnect Express) interfaces. Therefore, due to the data volume problem, tracing based on branches will inevitably lead to a large amount of complex logic.

[0005] In summary, the existing technologies for using FPGA to debug processor cores have technical defects such as a large amount of tracing data, difficult tracing, and difficult debugging. Summary of the Invention

[0006] In view of this, the present invention proposes a method and system for state tracking and positioning in the FPGA simulation process of a processor core. By adding a key state tracker in the processor core, the key state transitions of the processor core are tracked and restored to solve the technical defects of the existing methods for using FPGA to debug processor cores, such as a large amount of tracing data, difficult tracing, and difficult debugging.

[0007] In a first aspect, the present invention provides a method for state tracking and positioning in the FPGA simulation process of a processor core, including:

[0008] Monitoring the key states of the processor core to be verified on the target system under test to obtain tracing data, and transmitting the tracing data to the host computer through the simulation debugging interface. The key states of the processor core at least include the abnormal states entered by the processor core when program execution is interrupted, execution exceptions occur, system calls are made, and internal exceptions defined by the microarchitecture.

[0009] Restoring the tracing data into a tracing data frame, and obtaining a change sequence of the abnormal states of the processor core after processing and analyzing the tracing data frame.

[0010] Further, the method further includes:

[0011] Performing reliability encoding on the tracing data and then transmitting it to the host computer;

[0012] Decode the tracking data by using a decoding method corresponding to the reliability coding to obtain a data frame stream, and restore the key state of each abnormal point on the processor core through the obtained data frame.

[0013] In a second aspect, the present invention provides a state tracking and positioning system during the FPGA simulation of a processor core, including:

[0014] A target system to be tested, the target system to be tested is connected to a host computer through a simulation debugging interface, a processor core to be verified and a key state tracker implemented by FPGA are provided in the target system to be tested, and a receiving program module and a positioning and analysis module are run on the host computer;

[0015] After the key state tracker monitors the key state of the processor core to obtain tracking data, it outputs the tracking data to the host computer through the simulation debugging interface. The key state of the processor core at least includes the abnormal state entered by the processor core when program execution is interrupted, execution exception, system call, and internal exception defined by the microarchitecture;

[0016] The receiving program module restores the tracking data output by the key state tracker into a tracking data frame, and the positioning and analysis module processes and analyzes the tracking data frame to obtain a change sequence of the abnormal state of the processor core.

[0017] Further, the key state tracker further includes an encoder;

[0018] The encoder is used to perform reliability coding on the tracking data to enhance the reliability of the tracking data transmission.

[0019] Further, the key state tracker further includes an output controller;

[0020] The output controller is used to select to temporarily store the tracking data in the DDR memory or directly output it to the host computer.

[0021] Further, the key state tracker further includes a core tracker, and the core tracker is used to monitor the key state of the processor core to obtain tracking data; the core tracker includes:

[0022] A general register traverser, which is used to read and save the data saved in the general register when the operating system processes an exception; the general register traverser maintains a state machine, which is used to save the value of each general register read for the first time after the exception occurs to the first-in first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles;

[0023] A special-purpose register reader for reading and saving data saved to special-purpose registers when the operating system processes exceptions;

[0024] A custom register reader for reading and saving data saved to custom registers when the operating system processes exceptions, where the custom registers at least include a count value each time an exception is triggered and the process ID of the currently running task;

[0025] The first-in-first-out queue memory for storing the values saved by the general register traverser, the special-purpose register reader, and the custom register reader;

[0026] A frame packing module for packing the data stored in the first-in-first-out queue memory into data frames according to a fixed-order frame format.

[0027] Further, the positioning and analysis module is further configured to read the clock cycle interval between two adjacent trace data, and when the clock cycle interval is greater than a specified cycle threshold, output a prompt message of a software error that may have a long-term lock interruption.

[0028] Further, the positioning and analysis module is further configured to count the time when a specific interruption occurs. If the specific interruption does not occur in the trace data stream for more than a specified time, output a prompt message that the specific interruption may be lost. Or, count the number of times the specific interruption occurs. If the occurrence of the specific interruption in the trace data stream does not exceed a specified number of times, output a prompt message that the specific interruption may be lost.

[0029] Further, the positioning and analysis module is further configured to read the process ID and address space identifier in the trace data. If it is determined that the values of two adjacent trace data are different, output a prompt message of the process ID of the context switch and the new task.

[0030] Further, the operating system running on the processor core reads the exception count register before entering exception handling, interruption handling, or system calls.

[0031] In a third aspect, the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus; the memory is used for storing a computer program; when the processor is used to execute the program stored on the memory, it implements the state tracking and positioning method in the above-mentioned FPGA simulation process of the processor core.

[0032] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, it implements the state tracking and positioning method in the above-mentioned FPGA simulation process of the processor core.

[0033] The state tracking and positioning method and system during the FPGA simulation of the processor core provided by the present invention have the following advantages and beneficial effects:

[0034] Aiming at the problem of difficult simulation and debugging of the processor core on the existing FPGA, the present invention adds a key state tracker in the processor core. The key state tracker takes the exceptions of the processor core, such as interrupts, exceptions in the general sense, system calls, and internal exceptions defined by the microarchitecture, as the tracking points, and cooperates with the analysis and processing of the operating system kernel and the host computer to realize the tracking and restoration of the key state transitions of the processor core. Since the present invention tracks the exceptions of the processor core through the key state tracker in the processor core and does not need to track the program execution flow, the amount of tracking data is greatly reduced. Therefore, the amount of tracking data is much lower than the existing branch-instruction-based tracking method, and at the same time, the difficulty of tracking implementation is also reduced.

[0035] The present invention abandons the complex branch-instruction-based tracking method in the prior art, tracks the key states in the processor core, constructs the state change process of the processor core through the analysis software on the host computer, restores the key change sequences in the program execution process on each hardware thread, and corresponds to the software log of the operating system, which can effectively assist in locating the problems of complex programs and provide analysis materials for complex problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0037] Figure 1 is a flowchart of a state tracking and positioning method during the FPGA simulation of a processor core provided by an embodiment of the present invention;

[0038] Figure 2 is a block diagram of the composition of a state tracking and positioning system during the FPGA simulation of a processor core provided by an embodiment of the present invention;

[0039] Figure 3 is an implementation block diagram of a state tracking and positioning system during the FPGA simulation of a processor core provided by an embodiment of the present invention;

[0040] Figure 4 provided by an embodiment of the present invention Figure 3 is a structural block diagram of a key state tracker in;

[0041] Figure 5 provided by an embodiment of the present invention Figure 4 is a structural block diagram of a core tracker in;

[0042] Figure 6 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0043] The following will combine the accompanying drawings and give examples to further illustrate the technical solutions provided by the present invention. It should be understood that the system structure and service scenarios provided in the embodiments of the present invention are mainly for illustrating possible implementation manners of the technical solutions of the present invention, and should not be construed as the sole limitation of the technical solutions of the present invention. Those of ordinary skill in the art will know that with the evolution of the system structure and the emergence of new service scenarios, the technical solutions provided by the present invention are also applicable to similar technical problems.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. In case of inconsistency, the meaning described in this specification or the meaning obtained according to the content recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0045] As Figure 1 shown, Figure 1 A flowchart of a method for state tracking and positioning in the FPGA simulation of a processor core provided by an embodiment of the present invention is shown. The method includes the following steps:

[0046] Step S1, monitor the key states of the processor core to be verified on the target system to be tested to obtain tracking data, and transmit it to the host computer through the simulation debugging interface.

[0047] Among them, the critical states of the processor core at least include the exception states entered by the processor core when program execution is interrupted, execution exceptions occur, system calls are made, and internal exceptions defined by the microarchitecture. The critical states of the processor core can be the program counter (PC) value, system status value, general-purpose registers, exception cause, process identifier (PID) of the currently running task, address space identifier (ASID), and event counter (evcounter) when each exception is triggered, etc. For example, in a RISCV processor, the registers corresponding to these values are mepc (Machine Exception Program Counter), mstatus (Machine Status Register), GPR (General Purpose Registers), mcause (Machine Cause Register), satp (Supervisor Address Translation and Protection), and a separate register is added for the process number.

[0048] Optionally, the simulation debugging interface can be UART, JTAG, or Ethernet (Ethernet interface).

[0049] Step S2: Restore the trace data into trace data frames, and obtain the change sequence of the exception states of the processor core after processing and analyzing the trace data frames.

[0050] Optionally, in order to maintain high reliability of data transmission when using unreliable low-speed communication interfaces such as UART, JTAG, or Ethernet to transmit trace data to the host computer, the trace data can be reliability-encoded and then transmitted to the host computer. Encoding schemes such as error-correcting codes, redundant codes, or simple check codes can be used to encode the trace data from the perspective of the bit stream.

[0051] After the host computer receives the trace data, restore the trace data into trace data frames, and decode the trace data frames using a decoding method corresponding to the trace data encoding method to obtain a data frame stream, and restore the critical state of each exception point on the processor core through the obtained data frames.

[0052] The purpose of encoding the trace data in the embodiments of the present invention is to reduce the probability of bit errors occurring in data transmission and increase the reliability of the transmission process of the present invention.

[0053] Further, to better locate problems, the operating system running on the target system under test reads the value of the exception count (evcounter) register before entering exception handling, interrupt handling, and system calls. In this way, the tracking information of the hardware can be aligned with some log information of the software. In addition, the operating system running on the target system under test also needs to write the process ID of the currently running process into the process ID register during context switching. When monitoring processor core exceptions, this exception-related information can be read from the exception count register and the process ID register.

[0054] Further, a method for state tracking and location during the FPGA simulation of a processor core provided by an embodiment of the present invention may further include the following steps:

[0055] Read the clock cycle interval between two adjacent trace data. When the clock cycle interval is greater than the specified cycle threshold, output a prompt message for a software error that may cause a long-term lock interruption through a human-computer interaction method such as a graphical user interface;

[0056] Statistically analyze the time when a specific interruption occurs. If the specific interruption does not occur in the trace data stream for a period exceeding the specified time, output a prompt message indicating that the specific interruption may be lost through a human-computer interaction method such as a graphical user interface; or, statistically analyze the number of times a specific interruption occurs. If the number of occurrences of the specific interruption in the trace data stream does not exceed the specified number, output a prompt message indicating that the specific interruption may be lost through a human-computer interaction method such as a graphical user interface;

[0057] Read the process ID and address space identifier in the trace data. If it is determined that the values of two adjacent trace data are different, output a prompt message for the process ID of the context switch and the new task through a human-computer interaction method such as a graphical user interface.

[0058] As Figure 2 and Figure 3 shown, to implement the above method for state tracking and location during the FPGA simulation of a processor core provided by an embodiment of the present invention, an embodiment of the present invention provides a system for state tracking and location during the FPGA simulation of a processor core. The state tracking and location system includes a target system under test 101. The target system under test 101 is connected to a host computer 102 through a simulation debugging interface. A processor core 1011 to be verified and a key state tracker 1012 implemented with an FPGA are provided in the target system under test 101. A receiving program module 1021 and a location analysis module 1022 are run on the host computer 102.

[0059] Optionally, there may be one or more processor cores 1011 in the target system under test 101. When there are multiple processor cores 1011 in the target system under test 101, a key state tracker 1012 may be set in the target system under test 101 to monitor the key states of multiple processor cores 1011 simultaneously, or the same number of key state trackers 1012 as the number of processor cores 1011 may be set, with one processor core 1011 corresponding to one key state tracker 1012 to monitor the key state of the corresponding processor core 1011.

[0060] The key state of the processor core 1011 may be an abnormal state entered by the processor core when program execution is interrupted, execution exception under normal circumstances, system call, or internal exception defined by the microarchitecture. The key state tracker 1012 monitors the key state of the processor core 1011 to obtain tracking data.

[0061] The key state tracker 1012 outputs the tracking data to the host 102 through the simulation debugging interface. Optionally, the simulation debugging interface may be UART, JTAG, or Ethernet.

[0062] A receiving program module 1021 runs on the host 102 side. The receiving program module 1021 restores the received data stream into tracking data frames, and these tracking data frames can be handed over to the positioning and analysis module 1022 for processing. After processing and analysis, a change sequence of the abnormal states of each processor core 1011 in the system is obtained. The positioning and analysis module 1022 constructs the state change process of the processor, restores the key change sequence in the program execution process on each hardware thread, and corresponds to the software log of the operating system, which can effectively assist in positioning problems in complex programs.

[0063] Furthermore, in order to better locate problems, the operating system running on the target system under test 101 reads the value of the exception count register before entering exception handling, interrupt handling, or system call. In this way, the tracking information of the hardware can be aligned with some log information of the software. In addition, the operating system running on the target system under test 101 also needs to write the current running process ID into the process ID register during context switching. When the key state tracker 1012 monitors processor core exceptions, it can read this exception-related information from the exception count register and the process ID register.

[0064] Optionally, in order to maintain high reliability of data transmission when using unreliable low-speed communication interfaces such as UART, JTAG, or Ethernet to transfer tracking data to the host 102, such as Figure 4As shown, an encoder is added to the key state tracker 1012, and the encoder is used to perform reliability encoding on the tracking data to enhance the reliability of the tracking data transmission. The encoder can use coding schemes such as error correction code, redundant code or simple check code to encode the tracking data from the perspective of the bit stream, reduce the probability of bit errors in data transmission, and increase the reliability of the transmission process of the present invention.

[0065] Alternatively, if Figure 4 As shown, an output controller may be further added to the key state tracker 1012 , and the output controller is used to select whether to temporarily store the tracking data in a DDR memory (Double Data Rate Synchronous Dynamic RandomAccess Memory) or directly output the tracking data to the host machine 102 .

[0066] like Figure 4 As shown, the key state tracker 1012 is composed of a core tracker, an encoder, and an output controller. The core tracker completes the tracking of the key state of each processor core 1011 in the system on chip (SoC). The key state may include the program counter value, system status value, general register, exception reason, process number, address space identifier, etc. when an exception occurs. For example, in a RISCV processor, the registers corresponding to these values ​​are mepc, mstatus, GPR, mcause, satp, and for the process number, a separate register is added.

[0067] like Figure 5 As shown, the core tracker is the core component for tracking key states on each processor core 1011, and the core tracker consists of a general register traverser, a special purpose register reader, a custom register reader, a first-in-first-out queue memory, and a frame packing module.

[0068] Among them, the general register traverser is used to read and save the data saved to the general register when the operating system handles an exception. The general register traverser maintains a state machine for saving the value of each general register read for the first time after the exception occurs to the first-in-first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles.

[0069] General registers are indispensable in the process of program flow control and are usually an important part of the context in a computer operating system. However, in a high-performance processor, due to the presence of multiple execution pipelines, register files are read and written simultaneously. If all general registers are read in one cycle, too many reading ports are required, which is almost impossible to achieve. Therefore, the present invention adopts a traversal method, that is, gradually obtaining the values ​​of general registers through multiple cycles, rather than reading the values ​​of general registers at one time.

[0070] Considering that when an exception defined by the instruction set architecture occurs, the operating system generally saves the general registers when handling these exceptions, and there must be a process of reading the general registers. Therefore, after receiving the architecture-defined exception event, the general register traverser in the present invention monitors the read ports of the general registers, and maintains a state machine in the general register traverser to save the value of each general register read for the first time after the exception occurs to the first-in-first-out queue memory. When the values of all general registers are saved, this traversal is completed.

[0071] Among them, the special purpose register reader is used to read and save the data saved to the special purpose registers (Special Purpose Register, SPR) when the operating system processes exceptions. These registers include the program counter value, system status, exception cause, clock cycle count, address space identifier value, etc. when an exception occurs. For example, in the RISCV processor, the registers corresponding to these values are mepc, mstatus, mcause, satp, etc. The read values are saved to the first-in-first-out queue memory.

[0072] Among them, the custom register reader is used to read and save the data saved to the custom registers when the operating system processes exceptions. The custom registers at least include the count value when each exception is triggered and the process number of the currently running task. The exception count register is incremented each time an exception is triggered, and the process number register is used to save the process number of the currently running task.

[0073] Among them, the first-in-first-out queue memory is used to store the values saved by the general register traverser, the special purpose register reader, and the custom register reader.

[0074] The first-in-first-out queue memory is controlled by the general register traverser, the special purpose register reader, and the custom register reader for the write port, and is controlled by the frame packing module for the read port. That is, the general register traverser, the special purpose register reader, and the custom register reader write the values of the general registers, the special purpose registers, and the custom registers to the first-in-first-out queue memory through the write port of the first-in-first-out queue memory, and these values are read out by the frame packing module through the read port of the first-in-first-out queue memory in a first-in-first-out manner.

[0075] Preferably, in order to enable the first-in-first-out queue memory to provide more read and write ports to avoid read-write conflicts, in the embodiment of the present invention, multiple random access memories (RAMs) are spliced into a large-bitwidth first-in-first-out queue memory. The random access memory can use a simple dual-port random access memory, and the depth of the first-in-first-out queue memory can be relatively shallow, that is, the first-in-first-out queue memory can store a relatively small number of data items.

[0076] Among them, the frame packing module is used to pack the data stored in the first-in first-out queue memory into data frames according to a fixed-order frame format. The data in the data frames is arranged in a fixed order. Preferably, it is arranged in the order of the hardware thread number where an exception occurs, the clock cycle count value, the custom register value, the address space identifier value, the exception reason, the general register value, etc.

[0077] As Figure 3 shown, the processing and analysis tool of the host computer 102 provided by the embodiment of the present invention is divided into two parts: a receiving program module 1021 and a positioning and analysis module 1022. The receiving program module 1021 receives trace data packets from UART / JTAG / Ethernet. Optionally, the data packets are decoded according to the decoding method corresponding to the encoding method adopted by the encoder in the Figure 4 key status tracker. After decoding, the trace data frames can be obtained. The positioning and analysis module 1022 restores the key status of each exception point on the processor core through the obtained data frame stream.

[0078] Furthermore, the positioning and analysis module 1022 can also implement the following functions:

[0079] The positioning and analysis module 1022 reads the clock cycle interval between two adjacent trace data. When the clock cycle interval is greater than the specified cycle threshold, a prompt message of a software error that may cause a long-time lock interruption is output through a human-computer interaction method such as a graphical user interface.

[0080] The positioning and analysis module 1022 counts the time when a specific interruption occurs. If the specific interruption does not occur in the trace data stream for more than the specified time, a prompt message indicating that the specific interruption may be lost is output through a human-computer interaction method such as a graphical user interface; or, the number of times the specific interruption occurs is counted. If the occurrence of the specific interruption in the trace data stream does not exceed the specified number of times, a prompt message indicating that the specific interruption may be lost is output through a human-computer interaction method such as a graphical user interface.

[0081] Specifically, each interruption has a type identifier to distinguish different interruption sources or reasons. The time and number of occurrences of a specific interruption can be identified according to the type identifier of the specific interruption. If an interruption does not occur for a long time, it may be because the interruption is accidentally masked, there is a problem with the interruption handler, or the interruption processing flow is blocked due to hardware failure or other reasons.

[0082] The positioning and analysis module 1022 reads the process number and address space identifier in the trace data. If it is determined that the values of two adjacent trace data are different, a prompt message of the process number of the context switch and the new task is output through a human-computer interaction method such as a graphical user interface.

[0083] As shown Figure 6 in the figure, an embodiment of the present invention further provides an electronic device, including a processor 201, a communication interface 202, a memory 203, and a communication bus 204. Among them, the processor 201, the communication interface 202, and the memory 203 complete mutual communication through the communication bus 204. The memory 203 is used to store a computer program. When the processor 201 is used to execute the program stored on the memory 203, the state tracking and positioning method in the foregoing processor core FPGA simulation process provided by the embodiment of the present invention is implemented.

[0084] In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the state tracking and positioning method in the foregoing processor core FPGA simulation process provided by the embodiment of the present invention is implemented.

[0085] The computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this article, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.

[0086] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable medium may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0087] The program code included on the computer-readable medium may be transmitted by any suitable medium, including but not limited to wireless, wire, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the above.

[0088] Computer program code for performing the operations of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected through the Internet using an Internet service provider).

[0089] Embodiments of the present invention address the problem of difficult simulation and debugging of processor cores on existing FPGAs. A key state tracker is added inside the processor core. The key state tracker uses exceptions in the processor core, such as interrupts, exceptions in the general sense, system calls, and internal exceptions defined by the microarchitecture, as tracking points, and collaborates with the analysis and processing of the operating system kernel and the host computer to achieve tracking and restoration of key state transitions in the processor core. Since the present invention tracks exceptions in the processor core through the key state tracker inside the processor core and does not need to track the program execution flow, the amount of tracking data is greatly reduced. Therefore, the amount of tracking data is much lower than that of existing tracking methods based on branch instructions, and at the same time, the difficulty of tracking implementation is also reduced.

[0090] Embodiments of the present invention abandon the complex branch-instruction-based tracking method in the prior art, track the key states inside the processor core, construct the state change process of the processor core through analysis software on the host computer, restore the key change sequences during the program execution on each hardware thread, and correspond to the software logs of the operating system, which can effectively assist in locating problems in complex programs and provide analysis materials for complex problems.

[0091] It should be noted that the embodiments described in the present invention are only a part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention usually described and illustrated in the drawings may be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but only represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0092] The terms "first," "second," "third," etc. or similar terms such as Module A, Module B, Module C, etc. in the specification and claims are only used to distinguish similar objects and do not represent a specific order for the objects. Understandably, the specific order or sequence can be interchanged where permitted so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

[0093] In the above description, the reference numerals indicating steps do not necessarily mean that the steps will be executed in this order. It may also include intermediate steps or be replaced by other steps. Where permitted, the order of the front and rear steps can be interchanged, or the steps can be executed simultaneously.

[0094] The term "comprising" used in the specification and claims should not be construed as being limited to the content listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the stated features, wholes, steps, or components, but does not exclude the presence or addition of one or more other features, wholes, steps, or components and their groups. Therefore, the expression "a device comprising device A and B" should not be limited to a device consisting only of components A and B.

[0095] The "one embodiment" or "embodiment" mentioned in this specification means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. In addition, in various embodiments of the present invention, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0096] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, all of which fall within the protection scope of the present invention.

Claims

1. A state tracking and positioning system in a processor core FPGA simulation process, characterized in that: include: A target system to be tested, wherein the target system to be tested is connected to a host machine via a simulation debugging interface, wherein a processor core to be verified and a key state tracker implemented by FPGA are arranged in the target system to be tested, and a receiving program module and a positioning analysis module are running on the host machine; The key state tracker monitors the key state of the processor core to obtain tracking data and then outputs it to the host machine through the simulation debugging interface, wherein the key state of the processor core at least includes the abnormal state entered by the processor core when program execution is interrupted, execution is abnormal, system call, or internal abnormality defined by the micro-architecture; The receiving program module restores the tracking data output by the key state tracker into a tracking data frame, and the positioning analysis module processes and analyzes the tracking data frame to obtain a change sequence of the abnormal state of the processor core; The key state tracker includes a core tracker, and the core tracker is used to monitor the key state of the processor core to obtain tracking data; the core tracker includes: A general register traverser is used to read and save data saved to the general register when the operating system handles an exception; the general register traverser maintains a state machine for saving the value of each general register read for the first time after the exception occurs to a first-in-first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles; A special purpose register reader for reading and saving data saved to special purpose registers when the operating system handles an exception; A custom register reader, used to read and save data saved to the custom register when the operating system handles an exception, wherein the custom register includes at least a count value each time an exception is triggered and a process number of the currently running task; The first-in-first-out queue memory is used to store the values ​​saved by the general register walker, the special purpose register reader and the custom register reader; The frame packing module is used to pack the data stored in the first-in-first-out queue memory into data frames according to a fixed-order frame format.

2. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The key state tracker also includes an encoder; The encoder is used for performing reliability encoding on the tracking data to enhance the reliability of the tracking data transmission.

3. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The critical state tracker also includes an output controller; The output controller is used to select whether to temporarily store the tracking data in a DDR memory or directly output the tracking data to the host machine.

4. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The positioning analysis module is also used to read the clock cycle interval between two adjacent tracking data, and when the clock cycle interval is greater than a specified cycle threshold, output a prompt message of a software error that may occur during a long lock interruption.

5. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The positioning analysis module is also used to count the time when a specific interruption occurs. If the specific interruption does not appear in the tracking data stream for more than a specified time, a prompt message that the specific interruption may be lost is output; or, to count the number of times a specific interruption occurs. If the number of times the specific interruption appears in the tracking data stream does not exceed a specified number, a prompt message that the specific interruption may be lost is output.

6. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The positioning analysis module is also used to read the process number and address space identifier in the tracking data, and if it is determined that the values ​​of two adjacent tracking data are different, output prompt information of the context switch and the process number of the new task.

7. The state tracking and positioning system in the processor core FPGA simulation process according to claim 1, characterized in that: The operating system running on the processor core reads the exception count register before entering exception processing, interrupt processing or system call.

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