Module-level voltage drop detection method and device, electronic equipment and readable storage medium

Abstract

The invention provides a module-level voltage drop detection method and device, electronic equipment and a readable storage medium. The method comprises the following steps: acquiring top-layer design information of a chip; obtaining design information of all target modules from the top-layer design information to obtain to-be-detected design information; the target module comprises a to-be-detected module and modules around the to-be-detected module; and analyzing the to-be-detected design information to obtain a voltage drop detection result of the to-be-detected module. According to the scheme, when module-level voltage drop detection is carried out, the influence of the modules around the module to be detected on current distribution is considered, so that the accuracy of module-level voltage drop detection is improved to a certain extent, the detection reliability of the voltage drop risk in the early stage of chip design is improved, the chip design progress can be accelerated, and the chip design efficiency is improved. And the resource waste caused by repairing the detected inaccurate violation can be reduced to a certain extent.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and in particular to a module-level voltage drop detection method, device, electronic device and readable storage medium. Background Art

[0002] In the early to mid-stage of chip design, the voltage drop at the module level needs to be checked separately because the top-level voltage drop simulation data is incomplete. However, it is currently found that the module-level voltage drop simulation results are not accurate enough and there is a large deviation from the top-level voltage drop simulation results performed in the later stages of the design. Inaccurate voltage drop simulation results at the early module level will result in the inability to accurately detect the real voltage drop risk in the early stages of chip design, thereby delaying the chip design progress, and repairing the detected inaccurate violations will also result in a waste of resources. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a module-level voltage drop detection method, device, electronic device and readable storage medium, so as to solve the problem of inaccurate module-level voltage drop detection in related technologies to a certain extent.

[0004] An embodiment of the present application provides a module-level voltage drop detection method, including: obtaining top-level design information of a chip; obtaining design information of all target modules from the top-level design information to obtain design information to be detected; the target module includes a module to be detected and modules around the module to be detected; and analyzing the design information to be detected to obtain a voltage drop detection result of the module to be detected.

[0005] In the above implementation scheme, when performing voltage drop detection on the module to be detected, the design information of the module to be detected and the modules around the module to be detected are used as analysis objects for voltage drop detection analysis. In this way, when performing module-level voltage drop detection, the influence of the modules around the module to be detected on the current distribution is taken into account, thereby improving the accuracy of module-level voltage drop detection to a certain extent, and further improving the detection reliability of voltage drop risks in the early stage of chip design, which can improve the chip design progress and can also reduce the waste of resources caused by repairing inaccurate violations detected to a certain extent.

[0006] Furthermore, before obtaining the design information of all target modules from the top-level design information, the method also includes: taking the module to be detected as the center, determining a target area whose edge is a preset distance from the module to be detected; the preset distance is a distance that allows a power supply network to be present in the target area; and determining all target modules in the chip based on the target area.

[0007] In the above implementation, the target area whose edge is at a preset distance from the module to be detected is determined with the module to be detected as the center, and all target modules in the chip are determined with the target area as the reference. In this way, the design information of each module within the preset distance from the module to be detected around the module to be detected can be combined with the design information of the module to be detected to form the design information to be detected for analysis and detection, and because there is a power supply network in the target area, when analyzing based on the design information to be detected, in addition to obtaining the influence of the modules around the module to be detected on the current distribution, the influence of the power supply network used by each module on the current can also be obtained, thereby further improving the accuracy of module-level voltage drop detection.

[0008] Furthermore, the preset distance is equal to two bump pitches (the distance between center points of bumps of the same polarity).

[0009] It is found through experiments that when the area obtained by expanding 2 or more bump pitches around any module as the center, the voltage drop variation will converge. Therefore, in the above implementation, the preset distance is set to 2 bump pitches, so that the analysis of the design information to be detected can have better reliability, that is, the influence of the modules around the module to be detected and the power supply network used on the current distribution can be effectively introduced to improve the accuracy of the voltage drop detection result of the module to be detected, thereby reducing the number of target modules, thereby reducing the size of the design information to be detected and improving the efficiency of detection and analysis.

[0010] Further, all target modules in the chip are determined according to the target area, including: all modules in the chip that have intersections with the target area are determined as the target modules.

[0011] In the above implementation method, all modules in the chip that have intersections with the target area are determined as target modules, that is, all modules located in the target area and all modules with partial areas located in the target area are regarded as target modules. In this way, the design information to be tested can be more comprehensive, so that the analysis of the design information to be tested can have better reliability.

[0012] Further, the preset distance is N bump pitches; N is a positive integer greater than or equal to 3; and all target modules in the chip are determined according to the target area, including: determining all modules in the chip located in the target area as the target modules.

[0013] As mentioned above, when the preset distance is greater than or equal to 2 bump pitches, the voltage drop variation will converge. Then, when the preset distance is greater than or equal to 3 bump pitches, only all modules in the chip located in the target area are determined as target modules. Although not all modules with some areas located in the target area are used as target modules at this time, the positions of each module determined as a target module can basically cover the area extended by 2 bump pitches. Therefore, based on the above method, the influence of the modules around the module to be detected and the power supply network used on the current distribution can also be effectively introduced to improve the accuracy of the voltage drop detection result of the module to be detected. The number of target modules can be reduced, thereby reducing the size of the design information to be detected and improving the efficiency of detection and analysis.

[0014] Further, the preset distance is obtained according to the following method: respectively testing the voltage drop values ​​generated by the same standard unit after expanding different numbers of bump pitches; determining the number of bump pitches when the voltage drop value converges; and determining the preset distance according to the number of bump pitches when the voltage drop value converges.

[0015] In the above implementation, different areas after expansion are tested with the standard cell as the center point, so that the relationship between different numbers of bump pitches and the change in voltage drop can be effectively summarized. Since the module is composed of standard cells, the influence of modules on voltage drop is consistent with the influence of standard cells on voltage drop. Therefore, the test is directly based on the standard cell, and its test results can be applied to the module, and the test complexity is lower.

[0016] Furthermore, the top-level design information includes: modules included in the top level, the relationship between the modules, and the design information of each module; the design information of each module includes: standard units included in the module and the relationship between the standard units.

[0017] Furthermore, the design information to be tested is analyzed to obtain the voltage drop detection result of the module to be tested, including: obtaining the parasitic parameter information and time window information of each target module; inputting the design information to be tested, the parasitic parameter information and the time window information of each target module into a preset analysis tool to obtain the voltage drop detection result of the module to be tested.

[0018] In the above implementation, the design information to be tested, the parasitic parameter information of each target module and the time window information are input into a preset analysis tool for analysis. In this way, while considering the influence of the modules around the module to be tested on the current distribution, the parasitic parameter information and the time window information of each target module can be further considered, thereby further improving the accuracy of module-level voltage drop detection.

[0019] An embodiment of the present application also provides a module-level voltage drop detection device, including: a first acquisition module, used to obtain the top-level design information of the chip; a second acquisition module, used to obtain the design information of all target modules from the top-level design information to obtain the design information to be detected; the target module includes the module to be detected and the modules around the module to be detected; an analysis module, used to analyze the design information to be detected to obtain the voltage drop detection result of the module to be detected.

[0020] An embodiment of the present application also provides an electronic device, including: a processor and a memory; the processor is used to execute one or more programs stored in the memory to implement any of the above-mentioned module-level voltage drop detection methods.

[0021] A computer-readable storage medium is also provided in an embodiment of the present application. The computer-readable storage medium stores one or more programs. The one or more programs can be executed by one or more processors to implement any of the above-mentioned module-level voltage drop detection methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A basic flow chart of a module-level voltage drop detection method provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of a method for determining a target area provided in an embodiment of the present application;

[0025] Figure 3 A voltage drop variation trend diagram corresponding to different bump pitches provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the structure of a module-level voltage drop detection device provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0029] In order to solve the problem of inaccurate module-level voltage drop detection in the related art to a certain extent, a module-level voltage drop detection method is provided in the embodiment of the present application. Figure 1 As shown, Figure 1 The basic flow chart of the module-level voltage drop detection method provided in the embodiment of the present application includes:

[0030] S101: Obtain top-level design information of the chip.

[0031] In the embodiment of the present application, the top-level design information of the chip refers to the design information of the top level of the chip, including the modules contained in the top level, the relationship between the modules, and the design information of the modules. Exemplarily, the top-level design information of the chip may include a DEF (Design exchange format) file of the top level of the chip. In the DEF file of the top level of the chip, the modules of the top level, the location of the modules, the logical connection relationship between the modules, etc. are recorded.

[0032] In the embodiment of the present application, a module refers to a functional module used in a chip, which can realize a specific function that is set. A module is composed of a large number of standard cells. Therefore, in the embodiment of the present application, the design information of a module may include: the standard cells included in the module and the relationship between the standard cells. Exemplarily, the design information of a module may include a DEF file of the module. In the DEF file of the module, the standard cells included in the module, the location of each standard cell, the logical connection relationship between the standard cells, etc. are recorded.

[0033] In the embodiment of the present application, the so-called module-level voltage drop detection refers to: detecting the voltage drop of a module included in the top layer of the chip.

[0034] S102: Acquire design information of all target modules from the top-level design information to obtain design information to be tested.

[0035] In the embodiment of the present application, each module can be associated with the DEF file of each module by calling in the DEF file at the top level of the chip. Then, correspondingly, when obtaining the design information of all target modules from the top-level design information to obtain the design information to be tested, the DEF files of each target module can be gathered together by calling the DEF file at the top level of the chip to form a new DEF file, and the new DEF file can be used as the design information to be tested.

[0036] Of course, in some other optional implementations of the embodiments of the present application, the design information of each module may be directly written into the top-level design information, and then the design information of each target module may be directly extracted from the top-level design information to obtain the design information to be tested.

[0037] In the embodiment of the present application, the target module includes the module to be detected and the modules around the module to be detected. In this way, the obtained design information to be detected can include the design information of the module to be detected and the design information of the modules around the module to be detected, so that when the design information to be detected is subsequently analyzed, the influence of the modules around the module to be detected on the current distribution can be introduced, thereby improving the accuracy of module-level voltage drop detection.

[0038] In a feasible implementation of the embodiment of the present application, a target area can be determined based on the module to be detected, and then the target module can be determined based on the target area.

[0039] Exemplarily, the module to be detected can be taken as the center to determine the target area whose edge is at a preset distance from the module to be detected, and then all the target modules in the chip can be determined based on the target area. The preset distance is a distance that allows the target area to have a power supply network. In this way, the design information of each module within the preset distance from the module to be detected around the module to be detected can be combined with the design information of the module to be detected to form the design information to be detected for analysis and detection. Since there is a power supply network in the target area, when analyzing based on the design information to be detected, in addition to obtaining the influence of the modules around the module to be detected on the current distribution, the influence of the power supply network used by each module on the current can also be obtained, thereby further improving the accuracy of module-level voltage drop detection.

[0040] In the chip, the power mesh used inside the chip is introduced by the bump, so the preset distance can be set based on the bump pitch to include the power mesh in the target area. In theory, taking the module to be detected as the center and expanding the target area by at least one bump pitch, at least one bump can be included in the target area, so that the target area has a power mesh.

[0041] In an embodiment of the present application, an optional implementation method for determining a target area whose edge is a preset distance from the module to be detected with the module to be detected as the center is to draw a circle with a radius of the preset distance plus half of the diagonal distance of the module to be detected and the center position of the module to be detected as the center.

[0042] In an embodiment of the present application, another optional implementation method of determining a target area whose edge is a preset distance from the module to be detected with the module to be detected as the center is to use the coordinates of each vertex of the module to be detected as a reference, expand the preset distance respectively, and obtain a target area with a shape consistent with the module to be detected.

[0043] For example, see Figure 2 As shown, assuming that the four vertex coordinates of the module to be detected are (X1, Y1), (X2, Y2), (X3, Y3), and (X4, Y4), and the preset distance is L, the four vertex coordinates of the target area can be obtained as (X1-L, Y1-L), (X2-L, Y2+L), (X3+L, Y3+L), and (X4+L, Y4-L).

[0044] In an optional implementation of the embodiment of the present application, the preset distance can be determined based on the following method: testing the voltage drop values ​​generated by the same standard unit after expanding different numbers of bump pitches; determining the number of bump pitches when the voltage drop value converges; and determining the preset distance according to the number of bump pitches when the voltage drop value converges.

[0045] In this way, different areas after expansion are tested with the standard cell as the center point, so that the relationship between different numbers of bump pitches and the change in voltage drop can be effectively summarized. In addition, the module is composed of standard cells, so the relationship between modules and modules on voltage drop is consistent with the relationship between standard cells and standard cells on voltage drop. Therefore, the test results can be applied to modules directly based on standard cells, and the test complexity is lower.

[0046] It can be understood that, in theory, all bumps in the chip are of the same potential and can be short-circuited together. The resistance from the standard unit (instance) to each bump is close. The difference between the resistance path from the instance to the distant bump and to the nearby bump is that the resistance path of the bump far from the instance is longer than the resistance path of the bump close to the instance through the high-level metal, and the resistance of the high-level metal is very small.

[0047] Then, in the embodiment of the present application, the EDA tool can be used to test the voltage drop value of the same instance when it is expanded by 0 bump pitches (i.e., no expansion, recorded as bump pitch_0), expanded by 1 bump pitch (recorded as bump pitch_1), expanded by 2 bump pitches (recorded as bump pitch_2), and expanded by 3 bump pitches (recorded as bump pitch_3). Since the resistance from the standard unit (instance) to each bump is close, the main influencing factors of the change of the voltage drop value at this time are other instances in the area after expansion, and the influence of the connected pg mesh on the current distribution.

[0048] See also Figure 3 The voltage drop trend diagram corresponding to different bump pitches is shown. Figure 3 The horizontal axis represents bumppitch, and the vertical axis represents pressure drop. Figure 3 It can be seen that when the bump pitch is greater than or equal to 2, the voltage drop value of the instance tends to be stable, that is, the voltage drop value converges.

[0049] Therefore, in a feasible implementation of the embodiment of the present application, the preset distance may be N bump pitches, where N is a positive integer greater than or equal to 2.

[0050] Exemplarily, the preset distance may be equal to 2 bump pitches. In this way, the analysis of the design information to be detected can be made more reliable, that is, the number of target modules can be reduced while the influence of the modules around the module to be detected and the power supply network used on the current distribution is effectively introduced to improve the accuracy of the voltage drop detection result of the module to be detected, thereby reducing the size of the design information to be detected and improving the efficiency of the detection analysis.

[0051] In some other implementations of the embodiment of the present application, the preset distance may also be set to 1 bump pitch.

[0052] In an embodiment of the present application, an optional way to determine the target module is: after determining the target area, all modules in the chip that have an intersection with the target area can be determined as target modules. That is, all modules in the chip that are located in the target area, and all modules that have partial areas located in the target area can be used as target modules. The design information to be detected obtained in this way can be more comprehensive, so that the analysis of the design information to be detected can have better reliability.

[0053] In the embodiment of the present application, when the preset distance is 3 or more bump pitches, there is another optional way to determine the target module: after determining the target area, all modules in the chip located in the target area are determined as target modules.

[0054] As mentioned above, when the preset distance is greater than or equal to 2 bump pitches, the voltage drop variation will converge. Then, in the above method, when the preset distance is greater than or equal to 3 bump pitches, only all modules in the chip located in the target area are determined as target modules. Although all modules with partial areas located in the target area are not regarded as target modules at this time, the positions of each module determined as the target module can basically cover the area extended by 2 bump pitches. Therefore, based on the above method, the influence of the modules around the module to be detected and the power supply network used on the current distribution can also be effectively introduced to improve the accuracy of the voltage drop detection result of the module to be detected. The number of target modules can be reduced, thereby reducing the size of the design information to be detected and improving the efficiency of detection and analysis.

[0055] In another feasible implementation of the embodiment of the present application, the target module may also be determined directly based on the proximity to the module to be detected.

[0056] Exemplarily, in an optional embodiment, each first module directly adjacent to the module to be detected may be used as a target module together with the module to be detected.

[0057] As another example, in another optional embodiment, each first module directly adjacent to the module to be detected, each second module directly adjacent to each first module, and the module to be detected may be taken as the target module.

[0058] Also exemplarily, in another optional embodiment, each first module directly adjacent to the module to be detected, each second module directly adjacent to each first module, each third module directly adjacent to each second module, and the module to be detected can be taken as the target module.

[0059] S103: Analyze the design information to be tested to obtain the voltage drop test result of the module to be tested.

[0060] In the embodiment of the present application, a preset analysis tool may be used to analyze the design information to be detected to obtain a voltage drop detection result of the module to be detected.

[0061] The preset analysis tool may be an EDA tool, but is not limited thereto.

[0062] In a feasible implementation of the embodiment of the present application, the parasitic parameter information and time window information of each target module can also be obtained, and then the design information to be detected, the parasitic parameter information and time window information of each target module are input into a preset analysis tool to obtain the voltage drop detection result of the module to be detected. In this way, while considering the influence of the modules around the module to be detected on the current distribution, the parasitic parameter information and time window information of each target module can be further considered, thereby further improving the accuracy of module-level voltage drop detection.

[0063] In this optional implementation manner, the parasitic parameter information of each target module may be obtained by obtaining a SPEF (Standard Parasitic Extraction Format) file of each target module.

[0064] Based on the module-level voltage drop detection method provided in the embodiment of the present application, when performing voltage drop detection on the module to be detected, the design information of the module to be detected and the modules around the module to be detected are used as analysis objects for voltage drop detection analysis. In this way, when performing module-level voltage drop detection, the influence of the modules around the module to be detected on the current distribution is taken into account, thereby improving the accuracy of module-level voltage drop detection to a certain extent, and further improving the detection reliability of voltage drop risks in the early stage of chip design, which can improve the chip design progress and can also reduce the waste of resources caused by repairing inaccurate detected violations to a certain extent.

[0065] To facilitate understanding of the solutions of the embodiments of the present application, a specific implementation method is taken as an example to further illustrate the present application.

[0066] First, get the top-level DEF file for the chip.

[0067] The acquisition method may be to set the name of the analysis check to the top-level name of the chip design, thereby reading the DEF file of the top-level of the chip.

[0068] Then, with the module to be detected as the center, the target area within the range of two bump pitches around the module to be detected is determined.

[0069] Assuming that the four vertex coordinates of the module to be detected are (X1, Y1), (X2, Y2), (X3, Y3), (X4, Y4), the target area can be obtained as the four vertex coordinates (X1-2*bump_pitch, Y1-2*bump_pitch), (X2-2*bump_pitch, Y2+2*bump_pitch), (X3+2*bump_pitch, Y3+2*bump_pitch), (X4+2*bump_pitch, Y4-2*bump_pitch). Among them, bump_pitch is the distance of a single bump pitch.

[0070] Then, all modules in the chip that intersect with the target area are determined as target modules, and the design information to be tested is constructed by calling the DEF files of each target module inside the DEF file at the top level of the chip (still expressed in the form of a DEF file, and the expression method is consistent with the DEF file at the top level of the chip, but the content only includes the information of each target module compared to the DEF file at the top level of the chip, and does not include information of other modules except the target module).

[0071] The SPEF file of each target module and the Timing window (time window information) of each target module are read in parallel, and the design information to be tested, the SPEF file of each target module and the Timing window of each target module are analyzed together using conventional voltage drop simulation tools or methods to obtain the voltage drop test result of the module to be tested.

[0072] Through the above scheme, the present application can more accurately detect the violation points of voltage drop in the early stage of chip design, thereby improving the chip design progress, and can also reduce the waste of resources caused by repairing inaccurate violations detected, saving project resources.

[0073] Based on the same inventive concept, the present application also provides a module-level voltage drop detection device 400. Figure 4 As shown, Figure 4 Shows the use of Figure 1 The module-level voltage drop detection device of the method shown. It should be understood that the specific functions of the device 400 can be referred to the description above, and the detailed description is appropriately omitted here to avoid repetition. The device 400 includes at least one software function module that can be stored in a memory in the form of software or firmware or fixed in the operating system of the device 400. Specifically:

[0074] See also Figure 4 As shown, the device 400 includes: a first acquisition module, a second acquisition module and an analysis module. Among them:

[0075] The first acquisition module is used to acquire the top-level design information of the chip;

[0076] A second acquisition module is used to acquire design information of all target modules from the top-level design information to obtain design information to be detected; the target module includes the module to be detected and modules around the module to be detected;

[0077] The analysis module is used to analyze the design information to be detected to obtain the voltage drop detection result of the module to be detected.

[0078] In a feasible implementation of the embodiment of the present application, the device 400 may further include a determination module, which is used to determine a target area with a preset distance from the edge of the module to be detected, with the module to be detected as the center, before the second acquisition module acquires the design information of all target modules from the top-level design information, and determine all target modules in the chip according to the target area. The preset distance is a distance that allows the target area to have a power network.

[0079] In an optional embodiment of this feasible implementation mode, the preset distance is equal to the distance bump pitch between the center points of two bumps of the same polarity.

[0080] In an optional embodiment of this feasible implementation mode, the determination module is specifically used to determine all modules in the chip that have intersections with the target area as the target modules.

[0081] In an optional embodiment of this feasible implementation mode, the preset distance is N bump pitches; N is a positive integer greater than or equal to 3; and the determination module is specifically configured to determine all modules in the chip located in the target area as the target modules.

[0082] In an optional embodiment of this feasible implementation mode, the device 400 may further include a preset distance determination module, which is used to: test the voltage drop values ​​generated by the same standard unit after expanding different numbers of bump pitches; determine the number of bump pitches when the voltage drop value converges; and determine the preset distance according to the number of bump pitches when the voltage drop value converges.

[0083] In an embodiment of the present application, the top-level design information includes: the modules contained in the top level, the relationship between the modules, and the design information of each module; the design information of each module includes: the standard units contained in the module and the relationship between the standard units.

[0084] In a feasible implementation of an embodiment of the present application, the analysis module is specifically used to: obtain the parasitic parameter information and time window information of each of the target modules; input the design information to be tested, the parasitic parameter information and time window information of each of the target modules into a preset analysis tool to obtain the voltage drop detection result of the module to be tested.

[0085] It should be understood that, for the sake of brevity, some of the contents described in the method embodiments will not be repeated in the device embodiments.

[0086] Based on the same inventive concept, the present application embodiment provides an electronic device, see Figure 5 As shown, it includes a processor 501 and a memory 502. Among them:

[0087] The processor 501 is used to execute one or more programs stored in the memory 502 to implement the above module-level voltage drop detection method.

[0088] Processor 501 can be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence) processor, an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processor) data processing core, etc., or it can be a processor chip used in some large-scale data computing scenarios. Memory 502 can be RAM (Random Access Memory), ROM (Read-Only Memory), or flash memory. The above is only an example and should not be a limitation to this application.

[0089] Figure 5 The structure shown is for illustration only. The electronic device may also include Figure 5 More or fewer components as shown, or with Figure 5For example, it may also have an internal communication bus for realizing communication between the processor 501 and the memory 502; for another example, it may also have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; for another example, it may also have an information display component such as a display screen, but this is not a limitation.

[0090] The electronic device may be a server, an intelligent terminal (such as a host, a smart phone, a laptop computer, a desktop computer, a vehicle terminal, an intelligent operating platform, etc.), or other device with data processing capabilities, but this is not a limitation.

[0091] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the above module-level voltage drop detection method. No further details will be given here.

[0092] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0093] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0095] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0096] As used herein, a plurality refers to two or more than two.

[0097] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A module-level voltage drop detection method, characterized in that: include: Get the top-level design information of the chip; Acquire design information of all target modules from the top-level design information to obtain design information to be tested; The target module includes a module to be detected and modules around the module to be detected; The design information to be tested is analyzed to obtain a voltage drop test result of the module to be tested.

2. The module-level voltage drop detection method according to claim 1, characterized in that: Before acquiring design information of all target modules from the top-level design information, the method further includes: Taking the module to be detected as the center, determining a target area whose edge is a preset distance from the module to be detected; the preset distance is a distance that allows a power supply network to be present in the target area; All target modules in the chip are determined according to the target area.

3. The module-level voltage drop detection method according to claim 2, characterized in that: The preset distance is equal to the distance bump pitch between the center points of two bumps of the same polarity.

4. The module-level voltage drop detection method according to claim 2, characterized in that: Determining all target modules in the chip according to the target area includes: All modules in the chip that have intersections with the target area are determined as the target modules.

5. The module-level voltage drop detection method according to claim 2, characterized in that: The preset distance is N bumppitch; N is a positive integer greater than or equal to 3; Determining all target modules in the chip according to the target area includes: All modules in the chip located in the target area are determined as the target modules.

6. The module-level voltage drop detection method according to any one of claims 2 to 5, characterized in that: The preset distance is obtained according to the following method: Test the voltage drop of the same standard cell after expanding with different numbers of bump pitches. Determining the number of bump pitches when the pressure drop value converges; The preset distance is determined according to the number of bump pitches when the pressure drop value converges.

7. The module-level voltage drop detection method according to any one of claims 1 to 5, characterized in that: The top-level design information includes: The modules included in the top layer, the relationship between the modules, and the design information of the modules; the design information of each module includes: the standard units included in the module and the relationship between the standard units.

8. The module-level voltage drop detection method according to any one of claims 1 to 5, characterized in that: Analyzing the design information to be tested to obtain a voltage drop test result of the module to be tested, including: Obtaining parasitic parameter information and time window information of each of the target modules; The design information to be tested, the parasitic parameter information of each target module and the time window information are input into a preset analysis tool to obtain the voltage drop test result of the module to be tested.

9. A module-level voltage drop detection device, characterized in that: include: The first acquisition module is used to acquire the top-level design information of the chip; A second acquisition module is used to acquire design information of all target modules from the top-level design information to obtain design information to be detected; the target module includes the module to be detected and modules around the module to be detected; The analysis module is used to analyze the design information to be detected to obtain the voltage drop detection result of the module to be detected.

10. An electronic device, characterized in that: include: Processor and memory; The processor is used to execute one or more programs stored in the memory to implement the module-level voltage drop detection method as described in any one of claims 1-8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the module-level voltage drop detection method according to any one of claims 1-8.

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