Semiconductor device and memory device including complementary delay circuit

Abstract

The invention relates to a semiconductor device and a memory device including a complementary delay circuit. A semiconductor device includes: a first delay circuit having a first delay amount reduced according to a common bias, and configured to generate a first delay control signal based on the first delay amount; a second delay circuit having a second delay amount that increases according to the common bias, and configured to generate a second delay control signal based on the second delay amount; a signal generation circuit configured to generate a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and an internal operation circuit configured to complementarily perform the first operation and the second operation within a target time in response to the internal control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0135048, filed on October 11, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor design technology, and particularly to a semiconductor device and a memory device including a complementary delay circuit. Background Art

[0004] Generally, a semiconductor device such as a memory device needs to perform predetermined operations sequentially or in parallel within a time set in a specification. For this reason, a delay circuit for controlling the timing of each operation is provided inside the semiconductor device. A large number of delay circuits configured as described above are designed and used inside the semiconductor device, thereby reducing the area efficiency of the semiconductor device. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a semiconductor device and a memory device capable of performing an internal operation to be performed within a target time in conjunction with each other using delay circuits that complement each other based on a common bias.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a first delay circuit, which has a first delay amount that decreases according to a common bias and is configured to generate a first delay control signal based on the first delay amount; a second delay circuit, which has a second delay amount that increases according to the common bias and is configured to generate a second delay control signal based on the second delay amount; a signal generating circuit, which is configured to generate a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and an internal operation circuit, which is configured to complementarily perform a first operation and a second operation within a target time in response to the internal control signal.

[0007] According to an embodiment of the present disclosure, a memory device includes: a memory cell array; a control logic configured to generate a first delay control signal based on a first delay amount that decreases according to a common bias, to generate a second delay control signal based on a second delay amount that increases according to the common bias, and to generate a plurality of internal control signals corresponding to commands according to the first delay control signal and the second delay control signal; a row control circuit coupled to the memory cell array through a plurality of word lines and configured to drive the word lines in response to the internal control signals; and a sense amplifier circuit coupled to the memory cell array through a plurality of bit lines and configured to sense and amplify data of the bit lines in response to the internal control signals.

[0008] According to the embodiments of the present disclosure, a semiconductor device and a memory device can maximize operation efficiency and minimize an area occupied by a delay circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 Is used to describe Figure 1 A waveform diagram of the operation of the sense amplifier circuit.

[0011] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Detailed block diagram of the control logic.

[0012] Figure 4A and Figure 4B is a diagram showing a first embodiment according to the present disclosure Figure 3 Detailed circuit diagram of the first delay circuit and the second delay circuit.

[0013] Figure 5 4 is a waveform diagram for describing the operation of the first delay circuit and the second delay circuit of FIG. 4 .

[0014] Fig. 6A and Figure 6B is a diagram showing a second embodiment according to the present disclosure Figure 3 Detailed circuit diagram of the first delay circuit and the second delay circuit.

[0015] Fig. 7A and Figure 7B FIG. 2 is a diagram showing a third embodiment according to the present disclosure. Figure 3 Detailed circuit diagram of the first delay circuit and the second delay circuit.

[0016] Fig. 8A and Figure 8B It is shown Figure 1 Detailed circuit diagram of the sense amplifier circuit.

[0017] Fig. 9 2 is a waveform diagram for describing the operation of a memory device according to an embodiment of the present disclosure.

[0018] Fig.10 Is used to describe Figure 1 A waveform diagram of the operation of the sense amplifier circuit.

[0019] Fig.11 Another embodiment of the present disclosure is shown in FIG. Figure 1 Detailed block diagram of the control logic.

[0020] Fig.12is a waveform diagram for describing the operation of a memory device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the embodiments may be embodied in different forms and are therefore not to be construed as being limited to the embodiments set forth herein. Throughout the present disclosure, the same reference numerals refer to the same components in the various drawings and embodiments of the present invention. It should be noted that references to "an embodiment", "another embodiment", etc. do not necessarily mean only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. The term "embodiment" used herein does not necessarily refer to all embodiments.

[0022] It should be understood that although the terms "first", "second", "third", etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. Therefore, the first element in one example may also be referred to as the second or third element in another example without indicating any change in the element itself.

[0023] It should also be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Additionally, it should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Communication between two elements, whether direct or indirect connection / coupling, may be wired or wireless, unless otherwise specified or indicated by context.

[0024] As used herein, singular forms may also include plural forms and vice versa, unless the context clearly indicates otherwise.

[0025] It should also be understood that the terms "comprising" and "including" when used in this specification specify the presence of the elements described and do not exclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] Figure 1 is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0027] refer to Figure 1, the memory device 100 may be a memory device based on a semiconductor device. For example, the memory device 100 may be a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power DDR SDRAM (LPDDR SDRAM), a graphic DDR SDRAM (GDDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, or a thyristor RAM (TRAM), or the like, or may be a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM), or the like.

[0028] The memory device 100 may input / output data DATA from / to a memory controller in response to a command CMD and an address ADDR received from an external device (e.g., a memory controller (not shown)). The memory device 100 may include a memory cell array 110, a command decoder 112, a control logic 114, an address buffer 120, a row control circuit 130, a sense amplifier circuit 140, a column control circuit 150, and a data input / output (I / O) circuit 160.

[0029] The memory cell array 110 may include a plurality of memory cells MC arranged in an array form in a plurality of word lines WL and a plurality of bit lines BL. According to an embodiment, the memory cell array 110 may include a plurality of memory banks (not shown). The number of memory banks or the number of memory cells MC may be determined according to the capacity of the memory device 100.

[0030] The command decoder 112 may generate various internal commands required for the operation of the memory device 100 by decoding the command CMD. For example, the command decoder 112 may generate an active command ACT, a precharge command PCG, a read command RD, and a write command WT by decoding the command CMD transmitted from the memory controller.

[0031] The control logic 114 may generate internal control signals for controlling the overall operation of the memory device 100 based on the active command ACT, the precharge command PCG, the read command RD, and the write command WT provided from the command decoder 112. For example, the control logic 114 may generate a row control signal R_CTRL for controlling the operation of the row control circuit 130, a sense control signal S_CTRL for controlling the operation of the sense amplifier circuit 140, a column control signal C_CTRL for controlling the operation of the column control circuit 150, and an input / output control signal IO_CTRL for controlling the operation of the data input / output circuit 160.

[0032] The address buffer 120 may buffer the address ADDR received from the memory controller. The address ADDR may include a row address RADD for specifying a word line of the memory cell array 110 and a column address CADD for specifying a bit line of the memory cell array 110. The address buffer 120 may send the row address RADD to the row control circuit 130 and the column address CADD to the column control circuit 150.

[0033] The row control circuit 130 may be coupled to the memory cell array 110 through a plurality of word lines WL. The row control circuit 130 may drive a word line corresponding to the row address RADD among the plurality of word lines WL in response to a row control signal R_CTRL. For example, the row control circuit 130 may activate a word line selected by the row address RADD in response to a row control signal R_CTRL corresponding to an activation command ACT, and precharge the activated word line in response to a row control signal R_CTRL corresponding to a precharge command PCG.

[0034] The sense amplifier circuit 140 may be coupled to the memory cell array 110 through a plurality of bit lines BL. The sense amplifier circuit 140 may be distributed and disposed inside the memory cell array 110. The sense amplifier circuit 140 may include a plurality of bit line sense amplifiers 142 corresponding to the plurality of bit lines BL, respectively. The bit line sense amplifiers 142 may be coupled to the pull-up voltage line (see Figure 8B RTO in the Figure 8B SB in the bit line), and senses and amplifies the data of the bit line BL in response to the sense control signal S_CTRL. For example, the bit line sense amplifiers 142 are each connected to the bit line pair to sense and amplify the voltage difference between the bit line pair.

[0035] The column control circuit 150 may select a predetermined bit line BL corresponding to the column address CADD among the plurality of bit lines BL in response to the column control signal C_CTRL. The column control circuit 150 may read data from the memory cell array 110 through the bit line sense amplifier 142 coupled to the selected bit line BL in response to the column control signal C_CTRL corresponding to the read command RD. In addition, the column control circuit 150 may write data DATA provided from the memory controller into the memory cell array 110 through the bit line sense amplifier 142 coupled to the selected bit line BL in response to the column control signal C_CTRL corresponding to the write command WT.

[0036] The data input / output circuit 160 may be coupled to the column control circuit 150 to output data DATA provided from the column control circuit 150 to the memory controller or transmit data DATA provided from the memory controller to the column control circuit 150 .

[0037] In the above configuration, the sense amplification circuit 140 may sequentially perform a precharge operation, an offset cancellation operation, a charge sharing operation, and an amplification operation in response to the sense control signal S_CTRL.

[0038] Figure 2 Is used to describe Figure 1 The waveform diagram of the operation of the sense amplifier circuit 140 is shown in FIG. Figure 2 , a read operation of the bit line sense amplifier 142 is shown.

[0039] Reference Figure 2 During the interval from T0 to T1 before the active command ACT is input, the bit line sense amplifier 142 may perform a precharge operation of driving the bit line pair BLT and BLB to the precharge voltage VBLP. The precharge voltage VBLP may be set to an intermediate level between the core voltage VCORE and the ground voltage VSS.

[0040] When the activation command ACT is input at T1, the bit line sense amplifier 142 may perform an offset cancellation operation during an interval from T1 to T2 (hereinafter referred to as an "offset cancellation period tMC"). During the offset cancellation period tMC, the voltage level of the first bit line BLT may be higher than the voltage level of the second bit line BLB by an offset voltage.

[0041] During the interval from T2 to T3 (hereinafter, referred to as "charge sharing period tCS"), the bit line sense amplifier 142 may perform a charge sharing operation. Since the word line WL is activated, charge sharing may occur between the first bit line BLT and the memory cell MC. For example, when high data is stored in the memory cell MC (i.e., when the voltage level of the cell capacitor of the memory cell MC is greater than or equal to the reference value), the voltage level of the first bit line BLT may be increased by a voltage change amount ΔV during the charge sharing period tCS. Although Figure 2 Although not shown in the figure, when low data is stored in the memory cell MC, the voltage level of the first bit line BLT may be lowered by the voltage variation amount ΔV.

[0042] Thereafter, during the interval from T3 to T4 before the read command RD is input, the bit line sense amplifier 142 may perform a pre-sensing operation to ensure a sensing margin for a main sensing operation subsequently performed. According to an embodiment, the pre-sensing operation may be included in the charge sharing period tCS. When the read command RD is input at T4, during the interval from T4 to T5, the bit line sense amplifier 142 may sense and amplify the voltage difference between the first bit line BLT and the second bit line BLB by performing a main sensing operation. The main sensing operation may be defined as an amplification operation.

[0043] When the precharge command PCG is input at T5 , the bit line sense amplifier 142 may perform a precharge operation of driving the first and second bit lines BLT and BLB to the precharge voltage VBLP.

[0044] When the active command ACT is input at T6 , the above-mentioned operations, ie, the precharge operation, the offset cancellation operation, the charge sharing operation, and the amplification operation may be performed again.

[0045] In order to stably perform the operation of the memory device, various timing parameters are defined in the specification. For example, the time from inputting the activation command ACT to inputting the precharge command PCG, that is, Figure 2 The interval from T1 to T5 is defined as the row access time tRAS; and the time from inputting the precharge command PCG to inputting the activation command ACT, that is, Figure 2 The interval from T5 to T6 is defined as the row precharge time tRP. In addition, the time from inputting the row activation command (ie, the activation command ACT) to inputting the column activation command (eg, the read command RD), ie Figure 2 The interval from T1 to T4 is defined as the RAS to CAS delay time tRCD. Figure 2 As shown, the offset cancellation operation and the charge sharing operation can be sequentially performed within the RAS to CAS delay time tRCD.

[0046] Hereinafter, in an embodiment of the present disclosure, a method of controlling an offset cancellation operation and a charge sharing operation sequentially performed within a RAS to CAS delay time tRCD using a complementary delay circuit will be described.

[0047] Figure 3 is a detailed block diagram illustrating control logic 114A according to an embodiment of the present disclosure. Figure 3 The control logic 114A may correspond to Figure 1 Control logic 114 is shown.

[0048] Reference Figure 3 , the control logic 114A may include a timing control circuit 210 , a first delay circuit 220 , a second delay circuit 230 , and a signal generating circuit 240 .

[0049] The timing control circuit 210 may generate a source signal S_SRC and a plurality of timing control signals P_CTRL# based on internal commands (e.g., an activation command ACT, a precharge command PCG, a read command RD, and a write command WT). The source signal S_SRC may be a signal having a high level for a predetermined period. For example, the source signal S_SRC may have different levels during the offset cancellation period tMC and the charge sharing period tCS to distinguish the offset cancellation period tMC from the charge sharing period tCS. The plurality of timing control signals P_CTRL# may be transitions at committed timings to perform internal operations (such as Figure 2 The precharge operation, offset cancellation operation, charge sharing operation, and amplification operation described in the previous section are described in detail. Figure 3 In the embodiment of the present disclosure, the plurality of timing control signals P_CTRL# may include a preliminary word line drive signal, a preliminary bit line precharge signal, a preliminary pull-up drive signal, a preliminary pull-down drive signal, a preliminary offset cancellation signal, and a preliminary isolation signal to be described later.

[0050] The first delay circuit 220 may have a first delay amount tD1 that decreases according to the common bias C_BIAS. The first delay amount tD1 may decrease as the amplitude of the common bias C_BIAS increases. The first delay circuit 220 may generate a first delay control signal D_DEC based on the first delay amount tD1. For example, the first delay circuit 220 may generate the first delay control signal D_DEC by adjusting the pulse width of the source signal S_SRC according to the first delay amount tD1. As a result, compared with the source signal S_SRC, the first delay control signal D_DEC may have a pulse width that decreases as the amplitude of the common bias C_BIAS increases.

[0051] The second delay circuit 230 may have a second delay amount tD2 that increases according to the common bias C_BIAS. The second delay amount tD2 may increase as the amplitude of the common bias C_BIAS increases. The second delay circuit 230 may generate a second delay control signal D_INC based on the second delay amount tD2. For example, the second delay circuit 230 may generate the second delay control signal D_INC by adjusting the pulse width of the source signal S_SRC according to the second delay amount tD2. As a result, compared with the source signal S_SRC, the second delay control signal D_INC may have a pulse width that increases as the amplitude of the common bias C_BIAS increases.

[0052] The signal generating circuit 240 may generate a plurality of internal control signals according to at least one of the first delay control signal D_DEC and the second delay control signal D_INC. The signal generating circuit 240 may generate a plurality of internal control signals corresponding to a plurality of timing control signals P_CTRL# according to the first delay control signal D_DEC and the second delay control signal D_INC. The signal generating circuit 240 may generate a plurality of internal control signals by adjusting the transition timing of the plurality of timing control signals P_CTRL# according to the first delay control signal D_DEC and the second delay control signal D_INC. In an embodiment of the present disclosure, the internal control signal may include a row control signal R_CTRL and a sensing control signal S_CTRL. The row control signal R_CTRL includes a word line drive signal SWL for driving a word line selected from a plurality of word lines, and the sensing control signal S_CTRL includes a bit line precharge signal BLEQ, a pull-up drive signal SAP, a pull-down drive signal SAN, an offset cancellation signal OC, and an isolation signal ISO.

[0053] Specifically, the signal generating circuit 240 may include first to third transition control circuits 241 to 243 .

[0054] The first transition control circuit 241 may receive a preliminary word line drive signal and a preliminary offset cancellation signal among the timing control signal P_CTRL#, and generate a word line drive signal SWL and an offset cancellation signal OC by adjusting one of a falling edge and a rising edge of the received signal according to the first delay control signal D_DEC.

[0055] The second transition control circuit 242 can receive a preliminary bit line precharge signal, a preliminary pull-up drive signal and a preliminary pull-down drive signal among the timing control signal P_CTRL#, and generate a bit line precharge signal BLEQ, a pull-up drive signal SAP and a pull-down drive signal SAN by adjusting one of the falling edge and the rising edge of the received signal according to the first delay control signal D_DEC and adjusting the other of the falling edge and the rising edge of the received signal according to the second delay control signal D_INC.

[0056] The third transition control circuit 243 may receive the preliminary isolation signal among the timing control signal P_CTRL#, and generate the isolation signal ISO by adjusting one of the falling edge and the rising edge of the received signal according to the second delay control signal D_INC.

[0057] The word line drive signal SWL may be provided to the row control circuit 130 as the row control signal R_CTRL, and the bit line precharge signal BLEQ, the pull-up drive signal SAP, the pull-down drive signal SAN, the offset cancellation signal OC, and the isolation signal ISO may be provided to the sense amplifier circuit 140 as the sense control signal S_CTRL.

[0058] Figure 4A and Figure 4B is a detailed circuit diagram showing the first delay circuit 220A and the second delay circuit 230A according to the first embodiment of the present disclosure. Figure 4A and Figure 4B The first delay circuit 220A and the second delay circuit 230A may correspond to Figure 3 The first delay circuit 220 and the second delay circuit 230 are shown in FIG.

[0059] Reference Figure 4A , the first delay circuit 220A may include a plurality of NMOS transistors N11 to N14 coupled in series between an input terminal receiving a source signal S_SRC and an output terminal outputting a first delay control signal D_DEC. Each of the plurality of NMOS transistors N11 to N14 may receive a common bias C_BIAS through their gates. The NMOS transistor N11 of the first stage may receive a source signal S_SRC through its drain, and the NMOS transistor N14 of the last stage may output a first delay control signal D_DEC through its source. For reference, an NMOS transistor has a characteristic that a channel resistance decreases as a gate voltage increases and a channel resistance increases as a gate voltage decreases. As a result, the first delay circuit 220A may have a first delay amount tD1 in which the delay amount is reduced because the channel resistance decreases as the amplitude of the common bias C_BIAS increases.

[0060] Reference Figure 4B , the second delay circuit 230A may include a plurality of PMOS transistors P11 to P14 coupled in series between an input terminal receiving a source signal S_SRC and an output terminal outputting a second delay control signal D_INC. Each of the plurality of PMOS transistors P11 to P14 may receive a common bias C_BIAS through their gates, respectively. The PMOS transistor P11 of the first stage may receive the source signal S_SRC through its source, and the PMOS transistor P14 of the last stage may output the second delay control signal D_INC through its drain. For reference, the PMOS transistor has a characteristic that the channel resistance increases as the gate voltage increases and the channel resistance decreases as the gate voltage decreases. As a result, the second delay circuit 230A may have a second delay amount tD2 in which the delay amount increases because the channel resistance increases as the amplitude of the common bias C_BIAS increases.

[0061] With the above configuration, the first delay circuit 220A and the second delay circuit 230A can have delay amounts that are complementarily decreased and increased according to the common bias C_BIAS. Figure 4A and Figure 4B Four NMOS transistors N11 to N14 and four PMOS transistors P11 to P14 are shown, but the present invention is not limited thereto, and a predetermined number of transistors may be connected in series, respectively. In this case, the number of NMOS transistors N11 to N14 and the number of PMOS transistors P11 to P14 may be the same or different from each other.

[0062] Figure 5 4 is a waveform diagram for describing the operation of the first delay circuit 220A and the second delay circuit 230A of FIG. 4 .

[0063] Reference Figure 5 , the first delay circuit 220A may have a first delay amount tD1 that decreases as the amplitude of the common bias C_BIAS is increased by a voltage change amount ΔV, and the second delay circuit 230A may have a second delay amount tD2 that increases as the amplitude of the common bias C_BIAS is increased by a voltage change amount ΔV. Therefore, as the amplitude of the common bias C_BIAS increases, the first delay control signal D_DEC may have a pulse width that decreases compared to the pulse width PW of the source signal S_SRC, and the second delay control signal D_INC may have a pulse width that increases compared to the pulse width PW of the source signal S_SRC. That is, the first delay control signal D_DEC and the second delay control signal D_INC may have pulse widths that complementarily decrease and increase according to the common bias C_BIAS.

[0064] In the case where the first delay circuit 220A and the second delay circuit 230A are formed of the same number of transistors, if the amplitude of the common bias C_BIAS is increased by the first bias level, the first delay control signal D_DEC may have a pulse width reduced by the first width, and the second delay control signal D_INC may have a pulse width increased by the first width. In addition, when the amplitude of the common bias C_BIAS is increased by the second bias level, the first delay control signal D_DEC may have a pulse width reduced by the second width, and the second delay control signal D_INC may have a pulse width increased by the second width.

[0065] Fig. 6A and Figure 6B is a diagram showing a second embodiment of the present disclosure. Figure 3 Detailed circuit diagram of the first delay circuit 220B and the second delay circuit 230B. Fig. 6A and Figure 6BThe first delay circuit 220B and the second delay circuit 230B may correspond to Figure 3 The first delay circuit 220 and the second delay circuit 230 are shown in FIG.

[0066] Reference Fig. 6A , the first delay circuit 220B may include a plurality of NMOS transistors N21 to N24 coupled in series. The plurality of NMOS transistors N21 to N24 may receive a common bias C_BIAS through their gates. The first-stage NMOS transistor N21 may receive a source signal S_SRC through its drain, and the last-stage NMOS transistor N24 may output a first delay control signal D_DEC through its source. Fig. 6A The first delay circuit 220B has Figure 4A The first delay circuit 220B may have a configuration substantially the same as the first delay circuit 220A. The first delay circuit 220B may have a first delay amount tD1 in which the delay amount decreases because the channel resistance decreases as the magnitude of the common bias C_BIAS increases.

[0067] Reference Figure 6B , the second delay circuit 230B may include a bias control circuit 231B and a plurality of transistor groups G1 to G4. As the amplitude of the common bias C_BIAS increases, the bias control circuit 231B may reduce the number of high bits of the selection signal TM<1:4> and increase the number of low bits of the selection signal TM<1:4>. The plurality of transistor groups G1 to G4 may be coupled in parallel between an input terminal receiving a source signal S_SRC and an output terminal outputting a second delay control signal D_INC. The plurality of transistor groups G1 to G4 may include bias transistors N31 to N34 and selection transistors N41 to N44 coupled in series between the input terminal and the output terminal, respectively. The bias transistors N31 to N34 and the selection transistors N41 to N44 may be configured as NMOS transistors. The bias transistors N31 to N34 may receive the common bias C_BIAS through their gates, and the selection transistors N41 to N44 may receive the selection signal TM<1:4> through their gates, respectively. Each of the selection transistors N41 to N44 can be turned on according to the corresponding bit of the selection signal TM<1:4>. That is, the second delay circuit 230B can select some of the plurality of transistor groups G1 to G4 according to the selection signal TM<1:4>, and can determine the second delay amount tD2 according to the number of bias transistors N31 to N34 coupled in parallel to each other in the selected transistor group.

[0068] With the above configuration, as the amplitude of the common bias C_BIAS increases, the second delay circuit 230B can reduce the number of high bits of the selection signal TM<1:4>, and thus, the equivalent resistance of the plurality of transistor groups G1 to G4 increases. As a result, the second delay circuit 230B can have a second delay amount tD2 that increases as the amplitude of the common bias C_BIAS increases.

[0069] Fig. 7A and 7B is a diagram showing a third embodiment of the present disclosure. Figure 3 Detailed circuit diagram of the first delay circuit 220C and the second delay circuit 230C. Fig. 7A and Figure 7B The first delay circuit 220C and the second delay circuit 230C may correspond to Figure 3 The first delay circuit 220 and the second delay circuit 230 are shown in FIG.

[0070] Reference Fig. 7A , the first delay circuit 220C may include a first bias control circuit 221C and a plurality of first transistor groups G11 to G14. As the amplitude of the common bias C_BIAS increases, the first bias control circuit 221C may reduce the number of high bits of the first selection signal TM<11:14> and increase the number of low bits of the first selection signal TM<11:14>. The plurality of first transistor groups G11 to G14 may be coupled in parallel between an input terminal receiving a source signal S_SRC and an output terminal outputting a first delay control signal D_DEC. The plurality of first transistor groups G11 to G14 may respectively include first bias transistors N51 to N54 and first selection transistors N61 to N64 coupled in series between an input terminal and an output terminal. The first bias transistors N51 to N54 and the first selection transistors N61 to N64 may be configured as NMOS transistors. The first bias transistors N51 to N54 may receive a common bias C_BIAS through their gates, and the selection transistors N41 to N44 may receive first selection signals TM<11:14> through their gates, respectively. The first delay circuit 220C may select some of the plurality of first transistor groups G11 to G14 according to the first selection signal TM<11:14>, and may determine a first delay amount tD1 according to the number of first bias transistors N51 to N54 coupled in parallel to each other in the selected transistor group.

[0071] Reference Figure 7B, the second delay circuit 230C may include a second bias control circuit 231C and a plurality of second transistor groups G21 to G24. As the amplitude of the common bias C_BIAS increases, the second bias control circuit 231C may reduce the number of high bits of the second selection signal TM<21:24> and increase the number of low bits of the second selection signal TM<21:24>. The plurality of second transistor groups G21 to G24 may include second bias transistors N71 to N74 and second selection transistors N81 to N84 coupled in series between the input terminal and the output terminal, respectively. The second transistor groups G21 to G24 may have substantially the same configuration as the first transistor groups G11 to G14 of the first delay circuit 220C. Therefore, the second delay circuit 230C may select some of the second transistor groups G21 to G24 according to the second selection signal TM<21:24>, and may determine the second delay amount tD2 according to the number of second bias transistors N71 to N74 coupled in parallel to each other in the selected transistor group.

[0072] Specifically, in an embodiment of the present disclosure, as the common bias C_BIAS increases, the second bias control circuit 231C may control the number of high bits of the second selection signal TM<21:24> to be less than the number of high bits of the first selection signal TM<11:14>. Therefore, as the amplitude of the common bias C_BIAS increases, the equivalent resistance of the second delay circuit 230C increases more than the equivalent resistance of the first delay circuit 220C. As a result, the first delay circuit 220C may have a first delay amount tD1 that is relatively reduced as the amplitude of the common bias C_BIAS increases, and the second delay circuit 230C may have a second delay amount tD2 that is relatively increased as the amplitude of the common bias C_BIAS increases.

[0073] Fig. 8A and 8B It is shown Figure 1 Detailed circuit diagram of the sense amplifier circuit 140.

[0074] Reference Fig. 8A , a sensing amplifier circuit 140 for sensing a voltage change between a first bit line BLT and a second bit line BLB respectively coupled to a first memory cell MC1 and a second memory cell MC2 included in a memory cell array 110 is shown.

[0075] The first memory cell MC1 may be coupled between the first word line WL1 and the first bit line BLT, and include a cell transistor CT1 and a cell capacitor CP1. The cell capacitor CP1 may be coupled between the cell plate voltage (VCP) terminal and the cell transistor CT1. The cell transistor CT1 may be coupled between the cell capacitor CP1 and the first bit line BLT, and have a gate receiving a signal at the first word line WL1. Similarly, the second memory cell MC2 may be coupled between the second word line WL2 and the second bit line BLB, and include a cell transistor CT2 and a cell capacitor CP2. The cell capacitor CP2 may be coupled between the cell plate voltage (VCP) terminal and the cell transistor CT2. The cell transistor CT2 may be coupled between the cell capacitor CP2 and the second bit line BLB, and have a gate receiving a signal at the second word line WL2. For reference, when the first word line WL1 is activated, the first bit line BLT coupled to the cell transistor CT1 to be turned on becomes a target bit line from which output data is output, and the second bit line BLB becomes a reference bit line. Furthermore, when the second word line WL2 is activated, the second bit line BLB coupled to the cell transistor CT2 to be turned on becomes a target bit line from which output data is output, and the first bit line BLT becomes a reference bit line.

[0076] The sense amplification circuit 140 may include a first precharge circuit 310 , a second precharge circuit 320 , a driving circuit 330 , and a bit line sense amplifier 142 .

[0077] The first precharge circuit 310 may supply a precharge voltage VBLP to the pull-up voltage line RTO and the pull-down voltage line SB in response to the bit line precharge signal BLEQ. The second precharge circuit 320 may supply a precharge voltage VBLP to the first bit line BLT and the second bit line BLB in response to the bit line precharge signal BLEQ. The precharge voltage VBLP may have an intermediate voltage level between the ground voltage VSS and the core voltage VCORE. The core voltage VCORE may have a voltage level lower than the power supply voltage VDD. The first precharge circuit 310 may include first to third NMOS transistors MN1 to MN3, and the second precharge circuit 320 may include fourth to sixth NMOS transistors MN4 to MN6.

[0078] The driving circuit 330 can drive the pull-up voltage line RTO and the pull-down voltage line SB by supplying an operating voltage to the pull-up voltage line RTO and the pull-down voltage line SB. The driving circuit 330 may include a pull-up driver MN7 and a pull-down driver MN8. The pull-up driver MN7 may provide a core voltage VCORE to the pull-up voltage line RTO in response to a pull-up drive signal SAP. The pull-down driver MN8 may provide a ground voltage VSS to the pull-down voltage line SB in response to a pull-down drive signal SAN. Each of the pull-up driver MN7 and the pull-down driver MN8 may be implemented with an NMOS transistor.

[0079] The bit line sense amplifier 142 may be coupled between the pull-up voltage line RTO and the pull-down voltage line SB, and sense and amplify a voltage difference between the first bit line BLT and the second bit line BLB.

[0080] Reference Figure 8B The bit line sense amplifier 142 may include a first inverter 410 , a second inverter 420 , a first offset cancellation switch 441 , a second offset cancellation switch 442 , a first isolation switch 451 , and a second isolation switch 452 .

[0081] The first inverter 410 may have an input terminal coupled to the first bit line BLT through the first sense node GT and an output terminal coupled to the second internal bit line IB. The first inverter 410 may include a PMOS transistor 411 and an NMOS transistor 412 coupled in series between the pull-up voltage line RTO and the pull-down voltage line SB. The second inverter 420 may have an input terminal coupled to the second bit line BLB through the second sense node GB and an output terminal coupled to the first internal bit line IT. The second inverter 420 may include a PMOS transistor 421 and an NMOS transistor 422 coupled in series between the pull-up voltage line RTO and the pull-down voltage line SB.

[0082] The first offset cancel switch 441 can electrically couple the first internal bit line IT to the second bit line BLB through the second sense node GB in response to the offset cancel signal OC. The second offset cancel switch 442 can electrically couple the second internal bit line IB to the first bit line BLT through the first sense node GT in response to the offset cancel signal OC. Each of the first offset cancel switch 441 and the second offset cancel switch 442 can be implemented with an NMOS transistor.

[0083] The first isolation switch 451 can electrically couple the first internal bit line IT to the first bit line BLT in response to the isolation signal ISO. The second isolation switch 452 can electrically couple the second internal bit line IB to the second bit line BLB in response to the isolation signal ISO. Each of the first isolation switch 451 and the second isolation switch 452 can be implemented with an NMOS transistor.

[0084] Next, we will refer to Figures 1 to 9 The operation of the memory device 100 according to the embodiment is described.

[0085] Fig. 9 2 is a waveform diagram for describing the operation of a memory device according to an embodiment of the present disclosure.

[0086] Reference Fig. 9 , the sense amplifier circuit 140 of the memory device 100 may sequentially perform a precharge operation P0 , an offset cancellation operation P1 , a charge sharing operation P2 , and an amplification operation P3 .

[0087] During the precharge operation P0, the bit line precharge signal BLEQ and the offset cancellation signal OC are activated to a logic high level, but the isolation signal ISO is deactivated to a logic low level. In response to the bit line precharge signal BLEQ, the pull-up circuit 310 and the pull-down circuit 320 can apply the precharge voltage VBLP to the pull-up voltage line RTO and the pull-down voltage line SB, as well as to the first bit line BLT and the second bit line BLB. In response to the offset cancellation signal OC, the first offset cancellation switch 441 and the second offset cancellation switch 442 are turned on. As a result, during the precharge operation P0, the precharge voltage VBLP can be applied to all of the first internal bit line IT, the second internal bit line IB, the first bit line BLT, the second bit line BLB, the first sense node GT, and the second sense node GB, so that the first inverter 410 and the second inverter 420 can be disabled.

[0088] During the offset cancellation operation P1, in a state where the offset cancellation signal OC is activated, the bit line precharge signal BLEQ becomes deactivated to a logic low level. At this time, the pull-up drive signal SAP and the pull-down drive signal SAN are activated, so that the core voltage VCORE can be supplied to the pull-up voltage line RTO and the ground voltage VSS can be supplied to the pull-down voltage line SB, thereby activating the first inverter 410 and the second inverter 420. Since the first offset cancellation switch 441 and the second offset cancellation switch 442 are turned on, the input terminal of the first inverter 410 is coupled to its output terminal, and the input terminal of the second inverter 420 is coupled to its output terminal. In this case, the mismatch caused by the process variation between the PMOS transistors 411 and 421 and the NMOS transistors 412 and 422 in the first inverter 410 and the second inverter 420 may be reflected in the first bit line BLT and the second bit line BLB.

[0089] During the charge sharing operation P2, the pull-up drive signal SAP, the pull-down drive signal SAN, and the offset cancellation signal OC are deactivated to a logic low level, and the selected word line WL is activated. The bit line precharge signal BLEQ is activated so that the precharge voltage VBLP can be applied to the pull-up voltage line RTO and the pull-down voltage line SB. When the first bit line BLT and the second bit line BLB are isolated from each other, a charge sharing operation can be performed, in which the cell transistor of the memory cell MC connected to the selected word line WL is turned on and the charge stored in the cell capacitor flows into the first bit line BLT. Due to the charge sharing operation, the voltage level of the first bit line BLT may be slightly higher or lower than the voltage level of the second bit line BLB.

[0090] Before the amplification operation P3 , the bit line precharge signal BLEQ becomes deactivated while the isolation signal ISO is activated.

[0091] During the amplification operation P3, the pull-up drive signal SAP and the pull-down drive signal SAN are activated, so the pull-up voltage at the level of the core voltage VCORE and the pull-down voltage at the level of the ground voltage VSS are respectively supplied to the pull-up voltage line RTO and the pull-down voltage line SB, so the first inverter 410 and the second inverter 420 are activated. The first isolation switch 451 and the second isolation switch 452 are turned on, so that the first bit line BLT and the first internal bit line IT can be coupled, and the second bit line BLB and the second internal bit line IB can be coupled. Therefore, the voltage difference between the first bit line BLT and the second bit line BLB can be amplified. Since the amplification operation starts in a state reflecting the offset, the bit line sense amplifier 142 can perform the amplification operation relatively accurately. That is, the offset voltage can be reduced, thereby ensuring the accurate operation of the bit line sense amplifier 142.

[0092] In an embodiment of the present disclosure, the common bias C_BIAS may be increased by a predetermined level during the offset cancellation operation P1 and the charge sharing operation P2. Figure 5 As described in the specification, the first delay circuit 220 can generate a first delay control signal D_DEC according to a first delay amount tD1 (the first delay amount tD1 decreases according to a common bias _BIAS), and the second delay circuit 230 can generate a second delay control signal D_INC according to a second delay amount tD2 (the second delay amount tD2 increases according to a common bias C_BIAS).

[0093] The first transition control circuit 241 can generate a word line drive signal SWL whose rising edge is advanced and an offset cancellation signal OC whose falling edge is advanced according to the first delay control signal D_DEC. The second transition control circuit 242 can generate a bit line precharge signal BLEQ whose rising edge is advanced according to the first delay control signal D_DEC and whose falling edge is delayed according to the second delay control signal D_INC. In addition, the second transition control circuit 242 can generate a pull-up drive signal SAP and a pull-down drive signal SAN each having a falling edge advanced according to the first delay control signal D_DEC and a rising edge delayed according to the second delay control signal D_INC. The third transition control circuit 243 can generate an isolation signal ISO whose rising edge is delayed according to the second delay control signal D_INC.

[0094] In the prior art, since the delay circuits for controlling the offset cancellation operation P1 and the charge sharing operation P2 operate independently, the offset cancellation operation P1 is completed earlier than the predetermined offset cancellation period tMC, and the charge sharing operation P2 is performed only within the predetermined charge sharing period tCS, making it difficult to improve the overall performance. However, in an embodiment of the present disclosure, a delay circuit that operates complementary based on a common bias can be used to generate the row control signal R_CTRL and the sensing control signal S_CTRL. Therefore, if the offset cancellation operation P1 is completed earlier than the predetermined offset cancellation period tMC, the charge sharing operation P2 can be performed within a longer period that is complementary to the predetermined charge sharing period tCS. Therefore, in an embodiment of the present disclosure, the offset cancellation operation P1 and the charge sharing operation P2 to be performed within the RAS to CAS delay time tRCD can be performed in combination with each other, thereby maximizing the operating efficiency and minimizing the area occupied by the delay circuit.

[0095] In the above embodiment, the offset cancellation operation P1 and the charge sharing operation P2 are performed in conjunction with each other within the RAS to CAS delay time tRCD, but the embodiment is not limited thereto. This embodiment may be applicable to the configuration of internal operations to be performed in conjunction with each other within a target time.

[0096] Fig.10 Is used to describe Figure 1 The waveform diagram of the operation of the sense amplifier circuit 140 is shown in FIG. Figure 2 , a write operation of the bit line sense amplifier 142 is shown.

[0097] Reference Fig.10During the interval from T0 to T1 before the activation command ACT is input, the bit line sense amplifier 142 may perform a precharge operation of driving the bit line pair BLT and BLB to the precharge voltage VBLP. When the activation command ACT is input at T1, the offset cancellation operation during the interval from T1 to T2 and the charge sharing operation during the interval from T2 to T3 may be sequentially performed.

[0098] During the interval from T3 to T4 before the write command WT is input, the bit line sense amplifier 142 may perform a pre-sensing operation to ensure a sensing margin for a main sensing operation performed subsequently. When the write command WT is input at T4, during the interval from T4 to T5, the bit line sense amplifier 142 may sense and amplify a voltage difference between the first bit line BLT and the second bit line BLB by performing a main sensing operation. Fig.10 , a case where low data is written when high data is already stored in a memory cell is shown. The main sensing operation may be defined as a write operation.

[0099] When the precharge command PCG is input at T5 , the bit line sense amplifier 142 may perform a precharge operation of driving the bit line pair BLT and BLB to the precharge voltage VBLP.

[0100] When the active command ACT is input at T6 , the above-described operations including the precharge operation, the offset cancel operation, the charge sharing operation, and the write operation may be performed again.

[0101] At this time, the interval from applying the write command WT to applying the precharge command PCG (ie, Fig.10 The interval from T4 to T5 of the present invention) can be defined as the write recovery time tWR, and the interval from applying the precharge command PCG to applying the activate command ACT (ie, Fig.10 The interval from T5 to T6 of the write recovery time tWR may be defined as the row precharge time tRP. In the following, in an embodiment of the present disclosure, a method of using a complementary delay circuit to complementarily control the write recovery time tWR and the row precharge time tRP will be described.

[0102] Fig.11 Another embodiment of the present disclosure is shown in FIG. Figure 1 Detailed block diagram of control logic 114B. Fig.11 The control logic 114B may correspond to Figure 1 Control logic 114 is shown.

[0103] Reference Fig.11 , the control logic 114B may include a timing control circuit 510 , a first delay circuit 520 , a second delay circuit 530 , and a signal generating circuit 540 .

[0104] Fig.11The timing control circuit 510, the first delay circuit 520 and the second delay circuit 530 can be connected with Figure 3 The configurations of the first delay circuit 520 and the second delay circuit 530 are substantially the same. The first delay circuit 520 may have a first delay amount tD1 that decreases according to the common bias C_BIAS, and may generate a first delay control signal D_DEC by adjusting a pulse width of the source signal S_SRC according to the first delay amount tD1. The second delay circuit 530 may have a second delay amount tD2 that increases according to the common bias C_BIAS, and may generate a second delay control signal D_INC by adjusting a pulse width of the source signal S_SRC according to the second delay amount tD2. The detailed configurations and operations of the first delay circuit 520 and the second delay circuit 530 may correspond to Figures 4A to 7B Configuration and operation described in .

[0105] The signal generating circuit 540 may generate a plurality of internal control signals according to the first delay control signal D_DEC and the second delay control signal D_INC. The signal generating circuit 540 may generate a plurality of internal control signals corresponding to a plurality of timing control signals P_CTRL#. The signal generating circuit 540 may generate a plurality of internal control signals by adjusting one of the falling edge and the rising edge of the plurality of timing control signals P_CTRL# according to the first delay control signal D_DEC, and adjusting the other of the falling edge and the rising edge of the plurality of timing control signals P_CTRL# according to the second delay control signal D_INC. In an embodiment of the present disclosure, the internal control signal may include a row control signal R_CTRL and a sensing control signal S_CTRL. The row control signal R_CTRL includes a word line drive signal SWL for driving a word line selected from a plurality of word lines, and the sensing control signal S_CTRL includes a bit line precharge signal BLEQ, a pull-up drive signal SAP, a pull-down drive signal SAN, an offset cancellation signal OC, and an isolation signal ISO.

[0106] Next, we will refer to Figures 10 to 12 The operation of the memory device 100 according to another embodiment is described.

[0107] Fig.12 is a waveform diagram for describing the operation of a memory device according to another embodiment of the present disclosure.

[0108] Reference Fig.12 , the sense amplifier circuit 140 of the memory device 100 may sequentially perform a precharge operation P0 , an offset cancellation operation P1 , a charge sharing operation P2 , and an amplification operation P3 . Fig.12 The precharge operation P0, offset cancellation operation P1, charge sharing operation P2 and amplification operation P3 can be Fig. 9 The operation is basically the same.

[0109] In an embodiment of the present disclosure, the common bias C_BIAS may be increased by a predetermined level during the precharge operation P0. Therefore, the first delay circuit 520 may generate a first delay control signal D_DEC according to a first delay amount tD1 (which decreases according to the common bias C_BIAS), and the second delay circuit 530 may generate a second delay control signal D_INC according to a second delay amount tD2 (which increases according to the common bias C_BIAS).

[0110] The signal generating circuit 540 may generate a word line driving signal SWL, an isolation signal ISO, a pull-up driving signal SAP, and a pull-down driving signal SAN whose rising edge is advanced according to the first delay control signal D_DEC and whose falling edge is delayed according to the second delay control signal D_INC. In addition, the signal generating circuit 540 may generate a bit line precharge signal BLEQ and an offset cancellation signal OC whose rising edge is delayed according to the second delay control signal D_INC and whose falling edge is advanced according to the first delay control signal D_DEC.

[0111] As described above, in another embodiment of the present disclosure, a delay circuit based on a common bias complementary operation can be used to generate a row control signal R_CTRL and a sensing control signal S_CTRL. Therefore, the precharge operation P0 and the sensing operation P3 can be performed in conjunction with each other within the write recovery time tWR and the row precharge time tRP, thereby maximizing the operation efficiency and minimizing the area occupied by the delay circuit.

[0112] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the embodiments of the present disclosure, this is only for descriptive purposes and should not be interpreted as limiting. It should be understood by those skilled in the art that various changes may be made to the technical spirit of the present disclosure without departing from the technical spirit of the present disclosure.

[0113] For example, for the logic gates and transistors provided as examples in the above embodiments, different positions and types may be implemented according to the polarity of the input signal. In addition, these embodiments may be combined to form further embodiments.

[0114] From the foregoing it will be appreciated that although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited, except in accordance with the appended claims.

Claims

1. A semiconductor device comprising: a first delay circuit having a first delay amount that decreases according to a common bias, and generating a first delay control signal based on the first delay amount; a second delay circuit having a second delay amount increased according to the common bias and generating a second delay control signal based on the second delay amount; a signal generating circuit that generates a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and An internal operation circuit performs a first operation and a second operation complementarily within a target time in response to the internal control signal.

2. The semiconductor device according to claim 1, in, The first delay circuit adjusts the pulse width of the source signal according to the first delay amount to generate the first delay control signal, and The second delay circuit adjusts the pulse width of the source signal according to the second delay amount to generate the second delay control signal.

3. The semiconductor device according to claim 1, in, The first delay circuit includes a plurality of first type transistors, the plurality of first type transistors are coupled in series between an input terminal for receiving a source signal and an output terminal for outputting the first delay control signal, the plurality of first type transistors each having a gate for receiving the common bias, and The second delay circuit includes a plurality of second type transistors, which are coupled in series between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, and each of the plurality of second type transistors has a gate for receiving the common bias.

4. The semiconductor device according to claim 3, in, Each of the plurality of first type transistors has a channel resistance that decreases as a gate voltage increases, and Each of the plurality of second type transistors has a channel resistance that increases as a gate voltage increases.

5. The semiconductor device according to claim 1, in, The first delay circuit includes a plurality of first type transistors, the plurality of first type transistors are coupled in series between an input terminal for receiving a source signal and an output terminal for outputting the first delay control signal, the plurality of first type transistors all receive the common bias, and Wherein, the second delay circuit includes a plurality of transistor groups, which are selectively coupled in parallel between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, wherein the number of transistor groups coupled in parallel decreases as the common bias increases.

6. The semiconductor device according to claim 5, in, The second delay circuit further includes a bias control circuit, wherein the bias control circuit reduces the number of high bits of the selection signal and increases the number of low bits of the selection signal as the common bias increases, and Each of the plurality of transistor groups includes a selection transistor and a bias transistor coupled in series, the selection transistor having a gate receiving a corresponding bit of the selection signal, and the bias transistor having a gate receiving the common bias.

7. The semiconductor device according to claim 5, in, Each of the plurality of first type transistors has a channel resistance that decreases as a gate voltage increases, and Each of the plurality of transistor groups has an equivalent resistance that increases as the common bias increases.

8. The semiconductor device according to claim 1, in, The first delay circuit includes a plurality of first transistor groups, the plurality of first transistor groups are coupled in parallel between an input terminal receiving a source signal and an output terminal outputting the first delay control signal, The second delay circuit includes a plurality of second transistor groups, the plurality of second transistor groups are coupled in parallel between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, and As the common bias increases, the number of the second transistor groups coupled in parallel is controlled to be smaller than the number of the first transistor groups coupled in parallel.

9. The semiconductor device according to claim 8, in, The first delay circuit further includes a first bias control circuit, wherein the first bias control circuit reduces the number of high bits of the first selection signal and increases the number of low bits of the first selection signal as the common bias increases, and Each of the plurality of first transistor groups includes a first selection transistor and a first bias transistor coupled in series, the first selection transistor having a gate receiving a corresponding bit of the first selection signal, and the first bias transistor having a gate receiving the common bias.

10. The semiconductor device according to claim 9, in, The second delay circuit further includes a second bias control circuit, wherein the second bias control circuit reduces the number of high bits of the second selection signal and increases the number of low bits of the second selection signal as the common bias increases, wherein the second bias control circuit controls the number of high bits of the second selection signal to be smaller than the number of high bits of the first selection signal, and Each of the plurality of second transistor groups includes a second selection transistor and a second bias transistor coupled in series, the second selection transistor having a gate receiving a corresponding bit of the second selection signal, and the second bias transistor having a gate receiving the common bias.

11. The semiconductor device according to claim 1, in, the internal operation circuit sequentially performs the first operation and the second operation within the target time, and Wherein, the internal operation circuit increases the execution time of the second operation and reduces the execution time of the first operation as the common bias increases.

12. A memory device comprising: A memory cell array; a control logic that: generates a first delay control signal based on a first delay amount that decreases according to a common bias, generates a second delay control signal based on a second delay amount that increases according to the common bias, and generates a plurality of internal control signals corresponding to commands according to the first delay control signal and the second delay control signal; a row control circuit, which: is coupled to the memory cell array through a plurality of word lines; and drives the word lines in response to the internal control signal; and A sense amplifier circuit is coupled to the memory cell array through a plurality of bit lines and senses and amplifies data of the bit lines in response to the internal control signal.

13. The memory device of claim 12, wherein the control logic comprises: a timing control circuit, which generates a source signal and a plurality of timing control signals according to the command; A first delay circuit, which: has the first delay amount; and generates the first delay control signal by adjusting the pulse width of the source signal according to the first delay amount; a second delay circuit which: has the second delay amount; and generates the second delay control signal by adjusting the pulse width of the source signal according to the second delay amount; and A signal generating circuit generates the internal control signal corresponding to the plurality of timing control signals according to the first delay control signal and the second delay control signal.

14. The memory device according to claim 13, in, The first delay circuit includes a plurality of first type transistors, the plurality of first type transistors are coupled in series between an input terminal receiving a source signal and an output terminal outputting the first delay control signal, each of the plurality of first type transistors having a gate receiving the common bias, and The second delay circuit includes a plurality of second type transistors, which are coupled in series between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, and each of the plurality of second type transistors has a gate for receiving the common bias.

15. The memory device according to claim 13, in, The first delay circuit includes a plurality of first type transistors, the plurality of first type transistors are coupled in series between an input terminal receiving a source signal and an output terminal outputting the first delay control signal, each of the plurality of first type transistors having a gate receiving the common bias, and The second delay circuit includes a plurality of transistor groups, which are coupled in parallel between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, wherein the number of transistor groups coupled in parallel decreases as the common bias increases.

16. The memory device according to claim 13, in, The first delay circuit includes a plurality of first transistor groups, the plurality of first transistor groups are coupled in parallel between an input terminal receiving the source signal and an output terminal outputting the first delay control signal, The second delay circuit includes a plurality of second transistor groups, the plurality of second transistor groups are coupled in parallel between an input terminal for receiving the source signal and an output terminal for outputting the second delay control signal, and The number of the second transistor groups coupled in parallel is controlled to be smaller than the number of the first transistor groups coupled in parallel.

17. The memory device according to claim 12, in, The sense amplifier circuit sequentially performs an offset cancellation operation and a charge sharing operation within a RAS to CAS delay time, wherein the offset cancellation operation is used to remove an offset of a bit line pair, and the charge sharing operation is used to make a memory cell share charge with one bit line of the bit line pair. As the common bias increases, the sense amplifier circuit increases the execution time of the charge sharing operation and decreases the execution time of the offset cancellation operation.

18. The memory device according to claim 12, in, The sense amplifier circuit sequentially performs a main sensing operation for sensing and amplifying data of a bit line pair and a precharge operation for applying a precharge voltage to the bit line pair within a write recovery time and a row precharge time, As the common bias increases, the sense amplifier circuit increases the execution time of the main sensing operation and decreases the execution time of the pre-charging operation.

19. The memory device according to claim 14, in, Each of the plurality of first type transistors has a channel resistance that decreases as a gate voltage increases, and Each of the plurality of second type transistors has a channel resistance that increases as a gate voltage increases.

20. The memory device according to claim 15, in, Each of the plurality of first type transistors has a channel resistance that decreases as a gate voltage increases, and Each of the plurality of second type transistors has a channel resistance that increases as a gate voltage increases.

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