An operating method of a storage controller, a storage controller, and a storage system

Abstract

The present disclosure provides an operating method of a storage controller, a storage controller and a storage system, and relates to the technical field of semiconductor chips. The method comprises: in a first operation stage, performing multiple read operations according to a first reference voltage, obtaining multiple read results, determining a voltage offset direction of a second operation stage according to the number of failed bits, and determining a second reference voltage of the second operation stage according to the first reference voltage, the voltage offset amount of the second operation stage and the voltage offset direction of the second operation stage. The present disclosure aims to solve the problem that the read retry time is too long, which affects the read-write performance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to an operating method of a storage controller, a storage controller and a storage system. BACKGROUND

[0002] The threshold voltage of a storage unit can be changed by various factors, and if a reasonable read voltage is not set after the threshold voltage is changed, reading fails. After reading fails, reading retry is performed, and if the reading retry time is too long, the user experience is affected. SUMMARY

[0003] Embodiments of the present disclosure provide an operating method of a storage controller, a storage controller and a storage system, aiming to improve the problem that the read-write performance is affected when the reading retry time is too long.

[0004] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, an operating method of a storage controller is provided, the method comprising: in a first operation stage, performing multiple reading operations according to a first reference voltage to obtain multiple reading results, wherein the reading result comprises a number of failed bits. According to the numbers of failed bits, a voltage offset direction of a second operation stage is determined, a second reference voltage of the second operation stage is determined according to the first reference voltage, a voltage offset amount of the second operation stage and the voltage offset direction of the second operation stage, the voltage offset amount of the second operation stage is smaller than a voltage offset amount of the first operation stage, and the voltage offset amount of the second operation stage is a voltage offset amount of the second reference voltage relative to the first reference voltage.

[0006] The operating method of the storage controller provided by the present disclosure dynamically adjusts the voltage offset amount of the next operation stage according to the reading result of the previous operation stage, so that the voltage offset amount of each operation stage changes, thereby reducing the number of reading retries required to find the target read voltage, and further improving the reading performance of the storage and the user experience. Moreover, the operating method of the storage controller provided by the present disclosure does not require manual intervention by the user, and automatically finds the optimal read position through internal iteration of the processor, thereby reducing the workload of the user and reducing the operation complexity.

[0007] In some embodiments, the second reference voltage, the first reference voltage and the voltage offset amount of the second reading stage satisfy:

[0008] V n+1 = V n + (-1) m · S n+1

[0009] wherein Vn+1 V is the second reference voltage. n S is the first reference voltage. n+1 m represents the voltage offset in the second reading stage. When the voltage offset direction of the second reading stage is in the same direction as the voltage offset direction of the first reading stage, m is an even number; when the voltage offset direction of the second reading stage is in the opposite direction to the voltage offset direction of the first reading stage, m is an odd number.

[0010] In some embodiments, prior to the first operation phase, the method includes: acquiring a target voltage range and determining a first reference voltage as the endpoint voltage of the target voltage range.

[0011] The storage controller operation method disclosed herein avoids multiple reads at unnecessary threshold voltage positions by iterating and continuously adjusting the reference read voltage within a specific voltage range, thereby greatly reducing read retry time.

[0012] In some embodiments, performing multiple read operations based on a first reference voltage to obtain multiple read results includes: sequentially increasing or decreasing the first reference voltage to obtain multiple read voltages, performing read operations based on the multiple read voltages to obtain multiple read results, wherein the read results include the number of failure bits.

[0013] In some embodiments, determining the voltage offset direction of the second operation stage based on the plurality of failure bit numbers includes: determining the voltage offset direction of the second operation stage to be the opposite direction of the voltage offset direction of the first operation stage when the plurality of failure bit numbers increase sequentially, and determining the voltage offset direction of the second operation stage to be the same direction as the voltage offset direction of the first operation stage when the plurality of failure bit numbers decrease sequentially.

[0014] In some embodiments, determining the voltage offset direction of the second operation stage based on the changing trend of the number of failure bits further includes: determining the voltage offset direction of the second operation stage as the opposite direction of the voltage offset direction of the first operation stage when the number of multiple failure bits first increases and then decreases.

[0015] In some embodiments, the method further includes determining a first reference voltage as the target read voltage when the number of multiple failure bits decreases first and then increases.

[0016] In some embodiments, the method further includes: determining the first reference voltage as the target reading voltage when the voltage offset of the second reading stage is less than a preset threshold.

[0017] The storage controller operation method disclosed herein can automatically stop iteration when the voltage offset drops below the minimum value, ensuring the accuracy and stability of the voltage adjustment operation.

[0018] In a second aspect, a storage controller is provided, coupled to a memory. The storage controller includes a processor and an ECC circuit. The ECC circuit is configured to perform multiple read operations based on a first reference voltage in a first operation phase to obtain multiple read results, wherein the read results include a number of failure bits. The processor is configured to determine a voltage offset direction in a second operation phase based on the multiple failure bit numbers. The processor is also configured to determine a second reference voltage in the second operation phase based on the first reference voltage, the voltage offset in the second operation phase, and the voltage offset direction in the second operation phase. The voltage offset in the second operation phase is less than the voltage offset in the first operation phase, and the voltage offset in the second operation phase is the voltage offset of the second reference voltage relative to the first reference voltage.

[0019] In some embodiments, the second reference voltage, the first reference voltage, and the voltage offset of the second read phase satisfy the following:

[0020] V n+1 =V n +(-1) m ·S n+1

[0021] Where V n+1 V is the second reference voltage. n S is the first reference voltage. n+1 m represents the voltage offset in the second reading stage. When the voltage offset direction of the second reading stage is in the same direction as the voltage offset direction of the first reading stage, m is an even number; when the voltage offset direction of the second reading stage is in the opposite direction to the voltage offset direction of the first reading stage, m is an odd number.

[0022] In some embodiments, the processor is further configured to: acquire a target voltage range and determine a first reference voltage as the endpoint voltage of the target voltage range.

[0023] In some embodiments, the processor is specifically configured to: sequentially increase or decrease a first reference voltage to obtain multiple read voltages, perform read operations based on the multiple read voltages to obtain multiple read results, the read results including the number of failure bits.

[0024] In some embodiments, the processor is specifically configured to: determine that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage when the number of multiple failure bits increases sequentially, and determine that the voltage offset direction of the second operation stage is the same direction as the voltage offset direction of the first operation stage when the number of multiple failure bits decreases sequentially.

[0025] In some embodiments, the processor is specifically configured to: determine that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage when the number of multiple failure bits first increases and then decreases.

[0026] In some embodiments, the processor is further configured to determine the first reference voltage as the target read voltage when the number of multiple failure bits decreases first and then increases.

[0027] In some embodiments, the processor is further configured to determine the first reference voltage as the target read voltage when the voltage offset of the second read phase is less than a preset threshold.

[0028] Thirdly, a storage system is provided, comprising: a memory and a storage controller, the storage controller being connected to the memory via a flash memory interface circuit; the storage controller is the storage controller provided in any embodiment of the second aspect.

[0029] Fourthly, a computer-readable storage medium is provided, which stores computer-executable instructions; when executed, the computer-executable instructions are able to implement any of the methods in the first aspect above.

[0030] Fifthly, an electronic device is provided, including a host such as the storage system provided in the third aspect, the host being connected to the storage system to write data to the storage system or read data stored in the storage system.

[0031] Understandably, the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0032] Figure 1 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0033] Figure 2 A block diagram of a storage system provided in an embodiment of this disclosure;

[0034] Figure 3 A schematic diagram of a charge-trapping transistor provided in an embodiment of this disclosure;

[0035] Figure 4 A schematic diagram of the stored data of a charge-trapping transistor provided in an embodiment of this disclosure;

[0036] Figure 5 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of this disclosure;

[0037] Figure 6 A schematic diagram of the threshold voltage distribution of another memory cell provided in an embodiment of this disclosure;

[0038] Figure 7 A schematic diagram illustrating the determination of the target readout voltage provided in an embodiment of this disclosure;

[0039] Figure 8 A schematic diagram of a storage controller provided in an embodiment of this disclosure;

[0040] Figure 9 A flowchart illustrating the storage controller operation method provided in an embodiment of this disclosure;

[0041] Figure 10 A schematic diagram illustrating another method for determining the target readout voltage according to an embodiment of this disclosure;

[0042] Figure 11 A flowchart illustrating another storage controller operation method provided in an embodiment of this disclosure;

[0043] Figure 12 A schematic diagram illustrating another method for determining the target readout voltage according to an embodiment of this disclosure;

[0044] Figure 13 A schematic diagram illustrating another method for determining the target readout voltage according to an embodiment of this disclosure;

[0045] Figure 14 This is a flowchart illustrating another storage controller operation method provided in an embodiment of the present disclosure. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0050] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0051] "A and / or B" includes three combinations: A only, B only, and a combination of A and B. The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not preclude applicability to or configuration to perform additional tasks or steps on devices. Additionally, the use of "based on" implies openness and inclusivity, as processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0052] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0053] Embodiments of this disclosure provide an electronic device, such as any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc. See also Figure 1 , Figure 1The diagram illustrates an electronic device 10 provided in an embodiment of the present disclosure, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all act as masters to access the storage system.

[0054] For example, see Figure 2 , Figure 2 A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown. The storage system 110 includes a storage controller 111 and a memory 112. The storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2D) memory or a three-dimensional (3D) memory.

[0055] Storage system 110 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, storage system 110 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device that incorporates storage.

[0056] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 may be integrated into a memory card. The memory card includes any one of the following: a personal computer memory card (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD card), and UFS.

[0057] For example, taking flash memory as the storage medium of memory 112, the basic storage unit of flash memory includes floating gate field-effect transistors or charge trap transistors, etc. This disclosure will use charge trap transistors as an example for introduction.

[0058] See Figure 3 , Figure 3 A schematic diagram of a charge-trapping transistor is shown, including a control gate 211, a charge-trapping layer 212, a source 213, a drain 214, a substrate 215, an oxide layer 216, and a tunnel oxide layer 217. The source 213 and drain 214 are disposed on the substrate 215. In this embodiment, an N-channel charge-trapping field-effect transistor is used as an example, where the substrate 215 is a P-type semiconductor material, while the source 213 and drain 214 are N-type semiconductor materials. The substrate material between the source 213 and the drain 214 can form a conductive channel 218. A charge trapping layer 212 covers the conductive channel 218. A tunnel oxide layer 217 is located between the charge trapping layer 212 and the conductive channel 218, separating the charge trapping layer 212 from the source 213, the drain 214, and the conductive channel 218. A control gate 211 is disposed on the charge trapping layer 212. An oxide layer 216 is disposed between the control gate 211 and the charge trapping layer 212 to separate the control gate 211 from the charge trapping layer 212. Both the oxide layer 216 and the tunnel oxide layer 217 are made of an insulating material, such as silicon dioxide (SiO2).

[0059] The charge trapping layer 212 is made of an insulating material with a high charge trapping density. When writing data, the charge trapping layer 212 traps electrons, and the threshold voltage of the field-effect transistor changes. This characteristic is used to store data. When erasing data, holes in the channel are injected into the charge trapping layer 212 to neutralize the electrons in the charge trapping layer 212, thereby achieving erasure.

[0060] When electrons are trapped in the charge trapping layer, a higher threshold voltage is required to open the conductive channel due to the shielding effect of the electrons. Let V be the threshold voltage when no electrons are trapped in the charge trapping layer. th1 The threshold voltage in the charge trapping layer when electrons are trapped is denoted as V. th2 So, assuming we use a value greater than V th1 And less than V th2 The voltage is used to try to turn on the charge trap transistor. If the charge trap transistor is turned on, it can be determined that no electrons are trapped in the charge trap layer. If the charge trap transistor is not turned on, it can be determined that electrons are trapped in the charge trap layer. Based on this logic, when no electrons are trapped in the charge trap layer, the charge trap transistor is in the on state, which represents 1. When electrons are trapped in the charge trap layer, the charge trap transistor is in the off state, which represents 0. Therefore, data can be stored using these different states. The storage function can be achieved by changing the threshold voltage of the charge trap transistor by injecting or trapping electrons in the charge trap layer.

[0061] When a voltage is applied to the control gate, a tunneling effect occurs due to the potential difference between the control gate and the channel. Electrons can be injected into the charge trapping layer or captured by the charge trapping layer. When storing data, the data is stored in the charge trapping layer, and the presence or absence of charge in the charge trapping layer can indicate the data currently stored in the memory cell. For example, see... Figure 4 ,like Figure 4 As shown in Figure a, the state where the charge trapping layer has charge is 0, as... Figure 4 As shown in Figure b, the state of the charge trapping layer without charge is 'store 1'. The process of storing data in the memory cell is the process of programming the memory cell.

[0062] After programming, the threshold voltage of the memory cell is not constant but changes due to various factors; this phenomenon is called threshold voltage drift. The causes of threshold voltage drift typically include the following:

[0063] Intrinsic Voltage Shift (IVS): The charge in a memory cell is stored in a floating gate; however, this charge drifts over time, causing a change in the threshold voltage. This intrinsic voltage shift is caused by factors such as charge loss, random noise, and material properties.

[0064] Temperature effect: Temperature is another important factor that can significantly affect the threshold voltage. As temperature changes, the energy level distribution of electrons in the material changes, leading to a drift in the threshold voltage. For example, the threshold voltage may increase at high temperatures and decrease at low temperatures.

[0065] Furthermore, the threshold voltage will shift with increased usage or over time. Therefore, the threshold voltage of a storage cell is affected by various internal and external factors. After the threshold voltage of a storage cell shifts, the amplitude of the threshold voltage distribution becomes wider. Generally, the threshold voltage will shift to the right, so higher voltage is required for correct data reading, which will lead to a decrease in voltage accuracy.

[0066] If a normal read voltage is used to read data after the threshold voltage has shifted, a read error will occur.

[0067] For example, see Figure 5 This diagram illustrates the distribution of the threshold voltage of a memory cell before any shift occurs. It includes the threshold voltage distribution of memory cells in storage state P1 before a shift occurs, and the threshold voltage distribution of memory cells in storage state P2 before a shift occurs, for example, the areas enclosed by solid lines corresponding to D1 and D2. During data reading, a read voltage Vread1 is applied to obtain the storage state of each memory cell. The read voltage Vread1 is greater than the threshold voltage of the memory cells in region D1 and less than the threshold voltage of the memory cells in region D2. Therefore, before the threshold voltage shift occurs, when reading memory cells in storage state P1 or P2 using the read voltage Vread1, it is relatively easy to distinguish whether a memory cell is in storage state P1 or P2, thus obtaining the data stored within the memory cell.

[0068] When the threshold voltage of the memory cell changes, refer to Figure 6 The solid-lined region corresponding to D3 represents the threshold voltage distribution of the P1 storage state cell after a threshold voltage shift. The solid-lined region corresponding to D4 represents the threshold voltage distribution of the P2 storage state cell after a threshold voltage shift. Compared to regions D1 and D2, regions D3 and D4 show significant shape shifts and widening. Especially near the read voltage Vread1, an overlapping region appears between the two storage states. Figure 6(The shaded area in the image). In this situation, if the read voltage Vread1 is used to read data from each memory cell sequentially, a memory cell in storage state P2 may be incorrectly identified as a memory cell in storage state P1, or vice versa. Furthermore, when the threshold voltage of a memory cell is exactly equal to the read voltage Vread1, it is also impossible to accurately determine whether the memory cell is in storage state P1 or storage state P2, increasing the risk of read errors. This situation of data read errors is called a failure bit (Fb), and after each read operation, the number of data read errors in this read operation needs to be counted; this process is called the failure bit count (Fbc).

[0069] However, threshold voltage offset in memory cells is unavoidable. To ensure correct data reads, the memory system incorporates an Error Correcting Code (ECC) circuit. The ECC circuit counts the number of data read errors after each read operation, i.e., the number of failure bits. When the number of failure bits is low, fewer bits require ECC correction, increasing the probability of correct reads and reducing read time. In this case, the corresponding read voltage is optimal. Therefore, in... Figure 6 In the case of the threshold voltage distribution of two adjacent storage states shown, by setting the read voltage at the intersection point N of the two storage states corresponding to D3 and D4, the statistical value of the number of failure bits can be minimized. Thus, the read voltage Vread2 corresponding to this position is determined as the target read voltage, which is the optimal read voltage.

[0070] Therefore, determining the optimal read voltage setting when the threshold voltage of the storage cell deviates is a key concern in the industry. One possible approach is for the user to continuously adjust the input read voltage until it approaches the target read voltage, thus correctly reading the data. In other words, the target read voltage is determined through multiple adjustments.

[0071] However, if the target read voltage is far from the initially set read voltage, it will take a long time to find the target read voltage. Because a fixed step size is used, it's impossible to traverse the entire range in a single iteration, especially when the target read voltage is far from the initial read voltage. In this case, multiple adjustments to the read voltage are needed to gradually approach the target read voltage. Multiple iterations increase the time required to find the optimal read position, as each iteration requires trying different read voltages, checking the results, and gradually moving closer to the target read voltage. Since the user needs to sequentially traverse the manufacturer's pre-defined read retry table, the reading process becomes more time-consuming and less efficient.

[0072] For example, see Figure 7 The threshold voltage range [A, B] is the voltage range given by the voltage reading retry table. The target reading voltage is at the threshold voltage E, while the initial reading voltage is at the threshold voltage A. Therefore, the optimal reading voltage and the initial reading voltage are far apart. In this case, a reading operation is first performed based on reading voltage A to obtain the reading result when the reading voltage is A. Then, based on the reading result, it is determined that the target reading voltage requirement is not met. Therefore, the reading voltage needs to be adjusted to the next value in the voltage reading retry table, i.e., the threshold voltage C. Then, a reading operation is performed based on this reading voltage C to obtain the reading result when the reading voltage is C. This process is the first voltage adjustment process. The reading voltage is continued to be adjusted, moving the reading voltage to the right, until the fourth voltage adjustment is completed, moving the reading voltage to the threshold voltage E. It should be noted that in the above voltage adjustment process, the value of each voltage adjustment is the same. A reading operation is performed based on reading voltage E to obtain the reading result when the reading voltage is E. Then, based on this reading result, it is determined that the target reading voltage requirement is met, and the reading voltage E is determined as the target reading voltage.

[0073] In the above embodiment, the target read voltage falls precisely within the voltage range given by the voltage retry table. However, in practical applications, the number of voltage retry tables increases due to the variety of user scenarios. Therefore, it becomes necessary to iterate through all the voltage ranges given by the voltage retry tables and continuously adjust the read voltage to determine the target read voltage. This results in a longer time required to find the target read voltage, negatively impacting the user experience.

[0074] To address the aforementioned issues, embodiments of this disclosure provide a solution: dynamically adjusting the voltage offset of the next operation stage based on the read result of the previous operation stage, so that the voltage offset changes in each operation stage, reducing the number of read retries required to determine the target read voltage, and improving the read performance of the memory.

[0075] Figure 8 The diagram illustrates a storage controller 111 provided according to an embodiment of the present disclosure. The storage controller 111 may include a processor 311, a cache 312, an ECC circuit 313, a host interface circuit 314, and a flash memory interface circuit 315.

[0076] Processor 311 can communicate with host 100 via host interface circuit 314 and perform logical operations to control the operation of memory controller 111. For example, processor 311 can load programming commands, data files, or data structures in response to requests received from host 100 or external devices, perform various operations, or generate commands and addresses. For example, processor 311 can generate various commands for performing programming operations, read operations, erase operations, and parameter setting operations. In some possible examples, processor 311 can generate commands without a request from host 100; for example, processor 311 can generate commands such as background operations for garbage collection of memory 112, or processor 311 can generate commands to train the quality of bus transmission signals between memory controller 111 and memory 112.

[0077] ECC circuit 313 can perform error detection and correction functions on read data read from memory 112. For example, ECC circuit 313 can generate parity bits for write data to be written to memory 112, and the generated parity bits can be stored in memory 112 along with the write data. When reading data from memory 112, ECC circuit 313 can use the parity bits read from memory 112 along with the read data to correct errors in the read data, and can output the error-corrected read data.

[0078] The host interface circuit 314 can send data or commands to the host 100, or receive data or commands from the host 100. For example, commands sent from the host 100 to the host interface circuit 314, data to be written to the memory 112, etc., and responses to commands sent from the host interface circuit 314 to the host 100, data to be read from the memory 112, etc. The host interface circuit 314 may also include a protocol for exchanging data between the host 100 and the storage controller 111. For example, the host interface circuit 314 can communicate with the host 100 through at least one of the following interface protocols: Universal Serial Bus (USB) protocol, Microsoft Management Console (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0079] The flash memory interface circuit 315 can communicate with the memory 112 using a communication protocol under the control of the processor 311, including command, address, and data communication. The flash memory interface circuit 315 can send data to be written to the memory 112, or receive data read from the memory 112. The flash memory interface circuit 315 can be implemented in accordance with standard protocols such as Toggle or Open NAND Flash Interface (ONFI). For example, using the ONFI protocol, the memory controller 111 and the memory 112 can be connected via an ONFI bus.

[0080] Specifically, when the aforementioned processor 311 is working, it executes the following... Figure 9 The operation method shown includes steps S901-903, and the processor 311 can execute at least one of steps S901, S902 or S903.

[0081] Before executing step S902, an erase voltage must first be applied to the word line to erase the memory cell coupled to the word line. After erasing the memory cell coupled to the word line, the memory cell needs to be programmed to a different memory state. After completing the erasure and programming operations of the memory cell in the memory, the memory controller can execute the scheme of this disclosure to determine the target read voltage.

[0082] See Figure 9 The operation method of the storage controller provided in the embodiments of this disclosure includes:

[0083] S901: In the first operation phase, multiple read operations are performed based on the first reference voltage to obtain multiple read results, including the number of failure bits.

[0084] Determining the target read voltage typically involves multiple voltage offset operations to gradually approach or locate the target read voltage. Each voltage offset operation corresponds to an operation stage. Within each operation stage, multiple read operations are performed, using the reference voltage set for the current stage as a benchmark, generating multiple read results. This process is called automatic voltage detection (AVD). This process collects sufficient read results to determine the optimal read voltage or to perform more precise voltage adjustments in the next operation stage. Therefore, this process is iterative, involving multiple operation stages and multiple read operations to ultimately find the target read voltage, ensuring data accuracy and reliability. The read results include the number of failure bits, which refers to the number of bits detected as causing errors or failures during data reading or writing. The number of failure bits quantifies the extent of read errors.

[0085] For example, the number of failure bits is calculated by comparing the actual data read with the expected data. In the storage controller, the primary function of the ECC circuit 313 is to detect and correct errors in the data. During data reading, the ECC circuit 313 compares the data with the original data. If an error is detected—that is, if the data bits do not match the expected value—the ECC circuit 313 records the number of detected failure bits; this process is called failure bit counting. Therefore, by counting the failure bits, the ECC circuit 313 can obtain the number of failure bits in the read operation.

[0086] S902: Determine the voltage offset direction of the second operation stage based on the number of multiple failure bits.

[0087] The number of failure bits is an indicator used to measure how many bits in the read result are incorrect or inconsistent with the expected value. This indicator reflects the relationship between the current reference voltage and the target read voltage. A high number of failure bits means that more data does not match the expected value, or that the reference voltage used in the current operation phase is far from the target read voltage.

[0088] Conversely, a lower number of failure bits indicates higher accuracy in the read operation, meaning the reference voltage used in the current operation phase is closer to the target read voltage. Therefore, the number of failure bits not only measures the success of the read operation but also reflects the relative positional relationship between the reference voltage and the target read voltage during the operation phase. In practice, by monitoring and analyzing the trend of the failure bit count, the reference voltage can be adjusted to continuously bring it closer to the target read voltage.

[0089] Therefore, by observing multiple reads at each operational stage, the trend in the number of failure bits can be determined. This trend reflects the impact of voltage settings on read accuracy. By analyzing multiple reads at each operational stage, the trend in the number of failure bits is determined. Subsequently, based on this trend, the offset direction of the reference voltage for the next operational stage relative to the reference voltage of the current operational stage is determined. These reference voltage offset directions can be selected as reverse offset (adjusting the reference voltage in the opposite direction), same-direction offset (adjusting the reference voltage in the same direction), or no offset (keeping the reference voltage unchanged).

[0090] S903: Determine the second reference voltage for the second operation stage based on the first reference voltage, the voltage offset of the second operation stage, and the voltage offset direction of the second operation stage.

[0091] After the first operation phase is completed, the second operation phase begins. In the second operation phase, adjustments are made to the reference voltage established in the first phase to obtain the second reference voltage required for the second operation phase, thereby further improving the accuracy of the reading operation. The voltage offset in the second operation phase is a voltage adjustment value relative to the first reference voltage. This voltage offset can be an increase or decrease in voltage, depending on the voltage offset direction determined in the previous steps for the second operation phase.

[0092] In the second operation stage, the voltage needs to be further adjusted based on the first reference voltage. This adjustment value can be determined according to the previously determined voltage offset direction. If the first operation stage selected the direction of increasing voltage, then the second operation stage will continue to offset in the direction of increasing voltage, and vice versa.

[0093] Next, based on the first reference voltage, the voltage offset of the second operation stage, and the direction of the voltage offset in the second operation stage, the second reference voltage for the second operation stage can be determined. The second reference voltage is the reference voltage value used when performing multiple read operations during the second operation stage. Specifically, the second reference voltage can be calculated by adding or subtracting the first reference voltage from the voltage offset of the second operation stage.

[0094] It is important to emphasize that as the number of operation stages increases, the voltage offset for each stage gradually decreases. Gradually decreasing the voltage offset makes it easier to distinguish the different states of the memory cell within each operation stage, thereby improving read accuracy and reducing read errors. Furthermore, large voltage offsets can lead to data corruption or bit flips in the memory cell. By gradually reducing the voltage offset, this risk can be mitigated, ensuring that data is not subjected to unnecessary interference or damage during the read process.

[0095] For example, if the voltage offset in the first operation stage is the maximum voltage offset, then the voltage offset in the second operation stage can be 1 / 2 of the maximum voltage offset, 1 / 3 of the maximum voltage offset, etc.

[0096] After obtaining the reference voltage of the second operation stage, it will be used as the updated first reference voltage, and the iteration will continue to execute steps S901 to S903 until the condition for exiting the iteration is met, and the first reference voltage of the last iteration will be used as the target read voltage as the output.

[0097] For example, see Figure 10 The detailed implementation process of S901 to S903 is explained below. First, in the first operation stage, the reference voltage is the position corresponding to the dashed line 1, that is, the reference voltage of the first operation stage is L. Based on the reference voltage L of the first operation stage, multiple reading operations are performed to obtain multiple reading results under the reference voltage.

[0098] Based on the multiple reading results of the first operation stage, the voltage offset direction of the second operation stage is determined to be offset to the right, and the voltage offset amount of the second operation stage is max. Then, the reference voltage of the second operation stage (L+max), that is, the reference voltage of the second operation stage, is offset from the position of dashed line 1 to the position of dashed line 2. Based on the reference voltage (L+max) of the second operation stage, multiple reading operations are performed to obtain multiple reading results under the reference voltage.

[0099] Based on the multiple reading results from the second operation stage, the voltage offset direction of the third operation stage is determined to be to the left, and the voltage offset amount of the third operation stage is 1 / 2max. Then, the reference voltage of the third operation stage (L+max-1 / 2max), that is, the reference voltage of the third operation stage, has shifted from the position of dashed line 2 to the position of dashed line 3. Based on the reference voltage (L+max-1 / 2max) of the third operation stage, multiple reading operations are performed to obtain multiple reading results under this reference voltage.

[0100] Based on the multiple reading results from the third operation stage, the voltage offset direction of the fourth operation stage is determined to be to the left, and the voltage offset amount of the fourth operation stage is 1 / 4max. Then, the reference voltage of the third operation stage (L+max-1 / 2max+1 / 4max), that is, the reference voltage of the fourth operation stage, has shifted from the position of dashed line 3 to the position of dashed line 4. Based on the reference voltage of the fourth operation stage (L+max-1 / 2max+1 / 4max), multiple reading operations are performed to obtain multiple reading results under this reference voltage.

[0101] Based on the multiple reading results from the fourth operation stage, the voltage offset direction of the fifth operation stage is determined to be to the right, and the voltage offset amount of the fifth operation stage is 1 / 8max. Therefore, the reference voltage of the fifth operation stage is (L+max-1 / 2max+1 / 4max-1 / 8max), which means the reference voltage of the fifth operation stage has shifted from the position of dashed line 4 to the position of dashed line 5. Based on the reference voltage of the fifth operation stage (L+max-1 / 2max+1 / 4max-1 / 8max), multiple reading operations are performed to obtain multiple reading results under this reference voltage.

[0102] Based on the multiple reading results of the fifth operation stage, the voltage offset direction of the sixth operation stage is determined to be to the left, and the voltage offset of the sixth operation stage is 1 / 16max. Therefore, the reference voltage of the sixth operation stage (L+max-1 / 2max+1 / 4max-1 / 8max+1 / 16max), that is, the reference voltage of the third operation stage, has shifted from the position of dashed line 5 to the position of dashed line 6. The position of dashed line 6 is the position of the target reading voltage, because the statistical result of the number of failed bits is the smallest when the reading operation is performed based on the threshold voltage at this position.

[0103] In this disclosure, the voltage offset of the next operation stage is dynamically adjusted based on the reading results of the previous operation stage, thereby reducing the number of reading retries required to find the target reading voltage and the reading time required to find the target reading voltage.

[0104] In one possible implementation, the second reference voltage, the first reference voltage, and the voltage offset of the second read phase satisfy the following:

[0105] V n+1 =V n +(-1) m ·S n+1

[0106] Where V n+1 V is the second reference voltage. n S is the first reference voltage. n+1 m represents the voltage offset in the second reading stage. When the voltage offset direction of the second reading stage is in the same direction as the voltage offset direction of the first reading stage, m is an even number. When the voltage offset direction of the second reading stage is in the opposite direction to the voltage offset direction of the first reading stage, m is an odd number.

[0107] To avoid multiple reads at unnecessary threshold voltage locations, in one possible implementation, prior to the first operation phase, the method includes:

[0108] S900: Obtain the target voltage range and determine the first reference voltage as the endpoint voltage of the target voltage range.

[0109] The target voltage range is a pre-defined voltage range that is manually calibrated. The target reading voltage is located within the target voltage range. In order to reduce the number of reading retries required to find the target reading voltage, the first reference voltage needs to be determined as the endpoint voltage of the target voltage range. In this operation, the first reference voltage can be set at any endpoint of the target voltage range.

[0110] For example, see [link to relevant documentation]. Figure 10 The target voltage range is [L, R]. The L endpoint can be set as the first reference voltage, or the R endpoint can be set as the first reference voltage. This disclosure does not limit this. However, it should be noted that if the voltage of one endpoint of the target voltage range is set as the first reference voltage, then in the next operation stage, the voltage of the other endpoint is set as the reference voltage of this operation stage, and then steps S901 to S903 are executed.

[0111] See Figure 11 In one possible implementation, when obtaining multiple read results, S901 includes the following sub-steps:

[0112] S9011: Based on the first reference voltage, the voltage is increased or decreased sequentially to obtain multiple read voltages.

[0113] After determining the reference voltage, multiple voltage offsets are applied based on this reference voltage to obtain multiple read voltage values ​​with a certain offset relative to the reference voltage. It should be noted that the method of obtaining the read voltage is similar in each operation stage. The following is a detailed explanation of obtaining the read voltage in the first operation stage.

[0114] Specifically, in the first operation phase, starting from a first reference voltage, the voltage is gradually increased or decreased by an equal voltage offset to obtain a series of read voltage values ​​with a certain offset relative to the first reference voltage. This means that voltage values ​​are sequentially increased or decreased based on the reference voltage to generate a set of read voltages, each deviating from the first reference voltage to varying degrees.

[0115] For example, see Figure 12 and Figure 13 The voltage offset direction of the read voltage in the current operation stage must be the same as the offset direction of the reference voltage in the current operation stage. Since the first operation stage is the initial operation stage, its voltage offset direction is predetermined. Therefore, taking the operation stage represented by dashed line 3 as an example of four read operations, the reference voltage V3 is used as the starting point for the four read operations. Then, a series of read voltages with a certain offset relative to V2 are generated. These read voltages are Vrd1, Vrd2, Vrd3, and Vrd4, where Vrd1 is greater than Vrd2, Vrd2 is greater than Vrd3, and Vrd3 is greater than Vrd4. These read voltages are located to the left of the reference voltage V3, and their offsets are equal, meaning they decrease by the same amount.

[0116] It should be noted that the above example is only one possibility. In other possible examples, the read voltage is also located to the right of the reference voltage and increases sequentially with the same offset.

[0117] It should be noted that the offsets of the multiple read voltages generated based on the reference voltage may be equal or unequal.

[0118] For example, if the offset voltage value of the read voltage Vrd1 relative to the reference voltage is M, then the offset voltage value of the read voltage Vrd2 relative to Vrd1 can be M, or it can be any other value different from M. This means that in different application scenarios, the offset values ​​of the two read voltages can be the same or different, depending on the actual application requirements.

[0119] S9012: Performs a read operation based on multiple read voltages to obtain multiple read results, including the number of failure bits.

[0120] After obtaining multiple read voltages, a read operation is performed on each read voltage separately. Each time a different read voltage is used, a read result is obtained, resulting in multiple different read results. Then, based on the number of failure bits in the multiple read results, the voltage offset direction for the next operation stage can be determined.

[0121] For example, continuing with the above embodiment, in the second operation stage, after obtaining the read voltages Vrd1, Vrd2, Vrd3 and Vrd4, read operations are performed based on the read voltages Vrd1, Vrd2, Vrd3 and Vrd4 respectively, thereby obtaining the statistical results of the number of failed bits in each read result, namely Fbc1, Fbc2, Fbc3 and Fbc4. Then, based on the changing trends of Fbc1, Fbc2, Fbc3 and Fbc4, the voltage offset direction of the second operation stage is determined.

[0122] Based on the changing trend of the number of failed bits in the reading results, the relative positional relationship between the reference voltage and the target reading voltage is adjusted so that the reference voltage can quickly approach the target reading voltage.

[0123] See Figure 14 In one possible implementation, when determining the voltage offset direction of the second operation stage, S902 includes the following sub-steps:

[0124] S9021: When the number of multiple failure bits increases sequentially, the voltage offset direction of the second operation stage is determined to be the opposite direction of the voltage offset direction of the first operation stage.

[0125] When the number of failure bits in multiple read results increases sequentially, indicating an increasing trend, it signifies that the read voltage generated based on the reference voltage in this operation stage is deviating further from the target read voltage. In other words, this operation stage has shifted the reference voltage away from the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the opposite direction of the voltage shift in this operation stage, thus shifting the reference voltage closer to the target read voltage.

[0126] For example, let's continue with the example of Fbc1, Fbc2, Fbc3, and Fbc4 obtained from four read operations. Assume Fbc1 is 10, Fbc2 is 12, Fbc3 is 15, and Fbc4 is 20. It can be seen that as the read voltage increases, the number of Fbc values ​​gradually decreases. This indicates that the reference voltage in the current operation stage has shifted away from the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the opposite direction of the voltage shift in the current operation stage. The voltage shift direction in the current operation stage is left and right. Therefore, in the next operation stage, the reference voltage needs to be shifted to the right.

[0127] S9022: When the number of multiple failure bits decreases sequentially, the voltage offset direction of the second operation stage is determined to be the same as the voltage offset direction of the first operation stage.

[0128] When the number of failure bits in multiple read results decreases sequentially, indicating a decreasing trend, it signifies that the read voltage generated based on the reference voltage in this operation stage is getting closer to the target read voltage. In other words, this operation stage shifts the reference voltage towards the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the same direction as the voltage shift in this operation stage, thus shifting the reference voltage even closer to the target read voltage.

[0129] For example, continuing with the operation stage represented by dashed line 3, the Fbc1, Fbc2, Fbc3, and Fbc4 obtained from the four read operations are assumed to be 10 for Fbc1, 6 for Fbc2, 4 for Fbc3, and 3 for Fbc4. It can be seen that as the read voltage increases, the number of Fbc values ​​gradually decreases. This indicates that the reference voltage in the current operation stage has shifted towards the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the same direction as the voltage shift direction in the current operation stage. The voltage shift direction in the current operation stage is to the left, so in the next operation stage, the reference voltage needs to be shifted to the left.

[0130] In one possible implementation, S902 also includes:

[0131] S9023: When the number of multiple failure bits increases first and then decreases, the voltage offset direction of the second operation stage is determined to be the opposite direction of the voltage offset direction of the first operation stage.

[0132] For example, continuing with the example of Fbc1, Fbc2, Fbc3, and Fbc4 obtained from four read operations, assuming Fbc1 is 10, Fbc2 is 14, Fbc3 is 16, and Fbc4 is 10, it can be seen that as the read voltage increases, the change in the number of Fbc bits includes two stages. The first stage includes Fbc increasing from 10 to 16, and the second stage includes Fbc decreasing from 16 to 10. The first stage represents an increasing trend in the number of failure bits, indicating that the read voltage generated based on the reference voltage of this operation stage is increasingly deviating from the target read voltage. The second stage represents a decreasing trend in the number of failure bits, indicating that the read voltage generated based on the reference voltage of this operation stage is increasingly approaching the target read voltage. Therefore, the positional relationship between the reference voltage and the target read voltage represented by the two stages is contradictory. Therefore, it is necessary to shift the voltage offset direction of the next operation stage in the opposite direction to the voltage offset direction of the current operation stage.

[0133] As the number of operation stages increases iteratively, the voltage offset in each stage gradually decreases, meaning the difference between the reference voltage of the current stage and the reference voltage of the previous stage gradually narrows. This implies that with increasing iterations, the voltage offset adjustment becomes increasingly minute, causing the reference voltage of the current stage to gradually approach that of the previous stage. However, when the voltage offset decreases below a minimum value that prevents further voltage offset operations, the direction of the voltage offset in the next stage cannot be definitively determined. Therefore, to ensure the effectiveness of the iteration and avoid the predicament of being unable to determine the next operation, the voltage offset needs to be used as one of the criteria for exiting the iteration. This way, when the voltage offset falls below the minimum value, the iteration can automatically stop, ensuring the accuracy and stability of the voltage adjustment operation.

[0134] If the voltage offset in the second reading stage is less than a preset threshold, the first reference voltage is determined as the target reading voltage.

[0135] For example, suppose the reference voltage of the first operation stage is A, the voltage offset of the first operation stage is B, and the voltage offset gradually decreases in each iteration. A preset threshold is set to C, meaning that when the voltage offset is less than or equal to C, the voltage offset operation cannot continue, and this needs to be used as one of the conditions for exiting the iteration.

[0136] The example iteration process is as follows:

[0137] First operating stage: Voltage offset = B.

[0138] Second operation stage: Voltage offset = 1 / 2B.

[0139] Third operation stage: Voltage offset = 1 / 4B.

[0140] Fourth operating stage: Voltage offset = 1 / 8B.

[0141] In the fourth operation stage, the voltage offset has been reduced to 1 / 8B. Comparing 1 / 8B with C, it is determined that 1 / 8B is less than the preset threshold C. At this point, no further voltage offset operations can be performed, as further reducing the voltage offset may lead to uncertain results. Therefore, the voltage offset being less than or equal to the preset threshold can be used as a condition for exiting the iteration, stopping the iteration process, and outputting the reference voltage of the fourth operation stage as the target read voltage.

[0142] The storage controller operation method disclosed herein gradually reduces the voltage offset as the operation phases iterate, and stops iterating when the voltage offset is less than a preset threshold. This ensures that voltage offset operations will not continue when the voltage offset is less than the preset threshold, thereby maintaining stability and reliability.

[0143] In addition to using the relationship between the voltage drift and the preset threshold as the criterion for exiting the iteration, the trend of the number of failure bits can also be used as the criterion for exiting the iteration.

[0144] For example, when the number of multiple failure bits decreases first and then increases, the first reference voltage is determined as the target read voltage.

[0145] For example, continuing with the operation stage represented by dashed line 3, the four read operations yield Fbc1, Fbc2, Fbc3, and Fbc4. Assuming Fbc1 is 10, Fbc2 is 6, Fbc3 is 4, and Fbc4 is 7, it can be seen that the change in the number of Fbc bits as the read voltage increases includes two stages. The first stage involves Fbc decreasing from 10 to 4, and the second stage involves Fbc decreasing from 4 to 7. The first stage represents a decreasing trend in the number of failure bits, indicating that the read voltage generated based on the reference voltage of this operation stage is getting closer to the target read voltage. The second stage represents an increasing trend in the number of failure bits, indicating that the read voltage generated based on the reference voltage of this operation stage is deviating further from the target read voltage. Therefore, there is a turning point in the positional relationship between the reference voltage and the target read voltage represented by the two stages, indicating that the target read voltage is near this turning point. Therefore, the base voltage of this operation stage can be used as the target read voltage for output.

[0146] The storage controller operation method disclosed herein dynamically adjusts the voltage offset of the next operation stage based on the read result of the previous operation stage. This ensures that the voltage offset changes in each operation stage, thereby reducing the number of read retries required to find the target read voltage, thus improving the read performance of the memory and enhancing the user experience. Furthermore, the storage controller operation method disclosed herein does not require manual user intervention; it automatically finds the optimal read position through internal processor iterations, reducing user workload and operational complexity.

[0147] Embodiments of this disclosure also provide a storage controller, such as the one described above. Figure 8 The storage controller 111 shown includes a processor 311, a cache 312, an error check code (ECC) circuit 313, a host interface circuit 314, and a flash memory interface circuit 315. The storage controller 111 is coupled to the memory 112. For example, the processor 311 is connected to the host 100 via the host interface circuit 314 and to the memory 112 via the flash memory interface circuit 315.

[0148] EcC circuit 313 is configured to perform multiple read operations based on a first reference voltage in a first operation phase to obtain multiple read results, wherein the read results include the number of failure bits, and processor 311 is configured to determine the voltage offset direction in a second operation phase based on the multiple failure bit numbers.

[0149] The processor 311 is also configured to determine a second reference voltage for the second operation stage based on a first reference voltage, a voltage offset for the second operation stage, and a voltage offset direction for the second operation stage, wherein the voltage offset for the second operation stage is less than the voltage offset for the first operation stage, and the voltage offset for the second operation stage is the voltage offset of the second reference voltage relative to the first reference voltage.

[0150] In some embodiments, the second reference voltage, the first reference voltage, and the voltage offset of the second read phase satisfy the following:

[0151] V n+1 =V n +(-1) m ·S n+1

[0152] Where V n+1 V is the second reference voltage. n S is the first reference voltage. n+1 m represents the voltage offset in the second reading stage. When the voltage offset direction of the second reading stage is in the same direction as the voltage offset direction of the first reading stage, m is an even number; when the voltage offset direction of the second reading stage is in the opposite direction to the voltage offset direction of the first reading stage, m is an odd number.

[0153] In some embodiments, the processor 311 is further configured to: acquire a target voltage range and determine a first reference voltage as the endpoint voltage of the target voltage range.

[0154] In some embodiments, the processor 311 is specifically configured to: sequentially increase or decrease a first reference voltage to obtain multiple read voltages, perform read operations based on the multiple read voltages to obtain multiple read results, the read results including the number of failure bits.

[0155] In some embodiments, the processor 311 is specifically configured to: determine the voltage offset direction of the second operation stage as the opposite direction of the voltage offset direction of the first operation stage when the number of multiple failure bits increases sequentially, and determine the voltage offset direction of the second operation stage as the same direction as the voltage offset direction of the first operation stage when the number of multiple failure bits decreases sequentially.

[0156] In some embodiments, the processor 311 is specifically configured to: determine the voltage offset direction of the second operation stage as the opposite direction of the voltage offset direction of the first operation stage when the number of multiple failure bits first increases and then decreases.

[0157] In some embodiments, the processor 311 is further configured to determine the first reference voltage as the target read voltage when the number of multiple failure bits decreases first and then increases.

[0158] In some embodiments, the processor 311 is further configured to determine the first reference voltage as the target read voltage when the voltage offset of the second read phase is less than a preset threshold.

[0159] Embodiments of this disclosure also provide a storage system, such as the one described in the foregoing examples. Figure 2 The storage system shown includes a memory 112 and a storage controller 111 provided in the foregoing example. The storage controller 111 is coupled to the memory 112 via a flash memory interface circuit 315 to control the memory 112 to store data.

[0160] Embodiments of this disclosure also provide an electronic device, such as one described in the foregoing examples. Figure 1 The electronic device shown includes a host 100 and a storage system 110 provided in the foregoing embodiments. The host 100 is connected to the storage system 110 to write data to or read data stored in the storage system 110.

[0161] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0162] In the several embodiments provided in this disclosure, it should be understood that the provided programming methods and memory can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0163] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0164] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An operating method of a storage controller, characterized by, The method comprises: In a first operation stage, a plurality of read voltages are obtained by sequentially increasing or decreasing the first reference voltage by a voltage offset of the first operation stage; A read operation is performed based on the plurality of read voltages to obtain a plurality of read results, wherein the read results comprise a number of failed bits; A voltage offset direction of a second operation stage is determined according to the plurality of failed bits; A second reference voltage of the second operation stage is determined according to the first reference voltage, a voltage offset of the second operation stage, and the voltage offset direction of the second operation stage, wherein the voltage offset of the second operation stage is smaller than the voltage offset of the first operation stage, and the voltage offset of the second operation stage is a voltage offset of the second reference voltage relative to the first reference voltage.

2. The method of claim 1, wherein, The second reference voltage, the first reference voltage, and the voltage offset of the second operation stage satisfy: wherein is a second reference voltage, is a first reference voltage, is a voltage offset of the second operation phase; when the voltage offset direction of the second operation phase and the voltage offset direction of the first operation phase are in the same direction, is an even number when the voltage offset direction of the second operation phase and the voltage offset direction of the first operation phase are in opposite directions, is an odd number.

3. The method of claim 1, wherein, Before the first operation stage, the method comprises: Obtaining a target voltage interval, and determining the first reference voltage as an endpoint voltage of the target voltage interval.

4. The method of claim 1, wherein, Determining the voltage offset direction of the second operation stage according to the plurality of failed bits comprises: In a case where the plurality of failed bits sequentially increase, determining the voltage offset direction of the second operation stage as a reverse direction of the voltage offset direction of the first operation stage; In a case where the plurality of failed bits sequentially decrease, determining the voltage offset direction of the second operation stage as a same direction of the voltage offset direction of the first operation stage.

5. The method of claim 1, wherein, The determining the voltage offset direction of the second operation stage according to the failed bits further comprises: In a case where the plurality of failed bits first increase and then decrease, determining the voltage offset direction of the second operation stage as a reverse direction of the voltage offset direction of the first operation stage.

6. The method of claim 1, wherein, The method further comprises: In a case where the plurality of failed bits first decrease and then increase, determining the first reference voltage as a target read voltage.

7. The method according to any one of claims 1 to 6, characterized in that, The method further comprises: In a case where the voltage offset of the second operation stage is smaller than a preset threshold, determining the second reference voltage as a target read voltage.

8. A storage controller, comprising: The storage controller is coupled to a memory, and the storage controller comprises a processor and an error checking code (ECC) circuit; The ECC circuit is configured to, in a first operation stage, obtain a plurality of read voltages by sequentially increasing or decreasing a first reference voltage by a voltage offset of the first operation stage; A read operation is performed based on the plurality of read voltages to obtain a plurality of read results, wherein the read results comprise a number of failed bits; The processor is configured to determine a voltage offset direction of a second operation stage according to the plurality of failed bits; The processor is further configured to determine a second reference voltage of a second operation phase according to the first reference voltage, a voltage offset amount of the second operation phase, and a voltage offset direction of the second operation phase, the voltage offset amount of the second operation phase being less than the voltage offset amount of the first operation phase, and the voltage offset amount of the second operation phase being a voltage offset amount of the second reference voltage relative to the first reference voltage.

9. The storage controller of claim 8, wherein, The second reference voltage, the first reference voltage, and the voltage offset amount of the second operation phase satisfy: wherein is a second reference voltage, is a first reference voltage, is a voltage offset of the second operation phase; when the voltage offset direction of the second operation phase and the voltage offset direction of the first operation phase are in the same direction, is an even number when the voltage offset direction of the second operation phase and the voltage offset direction of the first operation phase are in opposite directions, is an odd number.

10. The storage controller of claim 8, wherein, The processor is further configured to: acquire a target voltage interval, and determine the first reference voltage as an endpoint voltage of the target voltage interval.

11. The storage controller of claim 8, wherein, The processor is specifically configured to: determine the voltage offset direction of the second operation phase as a reverse direction of the voltage offset direction of the first operation phase when the number of the plurality of failed bits increases successively; determine the voltage offset direction of the second operation phase as a same direction of the voltage offset direction of the first operation phase when the number of the plurality of failed bits decreases successively.

12. The storage controller of claim 8, wherein, The processor is specifically configured to: determine the voltage offset direction of the second operation phase as a reverse direction of the voltage offset direction of the first operation phase when the number of the plurality of failed bits increases first and then decreases.

13. The storage controller of claim 8, wherein, The processor is further configured to: determine the first reference voltage as a target read voltage when the number of the plurality of failed bits decreases first and then increases.

14. The storage controller of any of claims 8-13, wherein, The processor is further configured to: determine the first reference voltage as a target read voltage when the voltage offset amount of the second operation phase is less than a preset threshold.

15. A storage system, characterized by A memory system includes a memory and a memory controller coupled with the memory, wherein the memory controller is as claimed in any one of claims 8-14.

16. An electronic device, comprising: A storage system includes a host and a memory system as claimed in claim 15, the host being coupled with the memory system to write data to the memory system or read data stored in the memory system.

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