Power-on detection circuit and power-on detection method

Abstract

The invention provides a power-on detection circuit which is characterized by comprising a power supply detection part which inputs an external power supply signal from an external power supply, inputs a high-voltage signal higher than the voltage of the external power supply signal from an internal power supply of a chip, detects the high-voltage signal, and outputs the detected high-voltage signal; the voltage of the high-voltage detection signal is the same as that of the external power supply signal; a delay unit that delays the high voltage detection signal input from the power supply detection unit for a predetermined time to obtain a delayed voltage detection signal; and a latch unit that inputs an external power supply detection signal from the external power supply, inputs the delayed voltage detection signal from the delay unit, latches the delayed voltage detection signal, and outputs a final detection signal.

Description

Technical Field

[0001] The present invention relates to the field of circuit detection, and in particular to a power-on detection circuit and a power-on detection method. Background Art

[0002] Dram power-on is a critical step in the Dram workflow. Only when the internal power supply of the chip is ready, the Dram chip can enter normal operation or other test function states, and an initialization process can be used to establish the power supply required inside the Dram chip. This part of the circuit will have some output signals for power detection (the internal signal of the power-on module is used to indicate that the initialization is completed or the power supply is ready). Therefore, during the power-on process, the power-on detection signal should remain stable. However, during the boost process of some internal power supplies, due to some unexpected noise or problems, fluctuations may occur, which will cause the power-on detection signal to be unstable.

[0003] Some power-on detection signals are used to enable the level converter or latch. During the initialization process, the inputs of many circuit modules are in unknown states. The instability of these power-on detection signals will make the output states of the level converter or latch unknown. This may cause the next level circuit to capture some wrong states of wrong logic.

[0004] If the enable state is latched and kept stable when the power-on detection signal reaches the target value for the first time, the states of other related circuits in the power-on process can be determined earlier and more stably. Summary of the invention

[0005] Technical problem to be solved by the invention

[0006] The object of the present invention is to provide a power-on detection circuit and a power-on detection method, which can filter the glitches of the input signal under certain unexpected circumstances, and keep the output state unchanged when it is detected that the internal power supply signal reaches a specified value and tends to a stable state, thereby preventing the final power supply detection signal from becoming low unexpectedly for a short time.

[0007] Technical solutions to technical problems

[0008] According to one embodiment of the present invention, there is provided a power-on detection circuit, comprising: a power detection unit, wherein the power detection unit inputs an external power signal from an external power supply, inputs a high voltage signal whose voltage is higher than that of the external power signal from an internal power supply of the chip, detects the high voltage signal, and obtains a high voltage detection signal having the same voltage as that of the external power signal; a delay unit, wherein the delay unit delays the high voltage detection signal input from the power detection unit by a specified time, and obtains a delayed voltage detection signal; and a latch unit, wherein the latch unit inputs an external power detection signal from the external power supply, inputs the delayed voltage detection signal from the delay unit, latches the delayed voltage detection signal, and outputs a final detection signal.

[0009] Further, the power detection unit includes: a first transistor; a second transistor, the gate of the second transistor is connected to the gate of the first transistor to form a first connection point; a pull-down unit, the pull-down unit is used to pull down the first connection point to turn on the first transistor and the second transistor when the external power signal is powered on and reaches a specified external power detection threshold and the external power detection signal becomes a high level, so that the external power signal is output from the second connection point connected to the drain of the pull-down unit and the second transistor via the second transistor; a pull-up unit, the pull-up unit is used to pull up the first connection point to turn off the first switch element and the second switch element when the external power signal is powered on and reaches a specified external power detection threshold and the external power detection signal becomes a high level, when the high voltage signal is enabled to start climbing and is input into the pull-up unit and reaches above the specified detection threshold; and an inverter, the inverter is used to invert the signal of the second connection point.

[0010] Furthermore, when the high voltage signal rises above the detection threshold, the first connection point is pulled up by the pull-up unit so that the second transistor is turned off, and the second connection point is pulled down to a low level by the pull-down unit, thereby changing the high voltage detection signal to a high level.

[0011] Furthermore, when the high voltage signal is less than the detection threshold, the pull-up unit is turned off, the first connection point is pulled down by the pull-down unit, and the second connection point becomes the high level of the external power signal transmitted by the second transistor being turned on, thereby causing the high voltage detection signal to become a low level.

[0012] Further, when the high voltage detection signal is erroneously triggered to a high level in less than the specified time due to interference during the power-on process of the high voltage signal, the delay unit delays the specified time.

[0013] Furthermore, the prescribed time is the duration when the high voltage detection signal is erroneously triggered to a high level.

[0014] Furthermore, the prescribed time is set to 2ns to 4ns.

[0015] Furthermore, when the external power supply detection signal changes to a high level, the latch unit is enabled to start.

[0016] When receiving a high level signal of the delayed voltage detection signal from the delay unit, the final detection signal output by the latch unit becomes a high level, and the delayed voltage detection signal is latched.

[0017] According to another embodiment of the present invention, there is provided a power-on detection method, comprising: a power detection step, in which an external power signal is input from an external power supply, a high voltage signal which is higher than the voltage of the external power signal is input from an internal power supply of a chip, the high voltage signal is detected to obtain a high voltage detection signal which is the same as the voltage of the external power signal; a delay step, in which the input high voltage detection signal is delayed for a specified time to obtain a delayed voltage detection signal; and a latching step, in which an external power detection signal is input, and the delayed voltage detection signal obtained in the delay step is input, the delayed voltage detection signal is latched and a final detection signal is output.

[0018] Further, when the external power signal is powered on and reaches a specified external power detection threshold, the external power detection signal becomes a high level, and the first connection point is pulled down by the pull-down unit to turn on the first transistor and the second transistor, so that the external power signal is output from the second connection point connected to the drain of the second transistor by the pull-down unit via the second transistor. When the external power signal is powered on and reaches a specified external power detection threshold, the external power detection signal becomes a high level, when the high voltage signal is enabled to start climbing and is input into the pull-up unit and reaches the specified detection threshold, the first connection point is pulled up by the pull-up unit to turn off the first transistor and the second transistor, and the signal of the second connection point is inverted by the inverter.

[0019] Furthermore, when the high voltage signal rises above the detection threshold, the first connection point is pulled up by the pull-up unit so that the second transistor is turned off, and the second connection point is pulled down to a low level by the pull-down unit, thereby changing the high voltage detection signal to a high level.

[0020] Furthermore, when the high voltage signal is less than the detection threshold, the pull-up unit is turned off, the first connection point is pulled down by the pull-down unit, and the second connection point becomes the high level of the external power signal transmitted by the second transistor being turned on, thereby causing the high voltage detection signal to become a low level.

[0021] Furthermore, when the high voltage detection signal is erroneously triggered to a high level in less than the specified time due to interference during the power-on process of the high voltage signal, the specified time is delayed.

[0022] Furthermore, the prescribed time is the duration when the high voltage detection signal is triggered to a high level by mistake. Furthermore, the prescribed time is set to 2ns to 4ns.

[0023] Further, when the external power supply detection signal changes to a high level, the final detection signal changes to a high level when a high level signal of the delayed voltage detection signal is received, and the delayed voltage detection signal is latched.

[0024] Effects of the Invention

[0025] According to the present invention, a power-on detection circuit and a power-on detection method can be provided, which can filter the glitches of the input signal under certain unexpected circumstances, and keep the output state unchanged when it is detected that the internal power supply signal reaches a specified value and tends to a stable state, thereby preventing the final power supply detection signal from temporarily and unexpectedly becoming low. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention may be better understood by describing exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0027] Explanation of reference numerals: 100 power-on detection circuit, 1 power supply detection unit, 2 delay unit, 3 latch unit, 4 external power supply detection unit, Q1 first transistor, Q2 second transistor, Q3 third transistor, Q4 fourth transistor, Q5 fifth transistor, Q6 sixth transistor, 11 pull-up unit, 12 pull-down unit, 13, 21, 22, 23, 31 inverter, C1, C2 capacitor, RS1 first NOR gate, RS2 second NOR gate, VDDi external power supply signal, VSi ground, High_power high voltage signal, High_power_detect high voltage detection signal, Delay_power_detect delayed voltage detection signal, External_power_detect external power supply detection signal, Final detect final detection signal, External_power_detect_point external power supply detection threshold, High_power_detect_point detection threshold, P1 first connection point, P2 second connection point, P3 third connection point, P4 fourth connection point.

[0028] Figure 1 It is a structural block diagram of the power-on detection circuit involved in the present invention.

[0029] Figure 2 It is a structural diagram of a power supply detection unit in a power-on detection circuit involved in the present invention.

[0030] Figure 3 It is a structural diagram of a delay unit in a power-on detection circuit involved in the present invention.

[0031] Figure 4 It is a structural diagram of a latch unit in a power-on detection circuit according to the present invention.

[0032] Figure 5 It is a waveform diagram of the power-on process of the relevant signals involved in the present invention.

[0033] Figure 6 It is a brief flow chart of the power-on detection method involved in the present invention. DETAILED DESCRIPTION

[0034] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0035] In the description of the present disclosure, it should be noted that, unless otherwise specified, the meaning of "multiple" is more than two; the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", etc. are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation of the present disclosure. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The directional words appearing in the following description are all directions shown in the figure, and do not limit the specific structure of the present disclosure. In the description of the present disclosure, it should also be noted that, unless otherwise clearly specified and limited, the terms, "connected", "connected", "relative", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0036] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] The power-on detection circuit 100 and method according to the present invention will be described below with reference to the accompanying drawings.

[0038] Figure 1 1 is a block diagram of the power-on detection circuit 100 involved in the present invention. Figure 1 As shown, the power-on detection circuit 100 includes a power detection unit 1 , a delay unit 2 and a latch unit 3 .

[0039] like Figure 1As shown, the power detection unit 1 inputs an external power signal VDDi from an external power supply, and inputs a high voltage signal (High_power) higher than the voltage of the external power signal VDDi from the internal power supply of the Dr am chip. The power detection unit 1 detects the input high voltage signal and obtains a high voltage detection signal (High_power_detect) having the same voltage as the external power signal VDDi. In addition, the delay unit 2 is connected to the power detection unit 1, delays the high voltage detection signal input from the power detection unit 1 for a predetermined time, and obtains a delayed voltage detection signal (delay_power_detect). The latch unit 3 inputs an external power detection signal (External_power_detect) from an external power supply, inputs a delayed voltage detection signal from the delay unit 2, latches the delayed voltage detection signal and outputs a final detection signal (Final detect). The above-mentioned final detection signal is the power-on detection signal of the power-on detection circuit 100. In addition, the above-mentioned external power detection signal is obtained by the external power detection unit 4 detecting the external power signal VDDi.

[0040] Through the above structure, the burrs that may be generated by being triggered by mistake can be filtered out, and the output state of the power-on detection circuit 100 can be locked, so as to avoid the power-on detection signal, that is, the output final detection signal, from being inverted in logic when the voltage of the internal power supply is unstable or drops. In addition, a stable and noise-proof output signal can be provided for other circuits using the power-on detection signal.

[0041] Please refer to the attached Figure 2-4 The circuit configurations of the power supply detection unit 1 , the delay unit 2 , and the latch unit 3 will be described separately. Figure 2 FIG. 1 is a structural diagram of the power supply detection unit 1 in the power-on detection circuit 100 according to the present invention. Figure 3 2 is a structural diagram of the delay unit 2 in the power-on detection circuit 100 according to the present invention. Figure 4 1 is a diagram showing the structure of the latch unit 3 in the power-on detection circuit 100 according to the present invention.

[0042] like Figure 2 As shown, the power detection unit 1 mainly includes a pull-up unit 11 , a first transistor Q1 , a second transistor Q2 , a pull-down unit 12 , and an inverter 13 .

[0043] The gate of the first transistor Q1 and the gate of the second transistor Q2 are connected to form a first connection point P1, and the first connection point P1 is connected to the pull-up control output terminal up_Con of the pull-up unit 11 described below. In addition, the source of each transistor is respectively input with an external power supply signal VDDi from an external power supply. Here, the first and second transistors Q1 and Q2 are set as P-type transistors, but are not limited thereto.

[0044] The pull-down unit 12 includes a pull-down input terminal down_VIN1 for inputting an external power signal VDDi, a ground terminal GND (VSi) for grounding, a pull-down control terminal down_Con connected to the drain of the first transistor Q1 via a third connection point P3, and a pull-down output terminal down_OUT connected to the drain of the second transistor Q2 via a second connection point P2. In addition, the first connection point P1 is connected to the third connection point P3. The pull-down unit 12 is used for pulling down the first connection point P1 through the pull-down control terminal down_Con when the external power signal VDDi is powered on and reaches the specified external power detection threshold (External_power_detect_point), and when the external power detection signal obtained by detecting the external power signal VDDi through the external power detection unit 4 becomes a high level, that is, making the voltage at the first connection point P1 lower so that the voltage input to the gate of each transistor is a low level, thereby turning on the first transistor Q1 and the second transistor Q2, and the external power signal VDDi is output from the second connection point P2 connected to the drain of the second transistor Q2 via the pull-down output terminal down_OUT of the pull-down unit 12 to the inverter 13 described below.

[0045] The pull-up unit 11 includes a first pull-up input terminal up_VIN1 for inputting an external power signal VDDi, a second pull-up input terminal up_VIN2 for inputting a high voltage signal (High_power) higher than the voltage of the external power signal VDDi from the internal power supply of the chip, and a pull-up output control terminal up_Con. The pull-up unit 11 is used to pull up the first connection point P1 through the pull-up output control terminal up_Con, that is, to make the voltage at the first connection point P1 higher, so that the voltage input to the gate of each transistor is high, so that the first transistor Q1 and the second transistor Q2 are turned off.

[0046] In addition, the power supply detection unit 1 further includes an inverter 13, which inverts the input signal output from the drain of the second transistor Q2. In other words, the inverter 13 inverts the signal at the second connection point P2.

[0047] Next, the working principle of the power detection unit 1 is described. Specifically, when the external power signal reaches a predetermined external power detection threshold (External_power_detect_point) and the external power detection signal (External_power_detect) becomes high level, the high voltage signal (High_power) is enabled to start rising.

[0048] During the rising process of the high voltage signal, it may be disturbed and produce glitches. The appearance of these glitches will cause the output high voltage detection signal to be triggered incorrectly. In addition, the circuit controlled by the high voltage detection signal is enabled, and the load of the high voltage power supply increases in a short time, causing the high voltage signal to drop below the detection threshold specified by the pull-up unit 11. The pull-up function of the pull-up unit 11 is turned off, and the potential of the first connection point P1 is pulled down by the pull-down unit 12 and becomes a low level. The second connection point P2 becomes the high level of the external power supply signal VDDi transmitted by the conduction of the second transistor Q2, and is inverted by the inverter 13, and the high voltage detection signal finally output becomes a low level.

[0049] After the circuit stabilizes for a short period of time, the current consumption of the high voltage power supply of the circuit controlled by the high voltage detection signal gradually decreases and stabilizes. When the high voltage signal resumes its normal climbing state and reaches above the detection threshold specified by the pull-up unit 11, the potential of the first connection point P1 is pulled up to a high level again by the pull-up unit 11, so that the second transistor is cut off, and the potential of the second connection point P2 is pulled down to a low level by the pull-down unit 12, and is inverted by the inverter 13, and the high voltage detection signal finally output becomes a high level.

[0050] like Figure 3 As shown, the delay unit 2 includes: a third transistor Q3 to a sixth transistor Q6, capacitors C1, C2, and inverters 21 to 23. Assume that the third transistor Q3 and the fourth transistor Q4 are P-type transistors, and the fifth transistor Q5 and the sixth transistor Q6 are N-type transistors, but are not limited thereto. Specifically, the third transistor Q3 to the sixth transistor Q6 are connected in series in sequence, that is, the source of the third transistor Q3 inputs the external power signal VDDi from the external power supply, the source of the fourth transistor Q4 is connected to the drain of the third transistor Q3, the source of the fifth transistor Q5 is connected to the drain of the fourth transistor Q4, the source of the sixth transistor Q6 is connected to the drain of the fifth transistor Q5, and the drain of the sixth transistor Q6 is grounded. In addition, the gate of each transistor Q3 to Q6 is connected to an inverter 21, and the high voltage detection signal from the power detection unit 1 is input. The fourth connection point P4 where the drain of the fourth transistor Q4 is connected to the source of the fifth transistor Q5 is connected to two inverters 22 and 23 in sequence to output a delayed voltage detection signal (Delay_power_detect).

[0051] The delay unit 2 further includes capacitors C1 and C2 connected to the fourth connection point P4. One end of the capacitor C1 is connected to the external power signal, and the other end is connected to the fourth connection point P4. One end of the capacitor C2 is grounded, and the other end is connected to the fourth connection point P4. The capacitors C1 and C2 are used to filter unnecessary noise, etc.

[0052] The working principle of the delay unit 2 is explained. As mentioned above, during the rise of the high voltage signal, it may be interfered and generate glitches. The appearance of these glitches will cause the output high voltage detection signal to be triggered incorrectly in a very short time, that is, when the high voltage detection signal becomes a high level in a very short time due to interference during the power-on process of the high voltage signal, the delay unit 2 needs to perform a delay operation to prevent the high voltage detection signal from being triggered incorrectly. The time required for the delay, that is, the specified time, is generally the duration when the high voltage detection signal is mistakenly triggered to a high level, and the specified time can generally be set to 2ns to 4ns. In addition, the above-mentioned extremely short time generally refers to less than or equal to this specified time. This can solve the fluctuations caused by "small faults" during the power supply establishment process.

[0053] like Figure 4 As shown, the latch unit 3 includes two NOR gates RS1 and RS2 whose input and output terminals are cross-coupled with each other. Specifically, it is assumed that the input terminal RS1_VIN1 of the NOR gate RS1 inputs the delayed voltage detection signal from the delay unit 2, and the other input terminal RS1_VIN2 of the NOR gate RS1 is connected to the output terminal RS2_VOUT of another NOR gate RS2. In addition, it is assumed that the input terminal RS2_VIN1 of the NOR gate RS2 is connected to the output terminal RS1_VOUT of the NOR gate RS1, and the other input terminal RS2_VIN2 of the NOR gate RS2 inputs the external power supply detection signal from the outside, and the output terminal of the NOR gate RS2 is also connected to the inverter 31, thereby outputting the final detection signal (Final detect).

[0054] When the external power supply detection signal becomes high level, the latch unit 3 is enabled and started. And when receiving the high level signal of the delayed voltage detection signal from the delay unit 2, the output of the latch unit 3, i.e., the final detection signal, becomes high level, thereby locking the state of the delayed voltage detection signal. Thereafter, no matter what changes occur in the input of the latch unit 3, the output of the latch unit 3 will not change.

[0055] In addition, the external power detection signal input to the latch unit 3 is a signal obtained by detecting the external power signal VDDi by the external power detection unit 4. Figure 1 and Figure 4 As shown, the input terminal RS2_VIN2 of the NOR gate RS2 of the latch section 3 is connected to the external power supply detection section 4 .

[0056] Next, refer to Figure 5 , the power-on process of related signals is explained. Figure 5 : is a waveform diagram of the power-on process of the relevant signals involved in the present invention. Figure 5 As shown, from top to bottom, the waveform diagrams of the external power signal (VDDi), the high voltage signal (High_power), the high voltage detection signal (High_power_dete ct), the external power detection signal (External_power_detect), the delayed voltage detection signal (Delay_power_detect), and the final detection signal (Final detect) are shown. In addition, Figure 5 The upper horizontal dotted line in the middle represents the external power detection threshold (External_power_detect_point), and the lower horizontal dotted line represents the detection threshold (High_power_detect_point).

[0057] In addition, t1 to t4 represent time respectively. At t1, the external power signal is powered on and reaches the external power detection threshold, the external power detection signal becomes a high level, and the high voltage signal is enabled to start climbing.

[0058] At t2, the high voltage signal is disturbed during the climbing process and generates glitches. The appearance of these glitches causes the high voltage detection signal output by the power detection unit 1 to be triggered incorrectly in a very short time. Figure 5 As shown, the high voltage signal generates a burr at t2, which causes the high voltage detection signal to be triggered by mistake and become a high level, but the erroneous fluctuation is generally very short, about 2ns to 4ns. At this time, by setting the delay unit 2, the erroneous fluctuation can be filtered out.

[0059] At t3, when the high voltage signal climbs to the detection threshold, the delay signal becomes a high level, and the latch unit 3 receives the high level signal sent from the delay unit 2, so that the output of the latch unit 3 becomes a high level to lock the current state of the high voltage detection signal, that is, the high level state. When the high voltage signal climbs above the detection threshold, the relevant circuit enabled by the high voltage detection signal starts to work, and the load on the high voltage power supply increases in a short time, so that the high voltage signal drops below the detection threshold. At this time, since the high voltage signal is less than the detection threshold, the high voltage detection signal changes from a high level to a low level, and the delayed voltage detection signal of the delay unit 2 also changes from a high level to a low level. However, since the high level state of the high voltage detection signal is locked by the latch unit 3, the final detection signal to be output later will not change.

[0060] At t4, the power load is reduced, and the high voltage signal begins to gradually return to the normal climbing state. At this time, the high voltage signal has reached the detection threshold, so that the high voltage detection signal changes from a low level to a high level, and the delayed voltage detection signal also changes from a low level to a high level. After receiving the above-mentioned delayed voltage detection signal, the latch unit 3 outputs the final detection signal.

[0061] As described above, the structure of the present invention can filter out glitches that may be triggered by errors, and also lock the output state, thereby preventing the signal logic of the power-on detection circuit 100 from being reversed when the power supply is unstable or drops. The improved circuit can provide a stable and noise-proof output signal for other circuits that use the power-on detection signal.

[0062] In addition, compared with the detection circuit with single power input, the detection circuit with dual power input has the following characteristics: when the detected power supply voltage is higher than the system voltage, the output is the system voltage value, and the high voltage signal reaches the detection threshold, the output high voltage detection signal will become high level, and when the high voltage signal is less than the detection threshold, the output high voltage detection signal will become low level, that is, as long as the high voltage signal reaches the detection threshold, the output high voltage detection signal will immediately become high level, and as long as the high voltage signal is less than the detection threshold, the output high voltage detection signal will immediately become low level. However, the output of the detection circuit with single power supply becomes high after the power supply voltage signal is higher than the detection threshold. If the power supply voltage signal is pulled down and lower than the detection threshold at this time, as long as it is not pulled down too much (for example, the amplitude does not exceed 100mV), the output can still maintain a high level and will not become a low level.

[0063] Next, the power-on detection method according to this embodiment is described.

[0064] First, in the power detection step S1, an external power signal is input from an external power supply, and a high voltage signal whose voltage is higher than that of the external power signal is input from the internal power supply of the chip. The input high voltage signal is detected to obtain a high voltage detection signal having the same voltage as that of the external power signal.

[0065] In the delay step S2, the input high voltage detection signal is delayed for a predetermined time to obtain a delayed voltage detection signal. In the latching step S3, an external power supply detection signal is input, and the delayed voltage detection signal obtained in the delay step S2 is input, the delayed voltage detection signal is latched, and a final detection signal is output.

[0066] In addition, in the above-mentioned power supply detection step S1, when the external power supply signal is powered on and reaches the specified external power supply detection threshold, the external power supply detection signal becomes a high level, and the first connection point P1 is pulled down by the pull-down unit 12 to turn on the first transistor Q1 and the second transistor Q2, so that the external power supply signal is output from the second connection point P2 connected to the drain of the second transistor Q2 via the pull-down unit 12 via the second transistor Q2.

[0067] When the external power signal is powered on and reaches the specified external power detection threshold, the external power detection signal becomes a high level. When the high voltage signal is enabled to start climbing and is input into the pull-up unit 11 and reaches above the specified detection threshold, the first connection point P1 is pulled up by the pull-up unit 11 to turn off the first transistor Q1 and the second transistor Q2.

[0068] In addition, the signal of the second connection point P2 is inverted by the inverter 13 .

[0069] In addition, when the high voltage signal rises to a value above the specified detection threshold, the first connection point P1 is pulled up by the pull-up unit 11, so that the second transistor Q2 is turned off, and the pull-down unit 12 pulls the second connection point P2 down to a low level, thereby changing the high voltage detection signal to a high level. When the high voltage signal is less than the detection threshold, the pull-up unit 11 is turned off, the second connection point P2 becomes a high level of the external power supply signal VDDi transmitted by the second transistor Q2 being turned on, and the first connection point P1 is pulled down by the pull-down unit 12, thereby changing the high voltage detection signal to a low level.

[0070] In addition, in the above-mentioned delay step 2, when the high voltage detection signal is mistakenly triggered to a high level within a specified time or less due to interference during the power-on process of the high voltage signal, the specified time is delayed. The specified time is the duration when the high voltage detection signal is mistakenly triggered to a high level. The specified time is set to 2ns to 4ns. By delaying the above-mentioned specified time, signal glitches with a width of 2-4ns can be filtered out.

[0071] Furthermore, in the latching step 3, when the external power supply detection signal becomes high level, upon receiving the high level signal of the delay voltage detection signal, the final detection signal becomes high level, and the delay voltage detection signal is latched.

[0072] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A power-on detection circuit, characterized in that: include: A power detection unit, wherein the power detection unit inputs an external power signal from an external power supply, inputs a high voltage signal higher than the voltage of the external power signal from an internal power supply of the chip, detects the high voltage signal, and obtains a high voltage detection signal having the same voltage as the external power signal; a delay unit that delays the high voltage detection signal input from the power supply detection unit for a predetermined time to obtain a delayed voltage detection signal; and A latch unit receives an external power supply detection signal from the external power supply, receives the delayed voltage detection signal from the delay unit, latches the delayed voltage detection signal, and outputs a final detection signal.

2. The power-on detection circuit according to claim 1, characterized in that: The power detection unit comprises: a first transistor; a second transistor, wherein a gate of the second transistor is connected to a gate of the first transistor to form a first connection point; a pull-down unit, the pull-down unit being used for, when the external power signal reaches a specified external power detection threshold value and the external power detection signal becomes a high level, pulling down the first connection point to turn on the first transistor and the second transistor, so that the external power signal is output from the second connection point connected to the drain of the second transistor via the second transistor; a pull-up unit, the pull-up unit being configured to pull up the first connection point to turn off the first transistor and the second transistor when the external power signal is powered on and reaches a specified external power detection threshold and the external power detection signal becomes a high level, and when the high voltage signal is enabled to start climbing and is input into the pull-up unit and reaches above a specified detection threshold; and An inverter is used to invert the signal at the second connection point.

3. The power-on detection circuit according to claim 2, characterized in that: When the high voltage signal rises to above the detection threshold, the first connection point is pulled up by the pull-up unit so that the second transistor is turned off. The pull-down unit pulls down the second connection point to a low level, thereby changing the high voltage detection signal to a high level.

4. The power-on detection circuit according to claim 2, characterized in that: When the high voltage signal is less than the detection threshold, the pull-up unit is turned off. The first connection point is pulled down by the pull-down unit, and the second connection point becomes a high level of the external power signal transmitted by turning on the second transistor, so that the high voltage detection signal becomes a low level.

5. The power-on detection circuit according to claim 1, characterized in that: When the high voltage detection signal is erroneously triggered to a high level within a period less than or equal to the prescribed time due to interference during the power-on process of the high voltage signal, the delay unit delays the prescribed time.

6. The power-on detection circuit according to claim 5, characterized in that: The prescribed time is a duration when the high voltage detection signal is erroneously triggered to a high level.

7. The power-on detection circuit according to claim 6, characterized in that: The prescribed time is set to 2ns to 4ns.

8. The power-on detection circuit according to claim 1, characterized in that: When the external power supply detection signal becomes high level, the latch unit is enabled to start. When receiving a high level signal of the delayed voltage detection signal from the delay unit, the final detection signal output by the latch unit becomes a high level, and the delayed voltage detection signal is latched.

9. A power-on detection method, characterized in that: include: A power detection step, wherein the power detection step inputs an external power signal from an external power supply, inputs a high voltage signal higher than the voltage of the external power signal from an internal power supply of the chip, detects the high voltage signal, and obtains a high voltage detection signal having the same voltage as the external power signal; a delay step, wherein the delay step delays the input high voltage detection signal for a predetermined time to obtain a delayed voltage detection signal; as well as A latching step, wherein the latching step inputs an external power supply detection signal and the delayed voltage detection signal obtained in the delaying step, latches the delayed voltage detection signal and outputs a final detection signal.

10. The power-on detection method according to claim 9, characterized in that: When the external power signal reaches a predetermined external power detection threshold value when it is powered on, the external power detection signal changes to a high level, and the first connection point is pulled down by the pull-down unit to turn on the first transistor and the second transistor, so that the external power signal is output from the second connection point connected to the drain of the second transistor by the pull-down unit through the second transistor. When the external power signal is powered on and reaches a specified external power detection threshold, the external power detection signal becomes a high level, and when the high voltage signal is enabled to start climbing and is input into the pull-up unit and reaches above a specified detection threshold, the first connection point is pulled up by the pull-up unit to turn off the first transistor and the second transistor. The signal at the second connection point is inverted by an inverter.

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