Coding control method, memory storage device and memory control circuit unit

Abstract

The invention provides a coding control method, a memory storage device and a memory control circuit unit. The coding control method comprises the following steps: obtaining write-in data; performing, by an encoding circuit, an encoding operation according to the write data to generate first parity data and second parity data, wherein the second parity data is not generated according to the first parity data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data into the rewritable nonvolatile memory module, the first parity data being used for executing a decoding operation with the write data, and the second parity data being used for executing a decoding operation with the write data. The second parity data is used to match the first parity data and the write data to perform a decoding operation.

Description

Technical Field

[0001] The present invention relates to a coding control technology, and in particular to a coding control method, a memory storage device and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] Generally speaking, in order to maintain the reliability of data, before storing the data in the rewritable non-volatile memory module, the data will be encoded to generate a corresponding error correction code. Then, the error correction code will be stored in the rewritable non-volatile memory module along with the corresponding data. Thereafter, when the data is read out from the rewritable non-volatile memory module, the corresponding error correction code can be used to correct errors that may exist in the data. However, the data length of conventional error correction codes cannot be adjusted dynamically, and lacks flexibility in use. In addition, in order to improve the error correction capability, the data will first be encoded to generate a corresponding error correction code, and the data and the error correction code will be encoded again to generate another error correction code. This encoding method will cause delay problems, thereby affecting the performance of the rewritable non-volatile memory module. Summary of the invention

[0004] The present invention provides a coding control method, a memory storage device and a memory control circuit unit, which can adopt a parallel coding method to generate parity data with different data lengths, thereby improving the error correction capability without causing delay problems.

[0005] An exemplary embodiment of the present invention provides an encoding control method for a rewritable non-volatile memory module, the encoding control method comprising: obtaining write data; performing an encoding operation by an encoding circuit according to the write data to generate first parity data and second parity data, wherein the second parity data is not generated according to the first parity data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, wherein the first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

[0006] In an exemplary embodiment of the present invention, the encoding operation includes a first encoding operation and a second encoding operation, and the step of the encoding circuit performing the encoding operation according to the write data to generate the first parity data and the second parity data includes: a first encoding circuit in the encoding circuit performs the first encoding operation according to the write data to generate the first parity data; and a second encoding circuit in the encoding circuit performs the second encoding operation according to the write data to generate the second parity data, wherein the first encoding operation and the second encoding operation are performed at the same time point.

[0007] In an exemplary embodiment of the present invention, the encoding control method also includes: a third encoding circuit in the encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data; and a second write instruction sequence is sent to instruct to store the third parity data in the rewritable non-volatile memory module, wherein the third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data, wherein the first encoding operation, the second encoding operation and the third encoding operation are executed at the same time point.

[0008] An exemplary embodiment of the present invention further provides an encoding control method for a rewritable non-volatile memory module, the encoding control method comprising: obtaining write data; performing a first encoding operation by an encoding circuit according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate first parity data; performing a second encoding operation by the encoding circuit according to the write data, a third sub-matrix in the parity check matrix, and a fourth sub-matrix in the parity check matrix to generate second parity data; and sending a first write instruction sequence to instruct to store the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module, wherein the first encoding operation and the second encoding operation are performed at the same time point.

[0009] In an exemplary embodiment of the present invention, the first encoding operation includes: the encoding circuit generates first transient data according to the write data and the first sub-matrix; and the encoding circuit generates the first parity data according to the first transient data and the second sub-matrix.

[0010] In an exemplary embodiment of the present invention, the second encoding operation includes: generating second transient data by the encoding circuit according to the write data and the third sub-matrix; and generating the second parity data by the encoding circuit according to the second transient data and the fourth sub-matrix.

[0011] In an exemplary embodiment of the present invention, the encoding control method also includes: the encoding circuit performs a third encoding operation according to the write data, the fifth sub-matrix in the parity check matrix, and the sixth sub-matrix in the parity check matrix to generate third parity data; and sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module, wherein the first encoding operation, the second encoding operation and the third encoding operation are executed at the same time point.

[0012] In an exemplary embodiment of the present invention, the third encoding operation includes: the encoding circuit generates third transient data according to the write data and the fifth sub-matrix; and the encoding circuit generates the third parity data according to the third transient data and the sixth sub-matrix.

[0013] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to obtain write data. The memory control circuit unit is further used to send a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module. The memory control circuit unit includes an encoding circuit. The encoding circuit is used to perform an encoding operation according to the write data to generate the first parity data and the second parity data, wherein the second parity data is not generated according to the first parity data. The first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

[0014] In an exemplary embodiment of the present invention, the encoding circuit includes a first encoding circuit and a second encoding circuit, and the encoding operation includes a first encoding operation and a second encoding operation. The first encoding circuit performs the first encoding operation according to the write data to generate the first parity data. The second encoding circuit performs the second encoding operation according to the write data to generate the second parity data. The first encoding operation and the second encoding operation are performed at the same time point.

[0015] In an exemplary embodiment of the present invention, the encoding circuit includes a third encoding circuit. The third encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data. The memory control circuit unit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data. The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

[0016] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to obtain write data. The memory control circuit unit is further used to send a first write instruction sequence to indicate that the write data, the first parity data and the second parity data are stored in the rewritable non-volatile memory module. The memory control circuit unit includes an encoding circuit. The encoding circuit is used to perform a first encoding operation according to the write data, a first sub-matrix in a parity check matrix and a second sub-matrix in the parity check matrix to generate the first parity data. The encoding circuit is further used to perform a second encoding operation according to the write data, a third sub-matrix in the parity check matrix and a fourth sub-matrix in the parity check matrix to generate the second parity data, wherein the first encoding operation and the second encoding operation are performed at the same time point.

[0017] In an exemplary embodiment of the present invention, the encoding circuit includes a first encoding circuit and a second encoding circuit.

[0018] In an exemplary embodiment of the present invention, in the first encoding operation, the first encoding circuit generates first transient data according to the write data and the first sub-matrix, and generates the first parity data according to the first transient data and the second sub-matrix.

[0019] In an exemplary embodiment of the present invention, in the second encoding operation, the second encoding circuit generates second transient data according to the write data and the third sub-matrix, and generates the second parity data according to the second transient data and the fourth sub-matrix.

[0020] In an exemplary embodiment of the present invention, the encoding circuit performs a third encoding operation according to the write data, the fifth sub-matrix in the parity check matrix, and the sixth sub-matrix in the parity check matrix to generate third parity data. The memory control circuit unit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The first encoding operation, the second encoding operation, and the third encoding operation are performed at the same time point.

[0021] In an exemplary embodiment of the present invention, the encoding circuit includes a third encoding circuit. In the third encoding operation, the third encoding circuit generates third transient data according to the write data and the fifth sub-matrix, and generates the third parity data according to the third transient data and the sixth sub-matrix.

[0022] The exemplary embodiment of the present invention further provides a memory control circuit unit, which is used to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, an encoding circuit and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface and the encoding circuit. The memory management circuit is used to obtain write data. The memory management circuit is further used to send a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module. The encoding circuit is used to perform an encoding operation according to the write data to generate the first parity data and the second parity data, wherein the second parity data is not generated according to the first parity data. The first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

[0023] In an exemplary embodiment of the present invention, the encoding circuit includes a third encoding circuit. The third encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data. The memory management circuit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data. The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

[0024] The exemplary embodiment of the present invention further provides a memory control circuit unit, which is used to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, an encoding circuit and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface and the encoding circuit. The memory management circuit is used to obtain write data. The memory management circuit is further used to send a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module. The encoding circuit is used to perform a first encoding operation according to the write data, a first sub-matrix in a parity check matrix and a second sub-matrix in the parity check matrix to generate the first parity data. The encoding circuit is further used to perform a second encoding operation according to the write data, a third sub-matrix in the parity check matrix and a fourth sub-matrix in the parity check matrix to generate the second parity data, wherein the first encoding operation and the second encoding operation are performed at the same time point.

[0025] In an exemplary embodiment of the present invention, the encoding circuit performs a third encoding operation according to the write data, the fifth sub-matrix in the parity check matrix, and the sixth sub-matrix in the parity check matrix to generate third parity data. The memory management circuit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The first encoding operation, the second encoding operation, and the third encoding operation are performed at the same time point.

[0026] Based on the above, in the encoding control method, memory storage device and memory control circuit unit of the present invention, after obtaining the write data, the encoding circuit can generate the first parity data and the second parity data at the same time point, wherein, according to different operation conditions, the first parity data can be decoded alone or in combination with the second parity data and the write data. In this way, the error correction capability can be improved without causing encoding delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0029] Figure 3is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0030] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0031] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0033] Figure 7 is a schematic diagram of a decoding process according to an exemplary embodiment of the present invention;

[0034] Figure 8 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;

[0035] Fig. 9 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;

[0036] Fig.10 is a flow chart of an encoding control method according to an exemplary embodiment of the present invention;

[0037] Fig.11 is a flow chart of a coding control method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0039] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0040] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0041] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0042] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0043] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless manner.

[0044] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0045] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0046] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0047] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0048] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0049] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0050] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0051] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0052] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0053] In an exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasure unit contains the minimum number of storage cells that are erased together. For example, the physical erasure unit is a physical block.

[0054] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0055] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0057] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0059] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify commands and data of the host system 11. For example, the commands and data of the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0060] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0061] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0062] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correction code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correction code and / or error checking code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correction code and / or error checking code.

[0063] In an exemplary embodiment, the error checking and correction circuit 54 may support low-density parity check (LDPC) codes. For example, the error checking and correction circuit 54 may use low-density parity check codes for encoding and decoding. In an exemplary embodiment, the error checking and correction circuit 54 may also use other types of encoding / decoding algorithms, such as BCH or Reed-Solomon (RS) codes, etc., which are not limited by the present invention.

[0064] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0065] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0066] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0067] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

[0068] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0069] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0070] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0071] The memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0072] In an exemplary embodiment, the ECC circuit 54 may include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 is used to encode data. The decoding circuit 542 is used to decode data. In an exemplary embodiment, the encoding circuit 541 and the decoding circuit 542 may also be combined into a single encoding / decoding circuit.

[0073] In an exemplary embodiment, before the memory management circuit 51 writes data into the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data, and the data and parity data are then stored in the rewritable non-volatile memory module 43, wherein the data (also referred to as write data) that the memory management circuit 51 wants to write into the rewritable non-volatile memory module 43 may be, for example, data (user data) written by the host system 11, or management data of the memory management circuit 51. When the memory management circuit 51 wants to read a physical unit, the memory management circuit 51 may read the data in the physical unit and its corresponding parity data. The decoding circuit 542 in the error checking and correction circuit 54 may perform a decoding operation based on the parity data and the data read from the physical unit to detect and correct errors in the data.

[0074] In an exemplary embodiment, the memory management circuit 51 obtains the write data. The encoding circuit 541 may perform an encoding operation according to the write data to generate first parity data and second parity data. The encoding operation may include but is not limited to a first encoding operation and a second encoding operation. In an exemplary embodiment, the encoding circuit 541 may, for example, be provided with a first encoding circuit (not shown) and a second encoding circuit (not shown) that operate independently of each other. At a same time point, the first encoding circuit in the encoding circuit 541 may perform the first encoding operation according to the write data to generate first parity data, and the second encoding circuit in the encoding circuit 541 may perform the second encoding operation according to the write data to generate second parity data. That is, the first encoding operation and the second encoding operation are performed at the same time point to reduce the delay caused by the encoding operation. The second parity data is not generated according to the first parity data. In an exemplary embodiment, the first parity data is different from the second parity data. In addition, the first parity data may be decoded alone or in combination with the second parity data and the write data. The second parity data needs to be used together with the first parity data and the written data to perform a decoding operation, that is, the second parity data cannot be used alone to perform a decoding operation with the written data.

[0075] After encoding the write data, the memory management circuit 51 may send a write instruction sequence (also referred to as a first write instruction sequence) to the rewritable non-volatile memory module 43. The first write instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to store the write data, the first parity data, and the second parity data. In an exemplary embodiment, the memory management circuit 51 may store the write data and the first parity data in the same physical unit, and store the second parity data in another physical unit. For example, the memory management circuit 51 may first store the write data and the first parity data in the same physical unit, and temporarily store the second parity data in the buffer memory 55, and then store the second parity data in another physical unit in the rewritable non-volatile memory module 43 in a subsequent operation.

[0076] Thereafter, when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read the first parity data (and the second parity data) from the rewritable non-volatile memory module 43. The decoding circuit 542 may perform a decoding operation based on the first parity data (and the second parity data) and the write data read from the rewritable non-volatile memory module 43 to detect and correct errors in the write data.

[0077] It should be noted that when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may only read the first parity data first, and when a higher error correction capability is required (i.e., the first parity data decoding fails), read the second parity data to increase the decoding speed.

[0078] In an exemplary embodiment, the memory management circuit 51 may only read the write data and the first parity data from the rewritable non-volatile memory module 43 first. The decoding circuit 542 may perform a decoding operation based on the first parity data and the write data. If the decoding fails, the memory management circuit 51 may read the second parity data from the rewritable non-volatile memory module 43 again, so that the decoding circuit 542 may perform a decoding operation based on the first parity data and the second parity data and the write data. It should be noted that parity data with a longer data length has a higher error correction capability. The decoding circuit 542 may combine the first parity data and the second parity data into parity data with a longer data length, and perform a decoding operation based on the parity data with a longer data length and the write data to improve the decoding success rate.

[0079] It is worth mentioning that when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 can read the first parity data and the second parity data at the same time, so that the decoding circuit 542 can perform a decoding operation according to the first parity data and the second parity data to improve the decoding success rate.

[0080] In an exemplary embodiment, the memory management circuit 51 may read the write data, the first parity data, and the second parity data from the rewritable non-volatile memory module 43. The decoding circuit 542 may combine the first parity data and the second parity data into parity data with a longer data length (i.e., parity data with a higher error correction capability), and perform a decoding operation based on the parity data with a longer data length and the write data to improve the decoding success rate.

[0081] In an exemplary embodiment, the encoding operation may further include a third encoding operation. In addition to the above-mentioned first encoding circuit and the second encoding circuit, the encoding circuit 541 may further include a third encoding circuit (not shown). During the above-mentioned first encoding operation and the second encoding operation, the third encoding circuit in the encoding circuit 541 may perform the third encoding operation according to the write data to generate the third parity data. That is, the first encoding operation, the second encoding operation and the third encoding operation may be performed at the same time point to reduce the delay caused by the encoding operation. The second parity data is not generated according to the first parity data. The third parity data is not generated according to the first parity data and the second parity data. In an exemplary embodiment, the third parity data is different from the first parity data and the second parity data. In addition, the first parity data may be decoded alone, in combination with the second parity data, or in combination with the second parity data and the third parity data and the write data. The second parity data needs to be decoded in combination with the first parity data and the write data. The third parity data needs to be decoded in combination with the first parity data and the second parity data and the write data. In other words, the second parity data and the third parity data cannot be decoded separately from the write data.

[0082] After encoding the write data, the memory management circuit 51 may send a write instruction sequence (also referred to as a second write instruction sequence) to the rewritable non-volatile memory module 43. The second write instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to store the write data, the first parity data, the second parity data, and the third parity data. For example, the memory management circuit 51 may first store the write data and the first parity data in the same physical unit, and store the second parity data and the third parity data in another physical unit in the rewritable non-volatile memory module 43. For example, the second parity data and the third parity data may be stored in different physical units in the rewritable non-volatile memory module 43.

[0083] Thereafter, when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read the first parity data (and the second parity data and the third parity data) from the rewritable non-volatile memory module 43. The decoding circuit 542 may perform a decoding operation based on the first parity data (and the second parity data and the third parity data) and the write data to detect and correct errors in the write data.

[0084] Figure 7 is a schematic diagram of a decoding process according to an exemplary embodiment of the present invention. Figure 7 , assuming that the first parity data P(1), the second parity data P(2) and the third parity data P(3) are all generated by encoding the write data 701 stored in the rewritable non-volatile memory module 43. The relevant operation details have been described above and will not be repeated here.

[0085] The memory management circuit 51 can read the write data 701 and the first parity data P(1) from the same physical unit in the rewritable non-volatile memory module 43. The decoding circuit 542 can perform a decoding operation using the first parity data P(1) and the write data 701. If the write data 701 and the first parity data P(1) can be successfully decoded (for example, all errors in the read write data 701 are corrected), the decoding of the write data 701 can be terminated.

[0086] On the other hand, if the write data 701 and the first parity data P(1) cannot be successfully decoded (for example, all errors in the read write data 701 cannot be corrected), the memory management circuit 51 may read the second parity data P(2) from another physical unit in the rewritable non-volatile memory module 43. The decoding circuit 542 may perform a decoding operation using the first parity data P(1), the second parity data P(2) and the write data 701. For example, the decoding circuit 542 may combine the first parity data P(1) and the second parity data P(2) into parity data P(12) having a longer data length and a higher error correction capability, and perform a decoding operation based on the parity data P(12) and the write data 701 to improve the decoding success rate.

[0087] However, if the write data 701 and the parity data P(12) still cannot be decoded successfully, the memory management circuit 51 may further read the third parity data P(3) from another physical unit in the rewritable non-volatile memory module 43. The decoding circuit 542 may use the first parity data P(1), the second parity data P(2), the third parity data P(3) and the write data 701 to perform a decoding operation. For example, the decoding circuit 542 may combine the first parity data P(1), the second parity data P(2) and the third parity data P(3) into parity data P(13) with a longer data length and a higher error correction capability, and perform a decoding operation based on the parity data P(13) and the write data 701 to improve the decoding success rate. In an exemplary embodiment, by gradually increasing the data length of the parity data during the decoding process, the decoding circuit 542 may gradually improve the error correction capability of the write data 701.

[0088] In an exemplary embodiment, the encoding circuit 541 may perform multiple encoding operations on the same write data (e.g., the write data 701) to generate more parity data P(4)-P(N). Accordingly, when the write data 701 is subsequently decoded, in response to a decoding failure, more parity data P(4)-P(N) may be used to extend the parity data P(1) to effectively improve the decoding success rate of the write data 701.

[0089] In low-density parity-check codes, a check matrix (also called a parity-check matrix) is used to define valid codewords. The parity-check matrix is ​​denoted as matrix M below, and a codeword is denoted as V. According to the following equation (1), if the product of the parity-check matrix M and the codeword V is a zero vector, it means that the codeword V is a valid codeword. The operator × represents the matrix multiplication modulo 2 (mod2). In other words, the null space of the matrix M contains all valid codewords. However, the present invention does not limit the content of the codeword V. For example, the codeword V may also include an error correction code or an error checking code generated by any algorithm.

[0090] V×M T =0 (1)

[0091] The codeword V may include information bits and parity bits, that is, the codeword V may be expressed as [UP]. The vector U is composed of information bits. The vector P is composed of parity bits. The vector U is also called write data (or data to be encoded). The vector P is also called parity data.

[0092] In a codeword, parity bits (i.e., parity data) are used to protect information bits (i.e., written data) and can be considered as error correction codes or error checking codes generated corresponding to information bits. In addition, protecting information bits, for example, means maintaining the correctness of information bits. For example, when reading information bits from the rewritable non-volatile memory module 43, the parity bits corresponding to the information bits can be used to correct errors that may exist in the information bits.

[0093] When decoding a codeword V, a parity check operation is first performed on the codeword V, for example, by multiplying the matrix M and the codeword V to generate a vector (hereinafter labeled as S, as shown in the following equation (2)). Each element in the vector S is also called a syndrome. The vector S is also called syndrome data. If the vector S is a zero vector (i.e., each element in the vector S is zero), the codeword V can be directly output. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it means that there is at least one error in the codeword V and the codeword V is not a valid codeword. If the codeword V is not a valid codeword, the error checking and correction circuit 54 can perform a decoding operation to attempt to correct the error in the codeword V.

[0094] V×M T =S (2)

[0095] In an exemplary embodiment, the memory management circuit 51 may obtain write data from the host system 11. At a same time point, the encoding circuit 541 may perform an encoding operation (also referred to as a first encoding operation) according to the write data and a plurality of sub-matrices in the matrix M (also referred to as a first sub-matrix and a second sub-matrix) to generate parity data (also referred to as first parity data), and perform another encoding operation (also referred to as a second encoding operation) according to the write data and a plurality of sub-matrices in the matrix M (also referred to as a third sub-matrix and a fourth sub-matrix) to generate parity data (also referred to as second parity data). That is, the first encoding operation and the second encoding operation are performed at the same time point. The first parity data is different from the second parity data. In addition, the first parity data may be decoded alone or in combination with the second parity data and the write data. The second parity data cannot be decoded alone with the write data.

[0096] After encoding the write data, the memory management circuit 51 may send a write command sequence (also referred to as a first write command sequence) to the rewritable non-volatile memory module 43. The first write command sequence may be used to instruct the rewritable non-volatile memory module 43 to store the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module 43. Thereafter, when reading the write data from the rewritable non-volatile memory module 43, the memory management circuit 51 may read the first parity data (and the second parity data) from the rewritable non-volatile memory module 43 at the same time. The decoding circuit 542 may perform a decoding operation based on the first parity data (and the second parity data) and the write data read from the rewritable non-volatile memory module 43 to detect and correct errors in the write data.

[0097] Figure 8 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Figure 8 In an exemplary embodiment, the structure of the parity check matrix M is as shown in matrix 801. Matrix 801 includes sub-matrix A, sub-matrix B, sub-matrix C, sub-matrix D, sub-matrix W and sub-matrix X. Sub-matrices W and X are zero matrices, and sub-matrices A to D are not zero matrices. Sub-matrix A can be an m×k matrix. Sub-matrix B can be an m×m matrix. Sub-matrix C can be an x×k matrix. Sub-matrix D can be an x×x matrix. Sub-matrix W can be an m×x matrix. Sub-matrix X can be an x×m matrix. k, m and x are all positive integers, k can be greater than m, and m can be greater than x. The arrangement of sub-matrices A to D and sub-matrices W and X in matrix 801 is as shown. Figure 8 As shown, but not limited to.

[0098] In an exemplary embodiment, the first parity data may be generated according to the following equation (3). In equation (3), P(1) represents the first parity data, U represents the write data to be encoded, and A and B represent sub-matrix A and sub-matrix B in matrix 801, respectively. Equation (3) may be further decomposed into the following equations (3.1) and (3.2). In equations (3.1) and (3.2), Q(1) represents the transient data (also referred to as the first transient data) used in the process of generating the first parity data.

[0099] P(1)=(B T ) -1 ×(A T ×U) (3)

[0100] Q(1)=A T ×U(3.1)

[0101] P(1)=(B T ) -1×Q(1)(3.2)

[0102] In an exemplary embodiment, the second parity data may be generated according to the following equation (4). In equation (4), P(2) represents the second parity data, U represents the write data to be encoded, and C and D represent the sub-matrix C and the sub-matrix D in the matrix 801, respectively. Equation (4) may be further decomposed into the following equations (4.1) and (4.2). In equations (4.1) and (4.2), Q(2) represents the transient data (also referred to as the second transient data) used in the process of generating the second parity data.

[0103] P(2)=(D T ) -1 ×(C T ×U) (4)

[0104] Q(2)=C T ×U(4.1)

[0105] P(2)=(D T ) -1 ×Q(2)(4.2)

[0106] In an exemplary embodiment, the encoding circuit 541 may perform an encoding operation (also referred to as a first encoding operation) according to the written data U and the sub-matrix A (also referred to as the first sub-matrix) and the sub-matrix B (also referred to as the second sub-matrix) to generate parity data P(1) (also referred to as the first parity data). In the first encoding operation, the encoding circuit 541 may perform a matrix operation corresponding to equation (3.1) according to the written data U and the sub-matrix A to generate transient data Q(1), and then perform a matrix operation corresponding to equation (3.2) according to the transient data Q(1) and the sub-matrix B (i.e., the inverse matrix of the sub-matrix B) to generate parity data P(1).

[0107] In an exemplary embodiment, the encoding circuit 541 may perform an encoding operation (also referred to as a second encoding operation) according to the written data U and the sub-matrix C (also referred to as the third sub-matrix) and the sub-matrix D (also referred to as the fourth sub-matrix) to generate parity data P(2) (also referred to as the second parity data). In the second encoding operation, the encoding circuit 541 may perform a matrix operation corresponding to equation (4.1) according to the written data U and the sub-matrix C to generate transient data Q(2), and then perform a matrix operation corresponding to equation (4.2) according to the transient data Q(2) and the sub-matrix D (i.e., the inverse matrix of the sub-matrix D) to generate parity data P(2).

[0108] It should be noted that the encoding circuit 541 may be, for example, a first encoding circuit (not shown) and a second encoding circuit (not shown) that operate independently of each other. At the same time point, the first encoding circuit may be used to perform the first encoding operation, and the second encoding circuit may be used to perform the second encoding operation. The encoding circuit 541 may perform the first encoding operation and the second encoding operation simultaneously to increase the encoding speed.

[0109] It is worth mentioning that in the above exemplary embodiment, the sub-matrix X in the matrix 801 is a zero matrix, and the encoding circuit 541 can simultaneously generate the parity data P(1) and the parity data P(2) (that is, the parity data P(2) is not generated based on the parity data P(1)).

[0110] After encoding the write data, the memory management circuit 51 may send a write command sequence (also referred to as a first write command sequence) to the rewritable non-volatile memory module 43 to store the write data U, the first parity data P(1) and the second parity data P(2) in the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may store the write data U and the first parity data P(1) in the same physical unit in the rewritable non-volatile memory module 43, and store the second parity data P(2) in another physical unit in the rewritable non-volatile memory module 43.

[0111] Thereafter, when reading the write data U from a physical unit in the rewritable non-volatile memory module 43, the memory management circuit 51 may read the first parity data P(1) at the same time, and in response to a decoding failure, read the second parity data P(2) from another physical unit in the rewritable non-volatile memory module 43. Accordingly, the decoding circuit 542 may perform a decoding operation based on the first parity data P(1), the second parity data P(2) and the write data U to detect and correct errors in the write data. For details on the implementation of the decoding operation, please refer to Figure 7 The exemplary embodiments are not repeated here.

[0112] Fig. 9 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Fig. 9 In an exemplary embodiment, the structure of the parity check matrix M is shown in matrix 901. Matrix 901 includes Figure 8Matrix 801, submatrix E, submatrix F, submatrix Y and submatrix Z. Submatrix Y and submatrix Z are zero matrices, and submatrix E and submatrix F are not zero matrices. Submatrix E can be a y×k matrix. Submatrix F can be a y×y matrix. Submatrix Y can be a (m+x)×y matrix. Submatrix Z can be a y×(m+x) matrix. k, m, x and y are all positive integers, k can be greater than m, and m can be greater than x and y. Matrix 801 and submatrices E~F and Y~Z are arranged in matrix 901 as follows Fig. 9 In one exemplary embodiment, matrix 901 can be obtained by expanding matrix 801 (adding sub-matrices E-F and Y-Z).

[0113] In an exemplary embodiment, the third parity data may be generated according to the following equation (5). In equation (5), E and F represent submatrix E and submatrix F in matrix 901, respectively, and P(3) represents the third parity data. Equation (5) may be further decomposed into the following equations (5.1) and (5.2). In equations (5.1) and (5.2), Q(3) represents the transient data (also referred to as the third transient data) used in the process of generating the third parity data.

[0114] P(3)=(F T ) -1 ×(E T ×U) (5)

[0115] Q(3)=E T ×U(5.1)

[0116] P(3)=(F T ) -1 ×Q(3)(5.2)

[0117] In an exemplary embodiment, the encoding circuit 541 may perform an encoding operation (also referred to as a third encoding operation) according to the written data U and the sub-matrix E (also referred to as the fifth sub-matrix) and the sub-matrix F (also referred to as the sixth sub-matrix) to generate parity data P(3) (also referred to as the third parity data). In the third encoding operation, the encoding circuit 541 may perform a matrix operation corresponding to equation (5.1) according to the written data U and the sub-matrix E to generate transient data Q(3), and then perform a matrix operation corresponding to equation (5.2) according to the transient data Q(3) and the sub-matrix F (i.e., the inverse matrix of the sub-matrix F) to generate parity data P(3).

[0118] It should be noted that the encoding circuit 541 may be, for example, a first encoding circuit, a second encoding circuit and / or a third encoding circuit (not shown) that operate independently of each other. In an exemplary embodiment, the sub-matrix X is a zero matrix, and the parity data P(2) is not generated based on the parity data P(1). At the same time point, the first encoding circuit, the second encoding circuit and the third encoding circuit in the encoding circuit 541 may respectively perform the first encoding operation, the second encoding operation and the third encoding operation to generate the parity data P(1) to P(3), which can effectively improve the encoding speed.

[0119] After encoding the write data, the memory management circuit 51 may send a write command sequence to the rewritable non-volatile memory module 43 to store the write data U, the first parity data P(1), the second parity data P(2), and the third parity data P(3) in the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may store the write data U and the first parity data P(1) in the same physical unit in the rewritable non-volatile memory module 43, and store the second parity data P(2) and the third parity data P(3) in another physical unit in the rewritable non-volatile memory module 43. For example, the second parity data P(2) and the third parity data P(3) may be stored in different physical units in the rewritable non-volatile memory module 43.

[0120] Thereafter, when reading the write data U from a physical unit in the rewritable non-volatile memory module 43, the memory management circuit 51 may read the first parity data P(1) at the same time, and in response to a decoding failure, read the second parity data P(2) from the rewritable non-volatile memory module 43, and in response to a further decoding failure, read the third parity data P(3) from the rewritable non-volatile memory module 43. For details on the implementation of the decoding operation, please refer to Figure 7 The exemplary embodiments are not repeated here.

[0121] It is worth mentioning that the first parity data P(1) can be used alone, in combination with the second parity data P(2), or in combination with the second parity data P(2) and the third parity data P(3) to perform a decoding operation with the write data U. The second parity data P(2) needs to be used in combination with the first parity data P(1) and the write data U to perform a decoding operation. The third parity data P(3) needs to be used in combination with the first parity data P(1) and the second parity data P(2) and the write data U to perform a decoding operation. By expanding the matrix M (for example, by adding more sub-matrices to the matrix M), the encoding circuit 541 can encode the same write data according to the expanded matrix M to generate more parity data. Accordingly, when the write data is subsequently decoded, in response to a decoding failure, more parity data can be used in sequence to improve the decoding success rate of the write data.

[0122] Fig.10 is a flow chart of a coding control method according to an exemplary embodiment of the present invention. Fig.10 In step S1001, write data is obtained. In step S1002, the encoding circuit performs an encoding operation according to the write data to generate first parity data and second parity data, wherein the second parity data is not generated according to the first parity data. In step S1003, a first write instruction sequence is sent to instruct to store the write data, the first parity data and the second parity data in a rewritable non-volatile memory module, wherein the first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform a decoding operation with the first parity data and the write data.

[0123] Fig.11 is a flow chart of a coding control method according to an exemplary embodiment of the present invention. Fig.11 , in step S1101, the write data is obtained. In step S1102, the encoding circuit performs a first encoding operation according to the write data, the first sub-matrix in the parity check matrix, and the second sub-matrix in the parity check matrix to generate the first parity data. In step S1103, the encoding circuit performs a second encoding operation according to the write data, the third sub-matrix in the parity check matrix, and the fourth sub-matrix in the parity check matrix to generate the second parity data. In step S1104, a first write instruction sequence is sent to indicate that the write data, the first parity data, and the second parity data are stored in the rewritable non-volatile memory module, wherein the first encoding operation and the second encoding operation are performed at the same time point.

[0124] However, Fig.10 and Fig.11 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 and Fig.11 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10 and Fig.11 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0125] In summary, the exemplary embodiment of the present invention provides encoding the same written data at the same time point to generate corresponding multiple parity data. Thereafter, the multiple parity data can be used separately or in combination according to the decoding status, and used to perform a decoding operation with the written data. In this way, the decoding efficiency of the written data can be effectively improved, and the error correction capability can be improved.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A coding control method, characterized in that: For a rewritable non-volatile memory module, the encoding control method includes: Get write data; performing an encoding operation by an encoding circuit according to the write data to generate first parity data and second parity data, wherein the second parity data is not generated according to the first parity data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

2. The encoding control method according to claim 1, wherein the encoding operation comprises a first encoding operation and a second encoding operation, wherein the step of performing the encoding operation by the encoding circuit according to the write data to generate the first parity data and the second parity data comprises: The first encoding circuit in the encoding circuit performs the first encoding operation according to the write data to generate the first parity data; as well as performing the second encoding operation according to the write data by a second encoding circuit in the encoding circuit to generate the second parity data, The first encoding operation and the second encoding operation are performed at the same time point.

3. The encoding control method according to claim 2, further comprising: A third encoding circuit in the encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data; as well as sending a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module, wherein the third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data, The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

4. A coding control method, characterized in that: For a rewritable non-volatile memory module, the encoding control method includes: Get write data; The encoding circuit performs a first encoding operation according to the write data, a first sub-matrix in the parity check matrix, and a second sub-matrix in the parity check matrix to generate first parity data; The encoding circuit performs a second encoding operation according to the write data, a third sub-matrix in the parity check matrix, and a fourth sub-matrix in the parity check matrix to generate second parity data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The first encoding operation and the second encoding operation are performed at the same time point.

5. The encoding control method according to claim 4, wherein the first encoding operation comprises: The encoding circuit generates first transient data according to the written data and the first sub-matrix; as well as The encoding circuit generates the first parity data according to the first transient data and the second sub-matrix.

6. The encoding control method according to claim 4, wherein the second encoding operation comprises: The encoding circuit generates second transient data according to the written data and the third sub-matrix; as well as The encoding circuit generates the second parity data according to the second transient data and the fourth sub-matrix.

7. The encoding control method according to claim 4, further comprising: The encoding circuit performs a third encoding operation according to the write data, a fifth sub-matrix in the parity check matrix, and a sixth sub-matrix in the parity check matrix to generate third parity data; as well as sending a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module, The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

8. The encoding control method according to claim 7, wherein the third encoding operation comprises: The encoding circuit generates third transient data according to the written data and the fifth sub-matrix; as well as The encoding circuit generates the third parity data according to the third transient data and the sixth sub-matrix.

9. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, Wherein, the memory control circuit unit is used to: Get write data; sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The memory control circuit unit includes an encoding circuit, and the encoding circuit is used to: performing an encoding operation according to the write data to generate the first parity data and the second parity data, wherein the second parity data is not generated according to the first parity data, The first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

10. The memory storage device according to claim 9, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, and the encoding operation comprises a first encoding operation and a second encoding operation, The first encoding circuit performs the first encoding operation according to the write data to generate the first parity data, The second encoding circuit performs the second encoding operation according to the write data to generate the second parity data, The first encoding operation and the second encoding operation are performed at the same time point.

11. The memory storage device of claim 10, wherein the encoding circuit comprises a third encoding circuit, The third encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data, The memory control circuit unit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. wherein the third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data, The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

12. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, Wherein, the memory control circuit unit is used to: Obtaining write data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The memory control circuit unit includes an encoding circuit, and the encoding circuit is used to: performing a first encoding operation according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate the first parity data; as well as A second encoding operation is performed according to the write data, a third sub-matrix in the parity check matrix, and a fourth sub-matrix in the parity check matrix to generate the second parity data, wherein the first encoding operation and the second encoding operation are performed at the same time point. 13 . The memory storage device of claim 12 , wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit.

14. The memory storage device of claim 13, wherein in the first encoding operation, the first encoding circuit generates first transient data according to the write data and the first sub-matrix, and generates the first parity data according to the first transient data and the second sub-matrix.

15. The memory storage device of claim 13, wherein in the second encoding operation, the second encoding circuit generates second transient data according to the write data and the third sub-matrix, and generates the second parity data according to the second transient data and the fourth sub-matrix.

16. The memory storage device of claim 12 , wherein the encoding circuit performs a third encoding operation according to the write data, a fifth sub-matrix in the parity check matrix, and a sixth sub-matrix in the parity check matrix to generate third parity data, The memory control circuit unit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

17. The memory storage device according to claim 16, wherein the encoding circuit comprises a third encoding circuit, and in the third encoding operation, the third encoding circuit generates third transient data according to the write data and the fifth sub-matrix, and generates the third parity data according to the third transient data and the sixth sub-matrix.

18. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit comprises: A host interface for connecting to a host system; A memory interface, used to connect to the rewritable non-volatile memory module; encoding circuit; and a memory management circuit connected to the host interface, the memory interface and the encoding circuit, Wherein, the memory management circuit is used to: Obtaining write data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The encoding circuit is used to: performing an encoding operation according to the write data to generate the first parity data and the second parity data, wherein the second parity data is not generated according to the first parity data, The first parity data is used to perform a decoding operation with the write data, and the second parity data is used to perform the decoding operation in combination with the first parity data and the write data.

19. The memory control circuit unit according to claim 18, wherein the encoding circuit includes a first encoding circuit and a second encoding circuit, and the encoding operation includes a first encoding operation and a second encoding operation, The first encoding circuit performs the first encoding operation according to the write data to generate the first parity data, The second encoding circuit performs the second encoding operation according to the write data to generate the second parity data, The first encoding operation and the second encoding operation are performed at the same time point.

20. The memory control circuit unit according to claim 19, wherein the encoding circuit comprises a third encoding circuit, The third encoding circuit performs a third encoding operation according to the write data to generate third parity data, wherein the third parity data is not generated according to the first parity data and the second parity data, The memory management circuit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. wherein the third parity data is used to perform the decoding operation in combination with the first parity data, the second parity data and the write data, The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

21. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit comprises: A host interface for connecting to a host system; A memory interface, used to connect to the rewritable non-volatile memory module; encoding circuit; and a memory management circuit connected to the host interface, the memory interface and the encoding circuit, Wherein, the memory management circuit is used to: Obtaining write data; and sending a first write instruction sequence to instruct to store the write data, the first parity data and the second parity data in the rewritable non-volatile memory module, The encoding circuit is used to: performing a first encoding operation according to the write data, a first sub-matrix in a parity check matrix, and a second sub-matrix in the parity check matrix to generate the first parity data; and A second encoding operation is performed according to the write data, a third sub-matrix in the parity check matrix, and a fourth sub-matrix in the parity check matrix to generate the second parity data, wherein the first encoding operation and the second encoding operation are performed at the same time point.

22. The memory control circuit unit according to claim 21, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit.

23. The memory control circuit unit according to claim 22, wherein in the first encoding operation, the first encoding circuit generates first transient data according to the write data and the first sub-matrix, and generates the first parity data according to the first transient data and the second sub-matrix.

24. The memory control circuit unit according to claim 22, wherein in the second encoding operation, the second encoding circuit generates second transient data according to the write data and the third sub-matrix, and generates the second parity data according to the second transient data and the fourth sub-matrix.

25. The memory control circuit unit according to claim 21, wherein the encoding circuit performs a third encoding operation according to the write data, a fifth sub-matrix in the parity check matrix, and a sixth sub-matrix in the parity check matrix to generate third parity data, The memory management circuit sends a second write instruction sequence to instruct to store the third parity data in the rewritable non-volatile memory module. The first encoding operation, the second encoding operation and the third encoding operation are performed at the same time point.

26. The memory control circuit unit according to claim 25, wherein the encoding circuit comprises a third encoding circuit, and in the third encoding operation, the third encoding circuit generates third transient data according to the write data and the fifth sub-matrix, and generates the third parity data according to the third transient data and the sixth sub-matrix.

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