Embedded multi-layer interconnection electronic packaging structure and preparation process thereof

Abstract

The invention discloses an embedded multilayer interconnection electronic packaging structure and a preparation technology thereof, and the technology comprises the steps: providing an insulating substrate, forming a miniature caulking groove at a preset position of the insulating substrate, placing an electronic assembly in the caulking groove, superposing a dielectric layer and a conductive layer on the insulating substrate and the embedded electronic assembly layer by layer through employing a deposition technology, a multi-layer interconnection network is constructed, a vertical interconnection channel is formed through a deep reactive ion etching technology, a thermal management structure is introduced, a graphene-based cooling fin is integrated in the multi-layer interconnection network, packaging is carried out, a protective coating covers the multi-layer interconnection network, a connecting bonding pad of a leading-out end is defined, and the embedded multi-layer interconnection electronic packaging structure is formed; a high-density and multi-layer interconnection network is constructed by embedding and mounting the electronic component in the substrate and utilizing a method of depositing the dielectric layer and the conductive layer, so that miniaturization and high integration of the electronic equipment are realized, the requirements of compact size and heat dissipation performance are considered, and a solution of high-density interconnection and efficient heat dissipation is provided.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an embedded multi-layer interconnected electronic packaging structure and a preparation process thereof. Background Art

[0002] In recent years, with the continuous enhancement of electronic equipment functions and the expansion of application fields, electronic products are rapidly developing in the direction of miniaturization, high performance and high integration. In the fields of smart phones, wearable devices, IoT devices and high-performance computing, the market has an increasingly urgent demand for electronic packaging technology with compact size, high-density integration and excellent heat dissipation performance. This trend requires electronic packaging structures to be able to integrate more functional modules in a limited space, achieve higher circuit density and faster signal transmission speed, and also effectively manage the heat caused by high power density to ensure reliable operation of the equipment.

[0003] Existing electronic packaging technology mainly uses surface mount technology (SMT) to mount electronic components on the surface of a printed circuit board (PCB), and then achieve electrical connections through wiring layers. However, this traditional packaging method has some limitations. First, the surface mounting of components and multi-layer wiring lead to an increase in the thickness of the packaging structure, which limits the miniaturization and compact design of the device. Secondly, with the increase in the integration of electronic components, heat accumulates inside the package. Traditional heat dissipation methods are difficult to meet the heat dissipation requirements of high-power density devices, which can easily cause device overheating and affect performance and reliability. In addition, the complex process of multi-layer wiring increases manufacturing costs and restricts the economic efficiency of the product.

[0004] Therefore, it is necessary to improve the electronic packaging process in the prior art to solve the technical problem of poor comprehensive performance of integration and heat dissipation performance. Summary of the invention

[0005] The purpose of the present invention is to provide an embedded multi-layer interconnected electronic packaging structure and a preparation process thereof to solve the above technical problems.

[0006] To achieve this object, the present invention adopts the following technical solutions: A preparation process of an embedded multi-layer interconnected electronic packaging structure, comprising: Providing an insulating substrate, and forming a micro-embedding groove at a predetermined position of the insulating substrate; wherein the size of the micro-embedding groove matches the electronic component to be embedded; Placing the surface-treated electronic component in the embedding groove so that it is in close contact with the inner wall of the insulating substrate; Dielectric layers and conductive layers are stacked layer by layer on the insulating substrate and the embedded electronic components by using deposition technology to construct a multi-layer interconnection network, wherein vertical interconnection channels are formed by deep reactive ion etching technology to achieve electrical connection between the conductive layers; Introducing a thermal management structure, integrating a graphene-based heat sink in the multi-layer interconnection network, and forming a through thermal channel to obtain a component blank; The component blank is packaged, covered with a protective coating, and connection pads of lead-out terminals are defined to form an embedded multi-layer interconnected electronic packaging structure.

[0007] Optionally, providing an insulating substrate and forming a micro-embedded groove at a predetermined position of the insulating substrate specifically includes: Providing an insulating substrate with high thermal conductivity; the insulating substrate is a substrate made of a high molecular polymer material; Coating a layer of photosensitive etching glue on the surface of the insulating substrate to form a uniform photosensitive coating; By means of photolithography technology, a photolithography mask is used to expose a pattern of micro grooves on the photosensitive coating according to the size and position of the electronic component to be embedded; Performing a developing process on the exposed photosensitive coating to remove the photosensitive etching glue in the exposed area and reveal the micro-groove area on the surface of the insulating substrate; Laser micro-etching processing technology is used to etch the micro-groove area to form a micro-groove with a preset depth and size, so that the size of the micro-groove matches the electronic component to be embedded.

[0008] Optionally, the step of machining a micro-groove with a preset depth and size so that the size of the micro-groove matches the electronic component to be embedded may further include: Remove the residual photosensitive etching glue, and clean and dry the etched insulating substrate; The inner wall of the micro-groove is plasma cleaned to perform surface modification treatment.

[0009] Optionally, dielectric layers and conductive layers are stacked layer by layer on the insulating substrate and the embedded electronic components by using deposition technology to construct a multi-layer interconnection network, wherein vertical interconnection channels are formed by deep reactive ion etching technology to achieve electrical connection between the conductive layers, specifically including: The surfaces of the insulating substrate and the embedded electronic components are cleaned by a plasma cleaning method, and the cleaned surfaces are oxidized to form a thin oxide layer for surface treatment; Depositing a layer of dielectric material with a thickness of 200 nm to 1 μm on the surface after surface treatment by chemical vapor deposition technology to form a first dielectric layer; the dielectric material is silicon dioxide or silicon nitride; A layer of photoresist is spin-coated on the surface of the first dielectric layer, with a thickness of 1 μm to 3 μm, and a pattern of the through-hole position is exposed to the photoresist through a mask plate by using ultraviolet exposure photolithography technology, and a development process is performed to form an exposed area corresponding to the first interconnection through-hole on the first dielectric layer: In the plasma reaction chamber, an etching process parameter with a high aspect ratio is used to anisotropically etch the exposed area to form a first interconnection through hole penetrating the first dielectric layer.

[0010] Optionally, in the plasma reaction chamber, an etching process parameter with a high aspect ratio is used to anisotropically etch the exposed area to form a first interconnection through hole penetrating the first dielectric layer, and then the method further includes: Using physical vapor deposition technology, a layer of metal conductive material with a thickness of 100 nm to 500 nm is deposited on the first dielectric layer and the first interconnection through hole to form a first conductive layer: A layer of positive photoresist with a thickness of 1 μm to 3 μm is spin-coated on the first conductive layer, and a conductive pattern is prepared on the first conductive layer by using photolithography technology to obtain a first layer of metal interconnection lines.

[0011] Optionally, the method further comprises: preparing a conductive pattern on the first conductive layer by using photolithography technology to obtain a first layer of metal interconnection lines; and then: Depositing a layer of dielectric material again on the patterned first conductive layer to form a second dielectric layer, and forming a second interconnection via and a second conductive layer on the second dielectric layer; According to design requirements, multiple dielectric layers and conductive layers are repeatedly stacked to construct a multi-layer interconnection network with the required number of layers; wherein the multi-layer interconnection through holes constitute vertical interconnection channels.

[0012] Optionally, the step of introducing a thermal management structure, integrating a graphene-based heat sink in the multi-layer interconnection network, and forming a through thermal channel to obtain a component blank specifically includes: According to the thermal power consumption and heat distribution of embedded electronic components, determine the key areas that need to strengthen heat dissipation, design the layout, size and location of the heat dissipation channel that runs through the entire multi-layer interconnection network, and reserve the heat dissipation channel area in the layout design of the multi-layer interconnection network; Providing a graphene-based heat sink, and placing the graphene-based heat sink in the reserved heat dissipation channel area so that it is in close contact with the underlying dielectric layer; Depositing an adhesion promoting layer having a thickness of 5 nm to 20 nm on the upper and lower surfaces of the graphene-based heat sink respectively; A dielectric buffer layer with a thickness of 10 nm to 50 nm is deposited on each of the adhesion promoting layers, and the material of the dielectric buffer layer is silicon nitride or aluminum oxide.

[0013] Optionally, a dielectric buffer layer with a thickness of 10 nm to 50 nm is deposited on each of the adhesion promoting layers, and then the method further comprises: On the top layer or bottom layer of the multi-layer interconnection network, an etching process is used to open a thermal contact area corresponding to the position of the heat dissipation channel, and the top layer or bottom layer dielectric layer and protective layer are removed to expose the end surface of the graphene-based heat sink; A layer of high thermal conductivity interface material with a thickness of 10 μm to 50 μm is coated on the end surface of the graphene; the material of the high thermal conductivity interface material layer is a thermal conductive paste or thermal conductive glue containing silver nanoparticles; A heat dissipation component is installed in the thermal contact area of ​​the top layer or the bottom layer, respectively, so that the heat dissipation component is attached to the high thermal conductivity interface material layer; wherein the heat dissipation component is a metal heat sink, a heat pipe or a graphene film heat sink; During the patterning process of each dielectric layer, the heat dissipation channel of each layer is kept connected to form a connected heat channel to obtain a component blank.

[0014] Optionally, packaging the component blank, covering it with a protective coating, and defining connection pads of lead-out terminals to form an embedded multi-layer interconnected electronic packaging structure specifically includes: Clean and prepare the surface of the component blanks, using plasma cleaning and wet cleaning methods to remove impurity particles on the surface; Using spin coating technology, a protective coating with a thickness of 5 μm to 20 μm is evenly coated on the top layer and side wall surface of the component blank, and then cured; Defining the connection pad position of the lead-out terminal, spin-coating a layer of photoresist on the protective coating, exposing and developing by ultraviolet photolithography technology to form a pattern of the lead-out terminal position, and then etching the protective coating in the exposed area by anisotropic dry etching technology until the lead-out terminal of the conductive layer below is exposed; Performing metallization treatment on the exposed lead-out terminals, depositing a conductive metal layer with a thickness of 500 nm to 5 μm in the lead-out terminal area by using an electroless deposition technique to form a connection pad; The connecting pads are heat treated to form an embedded multi-layer interconnected electronic packaging structure.

[0015] The present invention provides an embedded multi-layer interconnected electronic packaging structure, which is prepared by the preparation process of the embedded multi-layer interconnected electronic packaging structure as described above. The embedded multi-layer interconnected electronic packaging structure comprises: An insulating substrate having a micro-groove, wherein the size of the micro-groove matches the embedded electronic component; The electronic components are embedded in the micro grooves of the insulating substrate after surface treatment, and are in close contact with the inner wall of the substrate; A multilayer interconnect network comprising multiple dielectric and conductive layers deposited alternately on an insulating substrate and embedded electronic components; Vertical interconnect channels, formed by deep reactive ion etching technology, penetrate multiple dielectric layers and are used to achieve electrical connections between various conductive layers and with embedded electronic components; A graphene-based heat sink, a thermal management structure integrated in the multi-layer interconnect network, forming a through thermal channel; Protective coatings that cover the surface of multi-layer interconnected electronic structures; Connection pads are external connection areas defined on the protective coating, formed by metallization, for connecting to external circuits.

[0016] Compared with the prior art, the present invention has the following beneficial effects: by pre-forming micro-embedded grooves matching the size of electronic components on an insulating substrate, the surface-treated electronic components are accurately embedded therein and in close contact with the inner wall of the substrate, and dielectric layers and conductive layers are stacked layer by layer on the substrate and the surface of the embedded electronic components by deposition technology to construct a multi-layer interconnection network structure; and vertical interconnection channels are formed by deep reactive ion etching technology, and graphene-based heat sinks are introduced into the multi-layer interconnection network to form a through heat channel to enhance the heat dissipation performance of the entire structure, and the component blanks are packaged, covered with a protective coating, and the connection pads of the lead-out ends are defined to complete the preparation of the embedded multi-layer interconnection electronic packaging structure; the method embeds and installs electronic components in the substrate, and uses the method of depositing dielectric layers and conductive layers to construct a high-density, multi-level interconnection network, thereby realizing the miniaturization and high integration of electronic equipment, taking into account the requirements of compact size and heat dissipation performance, and providing a high-density interconnection and efficient heat dissipation solution for the field of electronic packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0019] Figure 1 This is a schematic diagram of a process flow of a manufacturing process of an embedded multi-layer interconnected electronic packaging structure according to the first embodiment of the present invention; Figure 2 The second schematic diagram is a process flow diagram of the preparation process of the embedded multi-layer interconnected electronic packaging structure of the first embodiment; Figure 3 It is a schematic layout diagram of the embedded multi-layer interconnected electronic packaging structure of the second embodiment. DETAILED DESCRIPTION

[0020] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0022] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0023] Embodiment 1: Combination Figure 1 to Figure 2 As shown, an embodiment of the present invention provides a preparation process of an embedded multi-layer interconnected electronic packaging structure, comprising: S1, providing an insulating substrate, and forming a micro embedding groove at a predetermined position of the insulating substrate; wherein the size of the micro embedding groove matches the electronic component to be embedded; An insulating substrate (such as ceramic, glass or polymer material) is prepared, and micro-grooves are precisely machined at predetermined positions on the substrate. The dimensions of these grooves exactly match the electronic components to be embedded.

[0024] S2, placing the surface treated electronic component in the embedding groove so that it is in close contact with the inner wall of the insulating substrate; thus ensuring the mechanical stability and initial electrical contact of the electronic component.

[0025] S3, stacking dielectric layers and conductive layers layer by layer on the insulating substrate and embedded electronic components by deposition technology to build a multi-layer interconnection network, wherein vertical interconnection channels are formed by deep reactive ion etching technology to achieve electrical connection between various conductive layers; Through deposition techniques (such as chemical vapor deposition and physical vapor deposition), dielectric layers and conductive layers are alternately deposited on the substrate and embedded electronic components to build a multi-layer interconnection structure. Through deep reactive ion etching (DRIE), vertical interconnection channels (through holes or vias) are formed at designated locations to achieve electrical connections between conductive layers of different layers, build a three-dimensional circuit network, and greatly improve the integration and functionality of the circuit.

[0026] S4, introducing a thermal management structure, integrating a graphene-based heat sink in a multi-layer interconnection network, and forming a through thermal channel to obtain a component blank; By integrating a graphene-based heat sink with high thermal conductivity in a multi-layer interconnection network, introducing a thermal management structure, embedding the graphene heat sink in the reserved heat dissipation channel position, and forming a continuous heat channel through the top and bottom through design, it is ensured that the heat generated by the electronic components can be quickly transferred to the external heat sink, effectively reducing the operating temperature of the device, improving the performance and reliability of the components, and finally obtaining a component embryo with preliminary functions.

[0027] S5, encapsulating the component blank, covering it with a protective coating, and defining the connection pads of the lead-out terminals to form an embedded multi-layer interconnected electronic packaging structure.

[0028] The component blank is packaged as a whole. First, a protective coating is applied to cover the surface of the component blank to provide mechanical protection and environmental isolation. Then, the lead end of the internal conductive layer is exposed at the specified position through photolithography and etching processes, and a connection pad is formed after metallization treatment to achieve reliable connection with the external circuit. In this way, the preparation of the embedded multi-layer interconnected electronic packaging structure is completed, and a packaging product with high-density integration, excellent heat dissipation performance and reliable electrical connection is obtained.

[0029] The working principle of the present invention is as follows: by pre-forming micro-grooves matching the size of electronic components on an insulating substrate, the surface-treated electronic components are accurately embedded therein and in close contact with the inner wall of the substrate, and dielectric layers and conductive layers are stacked layer by layer on the substrate and the surface of the embedded electronic components by deposition technology to construct a multi-layer interconnection network structure; and vertical interconnection channels are formed by deep reactive ion etching technology, and graphene-based heat sinks are introduced into the multi-layer interconnection network to form a through heat channel to enhance the heat dissipation performance of the entire structure, and the component blanks are packaged, covered with a protective coating, and the connection pads of the lead-out ends are defined to complete the preparation of the embedded multi-layer interconnection electronic packaging structure; the method embeds and installs electronic components in the substrate, and uses the method of depositing dielectric layers and conductive layers to construct a high-density, multi-level interconnection network, thereby realizing the miniaturization and high integration of electronic equipment, taking into account the requirements of compact size and heat dissipation performance, and providing a high-density interconnection and efficient heat dissipation solution for the field of electronic packaging.

[0030] In this embodiment, it is specifically explained that step S1 specifically includes: S11, providing an insulating substrate with high thermal conductivity; the insulating substrate is selected from a substrate of a high molecular polymer material.

[0031] S12, coating a layer of photosensitive etching glue on the surface of the insulating substrate to form a uniform photosensitive coating; the photosensitive etching glue is sensitive to light of a specific wavelength and can undergo a chemical reaction through light in a subsequent photolithography process, thereby providing necessary conditions for the formation of a micro-groove pattern.

[0032] S13, using a photolithography technique and a photolithography mask to expose a pattern of micro grooves on the photosensitive coating according to the size and position of the electronic component to be embedded; Using photolithography and a customized photolithography mask, the designed micro-groove pattern is accurately exposed onto the photosensitive coating. According to the specific size and position of the electronic component to be embedded, the exposed pattern is ensured to accurately match the component. This step determines the positional accuracy and dimensional accuracy of the groove.

[0033] S14, developing the exposed photosensitive coating to remove the photosensitive etching resin in the exposed area, revealing the micro-groove area on the surface of the insulating substrate; The exposed photosensitive coating is developed, and the developer dissolves and removes the photosensitive etchant in the exposed area, leaving the etchant in the unexposed area to protect the substrate. In this way, an open area of ​​micro-grooves is formed on the surface of the insulating substrate, ready for subsequent etching processing.

[0034] S15, using laser micro-etching processing technology, etches the micro-groove area to process a micro-groove of preset depth and size, so that the size of the micro-groove matches the electronic component to be embedded.

[0035] Laser micro-etching technology is used to precisely etch the exposed micro-groove area. By controlling the energy, focus and scanning path of the laser, micro-grooves with preset depth and precise size are accurately processed to ensure that the grooves are perfectly matched with the size of the electronic components, providing an ideal physical space for the embedding of electronic components.

[0036] In this embodiment, it is further explained that after step S15, the following steps are further included: S16, removing the residual photosensitive etching glue, and cleaning and drying the etched insulating substrate; Use organic solvents (such as acetone and isopropyl alcohol) to remove the residual photosensitive etching glue on the surface of the substrate to ensure that there is no chemical residue. Subsequently, the etched insulating substrate is thoroughly cleaned to remove particles and impurities, and then dried. This step ensures the cleanliness of the substrate surface.

[0037] S17, plasma cleaning is performed on the inner wall of the micro-groove to perform surface modification treatment, so as to improve the bonding force between the electronic component and the inner wall of the groove, and ensure that the subsequently embedded electronic component has good mechanical stability and thermal conductivity.

[0038] In this embodiment, it is specifically described that step S3 specifically includes: S31, cleaning the surfaces of the insulating substrate and the embedded electronic components by a plasma cleaning method, and performing oxidation treatment on the cleaned surfaces to form a thin oxide layer for surface treatment; Plasma cleaning technology is used to thoroughly clean the surface of insulating substrates and embedded electronic components to remove organic matter, particles and other impurities on the surface. Subsequently, the cleaned surface is oxidized to form a thin oxide layer (such as silicon dioxide or aluminum oxide). This oxide layer can improve the adhesion of subsequent dielectric and conductive layers, improve interface quality, and ensure the uniformity and stability of subsequent deposited materials.

[0039] S32, depositing a layer of dielectric material with a thickness of 200 nm to 1 μm on the surface after the surface treatment by chemical vapor deposition technology to form a first dielectric layer; the dielectric material is silicon dioxide or silicon nitride; Using chemical vapor deposition (CVD) technology, a layer of dielectric material with a thickness between 200 nanometers and 1 micron is deposited on the surface of the surface-treated insulating substrate and electronic components. The commonly used materials are silicon dioxide (SiO2) or silicon nitride (Si3N4). This dielectric layer acts as an insulator, isolating the electrical interference between different conductive layers, while providing a smooth surface.

[0040] S33, spin-coating a layer of photoresist with a thickness of 1 μm to 3 μm on the surface of the first dielectric layer, using ultraviolet exposure lithography technology to expose the pattern of the through-hole position to the photoresist through a mask plate, and performing development treatment to form an exposed area corresponding to the first interconnected through-hole on the first dielectric layer.

[0041] S34, in the plasma reaction chamber, using etching process parameters with a high aspect ratio to anisotropically etch the exposed area to form a first interconnection through hole penetrating the first dielectric layer.

[0042] The processed sample is placed in a plasma reaction chamber, and a high aspect ratio anisotropic etching process is used to etch the exposed area after the photoresist is removed. By precisely controlling etching parameters such as gas composition, power and time, a first interconnection through hole with vertical sidewalls and precise dimensions is formed, penetrating the first dielectric layer, providing a channel for vertical electrical connection between conductive layers.

[0043] S35, using a physical vapor deposition technique, such as sputtering deposition, to deposit a layer of metal conductive material with a thickness of 100 nm to 500 nm on the first dielectric layer and the first interconnection through hole to form a first conductive layer: Using physical vapor deposition (PVD) technology (such as sputtering deposition or electron beam evaporation), a layer of metal conductive material with a thickness of 100 nanometers to 500 nanometers is deposited on the first dielectric layer and the first interconnection through hole etched. Commonly used metals are copper (Cu), aluminum (Al) or tungsten (W). This layer of conductive material fills the through hole and covers the surface of the dielectric layer to form the first conductive layer and build an electrical connection.

[0044] S36, spin-coating a layer of positive photoresist with a thickness of 1 μm to 3 μm on the first conductive layer, and using photolithography technology to prepare a conductive pattern on the first conductive layer to obtain a first layer of metal interconnection lines. The conductive pattern can be formed by exposing the conductive pattern to the photoresist, then developing, removing the photoresist in the exposed area, and then using dry etching to remove the exposed conductive material, leaving the conductive pattern protected by the photoresist.

[0045] S37, depositing a layer of dielectric material again on the patterned first conductive layer to form a second dielectric layer, and forming a second interconnection through hole and a second conductive layer on the second dielectric layer; In step S37, the process of step S32 is repeated to deposit a layer of dielectric material on the patterned first conductive layer again to form a second dielectric layer. Then, according to the processes of steps S33 and S34, a second interconnection via is formed on the second dielectric layer. Next, according to the processes of steps S35 and S36, a second conductive layer is deposited and patterned to form a second layer of metal interconnection lines to achieve vertical electrical connections and horizontal circuit layout between different layers.

[0046] S38, according to design requirements, repeatedly stack multiple dielectric layers and conductive layers to construct a multi-layer interconnection network with a required number of layers; wherein the multi-layer interconnection through holes constitute a vertical interconnection channel.

[0047] According to the requirements of the circuit design, the above steps of dielectric layer deposition, through-hole etching, conductive layer deposition and patterning are repeated to build multi-level dielectric and conductive layers layer by layer until the required number of layers is reached. The interconnecting through-holes between the layers form vertical interconnection channels to achieve electrical connections between the conductive layers, forming a complete three-dimensional multi-layer interconnection network to meet the integration requirements of complex circuit systems.

[0048] In this embodiment, it is specifically described that step S4 specifically includes: S41, determining the key areas where heat dissipation needs to be enhanced according to the heat power consumption and heat distribution of the embedded electronic components, designing the layout, size and position of the heat dissipation channel running through the entire multi-layer interconnection network, and reserving the heat dissipation channel area in the layout design of the multi-layer interconnection network; Design the layout, size, and location of the heat dissipation channels throughout the multi-layer interconnect network to ensure that heat can be efficiently transferred from the inside to the external heat dissipation components. During the layout design of the multi-layer interconnect network, reserve these heat dissipation channel areas and avoid placing conductive lines or filling dielectric materials at these locations.

[0049] S42, providing a graphene-based heat sink, and placing the graphene-based heat sink in the reserved heat dissipation channel area so as to be in close contact with the underlying dielectric layer; Prepare a graphene-based heat sink with high thermal conductivity and place it in the pre-reserved heat dissipation channel area. Ensure that the graphene-based heat sink is in close contact with the underlying dielectric layer to establish an effective heat conduction path. This step enhances the thermal management capabilities of the overall packaging structure by utilizing the excellent thermal conductivity of graphene, helping to quickly conduct heat generated by electronic components.

[0050] S43, depositing an adhesion promoting layer with a thickness of 5 nm to 20 nm on the upper and lower surfaces of the graphene-based heat sink respectively; In order to enhance the adhesion between the graphene-based heat sink and the upper and lower dielectric layers or conductive layers, an adhesion-promoting layer with a thickness of 5 to 20 nanometers is deposited on the upper and lower surfaces respectively. Commonly used adhesion-promoting materials include titanium (Ti) or chromium (Cr). This ultra-thin metal layer can improve the interfacial bonding between graphene and other materials, ensuring the mechanical stability and long-term reliability of the structure.

[0051] S44, depositing a dielectric buffer layer with a thickness of 10 nm to 50 nm on each of the adhesion promoting layers, wherein the material of the dielectric buffer layer is silicon nitride or aluminum oxide.

[0052] On the upper and lower surfaces of the adhesion-promoting layer, a dielectric buffer layer with a thickness of 10 to 50 nanometers is deposited, and the material used is silicon nitride (Si3N4) or aluminum oxide (Al2O3). This dielectric buffer layer has excellent insulation performance and thermal stability, which can not only protect the graphene-based heat sink, but also avoid electrical interference between the upper and lower conductive layers. In this embodiment, it is further explained that after step S44, the following steps are further included: S45, using an etching process to open a thermal contact area corresponding to the position of the heat dissipation channel on the top layer or bottom layer of the multi-layer interconnection network, remove the top layer or bottom layer dielectric layer and the protective layer, and expose the end surface of the graphene-based heat sink; At the top and bottom layers of the multi-layer interconnect network, the dielectric layer and protective layer corresponding to the heat dissipation channel are precisely removed through photolithography and etching processes to form thermal contact areas. In this way, the end surface of the graphene-based heat sink is exposed, providing a direct physical channel for subsequent connection with external heat dissipation components. S46, coating a layer of high thermal conductivity interface material with a thickness of 10 μm to 50 μm on the end face of the graphene; the material of the high thermal conductivity interface material layer is a thermal conductive paste or thermal conductive glue containing silver nanoparticles; and the process is completed by dispensing or screen printing.

[0053] S47, heat dissipation components are installed in the thermal contact area of ​​the top layer or the bottom layer respectively, so that the heat dissipation components are attached to the high thermal conductivity interface material layer; wherein the heat dissipation components are metal heat sinks, heat pipes or graphene film heat sinks; the internal heat is effectively transferred to the external heat sink to improve the overall heat dissipation performance.

[0054] S48, during the patterning process of each dielectric layer, the heat dissipation channel of each layer is kept connected to form a connected heat channel to obtain a component blank.

[0055] During the preparation and patterning of each dielectric layer, the heat dissipation channel is always aligned and connected in the vertical direction without being filled or blocked by other materials. In this way, a continuous heat channel is formed from the embedded electronic components to the external heat dissipation components, ensuring efficient heat conduction.

[0056] In this embodiment, it is specifically described that step S5 specifically includes: S51, cleaning and preparing the surface of the component blank, using plasma cleaning and wet cleaning methods to remove impurity particles on the surface; The entire surface of the component blank is cleaned. First, plasma cleaning technology is used to remove organic matter, particles and oxides on the surface using active plasma to improve surface cleanliness and surface energy. Subsequently, wet cleaning is performed using ultrapure water, anhydrous ethanol or other solvent cleaning agents to further remove residual impurities and particulate matter. Finally, the component blank is blown dry with high-purity nitrogen or clean compressed air to ensure that the surface is dust-free and contaminant-free, achieving a high level of cleanliness, and preparing for the subsequent coating of protective coatings.

[0057] S52, using spin coating technology, uniformly coating a protective coating with a thickness of 5 μm to 20 μm on the top layer and side wall surface of the component blank, and performing a curing treatment; the polymer protective coating is polyimide, epoxy resin or liquid crystal polymer; By controlling the rotation speed and time of spin coating, the coating thickness is adjusted between 5μm and 20μm to ensure the uniformity of the coating. Subsequently, the coated component blank is placed in a curing furnace and cured according to the temperature curve required by the material, so that the coating material is fully cross-linked and cured to form a dense protective layer, thereby improving the mechanical strength and environmental stability of the package.

[0058] S53, define the connection pad position of the lead-out terminal, spin-coat a layer of photoresist on the protective coating, use ultraviolet photolithography technology to expose and develop, form a pattern of the lead-out terminal position, and then use anisotropic dry etching technology to etch the protective coating in the exposed area until the lead-out terminal of the conductive layer below is exposed.

[0059] S54, metallizing the exposed lead-out terminals, using electroless deposition technology to deposit a conductive metal layer with a thickness of 500 nm to 5 μm in the lead-out terminal area to form a connecting pad; the conductive metal layer is such as gold, silver or nickel alloy.

[0060] Electroless deposition does not require external current and relies on chemical reactions to uniformly deposit metal films on the metal surface, which can form a uniform metal layer in complex shapes and tiny areas. This metal layer has high conductivity and good welding properties, forming a reliable connection pad.

[0061] S55, heat-treating the connection pads to form an embedded multi-layer interconnected electronic packaging structure. In order to improve the compactness and adhesion of the metal layer of the connection pads, heat treatment is performed on them. Heat treatment is usually carried out in an inert atmosphere (such as nitrogen, argon) or a reducing atmosphere (such as hydrogen), with a temperature range of 100°C to 300°C and a time of 30 minutes to 1 hour. Heat treatment can eliminate stress in the metal layer, improve the grain structure, and enhance the conductivity and corrosion resistance of the metal layer. At the same time, heat treatment helps the metal layer to combine with the underlying conductive layer, and improves the mechanical strength and reliability of the connection pads. After heat treatment, the preparation process of the entire embedded multi-layer interconnected electronic packaging structure is completed, and finally an electronic packaging product with high-density interconnection, high-performance heat dissipation and reliable electrical connection is obtained.

[0062] Embodiment 2: Combination Figure 3 As shown, the present invention further provides an embedded multi-layer interconnected electronic packaging structure, which is manufactured using the manufacturing process of the embedded multi-layer interconnected electronic packaging structure of the first embodiment, and the embedded multi-layer interconnected electronic packaging structure comprises: The insulating substrate 10 has a micro embedding groove 11 , and the size of the micro embedding groove 11 matches the embedded electronic component 20 .

[0063] The electronic component 20 is embedded in the micro groove 11 of the insulating substrate 10 after surface treatment, and is in close contact with the inner wall of the insulating substrate 10 .

[0064] The multi-layer interconnection network 30 includes a plurality of dielectric layers 31 and conductive layers 32 that are alternately deposited and stacked on the insulating substrate 10 and the embedded electronic components 20 .

[0065] The vertical interconnection channel 40 is formed by deep reactive ion etching technology, penetrates multiple dielectric layers 31, and is used to achieve electrical connection between each conductive layer 32 and between the embedded electronic components 20.

[0066] The graphene-based heat sink 50 is a thermal management structure integrated in the multi-layer interconnection network 30 , and a through thermal channel 60 is formed.

[0067] The protective coating 70 covers the surface of the multi-layer interconnected electronic structure.

[0068] The connection pads are external connection locations defined on the protective coating 70 and are formed by metallization processing for connecting to external circuits.

[0069] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A process for preparing an embedded multi-layer interconnected electronic packaging structure, characterized in that: include: Providing an insulating substrate, and forming a micro-embedding groove at a predetermined position of the insulating substrate; wherein the size of the micro-embedding groove matches the electronic component to be embedded; Placing the surface-treated electronic component in the embedding groove so that it is in close contact with the inner wall of the insulating substrate; Dielectric layers and conductive layers are stacked layer by layer on the insulating substrate and the embedded electronic components by using deposition technology to construct a multi-layer interconnection network, wherein vertical interconnection channels are formed by deep reactive ion etching technology to achieve electrical connection between the conductive layers; Introducing a thermal management structure, integrating a graphene-based heat sink in the multi-layer interconnection network, and forming a through thermal channel to obtain a component blank; The component blank is packaged, covered with a protective coating, and connection pads of lead-out terminals are defined to form an embedded multi-layer interconnected electronic packaging structure.

2. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 1, characterized in that: The step of providing an insulating substrate and forming a micro-groove at a predetermined position of the insulating substrate specifically includes: Providing an insulating substrate with high thermal conductivity; the insulating substrate is a substrate made of a high molecular polymer material; Coating a layer of photosensitive etching glue on the surface of the insulating substrate to form a uniform photosensitive coating; By means of photolithography technology, a photolithography mask is used to expose a pattern of micro grooves on the photosensitive coating according to the size and position of the electronic component to be embedded; Performing a developing process on the exposed photosensitive coating to remove the photosensitive etching glue in the exposed area and reveal the micro-groove area on the surface of the insulating substrate; Laser micro-etching processing technology is used to etch the micro-groove area to form a micro-groove with a preset depth and size, so that the size of the micro-groove matches the electronic component to be embedded.

3. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 2, characterized in that: The micro-embedding grooves with a preset depth and size are processed so that the size of the micro-embedding grooves matches the electronic components to be embedded, and then the process further includes: Remove the residual photosensitive etching glue, and clean and dry the etched insulating substrate; The inner wall of the micro-groove is plasma cleaned to perform surface modification treatment.

4. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 1, characterized in that: Dielectric layers and conductive layers are stacked layer by layer on the insulating substrate and the embedded electronic components by using deposition technology to construct a multi-layer interconnection network, wherein vertical interconnection channels are formed by deep reactive ion etching technology to achieve electrical connection between the conductive layers, specifically including: The surfaces of the insulating substrate and the embedded electronic components are cleaned by a plasma cleaning method, and the cleaned surfaces are oxidized to form a thin oxide layer for surface treatment; Depositing a layer of dielectric material with a thickness of 200 nm to 1 μm on the surface after surface treatment by chemical vapor deposition technology to form a first dielectric layer; the dielectric material is silicon dioxide or silicon nitride; A layer of photoresist is spin-coated on the surface of the first dielectric layer, with a thickness of 1 μm to 3 μm, and a pattern of the through-hole position is exposed to the photoresist through a mask plate by using ultraviolet exposure photolithography technology, and a development process is performed to form an exposed area corresponding to the first interconnection through-hole on the first dielectric layer: In the plasma reaction chamber, an etching process parameter with a high aspect ratio is used to anisotropically etch the exposed area to form a first interconnection through hole penetrating the first dielectric layer.

5. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 4, characterized in that: The method further comprises: anisotropically etching the exposed area in the plasma reaction chamber using etching process parameters with a high aspect ratio to form a first interconnection through hole penetrating the first dielectric layer; and then: Using physical vapor deposition technology, a layer of metal conductive material with a thickness of 100 nm to 500 nm is deposited on the first dielectric layer and the first interconnection through hole to form a first conductive layer: A layer of positive photoresist with a thickness of 1 μm to 3 μm is spin-coated on the first conductive layer, and a conductive pattern is prepared on the first conductive layer by using photolithography technology to obtain a first layer of metal interconnection lines.

6. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 5, characterized in that: The method further comprises: preparing a conductive pattern on the first conductive layer by using photolithography technology to obtain a first layer of metal interconnection lines; and then: Depositing a layer of dielectric material again on the patterned first conductive layer to form a second dielectric layer, and forming a second interconnection via and a second conductive layer on the second dielectric layer; According to design requirements, multiple dielectric layers and conductive layers are repeatedly stacked to construct a multi-layer interconnection network with the required number of layers; wherein the multi-layer interconnection through holes constitute vertical interconnection channels.

7. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 1, characterized in that: The step of introducing a thermal management structure, integrating a graphene-based heat sink in the multi-layer interconnection network, and forming a through thermal channel to obtain a component blank specifically includes: According to the thermal power consumption and heat distribution of embedded electronic components, determine the key areas that need to strengthen heat dissipation, design the layout, size and location of the heat dissipation channel that runs through the entire multi-layer interconnection network, and reserve the heat dissipation channel area in the layout design of the multi-layer interconnection network; Providing a graphene-based heat sink, and placing the graphene-based heat sink in the reserved heat dissipation channel area so that it is in close contact with the underlying dielectric layer; Depositing an adhesion promoting layer having a thickness of 5 nm to 20 nm on the upper and lower surfaces of the graphene-based heat sink respectively; A dielectric buffer layer with a thickness of 10 nm to 50 nm is deposited on each of the adhesion promoting layers, and the material of the dielectric buffer layer is silicon nitride or aluminum oxide.

8. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 7, characterized in that: The step of depositing a dielectric buffer layer with a thickness of 10 nm to 50 nm on the adhesion promoting layer respectively further comprises: On the top layer or bottom layer of the multi-layer interconnection network, an etching process is used to open a thermal contact area corresponding to the position of the heat dissipation channel, and the top layer or bottom layer dielectric layer and protective layer are removed to expose the end surface of the graphene-based heat sink; A layer of high thermal conductivity interface material with a thickness of 10 μm to 50 μm is coated on the end surface of the graphene; the material of the high thermal conductivity interface material layer is a thermal conductive paste or thermal conductive glue containing silver nanoparticles; A heat dissipation component is installed in the thermal contact area of ​​the top layer or the bottom layer, respectively, so that the heat dissipation component is attached to the high thermal conductivity interface material layer; wherein the heat dissipation component is a metal heat sink, a heat pipe or a graphene film heat sink; During the patterning process of each dielectric layer, the heat dissipation channel of each layer is kept connected to form a connected heat channel to obtain a component blank.

9. The process for preparing the embedded multi-layer interconnected electronic packaging structure according to claim 8, characterized in that: The step of packaging the component blank, covering it with a protective coating, and defining the connection pads of the lead-out terminals to form an embedded multi-layer interconnected electronic packaging structure specifically includes: Clean and prepare the surface of the component blanks, using plasma cleaning and wet cleaning methods to remove impurity particles on the surface; Using spin coating technology, a protective coating with a thickness of 5 μm to 20 μm is evenly coated on the top layer and side wall surface of the component blank, and then cured; Defining the connection pad position of the lead-out terminal, spin-coating a layer of photoresist on the protective coating, exposing and developing by ultraviolet photolithography technology to form a pattern of the lead-out terminal position, and then etching the protective coating in the exposed area by anisotropic dry etching technology until the lead-out terminal of the conductive layer below is exposed; Performing metallization treatment on the exposed lead-out terminals, depositing a conductive metal layer with a thickness of 500 nm to 5 μm in the lead-out terminal area by using an electroless deposition technique to form a connection pad; The connecting pads are heat treated to form an embedded multi-layer interconnected electronic packaging structure.

10. An embedded multi-layer interconnected electronic packaging structure, characterized in that: The method is prepared by using the preparation process of the embedded multi-layer interconnected electronic packaging structure according to any one of claims 1 to 9, wherein the embedded multi-layer interconnected electronic packaging structure comprises: An insulating substrate having a micro-groove, wherein the size of the micro-groove matches the embedded electronic component; The electronic components are embedded in the micro grooves of the insulating substrate after surface treatment, and are in close contact with the inner wall of the substrate; A multilayer interconnect network comprising multiple dielectric and conductive layers deposited alternately on an insulating substrate and embedded electronic components; Vertical interconnect channels, formed by deep reactive ion etching technology, penetrate multiple dielectric layers and are used to achieve electrical connections between various conductive layers and with embedded electronic components; A graphene-based heat sink, a thermal management structure integrated in the multi-layer interconnect network, forming a through thermal channel; Protective coatings that cover the surface of multi-layer interconnected electronic structures; Connection pads are external connection areas defined on the protective coating, formed by metallization, for connecting to external circuits.

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