Preparation method of shallow trench structure
By using radical etching technology in the BCD shallow trench process, the silicon nitride layer is consumed and a protective silicon oxide layer is generated, and the TDDB failure problem at the border between the shallow trench and the active region is solved, which significantly improves the voltage withstandness and life of the device.
Patent Information
- Application Number
- CN202510006506.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-11
AI Technical Summary
In the BCD shallow trench process, the shoulders bordering the shallow trench and the active region are prone to cause timing-related dielectric breakdown (TDDB) failure problems, resulting in device dielectric layer degradation and breakdown.
By forming a pad oxide layer and a silicon nitride layer on the silicon substrate, patterning and radical etching are performed, silicon tetrafluoride is reacted with the silicon nitride layer by reacting with the silicon nitride layer, consuming part of the silicon nitride layer, and reacting with the silicon substrate with oxygen radicals to generate a silicon oxide layer to protect the silicon substrate, thereby reducing the width of the silicon nitride layer.
This method effectively improves the voltage withstandability of the device and significantly extends the life of TDDB failure, from 11 years to 162 years, solving the problem of TDDB failure.
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Figure CN119812099A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a method for preparing a shallow trench structure. Background Art
[0002] With the development of microelectronics technology, in order to realize high-density, high-performance large-scale integrated circuits, the isolation process between semiconductor devices has become increasingly important. The existing technology generally uses shallow trench isolation (STI) technology to achieve isolation of active devices.
[0003] At present, in the BCD (Bipolar-CMOS-DMOS) shallow trench process, it is found through the failure analysis (FA) of the test mode that the shoulder (AA shoulder) where the active area and the shallow trench overlap is prone to cause the problem of time-dependent dielectric breakdown (TDDB) failure. Among them, TDDB refers to the phenomenon that under certain voltage and temperature conditions, the dielectric layer (usually the gate oxide) of the device gradually degrades over time and eventually leads to breakdown. The timing-dependent dielectric breakdown lifetime can be used to test and analyze it.
[0004] Therefore, it is necessary to provide a method for preparing a shallow trench structure. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a shallow trench structure, so as to solve the problem that the prior art easily causes TDDB failure in the shallow trench process.
[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a shallow trench structure, comprising the following steps:
[0007] providing a silicon substrate;
[0008] forming a pad oxide layer and a silicon nitride layer on the pad oxide layer on the silicon substrate;
[0009] Patterning the silicon nitride layer and the pad oxide layer to form an etching window exposing the silicon substrate;
[0010] Introducing an etching gas into the etching chamber, performing free radical etching based on the etching window, and the free radicals provided by the etching gas include fluorine free radicals and oxygen free radicals;
[0011] removing the silicon oxide layer to expose the silicon substrate;
[0012] The silicon substrate is etched to form shallow trenches, and the silicon substrate between adjacent shallow trenches constitutes an active area.
[0013] Optionally, when the thickness of the pad oxide layer is recorded as A, the width of the silicon nitride layer before free radical etching is recorded as F, and the width of the silicon nitride layer after free radical etching is recorded as G, then And / or when the thickness of the pad oxide layer is recorded as A, and the shoulder width of the active region is recorded as B, then
[0014] Optionally, when the thickness of the pad oxide layer is recorded as A, the width of the silicon nitride layer before free radical etching is recorded as F, and the width of the silicon nitride layer after free radical etching is recorded as G, then And / or when the thickness of the pad oxide layer is recorded as A, and the shoulder width of the active region is recorded as B, then
[0015] Optionally, the angle between the line connecting the end points of the side shoulders of the active region and the horizontal plane is denoted as θ, and the value range of θ is 25°≤θ≤40°.
[0016] Optionally, the gas in the etching gas that provides the fluorine free radicals includes carbon tetrafluoride or nitrogen trifluoride; and the gas in the etching gas that provides the oxygen free radicals includes oxygen.
[0017] Optionally, the flow rate of the etching gas ranges from 50 sccm to 200 sccm; and / or the pressure of the etching gas ranges from 30 mT to 100 mT; and / or the power of the etching gas ranges from 500 W to 1000 W.
[0018] Optionally, before patterning the silicon nitride layer and the pad oxide layer, the upper surface of the silicon nitride layer further includes an anti-reflective coating, and the anti-reflective coating includes a silicon oxynitride layer.
[0019] Optionally, the method further includes forming an isolation layer in the shallow trench and removing the silicon nitride layer and the pad oxide layer.
[0020] Optionally, the isolation layer includes a silicon oxide isolation layer, and a method of forming the silicon oxide isolation layer includes one or a combination of thermal oxidation, chemical vapor deposition, and physical vapor deposition.
[0021] Optionally, the method of removing the silicon nitride layer includes a chemical mechanical polishing method, and the method of removing the pad oxide layer includes a wet etching method.
[0022] As described above, the preparation method of the shallow trench structure of the present invention uses free radical etching to allow fluorine free radicals to react with the silicon nitride layer to consume part of the silicon nitride layer, and to allow oxygen free radicals to react with the silicon substrate to generate a silicon oxide layer to protect the silicon substrate, thereby reducing the width of the silicon nitride layer, thereby improving the voltage resistance of the device and effectively solving the problem of TDDB failure. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a schematic diagram of the process flow of preparing a shallow trench structure in an embodiment of the present invention.
[0024] Figure 2 It is a schematic diagram of the structure after the silicon nitride layer and the pad oxide layer are patterned in an embodiment of the present invention.
[0025] Figure 3 It is a state diagram showing free radical etching in an embodiment of the present invention.
[0026] Figure 4 Shown is a schematic diagram of the structure after free radical etching in an embodiment of the present invention.
[0027] Figure 5 It is a schematic diagram of the structure after shallow trenches are formed in an embodiment of the present invention.
[0028] Description of Reference Numerals
[0029] 100 Silicon substrate
[0030] 200 Pad Oxide
[0031] 300 Silicon nitride layer
[0032] 301 Silicon tetrafluoride
[0033] 400 Silicon oxide layer
[0034] 500 Shallow Groove DETAILED DESCRIPTION
[0035] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0036] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0037] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.
[0038] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0039] like Figure 1 This embodiment provides a method for preparing a shallow trench structure, comprising the following steps:
[0040] S1: Provide silicon substrate;
[0041] S2: forming a pad oxide layer and a silicon nitride layer on the pad oxide layer on the silicon substrate;
[0042] S3: patterning the silicon nitride layer and the pad oxide layer to form an etching window exposing the silicon substrate;
[0043] S4: introducing an etching gas into the etching chamber, performing free radical etching based on the etching window, and the free radicals provided by the etching gas include fluorine free radicals and oxygen free radicals;
[0044] S5: removing the silicon oxide layer to expose the silicon substrate;
[0045] S6: etching the silicon substrate to form shallow trenches, and the silicon substrate between adjacent shallow trenches constitutes an active area.
[0046] The preparation method of the shallow trench structure of the present embodiment uses the free radical etching to make the fluorine free radical react with the silicon nitride layer to consume part of the silicon nitride layer, and make the oxygen free radical react with the silicon substrate to generate the silicon oxide layer to protect the silicon substrate, thereby reducing the width of the silicon nitride layer, thereby improving the voltage resistance of the device and effectively solving the problem of TDDB failure.
[0047] The following is in conjunction with the instruction manual Figure 2 to Figure 5 , the preparation of the shallow trench structure is further explained.
[0048] First, see Figure 1 and Figure 2 , perform step S1 and provide a silicon substrate 100.
[0049] Specifically, the silicon substrate 100 may include, for example, a doped or undoped silicon substrate, a silicon-on-insulator substrate, etc. The size and specific type of the silicon substrate 100 are not excessively limited herein.
[0050] Next, see Figure 1 and Figure 2 , performing step S2 to form a pad oxide layer 200 on the silicon substrate 100 and a silicon nitride layer 300 located on the pad oxide layer 200 .
[0051] In this embodiment, the pad oxide layer 200 stacked from bottom to top and the silicon nitride layer 300 located on the pad oxide layer 200 are formed on the silicon substrate 100. The silicon nitride layer 300 is used as an etching hard mask to be suitable for patterning of small feature size and high aspect ratio (HAR) structure. The pad oxide layer 200 located between the silicon nitride layer 300 and the silicon substrate 100 can reduce the stress between the silicon nitride layer 300 and the silicon substrate 100, and avoid the phenomenon of silicon wafer cracking caused by stress concentration due to lattice constant mismatch between the silicon nitride layer 300 and the silicon substrate 100. In addition, the application of the pad oxide layer 200 can also help form a rounded wrap angle in the manufacturing process of STI, thereby optimizing the structure and performance of STI.
[0052] Next, see Figure 1 and Figure 2 , executing step S3 , patterning the silicon nitride layer 300 and the pad oxide layer 200 to form an etching window exposing the silicon substrate 100 .
[0053] Specifically, a patterned photoresist layer (not shown) may be formed on the silicon nitride layer 300. The silicon nitride layer 300 and the pad oxide layer 200 are sequentially etched based on the patterned photoresist layer, and then the remaining photoresist layer is removed by an ashing process to form an etching window to expose the silicon substrate 100. Figure 2 , illustrates a schematic diagram of the structure after etching, wherein the etching window penetrates the silicon nitride layer 300 and the pad oxide layer 200 , and the bottom is located in the silicon substrate 100 .
[0054] In another embodiment, an anti-reflective coating (not shown) may also be formed on the surface of the silicon nitride layer 300 to reduce the reflection of light during etching, reduce the standing wave effect, reduce the wavy sidewall of the pattern of the photoresist layer, and improve the photolithography accuracy. The anti-reflective coating may include, for example, a silicon oxynitride layer.
[0055] Next, see Figure 1 , Figure 3 and Figure 4 , execute step S4, introduce etching gas into the etching chamber, perform free radical etching based on the etching window, and the free radicals provided by the etching gas include fluorine free radicals and oxygen free radicals, the fluorine free radicals react with the silicon nitride layer 300 to generate silicon tetrafluoride 301, and the oxygen free radicals react with the silicon substrate 100 to generate a silicon oxide layer 400.
[0056] As an example, the fluorine radicals (F * ) gas includes carbon tetrafluoride (CF4) or nitrogen trifluoride (NF3), and the oxygen free radicals (O * ) gases include oxygen (O2).
[0057] Specifically, when the etching gas is introduced into the etching chamber, the carbon tetrafluoride and the oxygen may undergo the following reaction:
[0058] CF4→CF X * +F *
[0059] O2→2O *
[0060] The generated fluorine radicals react with the silicon nitride layer 300 to generate the silicon tetrafluoride 301 (SiF4), and the generated oxygen radicals react with the silicon substrate 100 to generate the silicon oxide layer 400 (SiO2), that is, the following reaction is performed:
[0061] SiN+F * →SiF4↑
[0062] Si+O * →SiO2
[0063] Among them, since the silicon tetrafluoride 301 is in a gaseous state, the formation of the silicon tetrafluoride 301 will consume part of the silicon nitride layer 300, so that the width of the silicon nitride layer 300 is reduced from the width F before the free radical etching to the width G after the free radical etching; and since the silicon oxide layer 400 is in a solid state, it can protect the silicon substrate 100, such as Figure 5 The width B in .
[0064] As an example, the flow range of the etching gas may be 50 sccm to 200 sccm, such as 50 sccm, 100 sccm, 150 sccm, 200 sccm, etc.; the pressure range may be 30 mT to 100 mT, such as 30 mT, 50 mT, 80 mT, 100 mT, etc.; the power range may be 500 W to 1000 W, such as 500 W, 800 W, 1000 W, etc.
[0065] The process parameters of the etching gas can be adjusted as needed, wherein the flow ratio of the carbon tetrafluoride or the nitrogen trifluoride to the oxygen can be, for example, 2:1, 2.5:1, 3:1, etc.
[0066] Next, see Figure 1 and Figure 5 , perform step S5 to remove the silicon oxide layer 400 to expose the silicon substrate 100.
[0067] Specifically, the method for removing the silicon oxide layer 400 may include wet etching, and the etching solution may be, for example, a hydrofluoric acid solution, etc., but the method for removing the silicon oxide layer 400 is not limited thereto.
[0068] Next, see Figure 1 and Figure 5 , step S6 is performed to etch the silicon substrate 100 to form shallow trenches 500, and the silicon substrate 100 between adjacent shallow trenches 500 constitutes an active area. The shallow trenches 500 may be formed by dry etching, and the specific etching process is not limited here.
[0069] When the thickness of the pad oxide layer 200 is recorded as A, the width of the silicon nitride layer 300 before free radical etching is recorded as F, and the width of the silicon nitride layer 300 after free radical etching is recorded as G, then If Best certainly The ratio can also be 2.55, 2.80, 3, etc.
[0070] When the thickness of the pad oxide layer 200 is recorded as A, and the shoulder width of the active region is recorded as B, then If Best Of course, the ratio of A to B can also be 2.3, 2.56, 2.60, 2.80, etc.
[0071] like Figure 5If the angle between the side shoulder endpoints of the active area and the horizontal plane is recorded as θ, the value range of θ is 25°≤θ≤40°, such as 29°≤θ≤36°. Of course, the angle θ can also be 29°, 30°, 35°, 36°, etc.
[0072] Next, the process also includes forming an isolation layer (not shown) in the shallow trench 500 and removing the silicon nitride layer 300 and the pad oxide layer 200 .
[0073] The isolation layer may include a silicon oxide isolation layer, and a method for forming the silicon oxide isolation layer may include one or a combination of thermal oxidation, chemical vapor deposition, and physical vapor deposition. The method for removing the silicon nitride layer 300 may include a chemical mechanical polishing method, and the method for removing the pad oxide layer 200 may include a wet etching method.
[0074] When the existing shallow trench structure that has not been prepared by the free radical etching is tested for TDDB, it is found that the morphology of the side shoulder of the active area has a strong correlation with the TDDB. Under the same test conditions, a comparative test of TDDB between the existing shallow trench structure that has not been prepared by the free radical etching and the shallow trench structure prepared by the free radical etching in this embodiment is conducted. It is found that the TDDB of the shallow trench structure that has not been prepared by the free radical etching is 11 years, while the TDDB of the shallow trench structure that has been prepared by the free radical etching in this embodiment is 162 years.
[0075] In summary, the preparation method of the shallow trench structure of the present invention uses free radical etching to make the fluorine free radicals react with the silicon nitride layer to generate silicon tetrafluoride to consume part of the silicon nitride layer, and to make the oxygen free radicals react with the silicon substrate to generate a silicon oxide layer to protect the silicon substrate, thereby improving the ratio of the pad oxide layer to the silicon nitride layer, thereby improving the voltage resistance of the device and effectively solving the problem of TDDB failure.
[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a shallow trench structure, characterized in that: The following steps are involved: providing a silicon substrate; forming a pad oxide layer and a silicon nitride layer on the pad oxide layer on the silicon substrate; Patterning the silicon nitride layer and the pad oxide layer to form an etching window exposing the silicon substrate; Introducing an etching gas into the etching chamber, performing free radical etching based on the etching window, and the free radicals provided by the etching gas include fluorine free radicals and oxygen free radicals; removing the silicon oxide layer to expose the silicon substrate; The silicon substrate is etched to form shallow trenches, and the silicon substrate between adjacent shallow trenches constitutes an active area.
2. The method for preparing a shallow trench structure according to claim 1, characterized in that: When the thickness of the pad oxide layer is recorded as A, the width of the silicon nitride layer before free radical etching is recorded as F, and the width of the silicon nitride layer after free radical etching is recorded as G, then And / or when the thickness of the pad oxide layer is recorded as A, and the shoulder width of the active region is recorded as B, then 3. The method for preparing a shallow trench structure according to claim 1, characterized in that: When the thickness of the pad oxide layer is recorded as A, the width of the silicon nitride layer before free radical etching is recorded as F, and the width of the silicon nitride layer after free radical etching is recorded as G, then And / or when the thickness of the pad oxide layer is recorded as A, and the shoulder width of the active region is recorded as B, then 4. The method for preparing a shallow trench structure according to claim 1, characterized in that: The angle between the line connecting the end points of the side shoulders of the active region and the horizontal plane is denoted as θ, and the value range of θ is 25°≤θ≤40°.
5. The method for preparing a shallow trench structure according to claim 1, characterized in that: The gas in the etching gas that provides the fluorine free radicals includes carbon tetrafluoride or nitrogen trifluoride; and / or the gas in the etching gas that provides the oxygen free radicals includes oxygen.
6. The method for preparing a shallow trench structure according to claim 1, characterized in that: The flow rate of the etching gas is in the range of 50 sccm to 200 sccm; and / or the pressure of the etching gas is in the range of 30 mT to 100 mT; and / or the power of the etching gas is in the range of 500 W to 1000 W.
7. The method for preparing a shallow trench structure according to claim 1, characterized in that: Before patterning the silicon nitride layer and the pad oxide layer, the upper surface of the silicon nitride layer further includes an anti-reflective coating, and the anti-reflective coating includes a silicon oxynitride layer.
8. The method for preparing a shallow trench structure according to claim 1, characterized in that: The method also includes the steps of forming an isolation layer in the shallow trench and removing the silicon nitride layer and the pad oxide layer.
9. The method for preparing a shallow trench structure according to claim 8, characterized in that: The isolation layer comprises a silicon oxide isolation layer, and a method of forming the silicon oxide isolation layer comprises one or a combination of thermal oxidation, chemical vapor deposition, and physical vapor deposition.
10. The method for preparing a shallow trench structure according to claim 8, characterized in that: The method of removing the silicon nitride layer includes a chemical mechanical polishing method, and the method of removing the pad oxide layer includes a wet etching method.