Method of forming pattern, package and method of manufacturing package

Abstract

A method of forming a pattern includes at least the following steps. A first dielectric layer having a first opening is provided. A first seed layer and a first conductive layer are deposited in the first opening. A portion of the first conductive layer is removed to form a recess. A hole migration barrier layer and a second conductive layer are deposited in the recess such that the first seed layer, the first conductive layer, the hole migration barrier layer, and the second conductive layer form a first pattern.

Description

Technical Field

[0001] The embodiments of the present invention relate to a method for forming a pattern, a package and a method for manufacturing the package. More specifically, the embodiments of the present invention relate to a method for forming a pattern, a package and a method for manufacturing the package having a void migration barrier layer. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic devices such as mobile phones and other mobile electronic devices are usually manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged together with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer-level packaging. For example, patterning technology plays an important role in wafer-level packaging. How to ensure the quality of the pattern and the simplicity of the process has become a challenge in this field. Summary of the invention

[0003] A method for forming a pattern includes at least the following steps: providing a first dielectric layer having a first opening; depositing a first seed layer and a first conductive layer in the first opening; removing a portion of the first conductive layer to form a recess; depositing a void migration barrier layer and a second conductive layer in the recess, so that the first seed layer, the first conductive layer, the void migration barrier layer and the second conductive layer form a first pattern.

[0004] A package includes a first tube core, a first encapsulation body and a redistribution wiring structure. The first encapsulation body laterally encapsulates the first tube core. The redistribution wiring structure is configured on the first tube core and the first encapsulation body. The redistribution wiring structure includes a first dielectric layer and a first conductive pattern embedded in the first dielectric layer. The first conductive pattern includes a seed layer, a first conductive layer, a void migration barrier layer and a second conductive layer. The void migration barrier layer is sandwiched between the first conductive layer and the second conductive layer.

[0005] A method for manufacturing a package includes at least the following steps. A tube core is provided. The tube core is encapsulated by an encapsulation body. A redistribution wiring structure is formed on the tube core and the encapsulation body. The redistribution wiring structure is formed by at least the following steps. A first dielectric layer is formed on the tube core. The first dielectric layer has a first opening. The first seed layer and the first conductive layer are filled into the first opening. A portion of the first conductive layer is removed to form a recess. A vacancy migration barrier layer and a second conductive layer are filled into the recess, so that the first seed layer, the first conductive layer, the vacancy migration barrier layer and the second conductive layer form a first conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1N is a schematic cross-sectional view of a method for forming a pattern according to some embodiments of the present disclosure.

[0008] Figure 2A as well as Figure 2B According to this disclosure Figure 1F Schematic cross-sectional views of some alternative embodiments.

[0009] FIG. 3A to FIG. 3C According to this disclosure Figure 1F 0014] Figure 2 is a top view of various embodiments of the structure in FIG.

[0010] FIG. 4A to FIG. 4N is a schematic cross-sectional view of a manufacturing process of a package according to some embodiments of the present disclosure.

[0011] Figure 5 is a schematic cross-sectional view of a package according to some alternative embodiments of the present disclosure.

[0012] Figure 6 is a schematic cross-sectional view of a package according to some alternative embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and is not itself indicative of the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate to enable testing of the 3D package or 3DIC, use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce cost.

[0016] Figures 1A to 1N is a schematic cross-sectional view of a method for forming a pattern according to some embodiments of the present disclosure. Figure 1A , providing a first dielectric layer 10. In some embodiments, the material of the first dielectric layer 10 includes polyimide, epoxy resin, acrylic resin, phenolic resin, polybenzoxazole (PBO), silicon carbide nitride (SiCN), silicon carbon nitride oxide (SiCON), benzocyclobutene (BCB), silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), molding compound, undoped silicate glass (undoped silicate glass, USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), metal oxides (e.g., ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO), metal nitrides (e.g., TiN, TaN, WN, TiAlN, TaCN), silicates (e.g., HfSiO, HfSiON, LaSiO, AlSiO), combinations thereof, etc.

[0017] In some embodiments, the first dielectric layer 10 is formed by a suitable manufacturing technique, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), thermal oxidation, some other suitable deposition or growth technique, or a combination thereof. In some embodiments, the first dielectric layer 10 is formed on a substrate (not shown). Depending on the application and location of the pattern to be formed later, the substrate can be made of a dielectric material, a metal material, or a semiconductor material.

[0018] Reference Figure 1B , forming a first opening OP1 in the first dielectric layer 10. In some embodiments, the first dielectric layer 10 is patterned by a photolithography process and an etching process to form the first opening OP1. The etching process includes, for example, a wet etching process or a dry etching process. An example of a wet etching process includes chemical etching, and an example of a dry etching process includes plasma etching.

[0019] Reference Figure 1C , a first seed material layer 22' is conformally formed on the first dielectric layer 10. For example, a first portion of the first seed material layer 22' is formed on the top surface of the first dielectric layer 10, and a second portion of the first seed material layer 22' extends into the first opening OP1 of the first dielectric layer 10. In other words, the first seed material layer 22' covers the sidewalls and the bottom of the first opening OP1. In some embodiments, the first seed material layer 22' is formed by a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the first seed material layer 22' is composed of two sub-layers (not shown). The first sub-layer may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sub-layer may include copper, copper alloy or other suitable materials.

[0020] Thereafter, a first conductive material layer 24' is formed on the first seed material layer 22'. In some embodiments, the first conductive material layer 24' also extends into the first opening OP1 of the first dielectric layer 10 to completely fill the first opening OP1. In some embodiments, the first conductive material layer 24' is formed by a sputtering process, a PVD process, a plating process, etc. The plating process is, for example, an electroplating process, an electroless plating process, an immersion plating process, etc. In some embodiments, the first conductive material layer 24' is made of aluminum, titanium, copper, tungsten, and / or alloys thereof.

[0021] Reference Figure 1C as well as Figure 1D , remove a portion of the first seed material layer 22' and a portion of the first conductive material layer 24'. Figure 1C The first seed material layer 22' and the first conductive material layer 24' are thinned until the underlying first dielectric layer 10 is exposed, thereby forming the first seed layer 22 and the first conductive layer 24 in the first opening OP1. That is, the first seed layer 22 and the first conductive layer 24 are embedded in the first dielectric layer 10. In some embodiments, the first seed material layer 22' and the first conductive material layer 24' are thinned by a grinding process, an etching process, etc. The grinding process includes, for example, a mechanical grinding process, a chemical mechanical polishing (CMP) process, etc. Figure 1D As shown, the first seed layer 22 surrounds the first conductive layer 24. For example, the first seed layer 22 is Figure 1D The cross-sectional view of FIG. 2 shows a U-shape to surround the first conductive layer 24 . In other words, the first seed layer 22 covers the sidewalls and the bottom surface of the first conductive layer 24 .

[0022] Reference Figure 1E , a patterned photoresist layer PR1 is formed on the first dielectric layer 10, the first seed layer 22, and the first conductive layer 24. In some embodiments, the patterned photoresist layer PR1 is made of a photosensitive material. In some embodiments, the patterned photoresist layer PR1 is formed by performing an exposure process and a development process on a photoresist layer (not shown) using a photomask PM as a mask. That is, the pattern on the photomask PM is transferred to the patterned photoresist layer PR1. For example, Figure 1E As shown, the patterned photoresist layer PR1 has a first hole AP1 exposing a portion of the first conductive layer 24 .

[0023] Reference Figure 1E as well as Figure 1F , removing a portion of the first conductive layer 24 to form a recess R. For example, the first conductive layer 24 may be subjected to an etching process using the patterned photoresist layer PR1 as a mask to form a recess R in the first conductive layer 24. That is, the position of the recess R corresponds to the position of the first hole AP1 of the patterned photoresist layer PR1. In some embodiments, the etching process includes, for example, a wet etching process or a dry etching process. Examples of wet etching processes include chemical etching, and examples of dry etching processes include plasma etching. After the recess R is formed, the patterned photoresist layer PR1 is removed by a dry stripping process, a wet stripping process, or other suitable processes.

[0024] like Figure 1FAs shown in FIG. 1 , the recess R has substantially vertical sidewalls. Meanwhile, the bottom of the recess R is substantially flat. In other words, the recess R is substantially flat. Figure 1F The cross-sectional view of the recess R is rectangular in shape. However, the present disclosure is not limited thereto. Depending on different etching processes or etching recipes, the recess R may have different profiles in the cross-sectional view. Figure 2A as well as Figure 2B Describes alternative shapes of the recess R.

[0025] Figure 2A as well as Figure 2B According to this disclosure Figure 1F Schematic cross-sectional views of some alternative embodiments of. Figure 2A , the recess R has an inclined sidewall. At the same time, the bottom of the recess R is substantially flat. In other words, the recess R is Figure 2A The cross-sectional view of the Figure 2B , the depression has curved sidewalls. At the same time, the bottom of the depression R is also curved. In other words, the depression R is Figure 2B The cross-sectional view of the embodiment of the present invention shows a hemispherical shape.

[0026] Depending on the shape of the pattern on the photomask PM and the shape of the first hole AP1 of the patterned photoresist layer PR1, the recess R may have different shapes from a top view. FIG. 3A to FIG. 3C A top view of the recess R is described.

[0027] FIG. 3A to FIG. 3C According to this disclosure Figure 1F A top view of various embodiments of the structure in FIG. Figure 3A , the depression R appears rectangular in a top view. For example, the depression R may be rectangular or square in a top view. Figure 3B , the depression R is circular in a top view. For example, the depression R may be circular in a top view. Figure 3C , the recess R presents an elliptical shape in a top view. For example, the recess R may be an elliptical shape when viewed from a top view.

[0028] Reference Figure 1G, a void migration barrier material layer 26' is conformally formed on the first dielectric layer 10, the first seed layer 22 and the first conductive layer 24. For example, a first portion of the void migration barrier material layer 26' is formed on the top surface of the first dielectric layer 10, the top surface of the first seed layer 22 and the topmost surface of the first conductive layer 24, while a second portion of the void migration barrier material layer 26' extends into the recess R. In other words, the void migration barrier material layer 26' covers the sidewalls and bottom surface of the recess R. In some embodiments, the void migration barrier material layer 26' is formed by a sputtering process, a PVD process, etc. In some embodiments, the void migration barrier material layer 26' is composed of two sublayers (not shown). The first sublayer may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer may include copper, copper alloy or other suitable materials.

[0029] Thereafter, a second conductive material layer 28' is formed on the void migration barrier material layer 26'. In some embodiments, the second conductive material layer 28' also extends into the recess R to completely fill the recess R. In some embodiments, the second conductive material layer 28' is formed by a sputtering process, a PVD process, a plating process, etc. The plating process is, for example, an electroplating process, an electroless plating process, an immersion plating process, etc. In some embodiments, the second conductive material layer 28' is made of aluminum, titanium, copper, tungsten, and / or alloys thereof. In some embodiments, the void migration barrier material layer 26' can serve as a seed layer for depositing the second conductive material layer 28'.

[0030] Reference Figure 1G as well as Figure 1H , remove the portion of the vacancy migration barrier material layer 26' and the portion of the second conductive material layer 28'. Figure 1G The vacancy migration barrier material layer 26' and the second conductive material layer 28' are thinned until the underlying first dielectric layer 10, the underlying first seed layer 22 and the underlying first conductive layer 24 are exposed, thereby forming the vacancy migration barrier material layer 26 and the second conductive layer 28 in the recess R. In some embodiments, the vacancy migration barrier material layer 26' and the second conductive material layer 28' are thinned by a grinding process, an etching process, etc. The grinding process includes, for example, a mechanical grinding process, a CMP process, etc.

[0031] In some embodiments, the vacancy migration barrier layer 26 surrounds the second conductive layer 28. For example, the vacancy migration barrier layer 26 is formed on the Figure 1H The cross-sectional view of FIG. 2 shows a U-shape to surround the second conductive layer 28. In other words, the vacancy migration barrier layer 26 covers the sidewalls and bottom surface of the second conductive layer 28. Figure 1HAs shown, the vacancy migration barrier layer 26 and the second conductive layer 28 are embedded in the first conductive layer 24. For example, the vacancy migration barrier layer 26 is spatially separated from the first seed layer 22. In some embodiments, the first conductive layer 24 is sandwiched between the first seed layer 22 and the vacancy migration barrier layer 26. At the same time, the vacancy migration barrier layer 26 is sandwiched between the first conductive layer 24 and the second conductive layer 28.

[0032] In some embodiments, the material of the first seed layer 22 is the same as the material of the vacancy migration barrier layer 26. However, the present disclosure is not limited thereto. In some alternative embodiments, the material of the first seed layer 22 is different from the material of the vacancy migration barrier layer 26. For example, the first seed layer 22 is composed of two sublayers (not shown). The first sublayer of the first seed layer 22 may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer of the first seed layer 22 may include copper, copper alloy or other suitable materials. Similarly, the vacancy migration barrier layer 26 is also composed of two sublayers (not shown). The first sublayer of the vacancy migration barrier layer 26 may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer of the vacancy migration barrier layer 26 may include copper, copper alloy or other suitable materials.

[0033] In some embodiments, the material of the first conductive layer 24 is the same as the material of the second conductive layer 28. However, the present disclosure is not limited thereto. In some alternative embodiments, the material of the first conductive layer 24 is different from the material of the second conductive layer 28. For example, the first conductive layer 24 and the second conductive layer 28 are respectively made of aluminum, titanium, copper, tungsten and / or alloys thereof. In some embodiments, the material of the first conductive layer 24 and the material of the second conductive layer 28 include copper.

[0034] In some embodiments, the first seed layer 22, the first conductive layer 24, the vacancy migration barrier layer 26, and the second conductive layer 28 are collectively referred to as a first pattern 20. Figure 1H As shown, the first pattern 20 completely fills the first opening OP1 . In other words, the first pattern 20 is embedded in the first dielectric layer 10 .

[0035] Reference Fig. 1I, a second dielectric layer 30 and a third dielectric layer 40 are sequentially deposited on the first dielectric layer 10 and the first pattern 20 . The materials of the second dielectric layer 30 and the third dielectric layer 40 may be the same as or different from the material of the first dielectric layer 10 . For example, the material of the second dielectric layer 30 and the material of the third dielectric layer 40 include polyimide, epoxy resin, acrylic resin, phenolic resin, PBO, SiCN, SiCON, BCB, SiN, SiO, SiON, molding compound, USG, PSG, BSG, BPSG, metal oxides (e.g., ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO), metal nitrides (e.g., TiN, TaN, WN, TiAlN, TaCN), silicates (e.g., HfSiO, HfSiON, LaSiO, AlSiO), combinations thereof, etc.

[0036] In some embodiments, the second dielectric layer 30 and the third dielectric layer 40 are formed by a suitable fabrication technique, such as spin coating, CVD, PECVD, ALD, thermal oxidation, some other suitable deposition or growth technique, or a combination thereof.

[0037] Reference Figure 1J , a patterned photoresist layer PR2 is formed on the third dielectric layer 40. In some embodiments, the patterned photoresist layer PR2 is made of a photosensitive material. In some embodiments, the patterned photoresist layer PR2 is formed by performing an exposure process and a development process on a photoresist layer (not shown) using a photomask PM' as a mask. That is, the pattern on the photomask PM' is transferred to the patterned photoresist layer PR2. For example, Figure 1J As shown, the patterned photoresist layer PR2 has a second hole AP2 exposing a portion of the third dielectric layer 40 .

[0038] Reference Figure 1J as well as Figure 1K , a portion of the third dielectric layer 40 is removed to form a second opening OP2 in the third dielectric layer 40. For example, the third dielectric layer 40 can be subjected to an etching process using the patterned photoresist layer PR2 as a mask to form the second opening OP2. That is, the position of the second opening OP2 corresponds to the position of the second hole AP2 of the patterned photoresist layer PR2. In some embodiments, the etching process includes, for example, a wet etching process or a dry etching process. Examples of wet etching processes include chemical etching, and examples of dry etching processes include plasma etching. After forming the second opening OP2, the patterned photoresist layer PR2 is removed by a dry stripping process, a wet stripping process, or other suitable processes.

[0039] Reference Figure 1L , a patterned photoresist layer PR3 is formed on the second dielectric layer 30 and the third dielectric layer 40. In some embodiments, the patterned photoresist layer PR3 extends into the second opening OP2 of the third dielectric layer 40. In some embodiments, the patterned photoresist layer PR3 is made of a photosensitive material. In some embodiments, the patterned photoresist layer PR3 is formed by performing an exposure process and a development process on a photoresist layer (not shown) using a photomask PM as a mask. That is, the pattern on the photomask PM is transferred to the patterned photoresist layer PR3. For example, Figure 1L As shown, the patterned photoresist layer PR3 has a third hole AP3 exposing a portion of the second dielectric layer 30. In some embodiments, Figure 1L The photomask PM in Figure 1E In other words, Figure 1L The size and shape of the second hole AP3 in the patterned photoresist layer PR3 are similar to Figure 1E The size and shape of the first hole AP1 in the patterned photoresist layer PR1 are the same. In some embodiments, Figure 1L The third hole AP3 of the patterned photoresist layer PR3 is smaller than Figure 1J A second hole AP2 in the patterned photoresist layer PR2.

[0040] Reference Figure 1L as well as Figure 1M , removing a portion of the second dielectric layer 30 to form a third opening OP3 in the second dielectric layer 30. For example, the second dielectric layer 30 can be subjected to an etching process using the patterned photoresist layer PR3 as a mask to form the third opening OP3. That is, the position of the third opening OP3 corresponds to the position of the third hole AP3 of the patterned photoresist layer PR3. In some embodiments, the etching process includes, for example, a wet etching process or a dry etching process. Examples of wet etching processes include chemical etching, and examples of dry etching processes include plasma etching. After forming the third opening OP3, the patterned photoresist layer PR3 is removed by a dry stripping process, a wet stripping process, or other suitable processes. Figure 1M As shown, the third opening OP3 penetrates the second dielectric layer 30 to expose a portion of the second conductive layer 28. Meanwhile, the second opening OP2 exposes the third opening OP3.

[0041] In some embodiments, due to the higher aspect ratio, the etching rate of the bottom of the second dielectric layer 30 may be slower than the etching rate of the top of the second dielectric layer 30. Therefore, the third opening OP3 is formed to have an inclined sidewall, such as Figure 1M As described above, due to the step of removing part of the first conductive layer 24 (such as Figure 1E as well as Figure 1F ) and a step of removing a portion of the second dielectric layer 30 (as shown Figure 1L as well as Figure 1M The same photomask PM is used as shown in FIG. 1 , so the size of the third opening OP3 can be the same as or slightly smaller than the size of the recess R (as shown in FIG. 1 ). Figure 1F In other words, the maximum width W of the third opening OP3 is OP3 Equal to or less than the width W of the second conductive layer 28 28 and the width W of the vacancy migration barrier layer 26 26 The sum of .

[0042] Reference Figure 1N , a second seed layer 52 and a third conductive layer 54 are deposited in the second opening OP2 and the third opening OP3. In some embodiments, the second seed layer 52 is formed by a sputtering process, a PVD process, etc. In some embodiments, the second seed layer 52 is composed of two sublayers (not shown). The first sublayer may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer may include copper, copper alloys or other suitable materials. In some embodiments, the third conductive layer 54 is formed by a sputtering process, a PVD process, a plating process, etc. The plating process is, for example, an electroplating process, an electroless electroplating process, an immersion plating process, etc. In some embodiments, the third conductive layer 54 is made of aluminum, titanium, copper, tungsten and / or their alloys. In some embodiments, the second seed layer 52 and the third conductive layer 54 are formed by the following steps. First, a second seed material layer (not shown) and a third conductive material layer (not shown) are formed on the third dielectric layer 40 and in the second opening OP2 and the third opening OP3. Afterwards, the second seed material layer and the third conductive material layer are thinned until the underlying third dielectric layer 40 is exposed, thereby forming a second seed layer 52 and a third conductive layer 54 in the second opening OP2 and the third opening OP3. In some embodiments, the second seed material layer and the third conductive material layer are thinned by a grinding process, an etching process, etc. The grinding process includes, for example, a mechanical grinding process, a CMP process, etc.

[0043] like Figure 1N As shown, the second seed layer 52 surrounds the third conductive layer 54. For example, the second seed layer 52 covers the sidewalls and bottom surface of the third conductive layer 54. In some embodiments, the third conductive layer 54 Figure 1N In some embodiments, the second seed layer 52 and the third conductive layer 54 are collectively referred to as the second pattern 50. Figure 1N As shown, the second pattern 50 completely fills the second opening OP2 and the third opening OP3 . In other words, the second pattern 50 is embedded in the second dielectric layer 30 and the third dielectric layer 40 .

[0044] In some embodiments, Figures 1J to 1N The process shown in can be referred to as a "dual damascene" process. For example, the second pattern 50 can be divided into a through-hole portion 50a and a line portion 50b configured on the through-hole portion 50a. In some embodiments, the through-hole portion 50a corresponds to the second seed layer 52 and the third conductive layer 54 located in the third opening OP3. At the same time, the line portion 50b corresponds to the second seed layer 52 and the third conductive layer 54 located in the second opening OP2. In other words, the through-hole portion 50a is embedded in the second dielectric layer 30 and the line portion 50b is embedded in the third dielectric layer 40. In some embodiments, the through-hole portion 50a is connected to the line portion 50b. Figure 1N As shown, the second pattern 50 is in physical contact with the first pattern 20. For example, the through hole portion 50a of the second pattern 50 is in physical contact with the second conductive layer 28 of the first pattern 20. As described above, the size of the third opening OP3 can be the same as or slightly smaller than the size of the recess R (e.g., Figure 1F Since the through hole portion 50a is formed by filling the third opening OP3, the maximum width W of the through hole portion 50a is 50a Equal to or less than the width W of the second conductive layer 28 28 and the width W of the vacancy migration barrier layer 26 26 The sum of Figure 1N As shown, the second pattern 50 falls on the span of the second conductive layer 28 of the first pattern 20. For example, the through-hole portion 50a of the second pattern 50 falls on the span of the second conductive layer 28 of the first pattern 20. In some embodiments, the through-hole portion 50a is completely located within the span of the void migration barrier layer 26 and the second conductive layer 28. For example, in the top view, the edge of the through-hole portion 50a does not extend beyond the outer edge of the void migration barrier layer 26. In some embodiments, in the top view, the outline of the through-hole portion 50a completely overlaps with the outer outline of the void migration barrier layer 26. However, the present disclosure is not limited to this. In some alternative embodiments, in the top view, the outline of the through-hole portion 50a can be located within the boundary defined by the outer outline of the void migration barrier layer 26.

[0045] In some embodiments, the first conductive layer 24 and the second conductive layer 28 have intrinsic vacancy in their materials. When a dual damascene process is performed to form the second pattern 50 on the first pattern 20, the vacancy in the first conductive layer 24 and the second conductive layer 28 may migrate to the interface between the first pattern 20 and the second pattern 50 due to the tensile stress generated by the thermal expansion mismatch. Then, the vacancy may gather at the interface between the first pattern 20 and the second pattern 50 to form a gap, thereby causing the connection between the first pattern 20 and the second pattern 50 to fail. However, as shown in FIG. Figure 1NAs shown, the first pattern 20 has a void migration barrier layer 26 sandwiched between the first conductive layer 24 and the second conductive layer 28. The void migration barrier layer 26 can fully block the voids in the first conductive layer 24 from reaching the interface between the first pattern 20 and the second pattern 50. In other words, the voids in the first conductive layer 24 will gather around the void migration barrier layer 26 without affecting the connection between the first pattern 20 and the second pattern 50. Although some voids in the second conductive layer 28 may migrate to the interface between the first pattern 20 and the second pattern 50, the amount of these voids can be ignored due to the small size of the second conductive layer 28. Therefore, the voids in the second conductive layer 28 will not form a large enough gap to cause the connection failure between the first pattern 20 and the second pattern 50. In summary, the void migration barrier layer 26 in the first pattern 20 can solve the problem of connection failure between the first pattern 20 and the second pattern 50 caused by void migration, thereby improving the reliability of the device having the first pattern 20 and the second pattern 50.

[0046] In some embodiments, Figures 1A to 1N The method for forming patterns shown can be applicable to various applications. In some embodiments, the method for forming patterns can be used to form conductive features in a package. For example, a conductive pattern in an internal wiring structure within a die in a package or a conductive pattern in a redistribution wiring structure in a package can be formed by this method. Alternatively, the method for forming patterns can also be used to form conductive features in a field effect transistor (FET). For example, a gate contact in a FET can be formed by this method. It is worth noting that the components listed above are merely exemplary, and the present disclosure is not limited thereto. The above method for forming patterns is also applicable to forming any other patterns. The following will illustrate the use of the above method for forming patterns in a redistribution wiring structure of a package.

[0047] FIG. 4A to FIG. 4N is a schematic cross-sectional view of a manufacturing process of a packaged PKG according to some embodiments of the present disclosure. Figure 4A , providing a carrier C1. In some embodiments, the carrier C1 is made of silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, tape, or other suitable materials for structural support. In some embodiments, there are no active components and passive components in the carrier C1. In some embodiments, there is no wiring in the carrier C1. For example, the carrier C1 can be a blank substrate, which only serves to support the components without any signal transmission function.

[0048] like Figure 4AAs shown, a first die 100 is placed on a carrier C1. In some embodiments, the first die 100 includes a semiconductor substrate 110, a plurality of devices 120, an internal wiring structure 130, a plurality of semiconductor through vias (TSV) 140, a plurality of conductive pads 150, and a passivation layer 160. The semiconductor substrate 110 may be made of the following materials: elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The semiconductor substrate 110 may be a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc. In some embodiments, the device 120 is formed in the semiconductor substrate 110. The device 120 may include active elements (e.g., transistors, etc.) and / or passive elements (e.g., resistors, capacitors, inductors, etc.).

[0049] like Figure 4A As shown, the interconnect structure 130 is formed on the semiconductor substrate 110. In some embodiments, the interconnect structure 130 includes a dielectric layer 132, a plurality of conductive patterns 134, and a plurality of vias 136. For simplicity, the dielectric layer 132 is illustrated as a single dielectric layer, and the conductive patterns 134 are illustrated as being embedded in the dielectric layer 132. However, from the perspective of the manufacturing process, the dielectric layer 132 is composed of at least two dielectric layers, and the conductive patterns 134 are sandwiched between two adjacent dielectric layers. In some embodiments, the conductive patterns 134 at different levels are connected to each other through the vias 136. In other words, the conductive patterns 134 are electrically connected to each other through the vias 136. In some embodiments, the bottommost via 136 is connected to the device 120 embedded in the semiconductor substrate 110. In other words, the bottommost via 136 establishes an electrical connection between the device 120 and the conductive pattern 134 of the interconnect structure 130. In some embodiments, the bottom-most via 136 may be referred to as a “contact structure” of the device 120 .

[0050] In some embodiments, the material of the dielectric layer 132 includes polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO or any other suitable polymer dielectric material. The dielectric layer 132 can be formed by a suitable manufacturing technique, such as spin coating, CVD, PECVD, etc. In some embodiments, the material of the conductive pattern 134 and the via 136 includes aluminum, titanium, copper, nickel, tungsten or alloys thereof. The conductive pattern 134 and the via 136 can be formed by, for example, electroplating, deposition and / or photolithography and etching. In some embodiments, the conductive pattern 134 and the underlying via 136 are formed simultaneously. It is worth noting that Figure 4AThe number of dielectric layers 132, the number of conductive patterns 134, and the number of vias 136 shown are for illustration purposes only, and the present disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of dielectric layers 132, conductive patterns 134, or vias 136 may be formed depending on the circuit design.

[0051] In some embodiments, the TSVs 140 are embedded in the semiconductor substrate 110 and the dielectric layer 132 of the interconnect structure 130. That is, the TSVs 140 extend from the semiconductor substrate 110 to the interconnect structure 130. For example, a portion of each TSV 140 is embedded in the semiconductor substrate 110, while another portion of the same TSV 140 is embedded in the dielectric layer 132 of the interconnect structure 130. In some embodiments, the TSVs 140 directly contact the conductive pattern 134 to provide electrical connection to the interconnect structure 130.

[0052] like Figure 4A As shown, the conductive pad 150 is formed on the interconnect structure 130. In some embodiments, the conductive pad 150 is electrically connected to the conductive pattern 134 of the interconnect structure 130 through the topmost via 136. In some embodiments, the conductive pad 150 is used to establish an electrical connection with other components (not shown) or a die (not shown) that are subsequently formed or provided. In some alternative embodiments, the conductive pad 150 can be a test pad. In some embodiments, the conductive pad 150 is an aluminum pad, a copper pad, or other appropriate metal pad.

[0053] In some embodiments, the passivation layer 160 is formed on the interconnect structure 130 and the conductive pad 150. In some embodiments, the material of the passivation layer 160 includes an oxide, such as silicon oxide. Alternatively, the passivation layer 160 may include polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO or any other suitable polymer dielectric material. The passivation layer 160 may be formed by a suitable manufacturing technique, such as spin coating, CVD, PECVD, etc.

[0054] Reference Figure 4B, a first encapsulant 200 is formed on the carrier C1 to laterally encapsulate the first tube core 100. In some embodiments, the material of the first encapsulant 200 includes a molding compound or a polymer material (such as polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, a combination thereof, or other appropriate polymer-based dielectric materials). In some alternative embodiments, the first encapsulant 200 may include silicon oxide and / or silicon nitride. In some embodiments, the first encapsulant 200 further includes a filler. Alternatively, the first encapsulant 200 may not contain a filler. In some embodiments, the first encapsulant 200 is formed by a molding process (such as a compression molding process), a spin coating process, a CVD process, a PECVD process, an ALD process, etc. Figure 4B As shown, the top surface of the passivation layer 160 is substantially coplanar with the top surface of the first encapsulant 200. In some embodiments, the first encapsulant 200 may be referred to as a "gap fill oxide".

[0055] Reference Figure 4C A plurality of bonding vias 170 are formed to penetrate the passivation layer 160 and at least a portion of the dielectric layer 132 of the interconnect structure 130 to establish electrical connections with the conductive pattern 134 of the interconnect structure 130. In some embodiments, the bonding vias 170 may be considered as part of the first die 100. Figure 4C As shown, the first die 100 has an active surface AS1 and a back surface RS1 opposite to the active surface AS1 .

[0056] In some embodiments, the first die 100 is capable of performing a storage function. For example, the first die 100 may be a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a static random access memory (SRAM), etc. However, the disclosure is not limited thereto. In some alternative embodiments, the first die 100 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field programmable gate array (FPGA), etc.

[0057] like Figure 4CAs shown, a bonding layer 300 is formed on the first die 100 and the first encapsulant 200. For example, the bonding layer 300 is formed on the active surface AS1 of the first die 100. In some embodiments, the bonding layer 300 includes a dielectric layer 302 and a plurality of bonding pads 304. In some embodiments, the bonding pads 304 are embedded in the dielectric layer 302. In some embodiments, the bonding pads 304 of the bonding layer 300 are electrically connected to the bonding vias 170 of the first die 100. That is, the bonding vias 170 electrically connect the interconnect structure 130 to the bonding pads 304. In some embodiments, the bonding pads 304 are also electrically connected to some of the conductive pads 150 through the conductive vias located between the bonding pads 304 and the conductive pads 150. That is, in some embodiments, some of the conductive pads 150 are electrically floating, and some of the conductive pads 150 can transmit signals to the bonding pads 304.

[0058] In some embodiments, the bonding via 170 and the bonding pad 304 can be formed by a dual damascene process. For example, a dielectric layer 302 is first formed on the passivation layer 160. In some embodiments, the material of the dielectric layer 302 includes an oxide, such as silicon oxide. Alternatively, the dielectric layer 302 may include polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO or any other suitable polymer dielectric material. The dielectric layer 302 can be formed by a suitable manufacturing technique, such as spin coating, CVD, PECVD, etc. Subsequently, a groove and a via hole (not shown) are formed in the dielectric layer 302 and the passivation layer 160 by removing portions of the dielectric layer 302 and the passivation layer 160. In some embodiments, the width of the groove is greater than the width of the via hole. Thereafter, a conductive material (not shown) is filled into the via hole to form the bonding via 170. At the same time, a conductive material (not shown) is also filled into the groove to form the bonding pad 304. That is, the bonding through-hole 170 and the bonding pad 304 are formed by filling the via hole and the overlying groove (not shown) at the same time. However, the present disclosure is not limited to this. In some alternative embodiments, the bonding through-hole 170 can be formed before the dielectric layer 302 and the bonding pad 304. In some embodiments, the width of each bonding pad 304 can be greater than the width of each underlying bonding through-hole 170. In some embodiments, the bonding through-hole 170 and the bonding pad 304 include the same material. For example, the bonding through-hole 170 and the bonding pad 304 can be made of aluminum, titanium, copper, nickel, tungsten or an alloy thereof. In some embodiments, the top surface of the dielectric layer 302 and the top surface of the bonding pad 304 are substantially located at the same horizontal height to provide a suitable top surface 300a for hybrid bonding.

[0059] Reference Figure 4D, providing a second die 400 and a plurality of dummy dies 600. In some embodiments, the second die 400 includes a semiconductor substrate 410, a plurality of devices 420, an internal wiring structure 430, a plurality of conductive pads 440, a passivation layer 450, and a plurality of bonding vias 460. In some embodiments, the device 420 is formed in the semiconductor substrate 410. The semiconductor substrate 410 and the device 420 of the second die 400 are similar to the semiconductor substrate 110 and the device 120 of the first die 100, respectively, and thus will not be described in detail herein.

[0060] like Figure 4D As shown, the interconnect structure 430 is disposed on the semiconductor substrate 410. In some embodiments, the interconnect structure 430 is electrically connected to the device 420 formed in the semiconductor substrate 410. In some embodiments, the interconnect structure 430 includes a dielectric layer 432, a plurality of conductive patterns 434, and a plurality of vias 436. The dielectric layer 432, the conductive pattern 434, and the vias 436 of the interconnect structure 430 are similar to the dielectric layer 132, the conductive pattern 134, and the vias 136 of the interconnect structure 130, respectively, and thus will not be described in detail herein.

[0061] In some embodiments, the conductive pad 440, the passivation layer 450, and the bonding via 460 are formed on the interconnect structure 430. In some embodiments, the conductive pad 440, the passivation layer 450, and the bonding via 460 of the second die 400 are similar to the conductive pad 150, the passivation layer 160, and the bonding via 170 of the first die 100, respectively, and thus are not described in detail herein. In some embodiments, the conductive pad 440 is electrically connected to the interconnect structure 430. In some embodiments, the bonding via 460 is formed to penetrate the passivation layer 450 and at least a portion of the dielectric layer 432 of the interconnect structure 430 to establish an electrical connection with the conductive pattern 434 of the interconnect structure 430. That is, a portion of each bonding via 460 is embedded in the passivation layer 450, and another portion of the same bonding via 460 is embedded in the dielectric layer 432 of the interconnect structure 430.

[0062] like Figure 4D As shown, the second die 400 has an active surface AS2 and a rear surface RS2 opposite to the active surface AS2. In some embodiments, the second die 400 can perform a storage function. For example, the second die 400 can be a DRAM, RRAM, SRAM, etc. However, the present disclosure is not limited to this. In some alternative embodiments, the second die 400 can be a CPU die, a GPU die, an FPGA, etc.

[0063] like Figure 4DAs shown, a bonding layer 500 is formed on the second tube core 400. For example, the bonding layer 500 is formed on the active surface AS2 of the second tube core 400. In some embodiments, the bonding layer 500 includes a dielectric layer 502 and a plurality of bonding pads 504. The dielectric layer 502 and the bonding pads 504 of the bonding layer 500 are similar to the dielectric layer 302 and the bonding pads 304 of the bonding layer 300, respectively, so they are not repeated here. In some embodiments, the bonding pads 504 are electrically connected to the bonding through-holes 460. That is, the bonding through-holes 460 electrically connect the interconnect structure 430 to the bonding pads 504. In some embodiments, the bonding pads 504 are also electrically connected to the conductive pads 440. In some embodiments, the bottom surface of the dielectric layer 502 and the bottom surface of the bonding pads 504 are substantially located at the same horizontal height to provide a suitable bottom surface 500a for hybrid bonding.

[0064] In some embodiments, each dummy die 600 includes a semiconductor substrate 610, an interconnect structure 620, a conductive pad 630, and a passivation layer 640. The semiconductor substrate 610 of the dummy die 600 is similar to the semiconductor substrate 110 of the first die 100, and thus will not be described again.

[0065] like Figure 4D As shown, the interconnect structure 620 is disposed on the semiconductor substrate 610. In some embodiments, the interconnect structure 620 includes a dielectric layer 622, a plurality of conductive patterns 624, and a plurality of vias 626. The dielectric layer 622, the conductive patterns 624, and the vias 626 of the interconnect structure 620 are similar to the dielectric layer 132, the conductive patterns 134, and the vias 136 of the interconnect structure 130, respectively, and thus will not be described in detail herein.

[0066] In some embodiments, the conductive pad 630 and the passivation layer 640 are formed on the interconnect structure 620. In some embodiments, the conductive pad 630 and the passivation layer 640 of the dummy die 600 are similar to the conductive pad 150 and the passivation layer 160 of the first die 100, respectively, and thus are not described in detail herein. In some embodiments, the conductive pad 630 is electrically connected to the interconnect structure 620 via a via located between the conductive pad 630 and the interconnect structure 620.

[0067] like Figure 4D As shown, each dummy die 600 has an active surface AS3 and a rear surface RS3 opposite to the active surface AS3. In some embodiments, each dummy die 600 does not contain active components and passive components. For example, the dummy die 600 may not contribute to the operation of the subsequently formed package PKG.

[0068] like Figure 4DAs shown, a bonding layer 700 is formed on each dummy die 600. For example, the bonding layer 700 is formed on the active surface AS3 of the dummy die 600. In some embodiments, the bonding layer 700 includes a dielectric layer 702 and a plurality of bonding pads 704. The dielectric layer 702 and the bonding pads 704 of the bonding layer 700 are similar to the dielectric layer 302 and the bonding pads 304 of the bonding layer 300, respectively, so they are not repeated here. In some embodiments, the bonding pads 704 are electrically isolated from the dummy die 600. In other words, the bonding pads 704 are dummy bonding pads. In some embodiments, the bottom surface of the dielectric layer 702 and the bottom surface of the bonding pads 704 are substantially located at the same horizontal height to provide a suitable bottom surface 700a for hybrid bonding.

[0069] In some embodiments, the second die 400 and the dummy die 600 are placed on the bonding layer 300 so that the second die 400 and the dummy die 600 are bonded to the first die 100. In some embodiments, the second die 400 and the dummy die 600 can be bonded to the first die 100 through a hybrid bonding process. The hybrid bonding process will be described in detail below.

[0070] First, the second die 400 and the dummy die 600, on which the bonding layer 500 and the bonding layer 700 are respectively formed, are picked up and placed on the bonding layer 300, so that the second die 400 and the dummy die 600 are electrically connected to the first die 100. In some embodiments, the dummy die 600 is disposed adjacent to the second die 400. In some embodiments, the second die 400 and the dummy die 600 are placed so that the bottom surface 500a of the bonding layer 500 and the bottom surface 700a of the bonding layer 700 are in contact with the top surface 300a of the bonding layer 300. At the same time, the bonding pads 504 of the bonding layer 500 and the bonding pads 704 of the bonding layer 700 are substantially aligned with and in direct contact with the corresponding bonding pads 304 of the bonding layer 300. In some embodiments, in order to promote the hybrid bonding between the first tube core 100, the second tube core 200 and the dummy tube core 600, the bonding surfaces (i.e., the top surface 300a, the bottom surface 500a and the bottom surface 700a) of the bonding layers 300, 500, 700 can be surface prepared. The surface preparation can include, for example, surface cleaning and activation. The top surface 300a, the bottom surface 500a, and the bottom surface 700a can be surface cleaned to remove particles on the bonding surface of the dielectric layer 302, the bonding surface of the bonding pad 304, the bonding surface of the dielectric layer 502, the bonding surface of the bonding pad 504, the bonding surface of the dielectric layer 702, and the bonding surface of the bonding pad 704. In some embodiments, the top surface 300a, the bottom surface 500a, and the bottom surface 700a can be cleaned, for example, by wet cleaning. Not only will the particles be removed, but also the native oxide (native oxide) formed on the bonding surface of the bonding pad 304, the bonding pad 504, and the bonding pad 704 can be removed. The native oxide formed on the bonding surfaces of the bonding pads 304 , 504 , and 704 may be removed, for example, by using chemicals in a wet cleaning process.

[0071] After cleaning the top surface 300a, the bottom surface 500a, and the bottom surface 700a, activation of the bonding surfaces of the dielectric layer 302, the dielectric layer 502, and the dielectric layer 702 may be performed to generate high bonding strength. In some embodiments, plasma activation may be performed to treat the bonding surfaces of the dielectric layer 302, the dielectric layer 502, and the dielectric layer 702. When the activated bonding surfaces of the dielectric layers 502, 702 contact the activated bonding surface of the dielectric layer 302, the dielectric layer 302 of the bonding layer 300, the dielectric layer 502 of the bonding layer 500, and the dielectric layer 702 of the bonding layer 700 are pre-bonded. In other words, the second die 400 and the dummy die 600 are pre-bonded to the first die 100.

[0072] After the second die 400 and the dummy die 600 are pre-bonded to the first die 100, hybrid bonding of the second die 400, the dummy die 600 and the first die 100 is performed. The hybrid bonding of the second die 400, the dummy die 600 and the first die 100 may include a thermal treatment for dielectric bonding and a thermal annealing for conductor bonding. In some embodiments, the thermal treatment for dielectric bonding is performed to strengthen the bonding between the dielectric layer 502, 702 and the dielectric layer 302. For example, the thermal treatment for dielectric bonding may be performed at a temperature ranging from about 200°C to about 400°C. After performing the thermal treatment for dielectric bonding, thermal annealing for conductor bonding is performed to promote bonding between the bonding pads 504, 704 and the bonding pad 304. For example, the thermal annealing for conductor bonding may be performed at a temperature ranging from about 150°C to about 400°C. After performing thermal annealing for conductor bonding, dielectric layers 502 and 702 are hybrid bonded to dielectric layer 302, and bonding pads 504 and 704 are hybrid bonded to bonding pad 304. For example, dielectric layers 502 and 702 are in direct contact with dielectric layer 302. Similarly, bonding pads 504 and 704 are in direct contact with bonding pad 304. Therefore, bonding layer 500 and bonding layer 700 are hybrid bonded to bonding layer 300. In other words, second die 400 and dummy die 600 are hybrid bonded to first die 100. Although Figure 4D Bonding pads 304, 504, and 704 are shown to have sharp corners (side walls perpendicular to the top / bottom surfaces), but the present disclosure is not limited thereto. In some alternative embodiments, after bonding pads 504, 704 are hybrid-bonded to bonding pad 304, corner rounding of the bonding pads may occur. For example, the corners of bonding pad 304 facing bonding pads 504, 704 are rounded. Similarly, the corners of bonding pads 504, 704 facing bonding pad 304 are also rounded. In other words, the edge of the top surface of each bonding pad 304 is arcuate. Similarly, the edge of the bottom surface of each bonding pad 504 and each bonding pad 704 is also arcuate. In addition, although Figure 4D The bonding pads 304 and the bonding pads 504 and 704 are shown to have the same width and the sidewalls of the bonding pads 304 are aligned with the sidewalls of the corresponding bonding pads 504 and 704, but the disclosure is not limited thereto. In some alternative embodiments, the width of each bonding pad 304 can be smaller or larger than the width of each bonding pad 504 and each bonding pad 704.

[0073] In some embodiments, since the first die 100 is encapsulated in the first encapsulation body 200 to form a wafer form, and the second die 400 and the dummy die 600 are in chip form, Figure 4DThe hybrid bonding process in the embodiment may be referred to as a “chip-on-wafer bonding process”. In some embodiments, since the active surface AS1 of the first die 100 faces the active surface AS2 of the second die 400 and the active surface AS3 of the dummy die 600, the bonding of the first die 100 with the second die 400 and the dummy die 600 may be considered as face-to-face bonding.

[0074] Reference Figure 4E , a second encapsulant 800 is formed on the bonding layer 300 to laterally encapsulate the second die 400 and the dummy die 600. In some embodiments, the forming method and material of the second encapsulant 800 are similar to the forming method and material of the first encapsulant 200, and thus will not be described in detail herein. Figure 4E As shown, the back surface RS2 of the second die 400 and the back surface RS3 of the dummy die 600 are substantially coplanar with the top surface 800a of the second encapsulant 800. In some embodiments, the second encapsulant 800 may be referred to as a “gap-fill oxide”.

[0075] Reference Figure 4E as well as Figure 4F ,Will Figure 4E The structure shown is turned upside down and attached to a carrier C2 through a bonding film BF. In some embodiments, the carrier C2 is made of silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, tape, or other suitable material for structural support. In some embodiments, Figure 4E The structure shown can be bonded to the carrier C2 and the bonding film BF by fusion bonding.

[0076] Reference Figure 4F as well as Figure 4G , the carrier C1 is removed. In some embodiments, the carrier C1 is removed by an etching process, a grinding process, a stripping process, etc. For example, the carrier C1 can be removed by a CMP process. After the carrier C1 is removed, the first die 100 and the first encapsulation body 200 are exposed. For example, the rear surface RS1 of the first die 100 is exposed.

[0077] Reference Figure 4G as well as Figure 4H, remove part of the first die 100 and part of the first encapsulant 200. For example, the first die 100 and the first encapsulant 200 are thinned until the TSV 140 is exposed. That is, the first die 100 is thinned from the rear surface RS1. In some embodiments, the first die 100 and the first encapsulant 200 may be thinned or planarized by a grinding process (such as a mechanical grinding process, a CMP process, etc.). In some embodiments, after the TSV 140 is exposed, the first die 100 and the first encapsulant 200 may be further thinned to reduce the overall thickness of the first die 100. Figure 4H As shown, after the thinning process, the TSV 140 penetrates the semiconductor substrate 110 of the first die 100 .

[0078] Reference Figure 4H as well as Fig. 4I , a portion of the first die 100 is removed to form the recess R1. For example, a portion of the semiconductor substrate 110 of the first die 100 is removed to form the recess R1. Fig. 4I As shown, each TSV 140 is partially located in the recess R1. In some embodiments, at least a portion of each TSV 140 protrudes from the semiconductor substrate 110 of the first die 100. That is, the top surface of each TSV 140 and the top surface of the first encapsulation body 200 are located at a higher level than the rear surface RS1 of the first die 100. In some embodiments, the semiconductor substrate 110 can be partially removed by an etching process. The etching process includes, for example, an isotropic process and / or an anisotropic etching process. For example, the semiconductor substrate 110 can be partially removed by a wet etching process, a dry etching process, or a combination thereof.

[0079] Reference Figure 4J , forming a protective layer 900 to fill the recess R1. In some embodiments, the protective layer 900 includes a molding compound, a molding underfill, etc. Alternatively, the protective layer 900 may be made of a polymer material, such as polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or any other suitable polymer-based dielectric material. In some embodiments, the protective layer 900 may include a filler. Alternatively, the protective layer 900 may not contain a filler. Figure 4J As shown, the protruding portion of each TSV 140 is laterally encapsulated by the protective layer 900. In some embodiments, the protective layer 900 can be formed by the following steps. First, a protective material layer (not shown) is formed in the recess R1 and on the first encapsulation body 200. Then, the protective material layer is subjected to a grinding or thinning process until the TSV 140 is exposed. The thinning process includes, for example, a mechanical grinding process, a CMP process, etc. Figure 4J As shown, the first encapsulation body 200 laterally encapsulates the protection layer 900 .

[0080] Reference Figures 4K to 4N , a redistribution circuit structure 1000 is formed on the first die 100 and the first encapsulation body 200. In some embodiments, Figures 1A to 1N The pattern forming method shown is used to form the redistribution wiring structure 1000. The process of forming the redistribution wiring structure 1000 will be described in detail below.

[0081] Reference Figure 4K , a dielectric layer 1010 is formed on the first die 100, the first encapsulant 200, and the protective layer 900. For example, the first dielectric layer 1010 is in physical contact with the TSV 140 of the first die 100, the first encapsulant 200, and the protective layer 900. In some embodiments, the dielectric layer 1010 has a plurality of openings OP4. In some embodiments, some of the openings OP4 expose the TSV 140 of the first die 100. In some embodiments, Figure 4K The dielectric layer 1010 and Figure 1A as well as Figure 1B The first dielectric layer 10 is similar to that in FIG. 1 , and thus a detailed description thereof is omitted here.

[0082] like Figure 4K As shown, a plurality of conductive patterns 1020 are formed to fill the opening OP4 of the dielectric layer 1000. In other words, the conductive patterns 1020 are embedded in the dielectric layer 1000. In some embodiments, some of the conductive patterns 1020 are in physical contact with the TSV 140 of the first die 100. In some embodiments, Figure 4K The conductive pattern 1020 and Figure 1H The first conductive pattern 20 is similar to that in FIG. Figure 4K Each conductive pattern 1020 can be transparent Figure 1C to Figure 1H The steps of forming the conductive pattern 1020 will be briefly described below.

[0083] First, a seed layer 1022 and a conductive layer 1024 are formed to fill the opening OP4. In some embodiments, Figure 4K The seed layer 1022 and the conductive layer 1024 are respectively Figure 1D The first seed layer 22 and the first conductive layer 24 are similar, so the detailed description thereof is omitted here. In some embodiments, the seed layer 1022 and the conductive layer 1024 are embedded in the dielectric layer 1010. Figure 4K As shown, the seed layer 1022 surrounds the conductive layer 1024. For example, the seed layer 1022 is Figure 4K The cross-sectional view of FIG. 1024 shows a U-shape to surround the conductive layer 1024. In other words, the seed layer 1022 covers the sidewalls and the bottom surface of the conductive layer 1024.

[0084] Thereafter, a portion of each conductive layer 1024 is removed to form a recess R2. Then, a void migration barrier layer 1026 and a conductive layer 1028 are formed to fill the recess R2. In some embodiments, Figure 4K The vacancy migration barrier layer 1026 and the conductive layer 1028 are similar to Figure 1H The void migration barrier layer 1026 and the second conductive layer 28 are not described in detail herein. In some embodiments, the void migration barrier layer 1026 surrounds the conductive layer 1028. For example, the void migration barrier layer 1026 is disposed at Figure 4K The cross-sectional view of FIG. 1 shows a U-shape to surround the conductive layer 1028. In other words, the vacancy migration barrier layer 1026 covers the sidewalls and bottom surface of the conductive layer 1028. Figure 4K As shown, the vacancy migration barrier layer 1026 and the conductive layer 1028 are embedded in the conductive layer 1024. For example, the vacancy migration barrier layer 1026 is spatially separated from the seed layer 1022. In some embodiments, the conductive layer 1024 is sandwiched between the seed layer 1022 and the vacancy migration barrier layer 1026. At the same time, the vacancy migration barrier layer 1026 is sandwiched between the conductive layer 1024 and the conductive layer 1028.

[0085] In some embodiments, the material of the seed layer 1022 is the same as the material of the vacancy migration barrier layer 1026. However, the present disclosure is not limited thereto. In some alternative embodiments, the material of the seed layer 1022 is different from the material of the vacancy migration barrier layer 1026. For example, the seed layer 1022 is composed of two sublayers (not shown). The first sublayer of the seed layer 1022 may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer of the seed layer 1022 may include copper, copper alloys or other suitable materials. Similarly, the vacancy migration barrier layer 1026 is also composed of two sublayers (not shown). The first sublayer of the vacancy migration barrier layer 1026 may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer of the vacancy migration barrier layer 1026 may include copper, copper alloys or other suitable materials.

[0086] In some embodiments, the material of the conductive layer 1024 is the same as the material of the conductive layer 1028. However, the present disclosure is not limited thereto. In some alternative embodiments, the material of the conductive layer 1024 is different from the material of the conductive layer 1028. For example, the conductive layer 1024 and the conductive layer 1028 are respectively made of aluminum, titanium, copper, tungsten and / or alloys thereof. In some embodiments, the material of the conductive layer 1024 and the material of the conductive layer 1028 include copper.

[0087] like Figure 4KAs shown, each conductive pattern 1020 includes a seed layer 1022 , a conductive layer 1024 , a vacancy migration barrier layer 1026 , and a conductive layer 1028 .

[0088] Reference Figure 4L , a dielectric layer 1030 and a dielectric layer 1040 are formed on the dielectric layer 1010 and the conductive pattern 1020. For example, the dielectric layer 1030 is in physical contact with the dielectric layer 1010 and the conductive pattern 1020. In some embodiments, the dielectric layer 1030 has a plurality of openings OP5 and the dielectric layer 1040 has a plurality of openings OP6. In some embodiments, the opening OP5 exposes the conductive layer 1028 of each conductive pattern 1020. At the same time, the opening OP6 exposes a portion of the dielectric layer 1030 and the opening OP5. In some embodiments, Figure 4L The dielectric layer 1030 and the dielectric layer 1040 are respectively Fig. 1I The second dielectric layer 30 and the third dielectric layer 40 are similar, and thus are not described again herein.

[0089] In some embodiments, the steps of forming the opening OP5 and the opening OP6 are similar to those of Figure 1J to Figure 1M The processes shown are similar and will be briefly described below.

[0090] First, a portion of the dielectric layer 1040 is removed to form an opening OP6 in the dielectric layer 1040. For example, an etching process may be performed on the dielectric layer 1040 to form the opening OP6. Subsequently, a portion of the dielectric layer 1030 is removed to form an opening OP5 in the dielectric layer 1030. For example, an etching process may be performed on the dielectric layer 1030 to form the opening OP5. In some embodiments, due to a higher aspect ratio, the etching rate at the bottom of the dielectric layer 1030 may be slower than the etching rate at the top of the dielectric layer 1030. Therefore, each opening OP5 is formed to have an inclined sidewall, such as Figure 4L As shown. In some embodiments, the step of removing a portion of the conductive layer 1024 to form the recess R2 and the step of removing a portion of the dielectric layer 1030 to form the opening OP5 use the same photomask. Therefore, the size of each opening OP5 can be the same as or slightly smaller than the size of each recess R2. In other words, the maximum width of each opening OP5 is equal to or less than the sum of the width of the conductive layer 1028 and the width of the vacancy migration blocking layer 1026.

[0091] like Figure 4LAs shown, a plurality of conductive patterns 1050 are formed to fill the opening OP5 of the dielectric layer 1030 and the opening OP6 of the dielectric layer 1040. In other words, the conductive patterns 1050 are embedded in the dielectric layer 1030 and the dielectric layer 1040. In some embodiments, the conductive patterns 1050 are in physical contact with the conductive patterns 1020. In some embodiments, each conductive pattern 1050 includes a seed layer 1052 and a conductive layer 1054. In other words, the seed layer 1052 and the conductive layer 1054 fill the opening OP5 and the opening OP6 to form the conductive pattern 1050. In some embodiments, Figure 4L The seed layer 1052 and the conductive layer 1054 are respectively Figure 1N 1054 is similar to the second seed layer 52 and the third conductive layer 54 in the embodiment, so they are not repeated here. In some embodiments, the seed layer 1052 is composed of two sublayers (not shown). The first sublayer may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, manganese, other suitable materials or combinations thereof. On the other hand, the second sublayer may include copper, copper alloy or other suitable materials. In some embodiments, the conductive layer 1054 is made of aluminum, titanium, copper, tungsten and / or their alloys.

[0092] like Figure 4L As shown, the seed layer 1052 surrounds the conductive layer 1054. For example, the seed layer 1052 covers the sidewalls and bottom surface of the conductive layer 1054. In some embodiments, the conductive layer 1054 Figure 4L In the cross-sectional view of FIG. 1 , each conductive pattern 1050 may be divided into a through-hole portion 1050a and a line portion 1050b disposed on the through-hole portion 1050a. In some embodiments, the through-hole portion 1050a corresponds to the seed layer 1052 and the conductive layer 1054 located in the opening OP5. Meanwhile, the line portion 1050b corresponds to the seed layer 1052 and the conductive layer 1054 located in the opening OP6. In other words, the through-hole portion 1050a is embedded in the dielectric layer 1030 and the line portion 1050b is embedded in the dielectric layer 1040. In some embodiments, each through-hole portion 1050a is connected to the corresponding line portion 1050b. Figure 4L As shown, the conductive pattern 1050 is in physical contact with the conductive pattern 1020. For example, the through hole portion 1050a of each conductive pattern 1050 is in physical contact with the conductive layer 1028 of the corresponding conductive pattern 1020. As described above, the size of each opening OP5 can be the same as or slightly smaller than the size of each recess R2. Since the through hole portion 1050a is formed by filling the opening OP5, the maximum width of the through hole portion 1050a is equal to or less than the sum of the width of the conductive layer 1028 and the width of the vacancy migration blocking layer 1026. Figure 4LAs shown, each conductive pattern 1050 falls on the span of the conductive layer 1028 of the corresponding conductive pattern 1020. For example, the through-hole portion 1050a of each conductive pattern 1050 falls on the span of the conductive layer 1028 of the corresponding conductive pattern 1020. In some embodiments, each through-hole portion 1050a is completely located within the span of the corresponding void migration barrier layer 1026 and the corresponding conductive layer 1028. For example, in the top view, the edge of each through-hole portion 1050a does not extend beyond the outer edge of the corresponding void migration barrier layer 1026. In some embodiments, in the top view, the outline of each through-hole portion 1050a completely overlaps with the outer outline of the corresponding void migration barrier layer 1026. However, the present disclosure is not limited thereto. In some alternative embodiments, in the top view, the outline of each through-hole portion 1050a can be located within the boundary defined by the outer outline of the corresponding void migration barrier layer 1026.

[0093] like Figure 4L As shown, each conductive pattern 1020 has a void migration barrier layer 1026 sandwiched between a conductive layer 1024 and a conductive layer 1028. The void migration barrier layer 1026 can fully block the voids in the conductive layer 1024 from reaching the interface between the conductive pattern 1020 and the conductive pattern 1050. In other words, the voids in the conductive layer 1024 will gather around the void migration barrier layer 1026 without affecting the connection between the conductive pattern 1020 and the conductive pattern 1050. Although some voids in the conductive layer 1028 may migrate to the interface between the conductive pattern 1020 and the conductive pattern 1050, the amount of these voids can be ignored due to the small size of the conductive layer 1028. Therefore, the voids in the conductive layer 1028 will not form a large enough gap to cause the connection between the conductive pattern 1020 and the conductive pattern 1050 to fail. In summary, the void migration barrier layer 1026 in the conductive pattern 1020 can solve the problem of connection failure between the conductive pattern 1020 and the conductive pattern 1050 due to void migration, thereby improving the reliability of the subsequently formed package PKG.

[0094] Reference Figure 4M, a dielectric layer 1060 and a dielectric layer 1070 are formed on the dielectric layer 1040 and the conductive pattern 1050. In some embodiments, the materials and the forming methods of the dielectric layer 1060 and the dielectric layer 1070 are similar to the forming methods and materials of the dielectric layer 1010, respectively, and therefore are not described in detail herein. In some embodiments, a plurality of conductive pads 1080 are formed in the dielectric layer 1060 and the dielectric layer 1070. That is, the conductive pads 1080 are embedded in the dielectric layer 1060 and the dielectric layer 1070. In some embodiments, each conductive pad 1080 has a through-hole portion 1080a and a line portion 1080b configured on the through-hole portion 1080a. In some embodiments, the through-hole portion 1080a is embedded in the dielectric layer 1060 and the line portion 1080b is embedded in the dielectric layer 1070. In some embodiments, the conductive pad 1080 is electrically connected to the conductive pattern 1050. For example, the through hole portion 1080a of each conductive pad 1080 is in physical contact with the conductive pattern 1050 to achieve electrical connection with the conductive pattern 1050. In some embodiments, the conductive pad 1080 is used to establish an electrical connection with other components (not shown) that are subsequently formed or provided. In some alternative embodiments, the conductive pad 1080 can be a test pad. In some embodiments, the conductive pad 1080 is an aluminum pad, a copper pad, or other appropriate metal pad. In some embodiments, the conductive pad 1080 is formed by a sputtering process, a PVD process, a plating process, etc.

[0095] Reference Figure 4N , a dielectric layer 1090 is formed on the dielectric layer 1070 and the conductive pad 1080. In some embodiments, the material and the forming method of the dielectric layer 1090 are similar to the material and the forming method of the dielectric layer 1010, respectively, and thus a detailed description thereof is omitted herein.

[0096] like Figure 4N As shown, a plurality of under bump metallization (UBM) patterns 1095 are formed on the dielectric layer 1090 and the conductive pad 1080 to complete the formation of the redistribution wiring structure 1000. Figure 4N As shown, the UBM pattern 1095 is partially embedded in the dielectric layer 1090. In some embodiments, the UBM pattern 1095 is in physical contact with the conductive pad 1080 to achieve electrical connection with the conductive pad 1080. In some embodiments, the UBM pattern 1095 is formed by a sputtering process, a PVD process, a plating process, etc. In some embodiments, the UBM pattern 1095 is made of aluminum, titanium, copper, tungsten and / or alloys thereof.

[0097] In some embodiments, the redistribution wiring structure 1000 includes a dielectric layer 1010, a conductive pattern 1020, dielectric layers 1030, 1040, a conductive pattern 1050, dielectric layers 1060, 1070, a conductive pad 1080, a dielectric layer 1090, and a UBM pattern 1095. Figure 4N As shown, the redistribution circuit structure 1000 and the second die 400 are disposed on opposite sides of the first die 100 .

[0098] After forming the redistribution wiring structure 1000 on the first die 100 and the first package 200, a plurality of conductive terminals 1100 are disposed on the UBM pattern 1095. In some embodiments, the conductive terminals 1100 are attached to the UBM pattern 1095 through flux. In some embodiments, the conductive terminals 1100 are, for example, solder balls, ball grid array (BGA) balls, or controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 1100 are made of a low resistivity conductive material, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof.

[0099] Afterwards, the redistribution structure 1000, the first package 200, the bonding layer 300, the second package 800, the bonding film BF, and the carrier C2 are subjected to a singulation process to obtain a plurality of packages PKG. In some embodiments, the singulation process generally involves cutting using a rotating blade and / or a laser beam. In other words, the singulation process includes a laser cutting process, a mechanical cutting process, a laser slotting process, other appropriate processes, or a combination thereof.

[0100] like Figure 4N As shown, the void migration barrier layer 1026 is only formed on the bottom layer (i.e., the conductive pattern 1020) of the redistribution wiring structure 1000. However, the present disclosure is not limited thereto. In some alternative embodiments, other layers of the redistribution wiring structure 1000 may include a void migration barrier layer. Figure 5 Embodiments having a vacancy migration barrier layer in other conductive patterns are described.

[0101] Figure 5 is a schematic cross-sectional view of a package PKG1 according to some alternative embodiments of the present disclosure. Figure 5 , Figure 5 The package PKG1 in Figure 4N The package PKG in FIG. 1 is similar, so similar elements are represented by the same reference numerals and their detailed description is omitted here. Figure 5 The package PKG1 in Figure 4N The difference between the package PKG in is that Figure 4NPart of the conductive pattern 1050 in the package PKG1 is replaced by the conductive pattern 1050'. Figure 5 As shown, each conductive pattern 1050' includes a seed layer 1052, a conductive layer 1054, a void migration barrier layer 1056, and a conductive layer 1058. In some embodiments, the seed layer 1052, the conductive layer 1054, the void migration barrier layer 1056, and the conductive layer 1058 are formed by methods and materials similar to those of Figure 4K The formation methods and materials of the seed layer 1022, the conductive layer 1024, the vacancy migration blocking layer 1026 and the conductive layer 1028 are described, and therefore a detailed description thereof is omitted here.

[0102] In some embodiments, the void migration barrier layer 1056 surrounds the conductive layer 1058. For example, the void migration barrier layer 1056 surrounds the conductive layer 1058. Figure 5 The cross-sectional view of FIG. 1056 is U-shaped to surround the conductive layer 1058. In other words, the vacancy migration blocking layer 1056 covers the sidewalls and bottom surface of the conductive layer 1058. Figure 5 As shown, the vacancy migration barrier layer 1056 and the conductive layer 1058 are embedded in the conductive layer 1054. For example, the vacancy migration barrier layer 1056 is spatially separated from the seed layer 1052. In some embodiments, the conductive layer 1054 is sandwiched between the seed layer 1052 and the vacancy migration barrier layer 1056. At the same time, the vacancy migration barrier layer 1056 is sandwiched between the conductive layer 1054 and the conductive layer 1058.

[0103] like Figure 5 As shown, some conductive patterns (i.e., conductive pattern 1050') in the second layer of redistribution wiring structure 1000 have void migration barrier layer 1056, while the remaining conductive patterns (i.e., conductive pattern 1050) in the second layer of redistribution wiring structure 1000 do not have void migration barrier layer. However, the present disclosure is not limited to this. In some alternative embodiments, all conductive patterns in the second layer of redistribution wiring structure 1000 may have void migration barrier layer 1056. Figure 5 As shown, the conductive pattern 1050 ′ is located directly below the conductive terminal 1100 . However, the present disclosure is not limited thereto. In some alternative embodiments, the conductive pattern 1050 ′ does not vertically overlap with the conductive terminal 1100 .

[0104] It is worth noting that only Figure 5 The void migration barrier layer (i.e., void migration barrier layer 1026, 1056) is shown to be located only in the first layer (i.e., the bottom layer) and the second layer of the redistribution wiring structure 1000, but the present disclosure is not limited thereto. In some alternative embodiments, the void migration barrier layer may also be present in the conductive patterns located in other layers of the redistribution wiring structure 1000.

[0105] like Figure 5 As shown, each conductive pattern 1050' has a void migration barrier layer 1056 sandwiched between the conductive layer 1054 and the conductive layer 1058. The void migration barrier layer 1056 can fully block the voids in the conductive layer 1054 from reaching the interface between the conductive pattern 1050' and the conductive pad 1080. In other words, the voids in the conductive layer 1054 will gather around the void migration barrier layer 1056 without affecting the connection between the conductive pattern 1050' and the conductive pad 1080. Although some voids in the conductive layer 1058 may migrate to the interface between the conductive pattern 1050' and the conductive pad 1080, the amount of these voids can be ignored due to the small size of the conductive layer 1058. Therefore, the voids in the conductive layer 1058 will not form a large enough gap to cause the connection between the conductive pattern 1050' and the conductive pad 1080 to fail. In summary, the void migration barrier layer 1056 in the conductive pattern 1050 ′ can solve the problem of connection failure between the conductive pattern 1050 ′ and the conductive pad 1080 caused by void migration, thereby improving the reliability of the package PKG1.

[0106] As mentioned above, Figures 1A to 1N The patterning method shown can be used to form conductive features in a package. Figure 6 The following examples illustrate the use of the above pattern forming method in redistribution circuit structures of different packages.

[0107] Figure 6 is a schematic cross-sectional view of a package PKG2 according to some alternative embodiments of the present disclosure. Figure 6 , the package PKG2 includes a plurality of integrated circuits 1200, an interposer 1500, a plurality of conductive terminals 1400, a substrate SUB, and a plurality of conductive terminals 1700. Figure 6 As shown, each integrated circuit 1200 includes a semiconductor substrate, an internal connection structure, a conductive pad, a passivation layer, and a post-passivation layer. The internal connection structure is disposed on the semiconductor substrate. The conductive pad, the passivation layer, and the post-passivation layer are sequentially disposed on the internal connection structure. In some embodiments, the integrated circuit 1200 can perform a logic function. For example, the integrated circuit 1200 can be a CPU die, a GPU die, an FPGA, etc.

[0108] In some embodiments, the interposer 1500 may be referred to as a redistribution line (RDL) interposer. In some embodiments, the interposer 1500 includes a plurality of dielectric layers 1510, a plurality of conductive patterns 1520a, and a plurality of conductive patterns 1520b. In some embodiments, the material of the dielectric layer 1510 includes polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or any other suitable polymer-based dielectric material. In some embodiments, the dielectric layer 1510 includes a resin mixed with a filler. The dielectric layer 1510 may be formed by a suitable manufacturing technique, such as film lamination, spin coating, CVD, PECVD, etc.

[0109] In some embodiments, each conductive pattern 1520a includes a seed layer 1522 and a conductive layer 1524. In some embodiments, the formation methods and materials of the seed layer 1522 and the conductive layer 1524 are respectively the same as those of Figure 4L The formation methods and materials of the seed layer 1052 and the conductive layer 1054 are similar, so the detailed description thereof is omitted here. In some embodiments, the conductive layer 1524 is disposed on the seed layer 1522.

[0110] In some embodiments, each conductive pattern 1520b includes a seed layer 1522, a conductive layer 1524, a void migration barrier layer 1526, and a conductive layer 1528. In some embodiments, the seed layer 1522, the conductive layer 1524, the void migration barrier layer 1526, and the conductive layer 1528 are formed by methods and materials similar to Figure 4K The formation methods and materials of the seed layer 1022, the conductive layer 1024, the vacancy migration barrier layer 1026, and the conductive layer 1028 are omitted here for details. In some embodiments, the vacancy migration barrier layer 1526 surrounds the conductive layer 1528. For example, the vacancy migration barrier layer 1526 is formed at Figure 6 The cross-sectional view of FIG. 15 shows a U-shape to surround the conductive layer 1528. In other words, the vacancy migration blocking layer 1526 covers the sidewalls and bottom surface of the conductive layer 1528. Figure 6 As shown, the vacancy migration barrier layer 1526 and the conductive layer 1528 are embedded in the conductive layer 1524. For example, the vacancy migration barrier layer 1526 is spatially separated from the seed layer 1522. In some embodiments, the conductive layer 1524 is sandwiched between the seed layer 1522 and the vacancy migration barrier layer 1526. At the same time, the vacancy migration barrier layer 1526 is sandwiched between the conductive layer 1524 and the conductive layer 1528.

[0111] The void migration barrier layer 1526 can fully block the voids in the conductive layer 1524 from reaching the interface between the conductive pattern 1520b and the vertically adjacent conductive pattern 1520a or the vertically adjacent conductive pattern 1520b. In other words, the voids in the conductive layer 1524 will gather around the void migration barrier layer 1526 without affecting the connection between the conductive pattern 1520b and the vertically adjacent conductive pattern 1520a or the vertically adjacent conductive pattern 1520b. Although some voids in the conductive layer 1528 may migrate to the interface between the conductive pattern 1520b and the vertically adjacent conductive pattern 1520a or the vertically adjacent conductive pattern 1520b, the amount of these voids can be ignored due to the small size of the conductive layer 1528. Therefore, the voids in the conductive layer 1528 will not form a large enough gap to cause the connection failure between the conductive pattern 1520b and the vertically adjacent conductive pattern 1520a or the vertically adjacent conductive pattern 1520b. In summary, the vacancy migration barrier layer 1526 in the conductive pattern 1520b can solve the problem of connection failure between the conductive pattern 1520b and the vertically adjacent conductive pattern 1520a or the vertically adjacent conductive pattern 1520b due to vacancy migration, thereby improving the reliability of the package PKG2.

[0112] like Figure 6 As shown, the integrated circuit 1200 is bonded to the interposer 1500. In some embodiments, the integrated circuit 1200 is attached to the interposer 1500 through the conductive pillars 1300 and the conductive terminals 1400. In some embodiments, the conductive pillars 1300 are in physical contact with the conductive pads of the integrated circuit 1200 and the conductive terminals 1400. On the other hand, the conductive terminals 1400 are in physical contact with the conductive pillars 1300 and the topmost conductive pattern 1520a. In other words, the integrated circuit 1200 is electrically connected to the interposer 1500. In some embodiments, the integrated circuit 1200 is attached to the interposer 1500 by flip-chip bonding.

[0113] In some embodiments, the substrate SUB includes a plurality of wiring patterns RP embedded therein. In some embodiments, the wiring patterns RP are interconnected with each other. That is, the wiring patterns RP are electrically connected to each other. In some embodiments, the substrate SUB is a printed circuit board (PCB) or the like. In some embodiments, the substrate SUB is referred to as a circuit substrate.

[0114] like Figure 6As shown, the interposer 1500 is connected to the substrate SUB through the conductive terminal 1600. In some embodiments, the conductive terminal 1600 is a solder ball, a ball grid array (BGA) ball, etc. In some embodiments, the conductive terminal 1600 is made of a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi or an alloy thereof. In some embodiments, the conductive terminal 1600 electrically connects the interposer 1500 to the substrate SUB.

[0115] In some embodiments, the conductive terminal 1700 is formed on the opposite side of the substrate SUB to the interposer 1500. In some embodiments, the conductive terminal 1700 is a solder ball, a BGA ball, etc. In some embodiments, the conductive terminal 1700 is made of a conductive material with a low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi, or an alloy thereof. In some embodiments, the conductive terminal 1700 is in physical contact with the wiring pattern RP of the substrate SUB. In some embodiments, the package PKG2 can be referred to as a chip-on-wafer-on substrate (CoWoS) package.

[0116] According to some embodiments of the present disclosure, a method for forming a pattern includes at least the following steps: providing a first dielectric layer having a first opening; depositing a first seed layer and a first conductive layer in the first opening; removing a portion of the first conductive layer to form a recess; depositing a vacancy migration barrier layer and a second conductive layer in the recess, so that the first seed layer, the first conductive layer, the vacancy migration barrier layer, and the second conductive layer form a first pattern.

[0117] According to some embodiments of the present disclosure, the method for forming a pattern further comprises at least the following steps: Depositing a second dielectric layer and a third dielectric layer on the first dielectric layer and the first pattern. Removing a portion of the third dielectric layer to form a second opening in the third dielectric layer. Removing a portion of the second dielectric layer to form a third opening in the second dielectric layer. Depositing a second seed layer and a third conductive layer in the second opening and the third opening to form a second pattern.

[0118] According to some embodiments of the present disclosure, the step of removing the portion of the first conductive layer and the step of removing the portion of the second dielectric layer use the same photomask.

[0119] According to some embodiments of the present disclosure, the second pattern is formed to fall on a span of the second conductive layer.

[0120] According to some embodiments of the present disclosure, the material of the first seed layer and the material of the vacancy migration barrier layer include titanium, titanium nitride, tantalum, tantalum nitride, cobalt and manganese, and the material of the first conductive layer and the material of the second conductive layer include copper.

[0121] According to some embodiments of the present disclosure, the vacancy migration barrier layer is formed to be sandwiched between the first conductive layer and the second conductive layer.

[0122] According to some embodiments of the present disclosure, a package includes a first die, a first encapsulant, and a redistribution wiring structure. The first encapsulant laterally encapsulates the first die. The redistribution wiring structure is configured on the first die and the first encapsulant. The redistribution wiring structure includes a first dielectric layer and a first conductive pattern embedded in the first dielectric layer. The first conductive pattern includes a seed layer, a first conductive layer, a void migration barrier layer, and a second conductive layer. The void migration barrier layer is sandwiched between the first conductive layer and the second conductive layer.

[0123] According to some embodiments of the present disclosure, the first conductive layer is sandwiched between the seed layer and the vacancy migration barrier layer.

[0124] According to some embodiments of the present disclosure, the vacancy migration barrier layer is U-shaped in a cross-sectional view.

[0125] According to some embodiments of the present disclosure, a material of the seed layer is the same as a material of the vacancy migration barrier layer, and a material of the first conductive layer is the same as a material of the second conductive layer.

[0126] According to some embodiments of the present disclosure, the material of the seed layer and the material of the vacancy migration blocking layer include titanium, titanium nitride, tantalum, tantalum nitride, cobalt and manganese, and the material of the first conductive layer and the material of the second conductive layer include copper.

[0127] According to some embodiments of the present disclosure, the redistribution wiring structure further includes a second dielectric layer, a third dielectric layer and a second conductive pattern. The second dielectric layer and the third dielectric layer are disposed on the first dielectric layer and the first conductive pattern. The second conductive pattern includes a through-hole portion and a line portion disposed on the through-hole portion. The through-hole portion is embedded in the second dielectric layer and is in physical contact with the first conductive pattern, and the line portion is embedded in the third dielectric layer.

[0128] According to some embodiments of the present disclosure, the through-hole portion of the second conductive pattern falls on the span of the second conductive layer of the first conductive pattern.

[0129] According to some embodiments of the present disclosure, a maximum width of the through hole portion is equal to or smaller than a sum of a width of the second conductive layer and a width of the vacancy migration barrier layer.

[0130] According to some embodiments of the present disclosure, the package further includes a second die, a dummy die, and a second encapsulation body. The second die is disposed on a side of the first die opposite to the redistribution structure. The dummy die is adjacent to the second die. The second encapsulation body laterally encapsulates the second die and the dummy die.

[0131] According to some embodiments of the present disclosure, a method for manufacturing a package includes at least the following steps. A tube core is provided. The tube core is encapsulated by an encapsulation body. A redistribution wiring structure is formed on the tube core and the encapsulation body. The redistribution wiring structure is formed by at least the following steps. A first dielectric layer is formed on the tube core. The first dielectric layer has a first opening. The first seed layer and the first conductive layer are filled into the first opening. A portion of the first conductive layer is removed to form a recess. A vacancy migration blocking layer and a second conductive layer are filled into the recess, so that the first seed layer, the first conductive layer, the vacancy migration blocking layer and the second conductive layer form a first conductive pattern.

[0132] According to some embodiments of the present disclosure, the step of forming the redistribution wiring structure further includes at least the following steps: forming a second dielectric layer and a third dielectric layer on the first dielectric layer and the first conductive pattern; removing a portion of the third dielectric layer to form a second opening in the third dielectric layer; removing a portion of the second dielectric layer to form a third opening in the second dielectric layer; and filling a second seed layer and a third conductive layer into the second opening and the third opening to form a second conductive pattern.

[0133] According to some embodiments of the present disclosure, the step of removing the portion of the first conductive layer and the step of removing the portion of the second dielectric layer use the same photomask.

[0134] According to some embodiments of the present disclosure, the second conductive pattern is formed to fall on a span of the second conductive layer.

[0135] According to some embodiments of the present disclosure, the vacancy migration barrier layer is formed to be sandwiched between the first conductive layer and the second conductive layer.

[0136] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a pattern, characterized in that: include: providing a first dielectric layer having a first opening; depositing a first seed layer and a first conductive layer in the first opening; removing a portion of the first conductive layer to form a recess; as well as A vacancy migration barrier layer and a second conductive layer are deposited in the recess, so that the first seed layer, the first conductive layer, the vacancy migration barrier layer and the second conductive layer form a first pattern.

2. The method for forming a pattern according to claim 1, characterized in that: Also includes: Depositing a second dielectric layer and a third dielectric layer on the first dielectric layer and the first pattern; removing a portion of the third dielectric layer to form a second opening in the third dielectric layer; removing a portion of the second dielectric layer to form a third opening in the second dielectric layer; as well as A second seed layer and a third conductive layer are deposited in the second opening and the third opening to form a second pattern.

3. The method for forming a pattern according to claim 2, characterized in that: The step of removing the portion of the first conductive layer and the step of removing the portion of the second dielectric layer use the same photomask.

4. A package, characterized in that: include: a first tube core; A first encapsulation body, laterally encapsulating the first tube core; as well as A redistribution circuit structure is configured on the first tube core and the first package, comprising: a first dielectric layer; as well as The first conductive pattern is embedded in the first dielectric layer, wherein the first conductive pattern comprises a seed layer, a first conductive layer, a vacancy migration barrier layer and a second conductive layer, and the vacancy migration barrier layer is sandwiched between the first conductive layer and the second conductive layer.

5. The package according to claim 4, characterized in that The first conductive layer is sandwiched between the seed layer and the vacancy migration barrier layer.

6. The package according to claim 4, characterized in that The vacancy migration barrier layer is U-shaped in a cross-sectional view.

7. The package according to claim 4, characterized in that The rerouting line structure further comprises: A second dielectric layer and a third dielectric layer are disposed on the first dielectric layer and the first conductive pattern; and The second conductive pattern includes a via portion and a line portion disposed on the via portion, wherein the via portion is embedded in the second dielectric layer and physically contacts the first conductive pattern, and the line portion is embedded in the third dielectric layer.

8. The package according to claim 4, characterized in that The through-hole portion of the second conductive pattern falls on a span of the second conductive layer of the first conductive pattern.

9. A method for manufacturing a package, characterized in that: include: Providing a tube die; encapsulating the die by an encapsulation body; as well as A redistribution circuit structure is formed on the tube die and the encapsulation body, comprising: forming a first dielectric layer on the die, wherein the first dielectric layer has a first opening; Filling the first opening with a first seed layer and a first conductive layer; removing a portion of the first conductive layer to form a recess; and A vacancy migration barrier layer and a second conductive layer are filled into the recess, so that the first seed layer, the first conductive layer, the vacancy migration barrier layer and the second conductive layer form a first conductive pattern.

10. The method for manufacturing a package according to claim 9, characterized in that: The vacancy migration blocking layer is formed to be interposed between the first conductive layer and the second conductive layer.

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