Method for manufacturing through-silicon-via wafer and method for manufacturing semiconductor

Abstract

The invention provides a manufacturing method of a silicon through hole wafer and a semiconductor manufacturing method. The manufacturing method comprises the following steps: providing a composite wafer comprising a first substrate, a first insulating layer and a dielectric layer which are stacked in sequence; forming a second insulating layer covering the first surface of the first substrate; forming at least one silicon through hole penetrating through the second insulating layer and the first substrate; forming a third insulating layer covering the side wall of the at least one silicon through hole, the second insulating layer and the first insulating layer at the bottom of the at least one silicon through hole; filling the at least one silicon through hole with a conductive material, and removing the redundant conductive material by adopting a CMP method; removing the dielectric layer by adopting a dry etching process; and forming at least one opening which exposes the conductive material in the at least one through silicon via on the first insulating layer and the third insulating layer. According to the method, the redundant film layer is removed by adopting the composite wafer and combining the CMP method and the dry etching process, so that the problem that the wafer is easy to crack in the traditional mechanical grinding process is avoided, and the production yield of the wafer is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a through silicon via wafer and a semiconductor manufacturing method. Background Art

[0002] In the field of semiconductor manufacturing, for some Micro-Electromechanical Systems (MEMS) devices that require multi-wafer bonding, a key manufacturing step is to form Through Silicon Via (TSV) wafers. By filling the through silicon vias of the TSV wafer with conductive materials, efficient electrical connection and signal transmission between different wafers can be achieved.

[0003] The existing TSV wafer manufacturing method generally includes: forming a patterned photoresist layer on a double-polished wafer; using the patterned photoresist layer as a mask, performing deep hole etching on the double-polished wafer to form TSV through holes on the double-polished wafer; removing the patterned photoresist; forming an insulating layer on the surface of the single- and double-polished wafers and the sidewalls of the TSV through holes; filling the TSV through holes with conductive materials; using a grinder to thin the double-polished wafer to remove unnecessary film layer materials (including insulating layers and conductive materials) on the upper and lower surfaces of the double-polished wafer to prepare for subsequent bonding and other processes.

[0004] However, when a grinder is used to mechanically grind the wafer, the grinding wheel of the grinder will exert a certain amount of pressure on the wafer, making the wafer extremely easy to break under the pressure of the grinding wheel, thereby reducing the production yield and increasing the manufacturing cost. In addition, the contact between the grinding wheel and the wafer surface during the grinding process is often difficult to achieve ideal uniformity, resulting in insufficient surface flatness of the film layer after removal. This uneven surface will not only affect the deposition quality and uniformity of the film layer in subsequent processes, but may also have an adverse effect on the bonding effect between the TSV wafer and other device wafers, such as reducing the bonding strength, increasing interface defects, etc., thereby affecting the performance and reliability of the final semiconductor device.

[0005] Therefore, how to improve the TSV wafer production yield and ensure the wafer bonding effect to meet the strict requirements of some semiconductor devices on TSV wafer surface quality and processing accuracy is a technical problem that needs to be solved urgently. Summary of the invention

[0006] In view of the above problems, the present disclosure is proposed to provide a method for manufacturing a through silicon via wafer and a semiconductor manufacturing method that overcomes the above problems or at least partially solves the above problems. By adopting a composite wafer structure and combining the CMP method and dry etching process to remove excess film layers, the method avoids the problem of easy breakage of the wafer during traditional mechanical grinding, which not only significantly improves the production yield of the wafer, but also effectively reduces the increase in manufacturing costs caused by wafer breakage.

[0007] In a first aspect, a method for manufacturing a through silicon via wafer is provided, comprising:

[0008] Providing a composite wafer, the composite wafer comprising a first substrate, a first insulating layer and a dielectric layer stacked in sequence;

[0009] forming a second insulating layer covering a first surface, wherein the first surface is a side of the first substrate away from the first insulating layer;

[0010] Forming at least one through silicon via penetrating the second insulating layer and the first substrate along a stacking direction of the composite wafer;

[0011] forming a third insulating layer, the third insulating layer comprising a first portion of the insulating layer covering the sidewall of the at least one through silicon via, a second portion of the insulating layer covering the second insulating layer, and a third portion of the insulating layer of the first insulating layer covering the bottom of the at least one through silicon via;

[0012] Filling the at least one through silicon via with a conductive material, and removing excess conductive material outside the at least one through silicon via by chemical mechanical polishing;

[0013] Using a dry etching process to remove the dielectric layer to expose the first insulating layer;

[0014] At least one opening is formed on the first insulating layer and the third partial insulating layer, the at least one opening corresponds to the at least one through silicon via one by one, and the at least one opening exposes the conductive material in the at least one through silicon via.

[0015] Optionally, forming at least one through silicon via penetrating the second insulating layer and the first substrate along the stacking direction of the composite wafer includes:

[0016] Performing a patterning process on the second insulating layer to form at least one first pattern opening on the second insulating layer, wherein the at least one first pattern opening exposes a portion of the first substrate;

[0017] A reactive ion etching process is used to remove the first substrate directly below the at least one first graphic opening and expose the first insulating layer to form at least one through silicon via penetrating the second insulating layer and the first substrate.

[0018] Optionally, the patterning of the second insulating layer includes:

[0019] Using photolithography technology to form a patterned photoresist layer on a side of the second insulating layer away from the first substrate;

[0020] Using the patterned photoresist layer as a mask, a dry etching process is used to etch the second insulating layer to form the at least one first pattern opening on the second insulating layer;

[0021] The patterned photoresist layer is removed.

[0022] Optionally, the third insulating layer is a thermal silicon oxide layer, and forming the third insulating layer includes:

[0023] The composite wafer is placed in a high-temperature oxidation furnace, and the heating temperature in the furnace is controlled to be 800-1500° C. and the heating time is 12-24 hours to form a thermal oxide silicon layer covering the second insulating layer, covering the sidewall of the at least one silicon through hole, and covering the first insulating layer at the bottom of the at least one silicon through hole.

[0024] Optionally, filling the at least one through silicon via with a conductive material and removing excess conductive material outside the at least one through silicon via using a chemical mechanical polishing method includes:

[0025] Filling the at least one through silicon via with a conductive material multiple times by using a low pressure chemical vapor deposition method until the at least one through silicon via is fully filled;

[0026] The wafer is thinned multiple times on the front and back sides by chemical mechanical polishing to remove excess conductive material outside the at least one through silicon via.

[0027] Optionally, forming at least one opening on the first insulating layer and the third partial insulating layer includes:

[0028] Using photolithography technology to form a patterned photoresist layer on a side of the first insulating layer away from the first substrate;

[0029] Using the patterned photoresist layer as a mask, etching the first insulating layer and the third portion of the insulating layer by a dry etching process to form the at least one opening on the first insulating layer and the third portion of the insulating layer;

[0030] The patterned photoresist layer is removed.

[0031] Optionally, the first substrate and the dielectric layer are both single crystal silicon layers, and the first insulating layer, the second insulating layer and the third insulating layer are all silicon oxide layers.

[0032] In a second aspect, a semiconductor manufacturing method is provided, comprising:

[0033] Providing a first wafer and a second wafer to be bonded, wherein the first wafer is a through silicon via wafer manufactured by the manufacturing method described in the first aspect, and the second wafer includes a second substrate;

[0034] forming a bonding structure within the at least one opening of the first wafer;

[0035] bonding the first wafer and the second wafer via the bonding structure;

[0036] At least one electrode is formed on a side of the first wafer away from the second wafer, the at least one electrode is arranged in a one-to-one correspondence with the at least one through silicon via, and each of the electrodes is electrically connected to the conductive material filled in the corresponding through silicon via;

[0037] A fourth insulating layer is formed on a side of the first wafer away from the second wafer, wherein the fourth insulating layer at least partially covers the electrode to expose a lead portion of the electrode.

[0038] Optionally, forming at least one electrode on a side of the first wafer away from the second wafer includes:

[0039] Forming an electrode material layer on a side of the first wafer away from the second wafer by physical vapor deposition, wherein the electrode material layer comprises a titanium layer and a gold layer stacked in sequence;

[0040] The electrode material layer is patterned to form the at least one electrode.

[0041] Optionally, forming a bonding structure in the at least one opening of the first wafer includes:

[0042] The bonding structure is formed in at least one opening of the first wafer by adopting a stripping process, wherein the bonding structure includes a titanium layer and a gold layer which are stacked.

[0043] The technical solution provided in the embodiments of the present disclosure has at least the following technical effects or advantages:

[0044] The disclosed embodiments provide a method for manufacturing a through silicon via wafer and a semiconductor manufacturing method, which adopts a composite wafer structure, including a first substrate, a first insulating layer and a dielectric layer stacked in sequence, wherein the first insulating layer serves as a stop layer for the TSV through hole, thereby ensuring precise control of the through hole formation and effectively avoiding excessive damage to the wafer body when forming the TSV through hole. The introduction of the dielectric layer not only enhances the overall structural strength of the wafer, but also effectively prevents the risk of the wafer being broken due to uneven force during the formation of the TSV through hole, thereby significantly improving the stability and safety of the production process. When removing excess film layers, the method removes the dielectric layer by using a dry etching process and removes excess conductive materials by using a chemical mechanical polishing method. Compared with traditional mechanical polishing, it can achieve a more uniform and fine removal effect, reduce physical damage to the wafer during processing, and thus significantly improve the flatness of the wafer surface. By optimizing the flatness of the wafer surface, the bonding effect between the TSV wafer and other device wafers is effectively enhanced, the interface defects are reduced, and the bonding strength is improved, thereby ensuring the overall performance and reliability of semiconductor products such as micro-vibration mirror arrays.

[0045] At the same time, the second insulating layer formed in the present method, covering the first surface of the first substrate, can provide additional electrical isolation and protection, help enhance the electrical stability of the entire wafer structure, and prevent potential current leakage or short circuit problems. The third insulating layer can prevent the conductive material in the TSV through hole from directly contacting other electrical components on the wafer, thereby ensuring the normal operation of the circuit and the accurate transmission of the signal. In addition, it also helps to protect the TSV through hole from erosion by the external environment and improve the reliability and service life of the wafer.

[0046] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0048] Figure 1 is a flow chart of a method for manufacturing a through silicon via wafer provided by an embodiment of the present disclosure;

[0049] Figure 2 is a schematic structural diagram of a composite wafer provided in step S110;

[0050] Figure 3 is a schematic structural diagram of a portion of a through silicon via wafer formed after executing step S120;

[0051] Figure 4 is a schematic structural diagram of a portion of a through silicon via wafer formed after executing step S130;

[0052] Figure 5 is a schematic structural diagram of a portion of a through silicon via wafer formed after executing step S140;

[0053] Figure 6 is a schematic structural diagram of a portion of a through silicon via wafer formed after executing step S150;

[0054] Figure 7 is a schematic structural diagram of a portion of a through silicon via wafer formed after executing step S160;

[0055] Figure 8 is a schematic diagram of the structure of a through silicon via wafer formed after executing step S170;

[0056] Fig. 9 is a flow chart of a semiconductor manufacturing method provided by an embodiment of the present disclosure;

[0057] Fig.10 is a schematic diagram of the structure of a through silicon via wafer formed after executing step S920;

[0058] Fig.11 is a schematic diagram of the structure of a through silicon via wafer formed after executing step S930;

[0059] Fig.12 is a schematic diagram of the structure of a through silicon via wafer formed after executing step S940;

[0060] Fig.13 It is a schematic diagram of the structure of the through silicon via wafer formed after executing step S950. DETAILED DESCRIPTION

[0061] In order to better understand the above-mentioned technical scheme, the above-mentioned technical scheme will be described in detail below in combination with the accompanying drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical scheme of the present disclosure, rather than limitations on the technical scheme of the present disclosure. In the absence of conflict, the embodiments of the present disclosure and the technical features in the embodiments can be combined with each other.

[0062] Figure 1 is a flow chart of a method for manufacturing a through silicon via wafer provided by an embodiment of the present disclosure, such as Figure 1 As shown, the manufacturing method includes:

[0063] Step S110 , providing a composite wafer, wherein the composite wafer includes a first substrate, a first insulating layer and a dielectric layer stacked in sequence.

[0064] In some implementations, the composite wafer may be an SOI wafer, the first substrate may be a single crystal silicon layer, the first insulating layer may be a silicon oxide layer, and the dielectric layer may be a single crystal silicon layer to facilitate production and manufacturing.

[0065] Among them, the thickness of the first substrate can be determined according to the diameter of the TSV silicon through hole to be formed. In some implementations, the ratio of the thickness of the first substrate to the diameter of the TSV silicon through hole can be less than 35:1. Due to equipment capacity limitations, the morphology of deep hole etching through holes with a depth-to-width ratio greater than 35 cannot be guaranteed, which will result in a low product yield. In this application, the depth of the TSV silicon through hole is the same as the thickness of the first substrate. Therefore, the ratio of the thickness of the first substrate to the diameter of the TSV silicon through hole is limited to less than 35:1. For example, the diameter of the TSV silicon through hole is 10um and the thickness of the first substrate is 300um. The morphology of the formed TSV silicon through hole can be guaranteed and the product yield can be improved. The thickness of the first insulating layer can be 0.5 to 2um to ensure its blocking effect. The thickness of the dielectric layer can be determined based on the required thickness of the entire wafer. When the thickness of the first substrate is thicker, the thickness of the dielectric layer can be set thinner. When the thickness of the first substrate is thinner, the thickness of the dielectric layer can be set thicker to play a supporting role, ensure the overall thickness of the wafer, and prevent the wafer from breaking during transportation. For example, the thickness of the first substrate may be 400 um, the thickness of the first insulating layer may be 1 um, and the thickness of the dielectric layer may be 100 um.

[0066] Figure 2 is a schematic diagram of the structure of a composite wafer provided in step S110, such as Figure 2 As shown, the composite wafer includes a first substrate 10, a first insulating layer 20 and a dielectric layer 30 stacked in sequence.

[0067] Step S120 , forming a second insulating layer covering the first surface, where the first surface is a side of the first substrate away from the first insulating layer.

[0068] In some implementations, the second insulating layer is thermal silicon oxide, which has better insulation performance and high temperature resistance than silicon oxide. Step S120 may include:

[0069] The composite wafer is placed in a high-temperature oxidation furnace, and the heating temperature in the furnace is controlled to be 800-1500° C. for a heating time of 12-24 hours to form thermally oxidized silicon covering the first surface to form a second insulating layer.

[0070] The thickness of the second insulating layer can be 0.5-2um, for example, 1um, so as to reduce the overall thickness of the wafer while ensuring its insulation effect. Before placing the composite wafer in the high-temperature oxidation furnace, the wafer can also be cleaned to ensure the smooth progress of the oxidation process and the quality and performance of the final product.

[0071] It should be noted that in the above-mentioned process of forming thermal silicon oxide using a high-temperature oxidation furnace, a thermal silicon oxide layer will also be formed on the side of the dielectric layer away from the first insulating layer. At this time, before removing the dielectric layer in step S160, chemical mechanical polishing or dry etching process can also be used to remove the thermal silicon oxide layer on the surface of this part of the dielectric layer.

[0072] In other implementations, silicon oxide may be prepared by various methods such as chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition to form the second insulating layer.

[0073] Figure 3 is a schematic diagram of the structure of a portion of the through silicon via wafer formed after executing step S120, such as Figure 3 As shown, a second insulating layer 40 is formed on a side of the first substrate 20 away from the first insulating layer.

[0074] Step S130 : forming at least one through silicon via penetrating the second insulating layer and the first substrate along the stacking direction of the composite wafer.

[0075] In some implementations, step S130 may include:

[0076] The second insulating layer is patterned to form at least one first graphic opening on the second insulating layer, and the at least one first graphic opening exposes a portion of the first substrate; a reactive ion etching process (bosch etching process) is used to remove the first substrate directly below the at least one first graphic opening and expose the first insulating layer to form at least one silicon through-hole penetrating the second insulating layer and the first substrate.

[0077] Among them, the second insulating layer after patterning is used as a hard mask. When the first substrate is removed by the Bosch etching process, the first substrate not covered by the second insulating layer after patterning (that is, the first substrate directly below at least one first graphic opening) is etched and removed until the first insulating layer is etched, thereby forming at least one required silicon via. The Bosch etching process can make the etching angle of at least one silicon via formed by etching close to 90±0.1°, thereby ensuring the etching morphology of the silicon via and improving the product yield.

[0078] In some implementations, patterning the second insulating layer includes:

[0079] A patterned photoresist layer is formed on a side of the second insulating layer away from the first substrate using photolithography technology; the second insulating layer is etched using a dry etching process using the patterned photoresist layer as a mask to form at least one first pattern opening on the second insulating layer; and the patterned photoresist layer is removed.

[0080] The photolithography technology may include: coating a photoresist layer on the side of the second insulating layer away from the first substrate, exposing and developing the photoresist layer using a preset mask, so as to present a graphic structure corresponding to the mask pattern of the mask on the photoresist layer, and obtain the desired graphic photoresist layer. In some implementations, a dry silicon oxide etching machine may be used to dry-etch the second insulating layer. The dry silicon oxide etching machine has the advantages of good etching effect, high production efficiency, excellent cost control, and good process flexibility. Compared with the traditional mechanical grinding method, it reduces the physical damage of the wafer during the processing, thereby significantly improving the flatness of the wafer surface.

[0081] Figure 4 is a schematic diagram of the structure of a portion of the through silicon via wafer formed after executing step S130, such as Figure 4 As shown, at this time, at least one through silicon via a penetrating the second insulating layer 40 and the first substrate 10 is formed on the composite wafer.

[0082] Step S140, forming a third insulating layer, the third insulating layer comprising a first insulating layer covering at least one through silicon via sidewall, a second insulating layer covering the second insulating layer, and a third insulating layer of the first insulating layer covering at least one through silicon via bottom.

[0083] In some implementations, the third insulating layer is a thermal silicon oxide layer, and step S140 may include:

[0084] The composite wafer is placed in a high-temperature oxidation furnace, and the heating temperature in the furnace is controlled to be 800-1500°C and the heating time is 12-24 hours to form a thermally oxidized silicon layer covering the second insulating layer, covering at least one sidewall of the silicon through hole, and covering the first insulating layer at the bottom of at least one silicon through hole, thereby forming a third insulating layer.

[0085] Among them, before placing the composite wafer in the high-temperature oxidation furnace, the wafer can also be cleaned to ensure the smooth progress of the oxidation process and the quality and performance of the final product.

[0086] It should be noted that, in the process of forming thermal silicon oxide by using a high-temperature oxidation furnace to form the third insulating layer, a thermal silicon oxide layer will also be formed on the side of the dielectric layer away from the first insulating layer. At this time, before removing the dielectric layer in step S160, chemical mechanical polishing or dry etching process can also be used to remove the thermal silicon oxide layer on the surface of this part of the dielectric layer.

[0087] In other implementations, silicon oxide may be prepared by various methods such as chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition to form the third insulating layer.

[0088] In some implementations, the thickness of the third insulating layer can be 0.5-2.75 um to ensure its insulation effect, while preventing the overall thickness of the wafer from being too thick and the growth cycle from being too long, which would affect the quality and performance of the final product.

[0089] Figure 5 is a schematic diagram of the structure of a portion of the through silicon via wafer formed after executing step S140. Figure 5 As shown, a third insulating layer 50 is formed on the composite wafer, and the third insulating layer includes a first partial insulating layer 51 covering the side wall of at least one through silicon via a, a second partial insulating layer 52 covering the second insulating layer 40, and a third partial insulating layer 53 covering the first insulating layer 20 at the bottom of at least one through silicon via.

[0090] Step S150 , filling at least one through silicon via with a conductive material, and removing excess conductive material outside the at least one through silicon via using a chemical mechanical polishing method.

[0091] In some implementations, step S150 may include:

[0092] A low-pressure chemical vapor deposition method is used to fill the at least one through-silicon via with conductive material for multiple times until the at least one through-silicon via is fully filled; a chemical mechanical polishing method is used to thin the front and back surfaces of the wafer for multiple times to remove excess conductive material outside the at least one through-silicon via.

[0093] Among them, the low-pressure chemical vapor deposition method has a fast filling speed, is not easy to seal prematurely to cause cavities, has good shape retention, and can reduce the generation of void defects. The chemical mechanical polishing method combines the dual effects of chemical corrosion and mechanical removal. While ensuring the material removal efficiency, it can obtain a more perfect surface than simple mechanical polishing, which is beneficial to improving the flatness of the wafer surface and has stronger process controllability.

[0094] In some implementations, the conductive material may be a doped polysilicon layer, the doping type may be P-type or N-type, and the doping concentration may be set according to the device resistance, which is not limited in the present application. Filling the conductive material multiple times can ensure the filling effect and reduce the generation of void defects. It should be noted that when the conductive material is filled multiple times, the conductive material may be deposited on the surface of the dielectric layer and the second part of the insulating layer 52 on the surface of the first substrate. Therefore, it is also necessary to use chemical mechanical polishing to thin the front and back surfaces of the wafer multiple times to remove excess conductive material on the surface of the dielectric layer and the second part of the insulating layer 52 on the surface of the first substrate.

[0095] Figure 6 is a schematic diagram of the structure of a portion of the through silicon via wafer formed after executing step S150. Figure 6 As shown, at least one through silicon via a is filled with a conductive material 60 .

[0096] After executing step S150 , the wafer may be turned over so as to proceed to step S160 .

[0097] Step S160: removing the dielectric layer by dry etching to expose the first insulating layer.

[0098] In some implementations, since the dielectric layer has a certain thickness, a DRIE (Deep Reactive Ion Etching) deep silicon etching machine can be used to remove the dielectric layer. The DRIE deep silicon etching machine has significant advantages over traditional mechanical grinding methods in terms of accuracy and resolution, etching rate and efficiency, damage and surface quality, flexibility and applicability, cost and sustainability.

[0099] Figure 7 is a schematic diagram of the structure of a portion of the through silicon via wafer formed after executing step S160, such as Figure 7 As shown, at this time, the dielectric layer 30 is removed to expose the first insulating layer 20 .

[0100] Step S170: forming at least one opening on the first insulating layer and the third portion of the insulating layer, wherein the at least one opening corresponds to the at least one through silicon via, and the at least one opening exposes the conductive material in the at least one through silicon via.

[0101] In some implementations, step S170 includes:

[0102] A patterned photoresist layer is formed on a side of the first insulating layer away from the first substrate using photolithography technology; the first insulating layer and the third portion of the insulating layer are etched using a dry etching process using the patterned photoresist layer as a mask to form at least one opening on the first insulating layer and the third portion of the insulating layer; and the patterned photoresist layer is removed.

[0103] The photolithography technology may include: coating a photoresist layer on a side of the first insulating layer away from the first substrate, exposing and developing the photoresist layer using a preset mask, so as to present a graphic structure corresponding to the mask pattern of the mask on the photoresist layer, and obtain the desired graphic photoresist layer. In some implementations, a dry silicon oxide etching machine may be used to dry-etch the first insulating layer and the third part of the insulating layer. The dry silicon oxide etching machine has the advantages of good etching effect, high production efficiency, excellent cost control and good process flexibility. Compared with the traditional mechanical grinding method, it reduces the physical damage of the wafer during the processing, thereby significantly improving the flatness of the wafer surface.

[0104] Figure 8 is a schematic diagram of the structure of the through silicon via wafer formed after executing step S170. Figure 8 As shown, at this time, at least one opening b is formed on the first insulating layer 20 and the third partial insulating layer 50, the at least one opening corresponds to at least one through silicon via a one-to-one, and the at least one opening b exposes the conductive material 60 in at least one through silicon via.

[0105] Based on the same inventive concept, the disclosed embodiment also provides a semiconductor manufacturing method for bonding a through silicon via wafer manufactured by the manufacturing method described in the above embodiment to other wafers to form a desired semiconductor structure. Fig. 9 is a flow chart of a semiconductor manufacturing method provided by an embodiment of the present disclosure, such as Fig. 9 As shown, the manufacturing method includes:

[0106] Step S910: providing a first wafer and a second wafer to be bonded, wherein the first wafer is a through silicon via wafer, and the second wafer includes a second substrate.

[0107] The first wafer is a through silicon via wafer manufactured by the manufacturing method shown in the above embodiment, and the second wafer is a device wafer.

[0108] Step S920: forming a bonding structure in at least one opening of the first wafer.

[0109] In some implementations, step S920 may include:

[0110] A bonding structure is formed in at least one opening of the first wafer by adopting a stripping process, wherein the bonding structure comprises a titanium layer and a gold layer which are stacked.

[0111] In some implementations, the thickness of the titanium layer can be 10-100nm, and the thickness of the gold layer can be 10-1000nm. Gold has good conductivity, and titanium has good adhesion, which can improve the adhesion effect between gold and the wafer. The lift-off process, i.e., the LIFT OFF technology, is to obtain a patterned photoresist structure or a metal mask on a substrate using a photolithography process, and then use a coating process to coat the target coating on the mask, and then use a stripping solution (also known as a stripping solution) to dissolve the photoresist or mechanically remove the metal hard mask to obtain a target graphic structure consistent with the pattern. That is, by using a photolithography process on the bonding surface of the first wafer to obtain a patterned photoresist structure or a metal mask, and then using a coating process to coat the mask with titanium / gold bonding material, and then using a stripping solution to dissolve the photoresist or mechanically remove the metal hard mask, a target graphic structure consistent with the pattern is obtained, and the desired bonding structure is obtained.

[0112] Fig.10 is a schematic diagram of the structure of the through silicon via wafer formed after executing step S920, such as Fig.10 As shown, at this time, a bonding structure 70 is formed in at least one opening b of the first wafer 100 .

[0113] Step S930: bonding the first wafer and the second wafer via a bonding structure.

[0114] In some implementations, the first wafer and the second wafer are subjected to high temperature gold-silicon bonding.

[0115] Fig.11 is a schematic diagram of the structure of the through silicon via wafer formed after executing step S930. Fig.11 As shown, at this time, the first wafer 100 and the second wafer 200 are bonded via the bonding structure 70 .

[0116] Step S940: forming at least one electrode on a side of the first wafer away from the second wafer, wherein the at least one electrode is arranged in one-to-one correspondence with the at least one through silicon via, and each electrode is electrically connected to the conductive material filled in the corresponding through silicon via.

[0117] In some implementations, step S940 may include:

[0118] A physical vapor deposition method is used to form an electrode material layer on a side of the first wafer away from the second wafer, wherein the electrode material layer comprises a titanium layer and a gold layer stacked in sequence; and the electrode material layer is patterned to form at least one electrode.

[0119] Among them, the titanium layer has excellent corrosion resistance, which can effectively prevent the electrode from being corroded and extend the service life of the electrode. Gold has good conductivity. The thickness of the titanium layer can be 10-100nm, and the thickness of the gold layer can be 10-1000nm.

[0120] Fig.12 is a schematic diagram of the structure of the through silicon via wafer formed after executing step S940, such as Fig.12 As shown, at this time, at least one electrode 80 is formed on a side of the first wafer 100 away from the second wafer 200, at least one electrode 80 is arranged in a one-to-one correspondence with at least one through silicon via, and each electrode 80 is electrically connected to the conductive material 60 filled in the corresponding through silicon via.

[0121] Step S950: forming a fourth insulating layer on a side of the first wafer away from the second wafer, wherein the fourth insulating layer at least partially covers the electrode to expose the lead portion of the electrode.

[0122] In some implementations, the fourth insulating layer is a silicon oxide layer, and step S950 may include:

[0123] A silicon oxide layer is formed on a side of a first wafer away from a second wafer by plasma enhanced chemical vapor deposition; the silicon oxide layer is patterned to form at least one second pattern opening on the silicon oxide layer, the at least one second pattern opening corresponds to at least one electrode one-to-one, and the at least one second pattern opening exposes a lead portion of at least one electrode.

[0124] Exemplarily, the silicon oxide layer may be patterned by photolithography.

[0125] Fig.13 is a schematic diagram of the structure of the through silicon via wafer formed after executing step S950, such as Fig.13 As shown, at this time, a fourth insulating layer 90 is formed on the side of the first wafer 100 away from the second wafer 200, and at least one second graphic opening c is formed on the fourth insulating layer 90, at least one second graphic opening c corresponds one-to-one to at least one electrode 80, and at least one second graphic opening c exposes the lead portion of at least one electrode.

[0126] The technical solution provided in the embodiments of the present disclosure has at least the following technical effects or advantages:

[0127] The disclosed embodiments provide a method for manufacturing a through silicon via wafer and a semiconductor manufacturing method, which adopts a composite wafer structure, including a first substrate, a first insulating layer and a dielectric layer stacked in sequence, wherein the first insulating layer serves as a stop layer for the TSV through hole, thereby ensuring precise control of the through hole formation and effectively avoiding excessive damage to the wafer body when forming the TSV through hole. The introduction of the dielectric layer not only enhances the overall structural strength of the wafer, but also effectively prevents the risk of the wafer being broken due to uneven force during the formation of the TSV through hole, thereby significantly improving the stability and safety of the production process. When removing excess film layers, the method removes the dielectric layer by using a dry etching process and removes excess conductive materials by using a chemical mechanical polishing method. Compared with traditional mechanical polishing, it can achieve a more uniform and fine removal effect, reduce physical damage to the wafer during processing, and thus significantly improve the flatness of the wafer surface. By optimizing the flatness of the wafer surface, the bonding effect between the TSV wafer and other device wafers is effectively enhanced, the interface defects are reduced, and the bonding strength is improved, thereby ensuring the overall performance and reliability of semiconductor products such as micro-vibration mirror arrays. At the same time, the second insulating layer formed in this method, covering the first surface of the first substrate, can provide additional electrical isolation and protection, help enhance the electrical stability of the entire wafer structure, and prevent potential current leakage or short circuit problems. The third insulating layer can prevent the conductive material in the TSV through-hole from directly contacting other electrical components on the wafer, thereby ensuring the normal operation of the circuit and accurate transmission of signals. In addition, it also helps to protect the TSV through-hole from erosion by the external environment and improve the reliability and service life of the wafer.

[0128] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0129] In the present disclosure, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present disclosure.

[0130] In the description of the present disclosure, unless otherwise clearly stipulated and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0131] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0132] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0133] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for manufacturing a through silicon via wafer, characterized in that: include: Providing a composite wafer, the composite wafer comprising a first substrate, a first insulating layer and a dielectric layer stacked in sequence; forming a second insulating layer covering a first surface, wherein the first surface is a side of the first substrate away from the first insulating layer; Forming at least one through silicon via penetrating the second insulating layer and the first substrate along a stacking direction of the composite wafer; forming a third insulating layer, the third insulating layer comprising a first portion of the insulating layer covering the sidewall of the at least one through silicon via, a second portion of the insulating layer covering the second insulating layer, and a third portion of the insulating layer of the first insulating layer covering the bottom of the at least one through silicon via; Filling the at least one through silicon via with a conductive material, and removing excess conductive material outside the at least one through silicon via by chemical mechanical polishing; Using a dry etching process to remove the dielectric layer to expose the first insulating layer; At least one opening is formed on the first insulating layer and the third partial insulating layer, the at least one opening corresponds to the at least one through silicon via one by one, and the at least one opening exposes the conductive material in the at least one through silicon via.

2. The manufacturing method according to claim 1, characterized in that: The step of forming at least one through silicon via penetrating the second insulating layer and the first substrate along the stacking direction of the composite wafer comprises: Performing a patterning process on the second insulating layer to form at least one first pattern opening on the second insulating layer, wherein the at least one first pattern opening exposes a portion of the first substrate; A reactive ion etching process is used to remove the first substrate directly below the at least one first graphic opening and expose the first insulating layer to form at least one through silicon via penetrating the second insulating layer and the first substrate.

3. The manufacturing method according to claim 2, characterized in that: The step of patterning the second insulating layer includes: Using photolithography technology to form a patterned photoresist layer on a side of the second insulating layer away from the first substrate; Using the patterned photoresist layer as a mask, a dry etching process is used to etch the second insulating layer to form the at least one first pattern opening on the second insulating layer; The patterned photoresist layer is removed.

4. The manufacturing method according to claim 1, characterized in that: The third insulating layer is a thermal silicon oxide layer, and the forming of the third insulating layer includes: The composite wafer is placed in a high-temperature oxidation furnace, and the heating temperature in the furnace is controlled to be 800-1500° C. and the heating time is 12-24 hours to form a thermal oxide silicon layer covering the second insulating layer, covering the sidewall of the at least one silicon through hole, and covering the first insulating layer at the bottom of the at least one silicon through hole.

5. The manufacturing method according to claim 1, characterized in that: The step of filling the at least one through silicon via with a conductive material and removing excess conductive material outside the at least one through silicon via by chemical mechanical polishing comprises: Filling the at least one through silicon via with a conductive material multiple times by using a low pressure chemical vapor deposition method until the at least one through silicon via is fully filled; The wafer is thinned multiple times on the front and back sides by chemical mechanical polishing to remove excess conductive material outside the at least one through silicon via.

6. The manufacturing method according to claim 1, characterized in that: The forming of at least one opening on the first insulating layer and the third partial insulating layer comprises: Using photolithography technology to form a patterned photoresist layer on a side of the first insulating layer away from the first substrate; Using the patterned photoresist layer as a mask, etching the first insulating layer and the third portion of the insulating layer by a dry etching process to form the at least one opening on the first insulating layer and the third portion of the insulating layer; The patterned photoresist layer is removed.

7. The manufacturing method according to claim 1, characterized in that: The first substrate and the dielectric layer are both single crystal silicon layers, and the first insulating layer, the second insulating layer and the third insulating layer are all silicon oxide layers.

8. A semiconductor manufacturing method, characterized in that: include: Providing a first wafer and a second wafer to be bonded, wherein the first wafer is a through silicon via wafer manufactured by the manufacturing method according to any one of claims 1 to 7, and the second wafer includes a second substrate; forming a bonding structure within the at least one opening of the first wafer; bonding the first wafer and the second wafer via the bonding structure; At least one electrode is formed on a side of the first wafer away from the second wafer, the at least one electrode is arranged in a one-to-one correspondence with the at least one through silicon via, and each of the electrodes is electrically connected to the conductive material filled in the corresponding through silicon via; A fourth insulating layer is formed on a side of the first wafer away from the second wafer, wherein the fourth insulating layer at least partially covers the electrode to expose a lead portion of the electrode.

9. The manufacturing method according to claim 8, characterized in that: The forming of at least one electrode on a side of the first wafer away from the second wafer comprises: Forming an electrode material layer on a side of the first wafer away from the second wafer by physical vapor deposition, wherein the electrode material layer comprises a titanium layer and a gold layer stacked in sequence; The electrode material layer is patterned to form the at least one electrode.

10. The manufacturing method according to claim 8, characterized in that: The forming of a bonding structure in the at least one opening of the first wafer comprises: The bonding structure is formed in at least one opening of the first wafer by adopting a stripping process, wherein the bonding structure includes a titanium layer and a gold layer which are stacked.

Images