Chip packaging structure and forming method thereof

Abstract

A chip package structure is provided. The chip package structure includes a carrier substrate. The chip package structure includes a chip structure over a carrier substrate. The chip structure includes a semiconductor substrate having a front side and a back side opposite the front side, the front side facing a carrier substrate, and a device layer between the front side and the carrier substrate. The chip package structure includes a heat dissipation cover over the backside of the semiconductor substrate. The heat dissipation cover has a plate portion and a first protruding portion below the plate portion, and the first protruding portion extends into the semiconductor substrate from the back surface. The embodiment of the invention also relates to a chip packaging structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a chip packaging structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced multiple generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0004] Some embodiments of the present application provide a chip packaging structure, comprising: a carrier substrate; a chip structure located above the carrier substrate, wherein the chip structure includes a semiconductor substrate and a device layer, the semiconductor substrate having a front side and a back side opposite to the front side, the front side faces the carrier substrate, and the device layer is located between the front side and the carrier substrate; and a heat dissipation cover located above the back side of the semiconductor substrate, wherein the heat dissipation cover has a plate portion and a first protrusion portion located below the plate portion, and the first protrusion portion extends from the back side into the semiconductor substrate.

[0005] Some other embodiments of the present application provide a chip packaging structure, comprising: a carrier substrate; a chip structure located on the carrier substrate, wherein the chip structure comprises a substrate and a device layer arranged along a front side of the substrate facing the carrier substrate, the substrate having a side wall forming a groove along a back side of the substrate opposite to the front side; a thermal conductive layer arranged between the side walls of the substrate, wherein a first thermal conductivity of the thermal conductive layer is greater than a second thermal conductivity of the substrate; and a heat dissipation cover located on the back side of the substrate and above the thermal conductive layer, wherein the heat dissipation cover comprises a protrusion extending outward from a lower surface of the heat dissipation cover toward the thermal conductive layer.

[0006] Still other embodiments of the present application provide a method for forming a chip packaging structure, comprising: forming a chip structure to have a device layer arranged along the front side of a substrate, the device layer having a hot spot area; etching the back side of the substrate to form a groove above the hot spot area; bonding the front side of the chip structure to a carrier substrate; and bonding a heat dissipation cover to the back side of the substrate, wherein the heat dissipation cover has a plate portion and a protrusion portion located below the plate portion, the plate portion being located above the back side of the substrate, and the protrusion portion being located in the groove on the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1A to 1D are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0009] Figure 1A-1 is a diagram showing a method according to some embodiments Figure 1A An enlarged cross-sectional view of a portion of a chip structure.

[0010] Figure 1A-2 According to some embodiments Figure 1A Top view of the chip structure.

[0011] Figure 1B-1 is a diagram showing a method according to some embodiments Figure 1B An enlarged cross-sectional view of a portion of a chip packaging structure.

[0012] Figure 1B-2 According to some embodiments Figure 1B Top view of the chip package structure.

[0013] Figure 1C-1 According to some embodiments Figure 1C Top view of the chip package structure.

[0014] Figure 1D-1 According to some embodiments Figure 1D Top view of the chip package structure.

[0015] Figure 2A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0016] Figure 2B According to some embodiments Figure 2A Top view of the chip package structure.

[0017] Figure 3A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0018] Figure 3B According to some embodiments Figure 3A Top view of the chip package structure.

[0019] Figure 4A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0020] Figure 4B According to some embodiments Figure 4A Top view of the chip package structure.

[0021] FIG. 5A to FIG. 5B are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0022] FIG. 6A to FIG. 6B are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0023] Figure 6A-1 According to some embodiments Fig. 6A Top view of the chip package structure.

[0024] Figure 6B-1 According to some embodiments Figure 6B Top view of the chip package structure. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0027] Those skilled in the art will understand the term "substantially" in the description (such as "substantially flat" or "substantially coplanar"). In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" may also include embodiments with "complete", "completely", "all", etc. The term "substantially" may vary in different technologies and is within the range of deviations understood by those skilled in the art. For example, the term "substantially" may also refer to 90% or more of the specified content, such as 95% or more of the specified content, particularly 99% or more of the specified content, including 100% of the specified content, but the disclosed embodiments are not limited thereto. In addition, terms such as "substantially parallel" or "substantially perpendicular" may be interpreted as not excluding insignificant deviations from the specified arrangement, and may include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition that "substantially does not contain" Y may be completely free of Y.

[0028] The term "approximately" may vary in different technologies and is within the range of deviations understood by those skilled in the art. The term "approximately" in conjunction with a specific distance or size should be interpreted as not excluding negligible deviations from the specified distance or size. For example, the term "approximately" may include deviations of up to 10% of the specified content, but the disclosed embodiments are not limited to this. The term "approximately" associated with a numerical value x may represent ±5% or ±10% of the specified content, but the disclosed embodiments are not limited to this.

[0029] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional components may be added to the chip packaging structure. For different embodiments, some of the components described below may be replaced or eliminated. Although some embodiments are discussed with operations implemented in a specific order, these operations may be implemented in another logical order.

[0030] As the component size of the components (e.g., transistors, interconnects, etc.) in the integrated chip continues to decrease, the integrated chip generates more heat. Integrated chip manufacturers have developed solutions that help dissipate such heat. Existing solutions usually focus on uniform heat dissipation (e.g., substantially homogeneous heat dissipation above the chip). However, it has been recognized that different devices in the integrated chip may generate different heat. For example, high performance computing products (HPC) may generate more heat than other devices in the integrated chip. The uneven generation of heat in the integrated chip leads to the formation of local hot spots. If the heat is not effectively dissipated from the local hot spots, it may cause performance degradation, reliability problems, and even cause chip failure.

[0031] Embodiments of the present disclosure relate to a chip packaging structure configured to improve heat dissipation from a local hot spot of an integrated chip (e.g., from an area of ​​a chip having a high-performance computing product). In some embodiments, the chip packaging structure includes a chip structure disposed above a carrier substrate. The chip structure includes a semiconductor substrate having a front side and a back side opposite to the front side. The front side faces the carrier substrate. The device layer is located between the front side and the carrier substrate. A heat dissipation cover is disposed along the back side of the semiconductor substrate. The heat dissipation cover has a plate portion and a protrusion extending outward from the plate portion. The protrusion extends from the back side into the semiconductor substrate and extends toward a local hot spot within the device layer. Because the protrusion is in close proximity to the local hot spot, the protrusion can improve heat dissipation from the local hot spot.

[0032] Figures 1A to 1D is a cross-sectional view of various stages of a process for forming a chip package structure according to some embodiments. Figure 1A As shown in , according to some embodiments, a chip structure 110 is provided. According to some embodiments, the chip structure 110 includes a semiconductor substrate 111, a device layer 112, a thermal conductive plug 113, and a conductive pillar 114.

[0033] According to some embodiments, semiconductor substrate 111 has a front side 111a and a back side 111b opposite to front side 111a. According to some embodiments, device layer 112 is formed over front side 111a. According to some embodiments, thermal conductive plug 113 is formed in semiconductor substrate 111. According to some embodiments, conductive pillar 114 is formed over device layer 112.

[0034] The semiconductor substrate 111 includes, for example, a semiconductor wafer such as a silicon wafer or a portion of a semiconductor wafer. In some embodiments, the semiconductor substrate 111 is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0035] In some other embodiments, the semiconductor substrate 111 is made of a compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide or indium arsenide), an alloy semiconductor (such as SiGe or GaAsP), or a combination thereof. The semiconductor substrate 111 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

[0036] In some embodiments, the device layer 112 includes various device elements and interconnect structures (not shown). Examples of various device elements include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed at the front side 111a of the semiconductor substrate 111. According to some embodiments, passive devices include resistors, capacitors, or other suitable passive devices.

[0037] For example, the transistor may be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), etc. In various embodiments, the MOSFET may include a planar FET, a FinFET, a gate-all-around transistor (e.g., a nanowire transistor), etc.

[0038] Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0039] In some embodiments, an isolation feature (not shown) is formed in semiconductor substrate 111. The isolation feature is used to surround the active region and electrically isolate various device elements formed in and / or over semiconductor substrate 111 in the active region. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0040] According to some embodiments, device layer 112 has a hot spot region 10. According to some embodiments, device elements in hot spot region 10 include, for example, high performance computing (HPC) elements or other elements that tend to generate more heat.

[0041] According to some embodiments, when device elements of device layer 112 operate, the temperature of device layer 112 in hot spot region 10 is higher than the temperature of device layer 112 in other regions.

[0042] In some embodiments, according to some embodiments, the interconnect structure of the device layer 112 includes a dielectric layer, a wiring layer, a conductive via, and a conductive pad. According to some embodiments, the wiring layer, the conductive via, and the conductive pad are located in the dielectric layer. According to some embodiments, the conductive via is electrically connected between the wiring layers, between the wiring layer and the conductive pad, and between the wiring layer and the device element.

[0043] According to some embodiments, the dielectric layer is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphate silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0044] Optionally, according to some embodiments, the dielectric layer includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide or lower than about 3.0 or about 2.5.

[0045] The dielectric layer is formed using a chemical vapor deposition (CVD) process, such as a low pressure CVD process, a plasma enhanced CVD process or a high density plasma CVD process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or another suitable process.

[0046] According to some embodiments, the wiring layers, the conductive vias, and the conductive pads are made of a conductive material, such as a metal (eg, copper, aluminum, or tungsten) or alloys thereof.

[0047] Figure 1A-1 is a diagram showing a method according to some embodiments Figure 1A FIG. 1 is an enlarged cross-sectional view of a portion 20 of a chip structure 110. Figure 1A and Figure 1A-1 As shown in FIG. 1 , according to some embodiments, the thermal conductive plug 113 does not pass through the semiconductor substrate 111 .

[0048] According to some embodiments, portion 111P of semiconductor substrate 111 is located between thermally conductive plug 113 and device layer 112. According to some embodiments, thermal conductivity of thermally conductive plug 113 is greater than thermal conductivity of semiconductor substrate 111.

[0049] According to some embodiments, each thermal plug 113 includes an insulating layer 113 a and a conductive pillar 113 b. According to some embodiments, the insulating layer 113 a wraps around the conductive pillar 113 b. According to some embodiments, the insulating layer 113 a separates the conductive pillar 113 b from the semiconductor substrate 111 .

[0050] According to some embodiments, the conductive pillar 113b is electrically insulated from the semiconductor substrate 111. According to some embodiments, the insulating layer 113a separates the conductive pillar 113b from the device layer 112. According to some embodiments, the conductive pillar 113b is electrically insulated from the device layer 112.

[0051] According to some embodiments, the insulating layer 113a is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphate silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0052] Optionally, according to some embodiments, the insulating layer 113a includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide or lower than about 3.0 or about 2.5. According to some embodiments, the conductive pillar 113b is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0053] According to some embodiments, the formation of the thermal plug 113 includes: partially removing the semiconductor substrate 111 to form a hole 111t in the semiconductor substrate 111; depositing an insulating material layer (not shown) over the back side 111b of the semiconductor substrate 111 and in the hole 111t; forming a conductive layer (not shown) over the insulating material layer and in the hole 111t; and removing the conductive layer and the insulating material layer outside the hole 111t.

[0054] like Figure 1A-1 As shown in FIG. 1 , according to some embodiments, the insulating material layer remaining in the hole 111 t forms the insulating layer 113 a of the thermal plug 113 . According to some embodiments, the conductive layer remaining in the hole 111 t forms the conductive pillar 113 b of the thermal plug 113 .

[0055] The insulating material layer is formed using a chemical vapor deposition (CVD) process, such as a low pressure CVD process, a plasma enhanced CVD process or a high density plasma CVD process, an atomic layer deposition process, a physical vapor deposition process, or another suitable deposition process.

[0056] According to some embodiments, the conductive layer is formed using a plating process (such as an electroplating process) or a deposition process (such as a physical vapor deposition process).

[0057] Figure 1A-2 According to some embodiments Figure 1A A top view of the chip structure 110 is shown. Figure 1A FIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 1A-2 The cross-sectional view of the section line I-I' in FIG. Figure 1A, Figure 1A-1 and Figure 1A-2 According to some embodiments, the thermally conductive plugs 113 are arranged in an array (eg, arranged in rows and columns at substantially equal intervals). In some other embodiments (not shown), the thermally conductive plugs 113 are randomly arranged (eg, spaced at unequal distances relative to each other).

[0058] like Figure 1A As shown in , according to some embodiments, a conductive pillar 114 is formed over a conductive pad of a device layer 112. According to some embodiments, the conductive pillar 114 is electrically connected to the conductive pad. According to some embodiments, the conductive pillar 114 is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0059] Figure 1B-1 is a diagram showing some embodiments of the present invention. Figure 1B FIG. 2 is an enlarged cross-sectional view of a portion 20 of the chip structure 110 . Figure 1B-2 According to some embodiments Figure 1B Top view of the chip package structure.

[0060] Figure 1B FIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 1B-2 Cross-sectional view along the section line II'.

[0061] like Figure 1B , Figure 1B-1 and Figure 1B-2 As shown in , according to some embodiments, the upper portions of the semiconductor substrate 111 and the thermal plugs 113 are removed to form a groove 111c in the semiconductor substrate 111. The groove 111c is formed by the sidewalls and the horizontally extending surface of the semiconductor substrate. According to some embodiments, the groove 111c exposes the top surface 113t of each thermal plug 113. According to some embodiments, the thermal plug 113 is located below the groove 111c.

[0062] like Figure 1B and Figure 1B-2 As shown in FIG. 1 , according to some embodiments, after the removal process, the semiconductor substrate 111 has a thicker portion 111 k and a thinner portion 111 n. According to some embodiments, the thinner portion 111 n is located below the groove 111 c. According to some embodiments, the thinner portion 111 n is thinner than the thicker portion 111 k.

[0063] According to some embodiments, the thicker portion 111 k continuously surrounds the thinner portion 111 n. According to some embodiments, the thermal plug 113 penetrates into the thinner portion 111 n. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0064] like Figure 1BAs shown in FIG. 1 , according to some embodiments, a solder bump 130 is formed on the conductive pillar 114. According to some embodiments, the solder bump 130 is made of tin (Sn) or another suitable conductive material having a melting point lower than that of the conductive pillar 114. According to some embodiments, the solder bump 130 is formed using a plating process such as an electroplating process.

[0065] like Figure 1B As shown in FIG. 1 , according to some embodiments, the chip structure 110 is bonded to a carrier substrate 120 (e.g., a wiring substrate) through solder bumps 130. According to some embodiments, a front side 111a of the semiconductor substrate 111 faces the carrier substrate 120. According to some embodiments, the device layer 112 is located between the front side 111a and the carrier substrate 120.

[0066] According to some embodiments, the carrier substrate 120 includes a dielectric layer, a conductive pad, a wiring layer, and a conductive via (not shown). According to some embodiments, the conductive pad is embedded in the dielectric layer. According to some embodiments, the solder bump 130 is bonded to the conductive pad of the carrier substrate 120 .

[0067] According to some embodiments, the wiring layers of the carrier substrate 120 and the conductive vias are formed in the dielectric layers of the carrier substrate 120. According to some embodiments, the conductive vias electrically connect between different wiring layers and between the wiring layers and the conductive pads.

[0068] According to some embodiments, the dielectric layer is made of an insulating material, such as a polymer material (e.g., polybenzoxazole or polyimide), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, etc. According to some embodiments, the dielectric layer is formed using a lamination process (or a deposition process), a photolithography process, and an etching process.

[0069] According to some embodiments, the conductive pad is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the wiring layer is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the conductive via is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0070] In some embodiments, the conductive pads, the wiring layer, and the conductive vias are made of the same material. In some other embodiments, the conductive pads, the wiring layer, and the conductive vias are made of different materials.

[0071] like Figure 1B As shown in , according to some embodiments, an underfill layer UF is formed between the chip structure 110 and the carrier substrate 120. According to some embodiments, the underfill layer UF surrounds the solder bumps 130 and the conductive pillars 114. According to some embodiments, the underfill layer UF is made of an insulating material, such as a polymer material.

[0072] Figure 1C-1 According to some embodiments Figure 1C Top view of the chip package structure. Figure 1C FIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 1C-1 The cross-sectional view of the section line I-I' in FIG. Figure 1C and Figure 1C-1 As shown in FIG. 1 , according to some embodiments, an adhesive layer 140 is formed over a carrier substrate 120 . According to some embodiments, the adhesive layer 140 has an opening 142 . According to some embodiments, the chip structure 110 is located in the opening 142 .

[0073] According to some embodiments, the adhesive layer 140 is made of a polymer material such as epoxy or silicone. According to some embodiments, the adhesive layer 140 is formed using a dispensing process.

[0074] like Figure 1C and Figure 1C-1 As shown in , according to some embodiments, the ring structure 150 is disposed above the adhesive layer 140. According to some embodiments, the ring structure 150 has a top surface 151. In some embodiments, the top surface 151 is higher than the back surface 111b of the semiconductor substrate 111. In some embodiments, the top surface 151 is substantially flush with the back surface 111b of the semiconductor substrate 111. In some embodiments, the top surface 151 is lower than the back surface 111b of the semiconductor substrate 111.

[0075] According to some embodiments, the ring structure 150 has an opening 152 above the opening 142 of the adhesive layer 140. According to some embodiments, the chip structure 110 is located in the opening 152.

[0076] According to some embodiments, the ring structure 150 is made of a rigid material, such as a metal (eg, copper or iron), an alloy thereof (eg, stainless steel), or another suitable material that is more rigid than the carrier substrate 120 .

[0077] like Figure 1C and Figure 1C-1 As shown in FIG. 1 , according to some embodiments, an adhesive layer 160 is formed over the ring structure 150 , and a thermal conductive layer 170 is formed over the back side 111 b of the semiconductor substrate 111 .

[0078] According to some embodiments, the adhesive layer 160 is made of a combination of a polymer and a metal (eg, silver paste) or a polymer (eg, epoxy or silicone). According to some embodiments, the adhesive layer 160 is formed using a dispensing process.

[0079] According to some embodiments, the thermal conductivity of the heat conductive layer 170 is greater than the thermal conductivity of the semiconductor substrate 111. According to some embodiments, the heat conductive layer 170 is made of a polymer material including silicone or epoxy. According to some embodiments, the polymer material is doped with particles, and the particles are made of aluminum oxide or zinc oxide. According to some embodiments, the heat conductive layer 170 is formed using a dispensing process.

[0080] like Figure 1C and Figure 1C-1 As shown in FIG. 1 , according to some embodiments, a heat conducting layer 180 is formed in a groove 111c of a semiconductor substrate 111. According to some embodiments, the heat conducting layer 180 is in thermal contact with the semiconductor substrate 111 and the heat conducting plug 113. According to some embodiments, the heat conducting layer 180 is in direct contact with the semiconductor substrate 111 and the heat conducting plug 113.

[0081] According to some embodiments, the thermal conductivity of the heat conducting layer 180 is greater than the thermal conductivity of the semiconductor substrate 111. According to some embodiments, the thermal conductivity of the heat conducting layer 180 is greater than the thermal conductivity of the heat conducting layer 170.

[0082] Thus, according to some embodiments, the heat conductive layer 180 may quickly conduct the heat generated by the hot spot area 10 to the heat dissipation cover, which is then bonded to the heat conductive layers 170 and 180 .

[0083] According to some embodiments, the adhesion of thermal conductive layer 170 to semiconductor substrate 111 and heat dissipation cover (heat dissipation cover is subsequently bonded to thermal conductive layers 170 and 180) is greater than the adhesion of thermal conductive layer 180. Therefore, according to some embodiments, thermal conductive layer 170 can firmly fix the heat dissipation cover above semiconductor substrate 111.

[0084] According to some embodiments, thermally conductive layer 180 has a top surface 182. According to some embodiments, top surface 182 faces away from carrier substrate 120. According to some embodiments, top surface 182 is lower than back surface 111b of semiconductor substrate 111. In other embodiments, top surface 182 may be substantially flush with back surface 111b or located above back surface 111b. In some such embodiments, thermally conductive layer 180 laterally contacts semiconductor substrate 111 and thermally conductive layer 170.

[0085] According to some embodiments, thermally conductive layers 170 and 180 are made of different materials. In some embodiments, thermally conductive layer 180 is made of a solid material. In other embodiments, thermally conductive layer 180 is made of a liquid material at room temperature (e.g., at a temperature between about 70 degrees Fahrenheit and about 100 degrees Fahrenheit). Thermally conductive layer 180 can be a liquid material because thermally conductive layer 180 is disposed in a groove that can accommodate a liquid material.

[0086] According to some embodiments, the solid material includes tin (Sn), indium (In), bismuth (Bi), or alloys thereof. According to some embodiments, the liquid material includes gallium (Ga), alloys thereof, or a resin material containing gallium (Ga) or alloys thereof.

[0087] According to some embodiments, if the heat conductive layer 180 is made of a solid material, the heat conductive layer 180 is formed by placing a metal sheet in the groove 111c. According to some embodiments, the metal sheet may be slightly narrower than the groove 111c. According to some embodiments, if the heat conductive layer 180 is made of a liquid material, the heat conductive layer 180 is formed using a dispensing process.

[0088] Figure 1D-1 According to some embodiments Figure 1D Top view of the chip package structure. Figure 1D FIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 1D-1 The cross-sectional view of the section line I-I' in FIG. Figure 1D and Figure 1D-1 As shown in FIG. 1 , according to some embodiments, heat dissipation cover 190 is bonded to ring structure 150 and semiconductor substrate 111 through adhesive layer 160, heat conductive layer 170, and heat conductive layer 180. In this step, according to some embodiments, chip package structure 100 is basically formed.

[0089] According to some embodiments, heat dissipation cover 190 has plate portion 192 and protrusion portion 194. According to some embodiments, protrusion portion 194 protrudes outward from the lower surface of plate portion 192 to below plate portion 192. According to some embodiments, plate portion 192 is located above back surface 111b of semiconductor substrate 111.

[0090] According to some embodiments, the plate portion 192 is located above the heat conducting layer 170. According to some embodiments, the heat conducting layer 170 is located between the semiconductor substrate 111 and the plate portion 192 of the heat dissipation cover 190.

[0091] According to some embodiments, the protruding portion 194 passes through the heat conductive layer 170. According to some embodiments, the thickness T194 of the protruding portion 194 is greater than the thickness T170 of the heat conductive layer 170. According to some embodiments, the protruding portion 194 extends from the back surface 111 b into the semiconductor substrate 111 .

[0092] According to some embodiments, the protrusion 194 is partially located in the groove 111c of the semiconductor substrate 111. According to some embodiments, the protrusion 194 contacts the sidewall of the heat conductive layer 170 and the inner wall s1 of the groove 111c of the semiconductor substrate 111. According to some embodiments, if the heat conductive layer 180 is made of a liquid material, the protrusion 194 may seal the heat conductive layer 180 in the groove 111c.

[0093] According to some embodiments, protrusion 194 is located above thermally conductive layer 180. According to some embodiments, protrusion 194 is in thermal contact with thermally conductive layer 180. According to some embodiments, protrusion 194 is in direct contact with thermally conductive layer 180. According to some embodiments, a thickness T194 of protrusion 194 is greater than a thickness T180 of thermally conductive layer 180.

[0094] According to some embodiments, the heat conductive layer 180 is located between the semiconductor substrate 111 and the protruding portion 194. According to some embodiments, the thickness T111n of the thinner portion 111n of the semiconductor substrate 111 is greater than the thickness T180 of the heat conductive layer 180. According to some embodiments, if the thickness T111n is less than the thickness T180, the thinner portion 111n may be too thin and easily broken.

[0095] According to some embodiments, the protruding portion 194 is located above the thinner portion 111n of the semiconductor substrate 111. According to some embodiments, the thermal conductive layer 180 is located between the thinner portion 111n and the protruding portion 194.

[0096] According to some embodiments, the thermal conductivity of the heat dissipation cap 190 is greater than the thermal conductivity of the semiconductor substrate 111. According to some embodiments, the thermal conductivity of the heat dissipation cap 190 is greater than the thermal conductivity of the heat conductive layer 180.

[0097] According to some embodiments, the heat dissipation cover 190 has a thermal conductivity greater than that of the heat conductive layer 170. According to some embodiments, the heat dissipation cover 190 having high thermal conductivity has a protruding portion 194 close to the hot spot area 10 so as to quickly conduct the heat generated by the hot spot area 10. By quickly conducting the heat generated by the hot spot area 10, the protruding portion 194 of the heat dissipation cover 190 can accelerate the heat dissipation from the hot spot area 10, thereby solving the uneven heat generation at a specific location within the semiconductor substrate 111 (for example, by high performance computing products).

[0098] The heat conductive layer 180 and the heat conductive plug 113 (which have a thermal conductivity greater than that of the semiconductor substrate 111) are also close to the hot spot area 10, thereby further enhancing the heat dissipation of the hot spot area. Therefore, according to some embodiments, the protrusion 194, the heat conductive layer 180 and the heat conductive plug 113 can improve the heat dissipation efficiency of the chip packaging structure 100.

[0099] According to some embodiments, the heat dissipation cover 190 is made of a high thermal conductivity material, such as a metal material (aluminum or copper), an alloy material (eg, stainless steel), or aluminum silicon carbide (AlSiC).

[0100] According to some embodiments, the bonding process includes an annealing process. According to some embodiments, during the annealing process, the adhesive layers 140 and 160 and the thermal conductive layer 170 are cured. According to some embodiments, if the thermal conductive layer 180 is made of a solid material (e.g., a metal sheet), during the annealing process, the solid material is reflowed to fit the shape of the groove 111c. Figure 1D-1 As shown in FIG. 1 , according to some embodiments, the protrusion 194 has a square shape.

[0101] Figure 2A is a cross-sectional view of a chip package structure 200 according to some embodiments. Figure 2B According to some embodiments Figure 2A FIG. 2 is a top view of a chip package structure 200 . Figure 2A FIG. 2 is a diagram showing a chip package structure 200 according to some embodiments. Figure 2B Cross-sectional view along the section line II'.

[0102] like Figure 2A and Figure 2B As shown in FIG. , according to some embodiments, the chip package structure 200 is similar to Figure 1D The chip package structure 100 is different in that the heat dissipation cover 190 further has a protruding portion 196 and the chip package structure 200 further includes a heat conducting layer 210. According to some embodiments, the device layer 112 further has a hot spot area 10A.

[0103] According to some embodiments, protrusion 196 is located below plate portion 192. According to some embodiments, protrusion 196 is spaced apart from protrusion 194. According to some embodiments, protrusion 196 is located above hot spot region 10A.

[0104] According to some embodiments, the protruding portion 196 passes through the heat conducting layer 170. According to some embodiments, the protruding portion 196 extends from the back surface 111b into the semiconductor substrate 111.

[0105] According to some embodiments, the heat conducting layer 210 is located in the groove 111d of the semiconductor substrate 111. According to some embodiments, the protrusion 196 is partially located in the groove 111d. According to some embodiments, the protrusion 196 is in thermal contact with the heat conducting layer 210. According to some embodiments, the protrusion 196 is in direct contact with the heat conducting layer 210. Figure 2B As shown in FIG. 1 , according to some embodiments, the protrusion 196 has a square shape.

[0106] It should be understood that although FIG. 2A to FIG. 2BA semiconductor substrate 111 having two hot spot regions is shown, but the disclosed chip package structure is not limited to having two protruding portions that enhance heat dissipation in two hot spot regions. Instead, the disclosed chip package structure may have additional protruding portions that enhance heat dissipation in additional hot spot regions.

[0107] Figure 3A is a cross-sectional view of a chip package structure 300 according to some embodiments. Figure 3B According to some embodiments Figure 3A FIG. 3 is a top view of a chip package structure 300 . Figure 3A FIG. 3 is a diagram showing a chip package structure 300 according to some embodiments. Figure 3B Cross-sectional view along the section line II'.

[0108] like Figure 3A and Figure 3B As shown in FIG. , according to some embodiments, the chip package structure 300 is similar to Figure 2A and Figure 2B The chip package structure 200 is different in that the protruding portion 194 extends across the hot spot areas 10 and 10A of the device layer 112. Figure 3B As shown in , according to some embodiments, protrusion 194 has a strip shape. In some embodiments (not shown), thermally conductive plugs 113 may be arranged in an array over hot spot regions 10 and 10A and spaced apart from each other by a distance greater than the spacing between thermally conductive plugs in the array.

[0109] Figure 4A is a cross-sectional view of a chip package structure 400 according to some embodiments. Figure 4B According to some embodiments Figure 4A FIG. 4 is a top view of a chip package structure 400 . Figure 4A FIG. 4 is a diagram showing a chip package structure 400 according to some embodiments. Figure 4B The cross-sectional view of the section line I-I' in FIG. Figure 4A and Figure 4B As shown in FIG. , according to some embodiments, the chip package structure 400 is similar to Figure 2A and Figure 2B The chip package structure 200 is different in that the protruding portion 194 and the hot spot area 10 have a ring shape.

[0110] FIG. 5A to FIG. 5B 5 is a cross-sectional view of various stages of a process for forming a chip package structure 500 according to some embodiments. Figure 5A As shown in , according to some embodiments, a chip structure 510 is provided. According to some embodiments, the chip structure 510 includes a substrate 514, a device layer 515, a thermal plug 113 and a conductive pillar 516.

[0111] According to some embodiments, substrate 514 has a front side 514a and a back side 514b opposite to front side 514a. According to some embodiments, device layer 515 is formed over front side 514a. According to some embodiments, thermal plug 113 is formed in substrate 514. According to some embodiments, conductive pillar 516 is formed over device layer 515.

[0112] According to some embodiments, the substrate 514 includes a lower semiconductor layer 511, an upper semiconductor layer 512, and a bonding layer 513. According to some embodiments, the bonding layer 513 is located between the lower semiconductor layer 511 and the upper semiconductor layer 512.

[0113] The lower semiconductor layer 511 or the upper semiconductor layer 512 includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the lower semiconductor layer 511 and the upper semiconductor layer 512 are made of elemental semiconductor materials including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0114] In some other embodiments, the lower semiconductor layer 511 and the upper semiconductor layer 512 are made of a compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide or indium arsenide), an alloy semiconductor (such as SiGe or GaAsP), or a combination thereof. According to some embodiments, the bonding layer 513 is made of an oxide-containing material (e.g., silicon oxide).

[0115] According to some embodiments, the formation of the substrate 514 and the thermal plug 113 includes: providing a lower semiconductor layer 511 and a dielectric layer 513a (e.g., an oxide layer) above the lower semiconductor layer 511; providing an upper semiconductor layer 512 and a dielectric layer 513b (e.g., an oxide layer) above the upper semiconductor layer 512; bonding the upper semiconductor layer 512 to the lower semiconductor layer 511 through the dielectric layers 513b and 513a; forming the thermal plug 113 in the substrate 514; and partially removing the upper semiconductor layer 512, the bonding layer 513, and the thermal plug 113 in the upper semiconductor layer 512 and the bonding layer 513 to form a groove 111c in the substrate 514.

[0116] According to some embodiments, dielectric layers 513a and 513b together form bonding layer 513. According to some embodiments, a bonding process for bonding dielectric layers 513a and 513b includes an oxide fusion bonding process.

[0117] In some embodiments, the device layer 515 includes various device elements and interconnect structures (not shown). Examples of various device elements include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed at the front side 514a of the substrate 514. Passive devices include resistors, capacitors, or other suitable passive devices.

[0118] For example, the transistor can be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), etc.

[0119] Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0120] In some embodiments, an isolation feature (not shown) is formed in the lower semiconductor layer 511. The isolation feature is used to surround the active region and electrically isolate various device elements formed in and / or over the lower semiconductor layer 511 in the active region. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0121] According to some embodiments, the device layer 515 has a hot spot region 10. According to some embodiments, the device elements in the hot spot region 10 include, for example, high performance computing (HPC) elements or other elements that tend to generate more heat.

[0122] According to some embodiments, when device elements of device layer 515 operate, the temperature of device layer 515 in hot spot region 10 is higher than the temperature of device layer 515 in other regions.

[0123] In some embodiments, according to some embodiments, the interconnect structure of the device layer 515 includes a dielectric layer, a wiring layer, a conductive via, and a conductive pad. According to some embodiments, the wiring layer, the conductive via, and the conductive pad are located in the dielectric layer.

[0124] According to some embodiments, the conductive vias electrically connect between wiring layers, between wiring layers and conductive pads, and between wiring layers and device elements.

[0125] According to some embodiments, the dielectric layer is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphate silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0126] Optionally, according to some embodiments, the dielectric layer includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide or lower than about 3.0 or about 2.5.

[0127] The dielectric layer is formed using a chemical vapor deposition (CVD) process, such as a low pressure CVD process, a plasma enhanced CVD process or a high density plasma CVD process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or another suitable process.

[0128] According to some embodiments, the wiring layers, the conductive vias, and the conductive pads are made of a conductive material, such as a metal (eg, copper, aluminum, or tungsten) or alloys thereof.

[0129] According to some embodiments, conductive pillar 516 is formed over conductive pad of device layer 515. According to some embodiments, conductive pillar 516 is electrically connected to conductive pad. According to some embodiments, conductive pillar 516 is made of conductive material, such as metal (e.g., copper, aluminum, or tungsten) or alloys thereof.

[0130] like Figure 5B As shown in , according to some embodiments, implementation Figures 1B to 1D The steps of forming carrier substrate 120, solder bumps 130, adhesive layer 140, ring structure 150, adhesive layer 160, thermal conductive layer 170, thermal conductive layer 180 and heat dissipation cover 190 are performed. In this step, according to some embodiments, chip package structure 500 is basically formed.

[0131] According to some embodiments, the heat conductive layer 180 is formed in the groove 111c. According to some embodiments, the heat conductive layer 180 is located in the upper semiconductor layer 512 and passes through the bonding layer 513. According to some embodiments, the heat conductive layer 180 is in thermal contact with the lower semiconductor layer 511, the upper semiconductor layer 512, and the bonding layer 513. According to some embodiments, the heat conductive layer 180 is in direct contact with the lower semiconductor layer 511, the upper semiconductor layer 512, and the bonding layer 513.

[0132] FIG. 6A to FIG. 6B are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. Figure 6A-1 According to some embodiments Fig. 6A Top view of the chip package structure. Fig. 6AFIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 6A-1 Cross-sectional view along the section line II'.

[0133] According to some embodiments, Figure 1B After the steps, Fig. 6A and Figure 6A-1 As shown in FIG. 1 , an adhesive layer 160 is formed over the ring structure 150 , and an adhesive layer 610 is formed over the back side 111 b of the semiconductor substrate 111 .

[0134] According to some embodiments, the adhesive layer 610 has a ring shape. According to some embodiments, the adhesive layer 610 has an opening 612. According to some embodiments, the opening 612 exposes a portion of the back side 111b of the semiconductor substrate 111.

[0135] According to some embodiments, the adhesive layer 610 is made of a combination of polymer and metal (eg, silver paste) or a polymer (eg, epoxy or silicone). According to some embodiments, the adhesive layer 610 is formed using a dispensing process.

[0136] like Fig. 6A and Figure 6A-1 As shown in FIG. 6 , according to some embodiments, a heat conducting layer 620 is formed in the opening 612 of the adhesive layer 610 and over the back surface 111 b of the semiconductor substrate 111. According to some embodiments, the heat conducting layer 620 has a ring shape.

[0137] According to some embodiments, the heat conductive layer 620 has an opening 622 above the groove 111c of the semiconductor substrate 111. According to some embodiments, the heat conductive layer 620 is made of graphite or a polymer material doped with carbon fillers.

[0138] like Fig. 6A and Figure 6A-1 As shown in FIG. 1 , according to some embodiments, a heat conducting layer 180 is formed in a groove 111 c of a semiconductor substrate 111 .

[0139] Figure 6B-1 According to some embodiments Figure 6B Top view of the chip package structure. Figure 6B FIG. 1 is a diagram showing a chip packaging structure according to some embodiments. Figure 6B-1 Cross-sectional view along the section line II'.

[0140] like Figure 6B and Figure 6B-1 As shown in FIG. 1 , according to some embodiments, heat dissipation cover 190 is bonded to ring structure 150 and semiconductor substrate 111 through adhesive layers 160 and 610, heat conductive layer 620, and heat conductive layer 180. In this step, according to some embodiments, chip package structure 600 is basically formed.

[0141] According to some embodiments, the thermal conductivity of the heat conducting layer 620 is greater than the thermal conductivity of the adhesive layer 610. According to some embodiments, the adhesion of the adhesive layer 610 to the semiconductor substrate 111 and the heat dissipation cover 190 is greater than the adhesion of the heat conducting layer 620.

[0142] The processes and materials used to form the chip package structures 200, 300, 400, 500, and 600 may be similar to or the same as those used to form the chip package structure 100 described above. Figure 1A to Figure 6B-1 The elements represented by the same or similar reference numerals in the present invention have the same or similar structures and materials. Therefore, their detailed description will not be repeated herein.

[0143] According to some embodiments, a chip packaging structure and a method for forming the same are provided. The method (for forming the chip packaging structure) forms a heat dissipation cover having a protruding portion extending toward a hot spot area of ​​a device layer. Because the protruding portion is close to the hot spot area, the protruding portion can quickly conduct the heat generated by the hot spot area.

[0144] The method (for forming a chip packaging structure) also forms a heat-conducting layer in the substrate of the chip structure and below the protruding portion, and the heat-conducting layer is close to the hot spot area. Therefore, the heat-conducting layer can quickly conduct the heat generated by the hot spot area to the heat dissipation cover. Therefore, the heat dissipation efficiency of the chip packaging structure is improved.

[0145] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure located above the carrier substrate. The chip structure includes a semiconductor substrate and a device layer, the semiconductor substrate has a front side and a back side opposite to the front side, the front side faces the carrier substrate, and the device layer is located between the front side and the carrier substrate. The chip packaging structure includes a heat dissipation cover located above the back side of the semiconductor substrate. The heat dissipation cover has a plate portion and a first protrusion located below the plate portion, and the first protrusion extends from the back side into the semiconductor substrate.

[0146] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure located on the carrier substrate. The chip structure includes a substrate and a device layer arranged along a front side of the substrate facing the carrier substrate, and the substrate has a side wall forming a groove along a back side of the substrate opposite to the front side. The chip packaging structure includes a heat conducting layer arranged between the side walls of the substrate. The first thermal conductivity of the heat conducting layer is greater than the second thermal conductivity of the substrate. The chip packaging structure includes a heat dissipation cover located on the back side of the substrate and above the heat conducting layer. The heat dissipation cover includes a protrusion extending outward from a lower surface of the heat dissipation cover toward the heat conducting layer.

[0147] According to some embodiments, a method for forming a chip package structure is provided. The method includes: forming a chip structure to have a device layer arranged along the front side of a substrate, the device layer having a hot spot area; etching the back side of the substrate to form a groove above the hot spot area; bonding the front side of the chip structure to a carrier substrate. The method includes: bonding a heat dissipation cover to the back side of the substrate. The heat dissipation cover has a plate portion and a protrusion portion located below the plate portion, the plate portion is located above the back side of the substrate, and the protrusion portion is located in the groove on the back side of the substrate.

[0148] Some embodiments of the present application provide a chip packaging structure, comprising: a carrier substrate; a chip structure located above the carrier substrate, wherein the chip structure includes a semiconductor substrate and a device layer, the semiconductor substrate having a front side and a back side opposite to the front side, the front side faces the carrier substrate, and the device layer is located between the front side and the carrier substrate; and a heat dissipation cover located above the back side of the semiconductor substrate, wherein the heat dissipation cover has a plate portion and a first protrusion portion located below the plate portion, and the first protrusion portion extends from the back side into the semiconductor substrate.

[0149] In some embodiments, the chip packaging structure further includes: a first heat-conducting layer, located between the semiconductor substrate of the chip structure and the plate portion of the heat dissipation cover. In some embodiments, the first protruding portion of the heat dissipation cover passes through the first heat-conducting layer. In some embodiments, the chip packaging structure further includes: a second heat-conducting layer, located between the semiconductor substrate of the chip structure and the first protruding portion of the heat dissipation cover. In some embodiments, the semiconductor substrate of the chip structure has a thicker portion and a thinner portion, the thinner portion is thinner than the thicker portion, and the first protruding portion of the heat dissipation cover is located above the thinner portion. In some embodiments, the thicker portion surrounds the thinner portion of the semiconductor substrate of the chip structure. In some embodiments, the chip packaging structure further includes: a heat-conducting layer, located between the thinner portion of the semiconductor substrate of the chip structure and the first protruding portion of the heat dissipation cover. In some embodiments, the chip packaging structure further includes: a thermally conductive plug, penetrating into the thinner portion of the semiconductor substrate of the chip structure, wherein the thermally conductive plug is electrically insulated from the device layer. In some embodiments, the thermally conductive plug includes a conductive column and an insulating layer wrapping the conductive column, and the insulating layer separates the conductive column from the device layer and the semiconductor substrate of the chip structure. In some embodiments, the chip packaging structure further includes: a thermally conductive layer located between the semiconductor substrate of the chip structure and the plate portion of the heat dissipation cover; and an adhesive layer surrounding the thermally conductive layer and located between the semiconductor substrate of the chip structure and the plate portion of the heat dissipation cover. In some embodiments, the heat dissipation cover also has a second protruding portion located below the plate portion and spaced apart from the first protruding portion, and the second protruding portion extends from the back side into the semiconductor substrate.

[0150] Some other embodiments of the present application provide a chip packaging structure, comprising: a carrier substrate; a chip structure located on the carrier substrate, wherein the chip structure comprises a substrate and a device layer arranged along a front side of the substrate facing the carrier substrate, the substrate having a side wall forming a groove along a back side of the substrate opposite to the front side; a thermal conductive layer arranged between the side walls of the substrate, wherein a first thermal conductivity of the thermal conductive layer is greater than a second thermal conductivity of the substrate; and a heat dissipation cover located on the back side of the substrate and above the thermal conductive layer, wherein the heat dissipation cover comprises a protrusion extending outward from a lower surface of the heat dissipation cover toward the thermal conductive layer.

[0151] In some embodiments, the thermally conductive layer has a top surface facing away from the carrier substrate, and the top surface is lower than the back surface of the substrate of the chip structure. In some embodiments, the substrate includes a lower semiconductor layer, an upper semiconductor layer, and a bonding layer located between the lower semiconductor layer and the upper semiconductor layer, and the thermally conductive layer is embedded in the upper semiconductor layer and passes through the bonding layer. In some embodiments, the thermally conductive layer contacts the lower semiconductor layer, the upper semiconductor layer, and the bonding layer.

[0152] Still other embodiments of the present application provide a method for forming a chip packaging structure, comprising: forming a chip structure to have a device layer arranged along the front side of a substrate, the device layer having a hot spot area; etching the back side of the substrate to form a groove above the hot spot area; bonding the front side of the chip structure to a carrier substrate; and bonding a heat dissipation cover to the back side of the substrate, wherein the heat dissipation cover has a plate portion and a protrusion portion located below the plate portion, the plate portion being located above the back side of the substrate, and the protrusion portion being located in the groove on the back side of the substrate.

[0153] In some embodiments, the method for forming a chip packaging structure further includes: before the heat dissipation cover is bonded to the back side of the substrate, forming a first heat conductive layer in the groove on the back side of the substrate, wherein the protruding portion of the heat dissipation cover is located above the first heat conductive layer. In some embodiments, the method for forming a chip packaging structure further includes: before the heat dissipation cover is bonded to the back side of the substrate, forming a second heat conductive layer above the back side of the substrate, wherein the plate portion of the heat dissipation cover is located above the second heat conductive layer. In some embodiments, the substrate of the chip structure includes a lower semiconductor layer, an upper semiconductor layer, and a bonding layer between the lower semiconductor layer and the upper semiconductor layer, and the first heat conductive layer is located in the upper semiconductor layer and passes through the bonding layer. In some embodiments, the chip structure further includes: a thermally conductive plug penetrating into a portion of the substrate below the groove, wherein the thermally conductive plug is electrically insulated from the device layer.

[0154] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A chip packaging structure, comprising: a carrier substrate; a chip structure located above the carrier substrate, wherein the chip structure comprises a semiconductor substrate and a device layer, the semiconductor substrate having a front side and a back side opposite to the front side, the front side faces the carrier substrate, and the device layer is located between the front side and the carrier substrate; and A heat dissipation cover is located above the back surface of the semiconductor substrate, wherein the heat dissipation cover has a plate portion and a first protrusion portion located below the plate portion, and the first protrusion portion extends from the back surface into the semiconductor substrate.

2. The chip packaging structure according to claim 1, further comprising: A first heat conducting layer is located between the semiconductor substrate of the chip structure and the plate portion of the heat dissipation cover.

3. The chip packaging structure according to claim 2, wherein: The first protruding portion of the heat dissipation cover passes through the first heat conductive layer.

4. The chip packaging structure according to claim 2, further comprising: The second heat-conducting layer is located between the semiconductor substrate of the chip structure and the first protruding portion of the heat dissipation cover.

5. The chip packaging structure according to claim 1, wherein: The semiconductor substrate of the chip structure has a thicker portion and a thinner portion, the thinner portion is thinner than the thicker portion, and the first protruding portion of the heat dissipation cover is located above the thinner portion.

6. The chip packaging structure according to claim 5, wherein: The thicker portion surrounds the thinner portion of the semiconductor substrate of the chip structure.

7. The chip packaging structure according to claim 5, further comprising: A heat conducting layer is located between the thinner portion of the semiconductor substrate of the chip structure and the first protruding portion of the heat dissipation cover.

8. The chip packaging structure according to claim 5, further comprising: A thermally conductive plug penetrates into the thinner portion of the semiconductor substrate of the chip structure, wherein the thermally conductive plug is electrically insulated from the device layer.

9. A chip packaging structure, comprising: a carrier substrate; A chip structure located on the carrier substrate, wherein the chip structure comprises a substrate and a device layer arranged along a front surface of the substrate facing the carrier substrate, and the substrate has a sidewall forming a groove along a back surface of the substrate opposite to the front surface; a heat-conducting layer disposed between the side walls of the substrate, wherein a first thermal conductivity of the heat-conducting layer is greater than a second thermal conductivity of the substrate; and A heat dissipation cover is located on the back side of the substrate and above the heat conduction layer, wherein the heat dissipation cover comprises a protrusion extending outward from a lower surface of the heat dissipation cover toward the heat conduction layer.

10. A method for forming a chip packaging structure, comprising: forming a chip structure to have a device layer disposed along a front side of a substrate, the device layer having a hot spot region; etching a back side of the substrate to form a recess over the hot spot region; bonding the front side of the chip structure to a carrier substrate; as well as A heat dissipation cover is bonded to the back side of the substrate, wherein the heat dissipation cover has a plate portion and a protrusion portion below the plate portion, the plate portion is located above the back side of the substrate, and the protrusion portion is located in the groove of the back side of the substrate.

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