Packaging structure and forming method thereof

Abstract

A package structure and a method of forming the same are provided. The package structure includes a first die formed over a substrate and a cap structure formed over the first die. The package structure also includes a thermal interface material structure between the first die and the cap structure. The thermal interface material structure includes a plurality of first protruding structures connected to the first die, a plurality of second protruding structures connected to the cap structure, and a thermally conductive material between the first protruding structures and the second protruding structures.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: depositing insulating or dielectric layers, conductive layers, and semiconductive material layers in sequence over a semiconductor substrate; and patterning the various material layers using photolithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and the individual dies on the wafer are separated by sawing along scribe lines between the integrated circuits. The individual dies are typically packaged individually, for example in a multi-chip module or other type of package.

[0003] New packaging technologies have begun to be developed, such as package-on-package (PoP), in which a top package with a device die is bonded to a bottom package with another device die. By adopting new packaging technologies, various packages with different or similar functions can be integrated together.

[0004] While existing packages and methods of making packages are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a packaging structure, including: a first tube core, located above a substrate; a cover structure, located above the first tube core; and a thermal interface material structure, located between the first tube core and the cover structure, wherein the thermal interface material structure includes: a plurality of protrusion structures connected to the first tube core; a plurality of additional protrusion structures connected to the cover structure; and a thermally conductive material, located between the protrusion structures and the additional protrusion structures.

[0006] Other embodiments of the present application provide a packaging structure, including: a first tube core and a second tube core, located above a substrate, wherein the top surface of the first tube core is higher than the top surface of the second tube core; a plurality of first protrusion structures extending upward from the first tube core; a plurality of second protrusion structures extending upward from the second tube core; a cover structure located on the first tube core and the second tube core; and a plurality of additional protrusion structures extending downward from the cover structure, wherein the first protrusion structures, the second protrusion structures and the additional protrusion structures are sealed by a thermally conductive material to form a thermal interface material structure.

[0007] Some other embodiments of the present application provide a method for forming a packaging structure, comprising: forming a first tube core on a substrate; forming a plurality of protrusion structures on the first tube core; setting a cover structure above the first tube core; forming a plurality of additional protrusion structures below the cover structure, wherein the plurality of protrusion structures are parallel to the plurality of additional protrusion structures; and forming a thermal interface material structure between the first tube core and the cover structure, wherein the plurality of protrusion structures and the plurality of additional protrusion structures are sealed by a thermally conductive material to form the thermal interface material structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] FIG. 1A to FIG. 1I Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0010] Figure 2 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0011] Figure 3 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0012] Figure 4 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0013] Figure 5 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0014] FIG. 6A to FIG. 6C Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0015] 7A to 7H Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0016] Figure 8 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0017] Fig. 9 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0018] Fig.10 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0019] Fig.11 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0020] Fig.12 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0021] FIG. 13A to FIG. 13C Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0022] FIG. 14A to FIG. 14C Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0023] Fig.15 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0024] FIG. 16A to FIG. 16F Cross-sectional representations of various stages in forming a package structure according to some embodiments of the present disclosure are shown.

[0025] Fig.17 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0026] Fig.18 A cross-sectional representation of a package structure according to some embodiments of the present disclosure is shown.

[0027] FIG. 19A to FIG. 19F A top view of a protruding structure according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.

[0030] The all-around gate (GAA) transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller spacing than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0031] The fins described below can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0032] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0033] Embodiments for packaging structures and methods for forming the same are provided. The packaging structure includes a tube core formed above a substrate. A protrusion structure thermally connected to the tube core is formed on the tube core. A cover structure having an additional protrusion structure is provided, and the additional protrusion structure is formed below the cover structure and thermally connected to the cover structure. The cover structure is arranged above the tube core, and a thermal interface material (TIM) structure is composed of a protrusion structure formed on the tube core and an additional protrusion structure formed below the cover structure. The heat or thermal energy generated by the tube core can be transmitted to the external environment through the protrusion structure and the additional protrusion structure in the thermal interface material (TIM) structure. The stacked alternating protrusion structure and the additional protrusion structure in the thermal interface material (TIM) structure are configured to improve heat dissipation efficiency. Therefore, the power efficiency and performance of the packaging structure are improved.

[0034] FIG. 1A to FIG. 1I Shown are cross-sectional representations of various stages in forming a package structure 100 a in accordance with some embodiments of the present disclosure.

[0035] refer to Figure 1A , a carrier substrate 102 is provided. According to some embodiments, the carrier substrate 102 is configured to provide temporary mechanical and structural support during subsequent processing steps. According to some embodiments, the carrier substrate 102 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof, etc. According to some embodiments, the carrier substrate 102 includes a metal frame.

[0036] An interconnect structure 110 is formed over the carrier substrate 102. The interconnect structure 110 may be used as a redistribution (RDL) structure for wiring. The interconnect structure 110 includes a plurality of dielectric layers 112 and a plurality of conductive layers 116. In some embodiments, some of the conductive layers 116 are exposed at or protrude from the top surface of the top of the dielectric layer 112. The exposed or protruding conductive layer 116 may be used as a bonding pad, where a conductive bump (such as a tin-containing solder bump) and / or a conductive pillar (such as a copper pillar) will be formed later.

[0037] The dielectric layer 112 may be made of or include one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymer materials, or a combination thereof. In some embodiments, the polymer material is photosensitive. In some embodiments, some or all of the dielectric layer 112 may be made of or include a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

[0038] Afterwards, if Figure 1BAs shown in , according to some embodiments of the present disclosure, a semiconductor die 120 is formed over a carrier substrate 102 .

[0039] The semiconductor die 120 is sawn from a wafer and may be a “known good die”. The semiconductor die 120 may be a system on chip (SoC) chip. In some other embodiments, the semiconductor die 120 is a system on integrated circuit (SoIC) device including two or more chips with integrated functions. The semiconductor die 120 is disposed above the interconnect structure 110.

[0040] The semiconductor die 120 has a substrate 121, a semiconductor structure 10 formed on the substrate 102, and a substrate 122 formed on the semiconductor structure 10. In some embodiments, the semiconductor structure 10 is a logic device. For example, in some embodiments, the semiconductor structure 10 may be or include a FinFET device, a planar FET, etc. In some embodiments, the semiconductor structure 10 is a full-all-around (GAA) transistor structure. In such an embodiment, the semiconductor structure 10 includes a nanostructure 12 (or referred to as a channel layer), an internal spacer layer 14, a source / drain (S / D) structure 16, and a gate structure 18 formed above the substrate 121. The internal spacer layer 14 is located between the nanostructure 12 and the S / D structure 16. The source / drain (S / D) structure or region may refer to a source or a drain, individually or collectively depending on the context.

[0041] In some embodiments, the nanostructure 12 is made of a semiconductor material, such as Si or SiGe. In some embodiments, the internal spacer layer 14 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the S / D structure 16 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.

[0042] The gate structure 18 includes a gate dielectric layer and a gate electrode layer. The nanostructure 12 is surrounded by (e.g., wrapped in) the gate dielectric layer. In some embodiments, the gate dielectric layer includes one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate electrode layer includes one or more conductive material layers, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, another suitable material, or a combination thereof.

[0043] Substrate 121 and substrate 122 may be semiconductor dies or wafers, such as silicon dies or wafers. Alternatively or additionally, substrate 121 and substrate 122 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP. In some embodiments, substrate 121 and substrate 122 are made of silicon (Si).

[0044] In some embodiments, a plurality of conductive pads 124 are formed under semiconductor die 120 and each of conductive pads 124 is bonded to conductive layer 126. Each of conductive layers 126 is bonded to each of conductive layers 116 through a plurality of conductive connectors 128.

[0045] The conductive pad 124 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, the conductive pad 124 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0046] Conductive layer 126 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, conductive layer 126 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process and / or physical vapor deposition (PVD) process.

[0047] The conductive connector 128 is made of a solder material, such as tin (Sn), tin-silver (SnAg), tin-lead (SnPb), tin-copper (SnCu), tin-silver-copper (SnAgCu), tin-silver-zinc (SnAgZn), tin-zinc (SnZn), tin-bismuth-indium (SnBiIn), tin-indium (SnIn), tin-gold (SnAu), tin-zinc-indium (SnZnIn), tin-silver-antimony (SnAgSb), or another suitable material. In some embodiments, the conductive connector 128 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process, and / or physical vapor deposition (PVD) process.

[0048] Afterwards, if Figure 1C As shown in FIG. 1 , according to some embodiments of the present disclosure, an underfill layer 148 is formed between the semiconductor die 120 and the interconnect structure 110. The underfill layer 148 surrounds and protects the conductive layer 126 and the conductive connector 128. In some embodiments, the underfill layer 148 is in direct contact with the conductive layer 126 and the conductive connector 128.

[0049] In some embodiments, the underfill layer 148 is made of or includes a polymer material. The underfill layer 148 may include an epoxy-based resin. In some embodiments, the underfill layer 148 includes a filler dispersed in an epoxy-based resin.

[0050] In some embodiments, the formation of the underfill layer 148 involves an injection process, a spin coating process, a dispensing process, a film lamination process, an application process, one or more other suitable processes, or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the underfill layer 148 .

[0051] Afterwards, encapsulation layer 150 is formed over underfill layer 148. Encapsulation layer 150 is also formed over substrate 122. An interface exists between underfill layer 148 and encapsulation layer 150, and the interface is lower than the top surface of semiconductor die 120.

[0052] Encapsulation layer 150 surrounds and protects semiconductor die 120 . In some embodiments, encapsulation layer 150 is in direct contact with portions of semiconductor die 120 .

[0053] The encapsulation layer 150 is made of a molding compound material. The molding compound material may include a polymer material, such as an epoxy-based resin with a filler dispersed therein. In some embodiments, a liquid molding compound material is applied over the semiconductor die 120. A thermal process is then used to cure the liquid molding compound material and convert it into the encapsulation layer 150.

[0054] Afterwards, if Figure 1DAs shown in FIG. 1 , according to some embodiments of the present disclosure, portions of encapsulation layer 150 are removed to expose a top surface of substrate 122 of semiconductor die 120. In some embodiments, portions of encapsulation layer 150 are removed by a planarization process, such as a chemical mechanical polishing (CMP) process.

[0055] Thereafter, according to some embodiments of the present disclosure, a carrier substrate 160 is formed over the substrate 122 of the semiconductor die 120 and the encapsulation layer 150 .

[0056] Carrier substrate 160 serves as a temporary substrate. Carrier substrate 160 provides mechanical and structural support during subsequent processing steps, such as those described in more detail later. In some embodiments, substrate 122 of semiconductor die 120 is bonded to carrier substrate 160. For example, substrate 122 and encapsulation layer 150 are attached to carrier substrate 160 by an adhesive layer (not shown). The adhesive layer serves as a temporary adhesive layer.

[0057] Afterwards, if Figure 1E As shown in , according to some embodiments of the present disclosure, flipping Figure 1D , and remove the carrier substrate 102. Next, according to some embodiments of the present disclosure, a portion of the conductive layer 116 of the interconnect structure 110 is removed. Thus, the conductive layer 116 of the interconnect structure 110 is exposed.

[0058] Afterwards, a plurality of conductive connectors 164 are formed over the exposed conductive layer 116 of the interconnect structure 110. The conductive connectors 164 are electrically connected to the conductive layer 116 of the interconnect structure 110. In some embodiments, the conductive connectors 164 are called controlled collapse chip connection (C4) bumps. In some other embodiments, the conductive connectors 164 are micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), ball grid array (BGA) bumps, etc.

[0059] Afterwards, if Figure 1F As shown in , according to some embodiments of the present disclosure, flipping Figure 1E , and the carrier substrate 160 is removed to expose the top surface of the substrate 122 .

[0060] Next, if Figure 1G As shown in , according to some embodiments of the present disclosure, a plurality of protrusion structures 210 are formed on the substrate 122 of the semiconductor die 120. The protrusion structures 210 are formed on the substrate 122 and are in direct contact with the substrate 122 of the semiconductor die 120. The protrusion structures 210 are parallel to each other. The protrusion structures 210 protrude from the top surface of the substrate 122 of the semiconductor die 120. In other words, the protrusion structures 210 extend upward from the top surface of the substrate 122 of the semiconductor die 120.

[0061] In some embodiments, the protruding structure 210 is made of a thermally conductive material. In some embodiments, the thermally conductive material of the protruding structure 210 includes aluminum (Al), Al alloy, copper (Cu), Cu alloy, silver (Ag), Ag alloy, gold (Au), Au alloy, a combination thereof, or another suitable material. In some embodiments, the thermally conductive material of the protruding structure 210 has a thermal conductivity ranging from about 200 W / m·K to about 2000 W / m·K.

[0062] In some embodiments, the protruding structure 210 is formed by a deposition process, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, electroplating, chemical plating, and / or printing.

[0063] Afterwards, if Figure 1H As shown in , according to some embodiments of the present disclosure, a cover structure 310 is provided, and a plurality of additional protrusion structures 320 are formed below a lower surface of the cover structure 310 .

[0064] The cover structure 310 has a main portion 310a and a leg portion 310b extending from the main portion 310a. The leg portion 310b is configured to be attached to the package substrate 360 ​​(see Fig. 1I In some embodiments, the cap structure 310 has a high thermal conductivity, for example, between about 200 W / m·K and about 400 W / m·K. In some embodiments, the cap structure 310 is made of copper (Cu), copper alloy, copper tungsten (CuW), or aluminum silicon carbide (AlSiC), or an applicable material.

[0065] The additional protrusion structure 320 is formed below the cover structure 310 and is in direct contact with the lower surface of the cover structure 310. The additional protrusion structures 320 are parallel to each other. In some embodiments, the protrusion structure 210 and the additional protrusion structure 320 are made of different materials. In some other embodiments, the protrusion structure 210 and the additional protrusion structure 320 are made of the same material.

[0066] In some embodiments, the additional protruding structure 320 is made of a thermally conductive material. In some embodiments, the thermally conductive material of the additional protruding structure 320 includes aluminum (Al), Al alloy, copper (Cu), Cu alloy, silver (Ag), Ag alloy, gold (Au), Au alloy, a combination thereof, or another applicable material. In some embodiments, the thermally conductive material of the additional protruding structure 320 has a thermal conductivity in the range from about 200 W / m·K to about 2000 W / m·K. In some embodiments, the additional protruding structure 320 is formed by a deposition process, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, electroplating, chemical plating, and / or printing. In some other embodiments, the additional protruding structure 320 is formed by metal precision processing.

[0067] Afterwards, if Fig. 1I As shown in , according to some embodiments, semiconductor die 120 is bonded to package substrate 360 ​​via conductive connector 164. In some embodiments, package substrate 360 ​​is a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate. During bonding of semiconductor die 120 to package substrate 360, protruding structure 210 is laterally staggered with additional protruding structure 320.

[0068] Next, one or more thermally conductive materials 325 are dispersed on semiconductor die 120 and between protruding structures 210 and additional protruding structures 320 and then cured by applying heat to form thermal interface material (TIM) structure 350. Lid structure 310 is attached to package substrate 360 ​​by adhesive 364.

[0069] Protruding structure 210 and additional protruding structure 320 are sealed by thermally conductive material 325 to form thermal interface material (TIM) structure 350 on semiconductor die 120 . Thermal interface material (TIM) structure 350 is configured to dissipate thermal energy or heat from semiconductor die 120 to cap structure 310 .

[0070] In some embodiments, the thermally conductive material 325 includes aluminum oxide, boron nitride, aluminum nitride, aluminum, copper, silver, indium, combinations thereof, or suitable materials.

[0071] In some embodiments, the thermal interface material (TIM) structure 350 includes a polymer material. In some embodiments, the thermal interface material (TIM) structure 350 includes other materials, such as metal-based or solder-based materials including silver, indium paste, or applicable materials. In some other embodiments, the thermal interface material (TIM) structure 350 includes a film-based or sheet-based material, such as a sheet-based material including synthetic carbon nanotubes (CNTs) or a thermally conductive sheet with vertically oriented graphite fillers. In some embodiments, the adhesive 364 is made of a polymer with good thermal conductivity.

[0072] Because protrusion structure 210 is physically and thermally connected to substrate 122 of semiconductor die 120, heat can be vertically transferred through protrusion structure 210. Additional protrusion structures 320 and protrusion structure 210 are arranged alternately, and heat can be horizontally transferred from protrusion structure 210 to additional protrusion structure 320 through thermal conductive material 325. Because additional protrusion structure 320 is physically and thermally connected to lid structure 310, heat can again be vertically transferred from additional protrusion structure 320 to lid structure 310. In some embodiments, arrow 327 indicates a general direction in which heat is dissipated from semiconductor die 120 through protrusion structure 210 and additional protrusion structure 320 to lid structure 310.

[0073] Heat generated by semiconductor die 120 may be transferred to the external environment through thermal interface material (TIM) structure 350. Heat may be transferred vertically and horizontally through protrusion structure 210 and additional protrusion structure 320. Protrusion structure 210 and additional protrusion structure 320 are stacked in an alternating manner to improve heat dissipation efficiency.

[0074] Furthermore, the protrusion structure 210 is thermally connected to the semiconductor die 120, and the additional protrusion structure 320 is thermally connected to the lid structure 310. When compared to the thermal interface material (TIM) structure 350 without any protrusion structure, the contact area of ​​the protrusion structure 210 and the semiconductor die 120 and the contact area of ​​the additional protrusion structure 320 and the lid structure 310 are larger to increase the heat dissipation efficiency.

[0075] The thermal interface material (TIM) structure 350 having the protruding structure 210 and the additional protruding structure 320 provides high heat dissipation efficiency and, therefore, improves the performance of the package structure 100 a .

[0076] Figure 2 FIG. 1 shows a cross-sectional representation of a package structure 100 b (eg, a semiconductor device structure) according to some embodiments of the present disclosure. The package structure 100 b is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1I The processes and materials used to form package structure 100b may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0077] Figure 2 and Fig. 1I The difference between the two is that an external cooling unit 370 is formed on the cap structure 310. The external cooling unit 370 is physically and thermally connected to the cap structure 310. The external cooling unit 370 is configured to dissipate heat from the semiconductor die 120 to the external environment through the thermal interface material (TIM) structure 350 and the cap structure 310.

[0078] In some embodiments, the external cooling unit 370 includes a heat sink for radiating heat to the surrounding environment. In some embodiments, the external cooling unit 370 includes at least one thermally conductive plate. In some other embodiments, the external cooling unit 370 includes another suitable heat transfer structure to help reduce the heat generated by the semiconductor die 120.

[0079] In some embodiments, the area of ​​the external cooling unit 370 is larger than the area of ​​the cap structure and the area of ​​the semiconductor die 120. The external cooling unit 370 is added after the cap structure 310 is formed on the package substrate 360. In some other embodiments, the external cooling unit 370 is added on the cap structure 310 before the cap structure 310 is formed on the package substrate 360.

[0080] Figure 3 FIG. 1 shows a cross-sectional representation of a package structure 100c according to some embodiments of the present disclosure. The package structure 100c is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1I The processes and materials used to form package structure 100c may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0081] Figure 3 and Fig. 1I The difference between the two is that the leg portion 310b of the cover structure 310 is replaced with a ring structure 312. The material of the ring structure 312 is different from that of the cover structure 310. The ring structure 312 is bonded to the cover structure 310 by an adhesive 364.

[0082] The ring structure 312 is made of a material with a low coefficient of thermal expansion. In some embodiments, the ring structure 312 is made of copper, a copper alloy, copper tungsten (CuW) or aluminum silicon carbide (AlSiC) or another suitable material.

[0083] Figure 4 FIG. 1 shows a cross-sectional representation of a package structure 100d according to some embodiments of the present disclosure. The package structure 100d is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1I The processes and materials used to form package structure 100d may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0084] Figure 4 and Fig. 1I The difference between the first stacked die 130a and the second stacked die 130b is that the first stacked die 130a and the second stacked die 130b are formed adjacent to the semiconductor die 120, and the external cooling unit 370 is formed on the cover structure 310. The protruding structure 210 is also formed on the first stacked die 130a and the second stacked die 130b, and is physically and thermally connected to the first stacked die 130a and the second stacked die 130b. More specifically, the protruding structure 210 is formed on the top substrate 132 of the first stacked die 130a and the second stacked die 130b.

[0085] The semiconductor die 120 is located between the first stacked die 130a and the second stacked die 130b. The first stacked die 130a and the second stacked die 130b are arranged above the interconnect structure 110. The first stacked die 130a and the second stacked die 130b are located at opposite sides of the semiconductor die 120. Each of the first stacked die 130a and the second stacked die 130b may include a plurality of semiconductor dies. In some embodiments, the semiconductor die is a memory die. The semiconductor die 120 has a function different from each of the memory die. The memory die may include a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) or another memory die. The number of semiconductor dies is not limited to four, and the number can be adjusted according to the actual application.

[0086] The semiconductor die is stacked on a buffer die (or base die) 131 implemented as a logic circuit. The semiconductor dies are bonded to each other through a plurality of bonding structures 136. A plurality of through substrate vias (TSVs) 134 are formed in the semiconductor die. Signals between semiconductors can be transmitted through the through substrate vias (TSVs) 134 and the bonding structures 136. A top substrate 132 is formed on the semiconductor die. In some embodiments, the top substrate 132 includes silicon, an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material.

[0087] Figure 5 FIG. 4 shows a cross-sectional representation of a package structure 100 e according to some embodiments of the present disclosure. The package structure 100 e is similar to Figure 4 The package structure 100d shown in FIG. Figure 4 The processes and materials used to form package structure 100e may be similar to or the same as those used to form package structure 100d, and a detailed description thereof will not be repeated herein.

[0088] Figure 5 and Figure 4 The difference between the thermal interface material (TIM) structure 350 is that the thermal interface material (TIM) structure 350 includes a first portion 350a, a second portion 350b, and a third portion 350c. The first portion 350a, the second portion 350b, and the third portion 350c of the thermal interface material (TIM) structure 350 are separated from each other. The first portion 350a, the second portion 350b, and the third portion 350c of the thermal interface material (TIM) structure 350 are physically disconnected.

[0089] The first portion 350a of the thermal interface material (TIM) structure 350 is separated from the second portion 350b by air, and the second portion 350b is separated from the third portion 350c by air. The air gap between adjacent dies can reduce lateral thermal interactions between dies.

[0090] FIG. 6A to FIG. 6C FIG. 1 shows a cross-sectional representation of a package structure 100f according to some embodiments of the present disclosure. The package structure 100f is similar to Figure 5 The package structure 100e shown in FIG. Figure 5 The processes and materials used to form package structure 100f may be similar to or the same as those used to form package structure 100e, and a detailed description thereof will not be repeated herein.

[0091] According to some embodiments of the present disclosure, Fig. 6A and Figure 5 The difference between the two is that a removable film 125 is formed above the substrate 122 of the semiconductor die 120. The top surface of the removable film 125 can be formed to be higher than the top surface of the first stacked die 130a and the top surface of the second stacked die 130b. The removable film 125 is used as a release film and will be removed in the following process. Afterwards, the encapsulation layer 150 is formed above the bottom filling layer 148 and the removable film 125. Next, by a planarization process, such as a chemical mechanical polishing (CMP) process, a portion of the removable film 125 and a portion of the encapsulation layer 150 are removed to expose the top surface of the top substrate 132. After the planarization process, the top surface of the removable film 125 can be located at the same height as the top surface of the first stacked die 130a and the second stacked die 130b. The carrier substrate 160 is formed above the removable film 125 and the top substrate 132, and the conductive connector 164 is formed below the conductive layer 116 of the interconnect structure 110.

[0092] In some embodiments, the removable film 125 is made of abrasive and low outgassing material. In some embodiments, the removable film 125 is made of a thermoplastic material such as polyethylene (PE), polypropylene (PP), polyethylene terephthalate (PET), or another suitable material.

[0093] Next, if Figure 6BAs shown in , according to some embodiments of the present disclosure, the carrier substrate 160 is removed, and then the removable film 125 is removed. Therefore, the top surface of the semiconductor die 120 is lower than the top surface of the first stacked die 130a and the top surface of the second stacked die 130b. In other words, the top surface of the first stacked die 130a and the top surface of the second stacked die 130b are higher than the top surface of the semiconductor die 120. In some embodiments, the removable film 125 is removed by an etching process. For example, the removable film 125 is removed by a wet etching process such as an acid solution.

[0094] Next, if Figure 6C As shown in , a first portion 350a of the thermal interface material (TIM) structure 350 is formed on the first stacked die 130a, a second portion 350b of the thermal interface material (TIM) structure 350 is formed on the semiconductor die 120, and a third portion 350c of the thermal interface material (TIM) structure 350 is formed on the second stacked die 130b.

[0095] like Figure 6C As shown in , each of the protruding structures 210 directly above the first stacked die 130a has a first height H1 in the vertical direction. Each of the protruding structures 210 directly above the semiconductor die 120 has a second height H2 in the vertical direction. In some embodiments, the second height H2 is greater than the first height H1.

[0096] The first portion 350a of the thermal interface material (TIM) structure 350 has a first thickness D1 along the vertical direction, and the second portion 350b of the thermal interface material (TIM) structure 350 has a second thickness D2 along the vertical direction. In some embodiments, the second thickness D2 is greater than the first thickness D1. In some embodiments, the second thickness D2 is in a range from about 20 micrometers (μm) to about 300 micrometers (μm).

[0097] There is a distance A1 between the top surface of the protruding structure 210 and the bottom surface of the cap structure. In some embodiments, the distance A1 is in a range from about 5 micrometers (μm) to about 30 micrometers (μm). There is a distance B1 between the bottom surface of the additional protruding structure 320 and the top surface of the top substrate 132. In some embodiments, the distance B1 is in a range from about 5 micrometers (μm) to about 30 micrometers (μm).

[0098] 7A to 7H A cross-sectional representation of various stages of forming package structure 100g according to some embodiments of the present disclosure is shown. The processes and materials used to form package structure 100g may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated here.

[0099] like Fig. 7A As shown in , a conductive structure 104 is formed in a substrate 102. The conductive structure 104 extends from a front side 102a of the substrate 102 toward a back side 102b of the substrate 102. In some embodiments, the conductive structure 104 is formed by forming a plurality of trenches (not shown) extending from the front side 102a of the substrate 102. Thereafter, a barrier layer 103 is filled into each of the trenches, and a conductive structure 104 is formed on the barrier layer 103 and in each of the trenches.

[0100] The interconnect structure 110 is formed over the conductive structure 104 and the substrate 102. The interconnect structure 110 may be used as a redistribution (RDL) structure for wiring. The interconnect structure 110 includes a plurality of conductive layers 114 and a conductive layer 116 formed in a plurality of dielectric layers 112. In some embodiments, the conductive layer 116 is exposed at or protrudes from the top surface of the top of the dielectric layer 112 to serve as a bonding pad.

[0101] Conductive layer 114 and conductive layer 116 may be made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, conductive layer 114 and conductive layer 116 are formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0102] Afterwards, if Figure 7B As shown in FIG. 1 , according to some embodiments of the present disclosure, a first semiconductor die 120a and a second semiconductor die 120b are formed over a conductive layer 116. Each of the first semiconductor die 120a and the second semiconductor die 120b includes a substrate 121 and an interconnect structure 123 over the substrate 121. The interconnect structure 123 of the semiconductor die 120 includes a plurality of conductive pads 124.

[0103] In some embodiments, the first semiconductor die 120a and the second semiconductor die 120b are sawn from a wafer and may be "known good dies". The first semiconductor die 120a and the second semiconductor die 120b may be system-on-chip (SoC) chips or memory dies. In some other embodiments, the first semiconductor die 120a and the second semiconductor die 120b are system-on-integrated circuit (SoIC) devices including two or more chips with integrated functions.

[0104] In some embodiments, a plurality of conductive layers 126 are formed under the conductive pads 124 of the first semiconductor die 120 a and the second semiconductor die 120 b , and each of the conductive layers 126 is bonded to each of the conductive layers 116 through a plurality of conductive connectors 128 .

[0105] Conductive layer 126 is made of a metal material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. In some embodiments, conductive layer 126 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD) process.

[0106] The conductive connector 128 is made of a solder material, such as tin (Sn), tin-silver (SnAg), tin-lead (SnPb), tin-copper (SnCu), tin-silver-copper (SnAgCu), tin-silver-zinc (SnAgZn), tin-zinc (SnZn), tin-bismuth-indium (SnBiIn), tin-indium (SnIn), tin-gold (SnAu), tin-zinc-indium (SnZnIn), tin-silver-antimony (SnAgSb), or another suitable material. In some embodiments, the conductive connector 128 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process, or physical vapor deposition (PVD) process.

[0107] Afterwards, if Figure 7C As shown in FIG. 1 , according to some embodiments of the present disclosure, an underfill layer 148 is formed between the first semiconductor die 120 a, the second semiconductor die 120 b, and the interconnect structure 110. The underfill layer 148 surrounds and protects the conductive layer 126 and the conductive connector 128. In some embodiments, the underfill layer 148 is in direct contact with the conductive layer 126 and the conductive connector 128.

[0108] Thereafter, encapsulation layer 150 is formed over underfill layer 148 and substrate 121 of semiconductor die 120 . Encapsulation layer 150 is also formed over substrate 122 .

[0109] The encapsulation layer 150 surrounds and protects the first semiconductor die 120a and the second semiconductor die 120b. In some embodiments, the encapsulation layer 150 is in direct contact with portions of the first semiconductor die 120a and the second semiconductor die 120b.

[0110] Next, if Fig.7D As shown in FIG. 1 , according to some embodiments of the present disclosure, a portion of the encapsulation layer 150 is removed to expose a top surface of the substrate 121. In some embodiments, a portion of the encapsulation layer 150 is removed by a planarization process, such as a chemical mechanical polishing (CMP) process.

[0111] Afterwards, if Fig. 7E As shown in FIG. 1 , according to some embodiments of the present disclosure, a carrier substrate 160 is formed over the substrate 121 and the encapsulation layer 150 and flipped over as shown in FIG. Fig.7DNext, the substrate 102 is thinned from the back side 102b until the conductive structure 104 is exposed. In some embodiments, the conductive structure 104 and the barrier layer 103 become exposed and penetrate the thinned substrate 102. Thus, a via structure 108 is formed in the substrate 102. In some embodiments, the conductive structure 104 is a through substrate via (TSV) structure.

[0112] Afterwards, a plurality of conductive connectors 164 are formed over the through-hole structure 108. In some embodiments, the conductive connectors 164 are called controlled collapse chip connection (C4) bumps. In some other embodiments, the conductive connectors 164 are micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), ball grid array (BGA) bumps, etc.

[0113] Next, if Figure 7F As shown in , according to some embodiments of the present disclosure, flipping Fig. 7E , and the carrier substrate 160 is removed to expose the top surface of the substrate 121. Thus, an interposer 170 is obtained. The interposer 170 includes a through-hole structure 108 in the substrate 102 and an interconnect structure 110 electrically connected to the through-hole structure 108. The first semiconductor die 120a and the second semiconductor die 120b are electrically connected to the conductive connector 164 through the interposer 170.

[0114] Afterwards, if Figure 7G As shown in , according to some embodiments of the present disclosure, a plurality of protrusion structures 210 are formed on the substrate 121 of the first semiconductor die 120a and the second semiconductor die 120b. The protrusion structures 210 are formed on the substrate 121 and are in direct contact with the substrate 121 of the first semiconductor die 120a and the second semiconductor die 120b. The protrusion structures 210 are parallel to each other. The protrusion structures 210 protrude from the top surface of the substrate 121 of the first semiconductor die 120a and the second semiconductor die 120b. In other words, the protrusion structures 210 extend upward from the first semiconductor die 120a and the second semiconductor die 120b.

[0115] Next, if Figure 7H As shown in , according to some embodiments of the present disclosure, a cover structure 310 is provided, and a plurality of additional protrusion structures 320 are formed below the lower surface of the cover structure 310. Next, according to some embodiments of the present disclosure, the protrusion structure 210 and the additional protrusion structure 320 are sealed by a thermally conductive material 325 to form a thermal interface material (TIM) structure 350. The thermal interface material (TIM) structure 350 is configured to dissipate thermal energy or heat from the first semiconductor die 120a and the second semiconductor die 120b to the cover structure 310. Next, the cover structure 310 is attached to the package substrate 360 ​​by an adhesive 364.

[0116] The additional protrusion structure 320 is formed below the cover structure 310 and is in direct contact with the lower surface of the cover structure 310. The additional protrusion structure 320 extends downward from the cover structure 310.

[0117] In some embodiments, the protruding structure 210 and the additional protruding structure 320 are made of different materials. In some other embodiments, the protruding structure 210 and the additional protruding structure 320 are made of the same material.

[0118] Figure 8 FIG. 1 shows a cross-sectional representation of a package structure 100h according to some embodiments of the present disclosure. The package structure 100h is similar to 7A to 7H The package structure shown in 100g or with 7A to 7H The processes and materials used to form package structure 100h may be similar to or the same as those used to form package structure 100g, and a detailed description thereof will not be repeated herein.

[0119] Figure 8 and Figure 7H The difference between the first semiconductor die 120a and the second semiconductor die 120b is that the external cooling unit 370 is formed on the cover structure 310. The external cooling unit 370 is thermally connected to the cover structure 310. The external cooling unit 370 is configured to dissipate heat from the first semiconductor die 120a and the second semiconductor die 120b to the external environment through the thermal interface material (TIM) structure 350 and the cover structure 310.

[0120] Fig. 9 FIG. 1 shows a cross-sectional representation of a package structure 100i according to some embodiments of the present disclosure. The package structure 100i is similar to Figure 8 The package structure shown in 100h or with Figure 8 The processes and materials used to form package structure 100i may be similar to or the same as those used to form package structure 100h, and a detailed description thereof will not be repeated herein.

[0121] Fig. 9 and Figure 8 The difference between the two is that the leg portion 310b of the cover structure 310 is replaced with a ring structure 312. The material of the ring structure 312 is different from that of the cover structure 310. The ring structure 312 is bonded to the cover structure 310 by an adhesive 364.

[0122] Fig.10 FIG. 1 shows a cross-sectional representation of a package structure 100j according to some embodiments of the present disclosure. The package structure 100j is similar to Fig. 9 The package structure 100i shown in FIG. Fig. 9The processes and materials used to form package structure 100j may be similar to or the same as those used to form package structure 100i, and a detailed description thereof will not be repeated herein.

[0123] Fig.10 and Fig. 9 The difference between the stacked die 130 and the semiconductor die 120 is that the stacked die 130 is formed adjacent to the semiconductor die 120. The protrusion structure 210 is also formed on the stacked die 130 and connected to the stacked die 130. More specifically, the protrusion structure 210 is formed on the top surface of the stacked die 130.

[0124] The stacked die 130 is disposed above the interconnect structure 110. Each of the stacked die 130 may include a plurality of semiconductor die. In some embodiments, the semiconductor die is a memory die. The semiconductor die 120 has a function different from each of the memory die. The memory die may include a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) or another memory die. The number of semiconductor dies is not limited to four, and the number can be adjusted according to the actual application.

[0125] Fig.11 FIG. 1 shows a cross-sectional representation of a package structure 100k according to some embodiments of the present disclosure. The package structure 100k is similar to Figure 8 The package structure shown in 100h or with Figure 8 The processes and materials used to form the package structure 100k may be similar to or the same as those used to form the package structure 100h, and a detailed description thereof will not be repeated herein.

[0126] Fig.11 and Figure 8 The difference between the two is that the plurality of optical components 107 are formed in the substrate 102, and the plurality of optical components 117 are formed in the dielectric layer 112 of the interconnect structure 110 of the interposer 170. The optical components 107 and 117 are configured to transmit optical signals.

[0127] Optical components 107 and 117 include optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, slab waveguides, etc.), couplers (e.g., grating couplers, edge couplers, etc.), optical switches (e.g., Mach-Zehnder silicon photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, optoelectronic converters (e.g., PN junctions), electro-optical converters, lasers, combinations of these, etc.

[0128] Optical components 107 and 117 are formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0129] It should be noted that because the distance between the optical component 117 of the interconnect structure 110 and the optical component 107 of the substrate 102 is greatly reduced, the coupling efficiency is greatly improved.

[0130] Fig.12 FIG. 1 shows a cross-sectional representation of a package structure 1001 according to some embodiments of the present disclosure. The package structure 1001 is similar to Fig.10 The package structure 100j shown in FIG. Fig.10 The processes and materials used to form package structure 1001 may be similar to or the same as those used to form package structure 100j, and a detailed description thereof will not be repeated herein.

[0131] Fig.12 and Fig.10 The difference between the two is that a first portion 350 a of the thermal interface material (TIM) structure 350 is formed on the stacked die 130 , and a second portion 350 b of the thermal interface material (TIM) structure 350 is formed on the semiconductor die 120 .

[0132] like Fig.12 As shown in , each of the protruding structures 210 directly above the stacked die 130 has a first height H1 along the vertical direction. Each of the protruding structures 210 directly above the semiconductor die 120 has a second height H2 along the vertical direction. In some embodiments, the second height H2 is greater than the first height H1.

[0133] The first portion 350a of the TIM structure 350 has a first thickness D1 along the vertical direction, and the second portion 350b of the TIM structure 350 has a second thickness D2 along the vertical direction. In some embodiments, the second thickness D2 is greater than the first thickness D1.

[0134] FIG. 13A to FIG. 13C FIG. 1 is a cross-sectional representation of various stages of forming a package structure 100 m according to some embodiments of the present disclosure. The package structure 100 m is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1IThe processes and materials used to form package structure 100m may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0135] According to some embodiments of the present disclosure, Fig.13A and Figure 1G The difference between the two is that a plurality of protrusion structures 210 and a plurality of second protrusion structures 212 are formed on the substrate 122 of the semiconductor die 120. The protrusion structures 210 and the second protrusion structures 212 are formed on the substrate 122 and are in direct contact with the substrate 122 of the semiconductor die 120. The protrusion structures 210 and the second protrusion structures 212 are parallel to each other. The protrusion structures 210 and the second protrusion structures 212 protrude from the top surface of the substrate 122 of the semiconductor die 120. In other words, the protrusion structures 210 and the second protrusion structures 212 extend upward from the top surface of the substrate 122 of the semiconductor die 120. In some embodiments, the height of each of the protrusion structures 210 is greater than the height of each of the second protrusion structures 212. In other words, the top surface of each of the protrusion structures 210 is higher than the top surface of each of the second protrusion structures 212. In some embodiments, the width of each of the protrusion structures 210 is different from the width of each of the second protrusion structures 212.

[0136] In some embodiments, the protrusion structure 210 and the second protrusion structure 212 are made of a thermally conductive material. In some embodiments, the thermally conductive material of the protrusion structure 210 and the second protrusion structure 212 includes aluminum (Al), Al alloy, copper (Cu), Cu alloy, silver (Ag), Ag alloy, gold (Au), Au alloy, a combination thereof, or another suitable material. In some embodiments, the thermally conductive material of the protrusion structure 210 and the second protrusion structure 212 has a thermal conductivity in a range from about 200 W / m·K to about 2000 W / m·K.

[0137] In some embodiments, the protrusion structure 210 and the second protrusion structure 212 are formed by a deposition process, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0138] Next, if Fig. 13B As shown in FIG. 3 , according to some embodiments of the present disclosure, a cover structure 310 without any protruding structure is provided.

[0139] Afterwards, if Fig. 13C As shown in , according to some embodiments, semiconductor die 120 is bonded to package substrate 360 ​​via conductive connectors 164. In some embodiments, package substrate 360 ​​is a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate.

[0140] Next, thermally conductive material 325 is dispersed on semiconductor die 120 and between protruding structure 210 and second protruding structure 212 and then cured by applying heat to form thermal interface material (TIM) structure 350. Lid structure 310 is attached to package substrate 360 ​​by adhesive 364.

[0141] Protruding structure 210 and second protruding structure 212 are sealed by thermally conductive material 325 to form thermal interface material (TIM) structure 350 on semiconductor die 120 . Thermal interface material (TIM) structure 350 is configured to dissipate thermal energy or heat from semiconductor die 120 to cap structure 310 .

[0142] FIG. 14A to FIG. 14C FIG. 1 is a cross-sectional representation of various stages of forming a package structure 100n according to some embodiments of the present disclosure. The package structure 100n is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1I The processes and materials used to form package structure 100n may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0143] According to some embodiments of the present disclosure, Fig.14A and Figure 1G The difference between the two is that no protruding structure is formed on the substrate 122 of the semiconductor die 120 .

[0144] Next, if Fig. 14B As shown in , according to some embodiments of the present disclosure, a cover structure 310 is provided, and a plurality of additional protrusion structures 320 and a plurality of second additional protrusion structures 322 are formed under a lower surface of the cover structure 310 .

[0145] The cover structure 310 has a main portion 310a and a leg portion 310b extending from the main portion 310a. The leg portion 310b is configured to be attached to the package substrate 360 ​​(see Fig. 1I In some embodiments, the cap structure 310 has a high thermal conductivity, for example, between about 200 W / m·K and about 400 W / m·K. In some embodiments, the cap structure 310 is made of copper (Cu), copper alloy, copper tungsten (CuW), or aluminum silicon carbide (AlSiC), or an applicable material.

[0146] The additional protruding structure 320 and the second additional protruding structure 322 are formed below the cover structure 310 and are in direct contact with the bottom surface of the cover structure 310. The additional protruding structure 320 and the second additional protruding structure 322 are parallel to each other. In some embodiments, the height of each of the additional protruding structures 320 is greater than the height of each of the second additional protruding structures 322. In some embodiments, the width of each of the additional protruding structures 320 is different from the width of each of the second additional protruding structures 322.

[0147] In some embodiments, the protruding structure 210, the additional protruding structure 320 and the second additional protruding structure 322 are made of different materials. In some other embodiments, the protruding structure 210, the additional protruding structure 320 and the second additional protruding structure 322 are made of the same material.

[0148] In some embodiments, the additional protruding structure 320 and the second additional protruding structure 322 are made of a thermally conductive material. In some embodiments, the thermally conductive material of the additional protruding structure 320 and the second additional protruding structure 322 includes aluminum (Al), Al alloy, copper (Cu), Cu alloy, silver (Ag), Ag alloy, gold (Au), Au alloy, a combination thereof, or another applicable material. In some embodiments, the thermally conductive material of the additional protruding structure 320 and the second additional protruding structure 322 has a thermal conductivity in the range from about 200 W / m·K to about 2000 W / m·K. In some embodiments, the additional protruding structure 320 and the second additional protruding structure 322 are formed by a deposition process, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. In some other embodiments, the additional protruding structure 320 and the second additional protruding structure 322 are formed by metal precision processing.

[0149] Afterwards, if Fig. 14C As shown in FIG. 1 , according to some embodiments, semiconductor die 120 is bonded to package substrate 360 ​​by conductive connectors 164. Cover structure 310 is attached to package substrate 360 ​​by adhesive 364. Additional protrusion structure 320 and second additional protrusion structure 322 are sealed by thermally conductive material 325 to form thermal interface material (TIM) structure 350 on semiconductor die 120.

[0150] Fig.15 FIG. 1 shows a cross-sectional representation of a package structure 100 o according to some embodiments of the present disclosure. The package structure 100 o is similar to FIG. 1A to FIG. 1I The package structure 100a shown in FIG. 1A to FIG. 1I The processes and materials used to form package structure 100o may be similar to or the same as those used to form package structure 100a, and a detailed description thereof will not be repeated herein.

[0151] Fig.15 and Fig. 1I The difference between the protruding structure 210 and the additional protruding structure 320 is that the protruding structure 210 and the additional protruding structure 320 have the same height. In addition, the protruding structure 210 is in direct contact with the cap structure 310 and the substrate 122 of the semiconductor die 120. In other words, there is no gap between the top surface of the protruding structure 210 and the cap structure 310. There is no gap between the bottom surface of the additional protruding structure 320 and the substrate 122 of the semiconductor die 120.

[0152] FIG. 16A to FIG. 16F Shown are cross-sectional representations of various stages in forming a package structure 100m in accordance with some embodiments of the present disclosure.

[0153] like Fig.16A As shown in , according to some embodiments, by FIG. 16A to FIG. 16B The steps of forming the optical tube core 50 ( Fig. 16B ) and includes forming a substrate 11, an insulating layer 13 and a silicon layer (not shown). In some embodiments, the optical die 50 is an optical interposer. In some embodiments, the optical die 50 is in wafer form.

[0154] An insulating layer 13 is formed over substrate 11, and a silicon layer (not shown) is formed over insulating layer 13. In some embodiments, substrate 11, insulating layer 13, and silicon layer (not shown) together are part of a silicon-on-insulator (SOI) substrate.

[0155] The substrate 11 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 11 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0156] The insulating layer 13 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination of these, or another suitable material. In some embodiments, the insulating layer 13 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic vapor deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0157] Next, according to some embodiments, the silicon layer (not shown) is patterned to form an optical component 20. Each optical component 20 is used to form a photonic integrated circuit (PIC). The optical component 20 includes an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a buried channel waveguide, a diffused waveguide, a slab waveguide, etc.), a coupler (e.g., a grating coupler, an edge coupler, etc.), an optical switch (e.g., a Mach-Zehnder silicon photonic switch, a microelectromechanical switch, a microring resonator, etc.), an amplifier, a multiplexer, a demultiplexer, a photoelectric converter (e.g., a PN junction), an electro-optical converter, a laser, a combination of these, etc. The optical component 20 is formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0158] In some embodiments, optical component 20 includes waveguide 22, coupler 24, modulator 26 and germanium modulator 27. Waveguide 22 is used to guide electromagnetic waves with minimal energy loss by limiting energy transmission to two dimensions. In some embodiments, multiple waveguides are formed and connected as a single continuous structure.

[0159] The coupler 24 may be integrated with the waveguide 22 and may be formed together with the waveguide 22. The coupler 24 is a photonic structure that allows optical signals and / or optical power to be transmitted between the waveguides 22. In some embodiments, the coupler 24 includes a grating coupler that allows optical signals and / or optical power to be transmitted between the waveguides 22.

[0160] The modulator 26 is optically coupled to the waveguide 22 to receive the electrical signal and generates a corresponding optical signal in the waveguide 22 by modulating the optical power in the waveguide 22. The modulator 26 may include a germanium modulator 27 above the modulator 26. In some embodiments, the germanium modulator 27 is formed by partially etching a portion of a silicon layer to form a groove and growing an epitaxial material in the groove on the remaining silicon layer. The silicon layer can be etched using photolithography and etching techniques. The epitaxial material may include a semiconductor material such as doped or undoped germanium (Ge).

[0161] Although Fig.16A 2 , a configuration or arrangement of the optical component 20 including the waveguide 22, the coupler 24, the modulator 26, and the germanium modulator 27 is shown, but the configuration or arrangement of the optical component 20 may be adjusted according to actual applications.

[0162] Thereafter, according to some embodiments, a dielectric layer 30 is formed on the optical component 20. More specifically, the dielectric layer 30 is formed on the waveguide 22, the coupler 24, the modulator 26, and the germanium modulator 27. The dielectric layer 30 is used to separate the individual optical components 20.

[0163] In some embodiments, dielectric layer 30 includes silicon oxide, silicon nitride, silicon oxynitride (SiON), or a combination thereof. In some embodiments, dielectric layer 30 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic vapor deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0164] Next, if Fig. 16B As shown in FIG. 1 , according to some embodiments, an interconnect structure 40 is formed over the dielectric layer 30. The interconnect structure 40 includes a conductive layer 44 and a conductive pad 46 embedded in the dielectric layer 42. The interconnect structure 40 can be used as a redistribution (RDL) structure for wiring. Thus, the optical die 50 is formed with the optical component 20 and the interconnect structure 40 for connecting other dies or chips.

[0165] It should be noted that one or more optical components may be formed in the dielectric layer 42 of the interconnect structure 40. The optical components may include optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, slab waveguides, etc.), couplers (e.g., grating couplers, edge couplers, etc.), optical switches (e.g., Mach-Zehnder silicon photonic switches, micro-electromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical-to-electrical converters (e.g., PN junctions), electro-optical converters, lasers, combinations of these, etc.

[0166] In some embodiments, dielectric layer 42 includes silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof. In some embodiments, dielectric layer 42 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic vapor deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0167] In some embodiments, the conductive layer 44 and the conductive pad 46 are made of a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, a combination thereof, or another suitable material. In some embodiments, the conductive layer 44 and the conductive pad 46 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another suitable deposition process.

[0168] Afterwards, if Fig. 16CAs shown in FIG. 2 , according to some embodiments, an electronic die 200 is bonded to an optical die 50. The electronic die 200 includes a substrate 202. In some embodiments, the electronic die 200 is an electronic integrated circuit (EIC). The electronic die 200 includes a conductive pad 246 embedded in a dielectric layer 242, and the conductive pad 246 is used to bond to the interconnect structure 40.

[0169] Electronic die 200 may include integrated circuits for interfacing with various photonic components formed in dielectric layer 42 of interconnect structure 40 or in dielectric layer 30 of optical die 50. Electronic die 200 is used to communicate with one or more of optical components 20 (e.g., photonic components) in optical die 50 using electrical signals.

[0170] In some embodiments, the electronic die 200 includes a suitable device, such as an xPU, a logic die, a 3DIC die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP), a SoC die, a MEMS die, or a combination thereof. Fig. 16C One electronic die 200 is formed in the interconnect structure 40 , but in various embodiments, two or more electronic dies may be bonded to the interconnect structure 40 .

[0171] Before the electronic die 200 and the optical die 50 are bonded together, a surface treatment is performed to activate the surfaces of the conductive pads 246 and the conductive pads 46. In some embodiments, the surface treatment includes dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, etc., or a combination thereof. After the surface treatment, a cleaning process is performed on the electronic die 200 and the optical die 50. Thereafter, the electronic die 200 and the optical die 50 are aligned so that the conductive pads 246 of the electronic die 200 can be bonded to the conductive pads 46 of the interconnect structure 40 of the optical die 50, and the dielectric layer 242 can be bonded to the dielectric layer 42 of the interconnect structure 40 of the optical die 50. In some embodiments, the alignment of the electronic die 200 and the optical die 50 can be achieved by using an optical sensing method.

[0172] After alignment is performed, the electronic die 200 and the optical die 50 are bonded together by a hybrid bonding process. Hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and dielectric-to-dielectric bonding. The electronic die 200 and the optical die 50 are hybrid bonded together by applying pressure and heat.

[0173] Next, if Fig.16DAs shown in , according to some embodiments, the substrate 11 and the insulating layer 13 are removed to expose the optical component 20. Next, a dielectric layer 48 is formed on the exposed surface of the optical component 20, and a through hole (not shown) is formed through the dielectric layer 30 and the dielectric layer 48. The composite die 400 includes the electronic die 200 and the optical die 50. The electronic die 200 is bonded to the optical die 50 by hybrid bonding.

[0174] The composite die 400 further includes a conductive pad 408 embedded in the bonding layer 406. Since the optical die 50 is formed below the electronic die 200, the passage of electrical and optical signals is reduced and the transmission speed of the electrical and optical signals is improved.

[0175] It should be noted that optical components 424 are formed in dielectric layer 48 of optical die 50 of composite die 400. Optical components 424 include optical waveguides, couplers, optical switches, amplifiers, multiplexers, optical-to-electrical converters (e.g., PN junctions), electrical-to-optical converters, combinations of these, and the like.

[0176] The optical component 424 is formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0177] Next, the interposer 430 is formed, and the interposer 430 includes a through hole (TV) 436 formed in the substrate 432. The interposer 430 also includes a front-side interconnect structure and a back-side interconnect structure. The front-side interconnect structure includes a conductive layer 446 embedded in the dielectric layer 442. A conductive pad 448 is embedded in the bonding layer 443. The back-side interconnect structure includes a conductive layer 454 embedded in the dielectric layer 452, a UBM layer 456 formed under the conductive layer 454, and a conductive connector 458 formed under the UBM layer 456.

[0178] The UBM layer 456 may include an adhesion layer and / or a wetting layer. In some embodiments, the UBM layer 456 is made of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), etc. In some embodiments, the UBM layer 456 also includes a copper seed layer. In some embodiments, the UBM layer 456 is formed by electroplating, chemical plating, printing, chemical vapor deposition (CVD) process, physical vapor process, or another suitable process.

[0179] After forming the interposer 430, the composite die 400 is bonded to the interposer 430. The conductive pads 408 of the composite die 400 are aligned with and bonded to the conductive pads 448 of the interposer 430 to form a metal-to-metal bond, and the bonding layer 406 of the composite die 400 is aligned with and bonded to the bonding layer 443 of the interposer 430 to form a dielectric-to-dielectric bond. Thus, a hybrid bonding structure having a metal-to-metal bond and a dielectric-to-dielectric bond is formed between the composite die 400 and the interposer 430.

[0180] Next, a stacked die 500 is provided. The stacked die 500 may be a memory die, such as a static random access memory (SRAM) device, a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) device, or another memory device.

[0181] The stacked die 500 includes a substrate 502 and a conductive pad 508 embedded in a bonding layer 506. The substrate 502 may include a memory die in the form of a die stack. The conductive pad 508 of the stacked die 500 is aligned with the conductive pad 448 of the interposer 430, and the bonding layer 506 of the stacked die 500 is aligned with the bonding layer 443 to form a hybrid bonding structure between the stacked die 500 and the interposer 430.

[0182] After the composite die 400 and the stacked die 500 are bonded to the interposer 430 , an encapsulation layer 590 is formed to surround the composite die 400 and the stacked die 500 .

[0183] Afterwards, if Fig.16E As shown in FIG. 1 , according to some embodiments of the present disclosure, a plurality of protrusion structures 210 are formed on the substrate 502 of the stacked die 500 and the substrate 202 of the electronic die 200 . The protrusion structures 210 are formed on the substrate 202 and are in direct contact with the substrate 202 of the electronic die 200 .

[0184] Next, if Fig.16F As shown in , according to some embodiments of the present disclosure, a cover structure 310 is provided, and a plurality of additional protrusion structures 320 are formed below the lower surface of the cover structure 310. Next, according to some embodiments of the present disclosure, the protrusion structure 210 and the additional protrusion structure 320 are sealed by a thermally conductive material 325 to form a thermal interface material (TIM) structure 350.

[0185] It should be noted that the heat generated by the composite die 400 and the stacked die 500 may be transferred to the external environment through the protruding structure 210 and the additional protruding structure 320 in the thermal interface material (TIM) structure 350 .

[0186] Fig.17 FIG. 1 shows a cross-sectional representation of a package structure 100n according to some embodiments. The package structure 100n may be similar to Fig.16F 100m, wherein the same reference numerals indicate the same elements formed using the same process unless otherwise specified. The processes and materials used to form the package structure 100n may be similar to or the same as those used to form the package structure 100m, and are not repeated here.

[0187] Fig.17 and Fig.16F The difference between the two is that a local silicon interconnect (LSI) die 438 is formed in the substrate 432. The LSI die 438 may be sealed in an encapsulant. A plurality of through holes (not shown) may be formed to penetrate the encapsulant.

[0188] Fig.18 FIG. 1 shows a cross-sectional representation of a package structure 100 o according to some embodiments of the present disclosure. The package structure 100 o is similar to Fig.16F The package structure shown in 100m or with Fig.16F The processes and materials used to form the package structure 100o may be similar to or the same as those used to form the package structure 100m, and a detailed description thereof will not be repeated herein.

[0189] Fig.18 and Fig.16F The difference between the two is that the first portion 350a of the thermal interface material (TIM) structure 350 is formed on the stacked die 500, and the second portion 350b of the thermal interface material (TIM) structure 350 is formed on the composite die 400. The first portion 350a of the thermal interface material (TIM) structure 350 is separated from the second portion 350b of the thermal interface material (TIM) structure 350 by air.

[0190] like Fig.18 As shown in , each of the protruding structures 210 directly above the stacked die 500 has a first height H1 along the vertical direction. Each of the protruding structures 210 directly above the composite die 400 has a second height H2 along the vertical direction. In some embodiments, the second height H2 is greater than the first height H1.

[0191] The first portion 350a of the TIM structure 350 has a first thickness D1 along the vertical direction, and the second portion 350b of the TIM structure 350 has a second thickness D2 along the vertical direction. In some embodiments, the second thickness D2 is greater than the first thickness D1.

[0192] FIG. 19A to FIG. 19F A top view of the protruding structure 210 and the additional protruding structure 320 of a thermal interface material (TIM) structure 350 is shown according to some embodiments of the present disclosure.

[0193] like Fig.19A As shown in , the protrusion structures 210 and the additional protrusion structures 320 are alternately arranged. Each of the protrusion structures 210 has a first width W1 along a first direction (e.g., X-axis) and a first length L1 along a second direction (e.g., Y-axis). Each of the additional protrusion structures 320 has a second width W2 along the first direction (e.g., X-axis) and a second length L2 along the second direction (e.g., Y-axis). In some embodiments, the first width W1 of the protrusion structure 210 is substantially equal to the second width W2 of the additional protrusion structure 320. In some embodiments, the first length L1 of the protrusion structure 210 is substantially equal to the second length L2 of the additional protrusion structure 320.

[0194] like Fig.19B As shown in FIG. 2 , the first width W1 of the protrusion structure 210 is substantially equal to the second width W2 of the additional protrusion structure 320 . In some embodiments, the first length L1 of the protrusion structure 210 is greater than the second length L2 of the additional protrusion structure 320 .

[0195] There is a distance C1 between the left side wall surface of the protruding structure 210 and the left side wall surface of the adjacent protruding structure 210. In some embodiments, the distance C1 is in a range from about 5 micrometers (μm) to about 50 micrometers (μm).

[0196] There is a distance D1 between the right side wall surface of the additional protruding structure 320 and the left side wall surface of the protruding structure 210. In some embodiments, the distance D1 is in a range from about 5 micrometers (μm) to about 400 micrometers (μm).

[0197] There is a distance E1 between the left sidewall surface of the additional protruding structure 320 and the left sidewall surface of the adjacent additional protruding structure 320. In some embodiments, the distance E1 is in a range from about 5 micrometers (μm) to about 400 micrometers (μm).

[0198] like Fig.19C As shown in FIG. 2 , the protrusion structures 210 and the additional protrusion structures 320 are alternately arranged in a first direction (eg, X-axis) and in a second direction (eg, Y-axis).

[0199] like Fig.19D As shown in , the size of the additional protruding structure 320 is larger than the size of the protruding structure 210. In some embodiments, the first width W1 of the protruding structure 210 is smaller than the second width W2 of the additional protruding structure 320.

[0200] like Fig.19EAs shown in , when the hot spot is located at the central portion of the die, the protruding structures 210 and the additional protruding structures 320 are alternately arranged and are mainly distributed at the central portion of the thermal interface material (TIM) structure 350 .

[0201] like Fig.19F As shown in , when the hot spot is located at the peripheral portion of the die, the protrusion structures 210 and the additional protrusion structures 320 are alternately arranged and are mainly distributed at the peripheral portion of the thermal interface material (TIM) structure 350 .

[0202] In some embodiments, protrusion structures 210 are formed on semiconductor die 120 and stacked die 130 to help heat dissipation efficiency. Additional protrusion structures 320 are formed below cover structure 310 to help heat dissipation efficiency. Heat generated by semiconductor die 120 and stacked die 130 can be transferred horizontally and vertically to the external environment through the stacked alternating protrusion structures. In some embodiments, semiconductor die 120 is a logic die and stacked die 130 is a memory die.

[0203] In some embodiments, the protrusion structure 210 is formed on the composite die 400 having the electronic die 200 and the optical die 50. Since the optical die 50 is formed below the electronic die 200, the passage of electrical and optical signals is reduced and the transmission speed of the electrical and optical signals is improved.

[0204] Embodiments for forming a package structure and a method for forming the same are provided. The package structure includes a tube core formed above a substrate. A protrusion structure is formed on the tube core and is thermally connected to the tube core. A cover structure having a protrusion structure is provided, and the protrusion structure is thermally connected to the cover structure. The cover structure is arranged above the tube core, and a thermal interface material (TIM) structure is composed of a protrusion structure formed on the tube core and a protrusion structure formed below the cover structure. The heat or thermal energy generated by the tube core can be transmitted to the external environment through the protrusion structure in the TIM. The stacked alternating protrusion structure in the TIM is configured to improve the heat dissipation efficiency. Therefore, the power efficiency and performance of the package structure are improved.

[0205] In some embodiments, a package structure is provided. The package structure includes a first tube core located above a substrate and a cover structure located above the first tube core. The package structure also includes a thermal interface material structure located between the first tube core and the cover structure. The thermal interface material structure includes a plurality of protrusion structures connected to the first tube core, a plurality of additional protrusion structures connected to the cover structure, and a thermally conductive material located between the protrusion structures and the additional protrusion structures.

[0206] In some embodiments, a packaging structure is provided. The packaging structure includes a first tube core and a second tube core located above a substrate, and the top surface of the first tube core is higher than the top surface of the second tube core. The packaging structure includes a plurality of first protrusion structures extending upward from the first tube core and a plurality of second protrusion structures extending upward from the second tube core. The packaging structure includes a cover structure located on the first tube core and the second tube core. The packaging structure also includes a plurality of additional protrusion structures extending downward from the cover structure, and the first protrusion structure, the second protrusion structure, and the additional protrusion structure are sealed by a thermally conductive material to form a thermal interface material structure.

[0207] In some embodiments, a method for forming a package structure is provided. The method includes: forming a first tube core on a substrate; and forming a plurality of protrusion structures on the first tube core. The method includes: providing a cover structure above the first tube core; and forming a plurality of additional protrusion structures below the cover structure, wherein the plurality of protrusion structures are parallel to the plurality of additional protrusion structures. The method includes: forming a thermal interface material structure between the first tube core and the cover structure, and the plurality of protrusion structures and the plurality of additional protrusion structures are sealed by a thermally conductive material to form the thermal interface material structure.

[0208] Some embodiments of the present application provide a packaging structure, including: a first tube core, located above a substrate; a cover structure, located above the first tube core; and a thermal interface material structure, located between the first tube core and the cover structure, wherein the thermal interface material structure includes: a plurality of protrusion structures connected to the first tube core; a plurality of additional protrusion structures connected to the cover structure; and a thermally conductive material, located between the protrusion structures and the additional protrusion structures.

[0209] In some embodiments, the protrusion structure and the additional protrusion structure are alternately stacked. In some embodiments, the package structure further includes: an external cooling unit formed on the cover structure, wherein the first die is thermally connected to the external cooling unit through the thermal interface material structure. In some embodiments, the package structure further includes: a second die adjacent to the first die, wherein the protrusion structure is connected to the second die. In some embodiments, the package structure further includes: a second die adjacent to the first die; and a second protrusion structure connected to the second die, wherein the thermal interface material structure further includes the second protrusion structure. In some embodiments, each of the protrusion structures has a first height, each of the second protrusion structures has a second height, and the second height is greater than the first height. In some embodiments, the thermal interface material structure has a first portion located between the protrusion structure and the additional protrusion structure and a second portion located between the second protrusion structure and the additional protrusion structure, wherein the first portion has a first thickness, the second portion has a second thickness, and the second thickness is greater than the first thickness. In some embodiments, the first die includes a plurality of memory dies and an additional substrate located above the memory dies, and the protrusion structure is formed on the additional substrate of the first die. In some embodiments, the first die includes an electronic die and an optical die, and the optical die includes an optical component.

[0210] Other embodiments of the present application provide a packaging structure, including: a first tube core and a second tube core, located above a substrate, wherein the top surface of the first tube core is higher than the top surface of the second tube core; a plurality of first protrusion structures extending upward from the first tube core; a plurality of second protrusion structures extending upward from the second tube core; a cover structure located on the first tube core and the second tube core; and a plurality of additional protrusion structures extending downward from the cover structure, wherein the first protrusion structures, the second protrusion structures and the additional protrusion structures are sealed by a thermally conductive material to form a thermal interface material structure.

[0211] In some embodiments, each of the first protruding structures has a first height, each of the second protruding structures has a second height, and the second height is greater than the first height. In some embodiments, the thermal interface material structure has a first portion and a second portion, and the first portion is separated from the second portion by air. In some embodiments, the first die includes a plurality of memory die, and the second die includes an electronic die and an optical die. In some embodiments, the packaging structure further includes: an interposer located between the first die and the substrate, wherein the interposer includes an optical component. In some embodiments, the packaging structure further includes: an interposer located between the first die and the substrate, wherein the interposer includes a plurality of local silicon interconnect (LSI) dies.

[0212] Some other embodiments of the present application provide a method for forming a packaging structure, comprising: forming a first tube core on a substrate; forming a plurality of protrusion structures on the first tube core; setting a cover structure above the first tube core; forming a plurality of additional protrusion structures below the cover structure, wherein the plurality of protrusion structures are parallel to the plurality of additional protrusion structures; and forming a thermal interface material structure between the first tube core and the cover structure, wherein the plurality of protrusion structures and the plurality of additional protrusion structures are sealed by a thermally conductive material to form the thermal interface material structure.

[0213] In some embodiments, the method further includes: forming an interposer between the first die and the substrate, wherein the interposer includes a plurality of optical components. In some embodiments, the first die includes an electronic die and an optical die and a hybrid bonding structure located between the electronic die and the optical die. In some embodiments, the thermal interface material structure has a first portion and a second portion, and the first portion is separated from the second portion by air. In some embodiments, the method further includes: forming an external cooling unit on the cover structure, wherein the first die is thermally connected to the external cooling unit through the thermal interface material structure.

[0214] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A packaging structure, comprising: A first die is located above the substrate; a cover structure, located above the first tube core; as well as A thermal interface material structure is located between the first tube core and the cover structure, wherein the thermal interface material structure includes: a plurality of protruding structures connected to the first die; a plurality of additional protruding structures connected to the cover structure; and A thermally conductive material is located between the protruding structure and the additional protruding structure.

2. The packaging structure according to claim 1, wherein: The protruding structures and the additional protruding structures are stacked alternately.

3. The packaging structure according to claim 1, further comprising: An external cooling unit is formed on the cover structure, wherein the first die is thermally connected to the external cooling unit through the thermal interface material structure.

4. The packaging structure according to claim 1, further comprising: A second tube die is adjacent to the first tube die, wherein the protruding structure is connected to the second tube die.

5. The packaging structure according to claim 1, further comprising: a second tube die, adjacent to the first tube die; as well as A second protruding structure is connected to the second tube die, wherein the thermal interface material structure also includes the second protruding structure.

6. The packaging structure according to claim 5, wherein: Each of the protruding structures has a first height, each of the second protruding structures has a second height, and the second height is greater than the first height.

7. The packaging structure according to claim 5, wherein: The thermal interface material structure has a first portion located between the protruding structure and the additional protruding structure and a second portion located between the second protruding structure and the additional protruding structure, wherein the first portion has a first thickness, the second portion has a second thickness, and the second thickness is greater than the first thickness.

8. The packaging structure according to claim 1, wherein: The first die includes a plurality of memory dies and an additional substrate over the memory dies, and the protruding structure is formed on the additional substrate of the first die.

9. A packaging structure, comprising: A first tube die and a second tube die are located above the substrate, wherein a top surface of the first tube die is higher than a top surface of the second tube die; a plurality of first protruding structures extending upward from the first tube core; a plurality of second protruding structures extending upward from the second die; a cover structure located on the first tube core and the second tube core; and A plurality of additional protrusion structures extend downwardly from the cover structure, wherein the first protrusion structure, the second protrusion structure and the additional protrusion structures are sealed by a thermally conductive material to form a thermal interface material structure.

10. A method for forming a package structure, comprising: forming a first die on a substrate; forming a plurality of protruding structures on the first die; disposing a cover structure above the first tube core; forming a plurality of additional protruding structures below the cover structure, wherein the plurality of protruding structures are parallel to the plurality of additional protruding structures; and A thermal interface material structure is formed between the first die and the lid structure, wherein the plurality of protrusion structures and the plurality of additional protrusion structures are sealed by a thermally conductive material to form the thermal interface material structure.

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