Low-resistance gate metal oxide semiconductor transistor and manufacturing method thereof
By filling the low-resistivity metal block between the polysilicon gate and the gate contact plug of the MOS transistor, the problem of high gate resistance of traditional MOS transistors is solved, and the effect of higher operating frequency and reducing high-frequency noise is achieved.
Patent Information
- Application Number
- CN202411965019.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-11
AI Technical Summary
Traditional MOS transistors have high gate resistance, which is difficult to meet the needs of modern high-frequency applications.
The polysilicon gate and the gate contact plug are filled with low resistivity metal blocks to reduce the lateral resistance of the gate.
Reduces voltage drop on the gate of the MOS transistor, achieves higher operating frequency and reduces high-frequency noise.
Smart Images
Figure CN119812148A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a low-resistance gate metal oxide semiconductor transistor and a manufacturing method thereof. Background Art
[0002] A metal oxide semiconductor (MOS) transistor includes a source and a drain, and a gate that controls the electrical connectivity of the source and drain regions through the body region below. The gate length of a MOS transistor is one of the key parameters that determine the performance of the transistor. Generally, MOS transistors with a smaller gate length have better performance in terms of cutoff frequency, transconductance, and integration size. The gate of a conventional MOS transistor has a three-layer structure, including a silicide layer, a doped polysilicon layer, and a gate oxide layer that insulates the gate from the lower body region.
[0003] In the traditional manufacturing process of MOS transistors, the semiconductor substrate is divided into various active areas by isolation bands, and the polysilicon gate forms the gate of the MOS device on the insulating gate dielectric layer on the semiconductor substrate. Impurities are injected into the semiconductor substrate from the top to produce a lightly doped extension area. Spacers are formed on the sidewalls of the polysilicon gate, and the spacers are used as masks to form source / drain regions by injecting them into the semiconductor substrate from the top. The back-end interconnection process deposits a planarized interlayer dielectric ILD layer on the above structure, then etches contact holes in the interlayer dielectric ILD layer, and then fills them with conductive materials to form contact plugs. Finally, an interconnection metal is formed on the top of the contact plugs to connect the gate electrodes.
[0004] As the gate length of MOS transistors decreases, the gate resistance of MOS transistors manufactured using conventional processes is usually higher. However, modern high-frequency applications and circuits generally require devices with lower gate resistance. Summary of the invention
[0005] The present invention aims to overcome the deficiencies in the prior art and provide a low-resistance gate metal oxide semiconductor transistor and a method for manufacturing the same. By filling a low-resistivity metal block between a polysilicon gate and a gate contact plug, the lateral resistance of the gate is reduced, thereby reducing the voltage drop on the gate, so that the MOS transistor can achieve a higher operating frequency.
[0006] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a low resistance gate metal oxide semiconductor transistor, comprising: A semiconductor substrate having integrated polysilicon gate and source / drain regions; A silicon nitride etching stop layer and an interlayer dielectric layer are sequentially arranged on the top of the semiconductor substrate from bottom to top; A metal block is arranged on the top of the polysilicon gate, the top of the metal block extends into the interlayer dielectric layer directly opposite to the top of the polysilicon gate, a gate contact hole is opened on the interlayer dielectric layer directly opposite to the top of the polysilicon gate, the bottom of the gate contact hole extends to the top of the metal block, and the gate contact hole is filled with a gate contact plug; A source / drain contact hole is opened on the silicon nitride etching stop layer and the interlayer dielectric layer facing the top of the source / drain region, the bottom of the source / drain contact hole extends to the top of the source / drain region, and the source / drain contact hole is filled with a source / drain contact plug; Interconnection metals are respectively arranged on the top of the interlayer dielectric layer facing the top of the polysilicon gate and the top of the interlayer dielectric layer facing the top of the source / drain region, and the top of the gate contact plug and the top of the source / drain contact plug are respectively connected to the corresponding bottom of the interconnection metals.
[0007] Optionally, the semiconductor substrate integrated with a polysilicon gate and source / drain regions comprises: An isolation zone and an active area are formed inside the semiconductor substrate, wherein the isolation zone defines the active area of the semiconductor substrate; An insulating gate dielectric layer is disposed above the active area, and the polysilicon gate is formed on the insulating gate dielectric layer; The source / drain regions are formed on the inner surface of the active region, and the source region and the drain region are distributed on opposite sides of the polysilicon gate.
[0008] Optionally, the metal block passes through a silicon nitride etching stop layer directly opposite to the top of the polysilicon gate; The source / drain contact plug passes through the insulating gate dielectric layer and the silicon nitride etching stop layer directly facing the top of the source / drain region.
[0009] In a second aspect, the present invention provides a method for manufacturing a low-resistance gate metal oxide semiconductor transistor, comprising: Generating a silicon nitride etch stop layer on top of a semiconductor substrate integrated with a polysilicon gate and source / drain regions; depositing a pre-metal dielectric layer on top of the silicon nitride etch stop layer; planarizing the pre-metal dielectric layer on top of the silicon nitride etch stop layer, and depositing an interlayer dielectric layer on top of the planarized pre-metal dielectric layer; Opening a gap in the interlayer dielectric layer and the silicon nitride etching stop layer on the top of the polysilicon gate to the top surface of the polysilicon gate, and depositing a metal layer on the top of the interlayer dielectric layer to fill the gap space, forming a metal block contacting the polysilicon gate inside the interlayer dielectric layer, wherein the deposited metal layer uses a low resistivity metal; Planarization removes the metal layer on top of the interlayer dielectric layer; The back-end interconnection processing is performed to make the polysilicon gate and the source / drain regions respectively conductive to the outer surface of the semiconductor transistor.
[0010] Optionally, the method of integrating a polysilicon gate and a source / drain region on a semiconductor substrate includes: forming an insulating gate dielectric layer on top of the active region on the semiconductor substrate; forming a polysilicon gate on the insulating gate dielectric layer; Using the polysilicon gate as a mask, impurities are injected into the active area to form a lightly doped extension area; forming spacers on sidewalls of the polysilicon gate; Using the spacer as a mask, dopants are implanted into the lightly doped extension region to form source / drain regions.
[0011] Optionally, planarizing the pre-metal dielectric layer on top of the silicon nitride etch stop layer includes: taking the top contact point of the silicon nitride etch stop layer as an endpoint, and planarizing the pre-metal dielectric layer above the endpoint by a chemical mechanical planarization process.
[0012] Optionally, the interlayer dielectric layer and silicon nitride etch stop layer on top of the polysilicon gate open a gap to the top surface of the polysilicon gate, including: using a mask to align the polysilicon gate, etching the interlayer dielectric layer and silicon nitride layer on top of the polysilicon gate, and stopping etching until the top surface of the polysilicon gate.
[0013] Optionally, the back-end interconnection processing is performed to make the polysilicon gate and the source / drain regions respectively conductive to the outer surface of the semiconductor transistor, including: Continue to deposit and planarize the interlayer dielectric layer on the interlayer dielectric layer after the top metal layer is removed; Etching the interlayer dielectric layer on the top of the polysilicon gate until the etching stops on the top surface of the metal block to form a gate contact hole, and etching the interlayer dielectric layer and the pre-metal dielectric layer on the top of the source / drain region until the etching stops on the top surface of the silicon layer in the source / drain region to form a source / drain contact hole; Filling the gate contact hole and the source / drain contact hole with conductive materials to form a gate contact plug and a source / drain contact plug respectively; Interconnect metal is formed on top of the gate contact plug and the source / drain contact plugs.
[0014] Compared with the prior art, the present invention has the following beneficial effects: by filling a low-resistivity metal block between the polysilicon gate and the gate contact plug, the lateral resistance of the gate electrode can be reduced, thereby reducing the voltage drop on the gate of the MOS transistor, achieving a higher operating frequency, and helping to reduce high-frequency noise; when planarizing the pre-metal dielectric layer, the endpoint method is used to make the planarization process accurately stop on the silicon nitride layer, resulting in extremely small silicon nitride loss, providing precise thickness control for the low-resistivity metal block that subsequently contacts the polysilicon gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 FIG. 1 is a schematic diagram of a semiconductor substrate structure after a silicon nitride etching stop layer is deposited in one embodiment of the present invention;
[0016] Figure 2 FIG. 1 is a schematic diagram of a semiconductor substrate structure after a pre-metal dielectric layer is deposited in one embodiment of the present invention;
[0017] Figure 3 FIG. 1 is a schematic diagram of a semiconductor substrate structure after planarizing a pre-metal dielectric layer and depositing an interlayer dielectric layer in an embodiment of the present invention;
[0018] Figure 4 FIG. 1 is a schematic diagram of a semiconductor substrate structure after a low-resistivity metal layer is deposited in one embodiment of the present invention;
[0019] Figure 5 FIG. 1 is a schematic diagram of a semiconductor substrate structure after removing a low-resistivity metal layer in an embodiment of the present invention;
[0020] Figure 6 FIG. 1 is a schematic diagram of the structure of a low-resistance gate metal oxide semiconductor transistor in an embodiment of the present invention;
[0021] Figure 7 FIG. 1 is a flow chart of a method for manufacturing a low resistance gate metal oxide semiconductor transistor according to an embodiment of the present invention.
[0022] In the figure: 100, semiconductor substrate; 105, isolation zone; 110, polysilicon gate; 115, insulating gate dielectric layer; 120, spacer; 125, silicon nitride etch stop layer; 130, pre-metal dielectric layer; 135, interlayer dielectric layer; 140, metal layer; 145, metal block; 150, gate contact hole; 155, gate contact plug; 160, gate interconnection metal; 165, source / drain contact hole; 170, source / drain contact plug; 175, source / drain interconnection metal. DETAILED DESCRIPTION
[0023] The low resistance gate metal oxide semiconductor transistor and its manufacturing method are further described below in conjunction with the accompanying drawings. However, it should be understood that the embodiments provided below are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.
[0024] Example 1
[0025] like Figure 6As shown, this embodiment provides a low resistance gate metal oxide semiconductor transistor, including: a semiconductor substrate 100 and an isolation zone 105, the isolation zone 105 can be a PN junction, a shallow trench isolation STI or a local oxidation of silicon LOCOS. The isolation zone 105 defines an active area of the semiconductor substrate 100, an insulating gate dielectric layer 115 is arranged above the active area, and a polysilicon gate 110 is formed on the insulating gate dielectric layer 115. A source region and a drain region are arranged on the surface of the active region, and the source region and the drain region are distributed on opposite sides of the polysilicon gate 110.
[0026] The insulating gate dielectric layer 115 not covered by the polysilicon gate 110 has a planar silicon nitride etch stop layer 125 , a pre-metal dielectric layer 130 , and an interlayer dielectric layer 135 on top. The polysilicon gate 110 has an interlayer dielectric layer 135 on top.
[0027] The polysilicon gate 110 is electrically connected to the gate contact plug 155, and the gate contact plug 155 passes through the interlayer dielectric layer 135 directly opposite the top of the polysilicon gate 110. A low-resistivity metal block 145 is electrically connected between the polysilicon gate 110 and the gate contact plug 155, and the top of the gate contact plug 155 is electrically connected to the bottom of the gate interconnection metal 160.
[0028] The source / drain regions are electrically connected to the source / drain contact plugs 170, respectively. The source / drain contact plugs 170 pass through the insulating gate dielectric layer 115, the silicon nitride etching stop layer 125 and the interlayer dielectric layer 135 directly opposite the top of the source / drain region. The tops of the source / drain contact plugs 170 are electrically connected to the bottoms of the corresponding source / drain interconnection metals 175, respectively.
[0029] Example 2
[0030] like Figure 7 As shown, this embodiment provides a method for manufacturing a low-resistance gate metal oxide semiconductor transistor, which is specifically divided into the following steps.
[0031] Step 1: deposit a silicon nitride layer on the top of the semiconductor substrate 100 integrated with the polysilicon gate 110 and the source / drain regions to provide an etching stop.
[0032] like Figure 1As shown, the semiconductor substrate 100 is divided into independent active areas by isolation bands 105. The isolation bands 105 can be PN junctions, shallow trench isolations or local oxidation of silicon. Silicide is applied to the polysilicon gate electrode 110 and the source / drain regions to reduce resistance and provide a good contact interface for subsequent processes. The polysilicon gate 110 can be prepared with a smaller thickness. The insulating gate dielectric layer 115 is usually thermally grown silicon dioxide. Impurities are implanted into the semiconductor substrate 100 from the top to produce a lightly doped extension region. Then a spacer 120 is formed on the sidewall of the polysilicon gate 110. The source / drain region is formed by implanting into the semiconductor substrate 100 from the top using the spacer 120 as a mask. Then a silicon nitride etch stop layer 125 is deposited on the above semiconductor structure to serve as an etch stop.
[0033] Step 2: Figure 2 As shown, a pre-metal dielectric layer 130 is deposited on top of the silicon nitride etch stop layer 125 using a chemical vapor deposition (CVD) process.
[0034] Step 3: planarize the pre-metal dielectric layer 130 above the tangent line of the top of the silicon nitride etch stop layer 125 , and deposit an interlayer dielectric layer 135 on top of the planarized pre-metal dielectric layer 130 .
[0035] like Figure 3 As shown, the pre-metal dielectric layer 130 is planarized by a chemical mechanical planarization (CMP) process. The manufacturing process uses an endpoint method to accurately stop on the silicon nitride etch stop layer 125. Due to the precise control of the CMP process on the silicon nitride etch stop layer 125, the silicon nitride loss caused is minimal. An interlayer dielectric layer 135 is deposited on top of the entire structure. These two steps provide precise thickness control for the subsequent metal contact of the polysilicon gate 110.
[0036] Step 4: Open a gap in the interlayer dielectric layer 135 and the silicon nitride etch stop layer 125 on top of the polysilicon gate 110, deposit a metal layer 140 on top of the interlayer dielectric layer 135 to fill the gap space, and form a metal block 145 inside the interlayer dielectric layer 135 that contacts the polysilicon gate 110.
[0037] like Figure 4 As shown, a photomask is aligned with the polysilicon gate 110, and then an isotropic etching process is used to open the space on top of the polysilicon gate 110. The etching will pass through the interlayer dielectric layer 135 and the silicon nitride etch stop layer 125, and this step exposes the top surface of the polysilicon gate 110. A metal layer 140 is deposited on the device to completely fill the gap and contact the polysilicon gate 110, and a metal block 145 electrically connected to the polysilicon gate 110 is formed inside the interlayer dielectric layer 135. The deposited metal layer is selected from low-resistivity metals, such as copper or aluminum.
[0038] Step 5: Figure 5 As shown, the deposited metal layer 140 on the interlayer dielectric layer 135 is removed by chemical mechanical planarization, and the metal block 145 on the top of the polysilicon gate 310 remains.
[0039] Step 6: Perform back-end interconnection processing to make the polysilicon gate 110 and the source / drain regions conductive to the outer surface of the semiconductor transistor.
[0040] Reference picture Figure 6 As shown, the back-end interconnection process is continued. First, the interlayer dielectric layer 135 is deposited and planarized on the structure produced by the above steps. Then the interlayer dielectric layer 135 on the top of the polysilicon gate is etched to stop at the metal block 145, a gate contact hole 150 is formed, and the gate contact hole 150 is filled with a conductive material to form a gate contact plug 155. A gate interconnection metal 160 is formed on the top of the gate contact plug 155 to be electrically connected to the metal block 145 on the top of the silicon wafer gate electrode 110. Then the insulating gate dielectric layer 115, the silicon nitride etch stop layer 125, the pre-metal dielectric layer 130 and the interlayer dielectric layer 135 on the top of the source region and the drain region are etched to form a source / drain contact hole 165, and the source / drain contact hole 165 is filled with a conductive material to form a source / drain contact plug 170. A source / drain interconnection metal 175 is formed on the top of the source / drain contact plug 170 to be electrically connected to the source / drain region.
[0041] The low-resistivity metal block 145 on top of the polysilicon gate 110 reduces the lateral resistance of the gate electrode. This can reduce the voltage drop on the gate of the MOS transistor and achieve a higher operating frequency. The low-resistance gate also helps to reduce high-frequency noise. In some embodiments, due to the low resistance of the gate electrode, the gate contact plug 155 can be sparsely applied to the low-resistivity metal block 145 to reduce parasitic effects. In another embodiment, the gate contact plug 155 can even be applied only to the end of the low-resistivity metal block 145.
[0042] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.
Claims
1. A low resistance gate metal oxide semiconductor transistor, characterized in that: include: A semiconductor substrate having integrated polysilicon gate and source / drain regions; A silicon nitride etching stop layer and an interlayer dielectric layer are sequentially arranged on the top of the semiconductor substrate from bottom to top; A metal block is arranged on the top of the polysilicon gate, the top of the metal block extends into the interlayer dielectric layer directly opposite to the top of the polysilicon gate, a gate contact hole is opened on the interlayer dielectric layer directly opposite to the top of the polysilicon gate, the bottom of the gate contact hole extends to the top of the metal block, and the gate contact hole is filled with a gate contact plug; A source / drain contact hole is opened on the silicon nitride etching stop layer and the interlayer dielectric layer facing the top of the source / drain region, the bottom of the source / drain contact hole extends to the top of the source / drain region, and the source / drain contact hole is filled with a source / drain contact plug; Interconnection metals are respectively arranged on the top of the interlayer dielectric layer facing the top of the polysilicon gate and the top of the interlayer dielectric layer facing the top of the source / drain region, and the top of the gate contact plug and the top of the source / drain contact plug are respectively connected to the corresponding bottom of the interconnection metals.
2. The low resistance gate metal oxide semiconductor transistor according to claim 1, characterized in that: The semiconductor substrate integrated with polysilicon gate and source / drain regions comprises: An isolation zone and an active area are formed inside the semiconductor substrate, wherein the isolation zone defines the active area of the semiconductor substrate; An insulating gate dielectric layer is disposed above the active area, and the polysilicon gate is formed on the insulating gate dielectric layer; The source / drain regions are formed on the inner surface of the active region, and the source region and the drain region are distributed on opposite sides of the polysilicon gate.
3. The low resistance gate metal oxide semiconductor transistor according to claim 2, characterized in that: The metal block passes through the silicon nitride etching stop layer directly opposite to the top of the polysilicon gate; The source / drain contact plug passes through the insulating gate dielectric layer and the silicon nitride etching stop layer directly facing the top of the source / drain region.
4. A method for manufacturing a low resistance gate metal oxide semiconductor transistor, characterized in that: include: Generating a silicon nitride etch stop layer on top of a semiconductor substrate integrated with a polysilicon gate and source / drain regions; depositing a pre-metal dielectric layer on top of the silicon nitride etch stop layer; planarizing the pre-metal dielectric layer on top of the silicon nitride etch stop layer, and depositing an interlayer dielectric layer on top of the planarized pre-metal dielectric layer; Opening a gap in the interlayer dielectric layer and the silicon nitride etching stop layer on the top of the polysilicon gate to the top surface of the polysilicon gate, and depositing a metal layer on the top of the interlayer dielectric layer to fill the gap space, forming a metal block contacting the polysilicon gate inside the interlayer dielectric layer, wherein the deposited metal layer uses a low resistivity metal; Planarization removes the metal layer on top of the interlayer dielectric layer; The back-end interconnection processing is performed to make the polysilicon gate and the source / drain regions respectively conductive to the outer surface of the semiconductor transistor.
5. The method for manufacturing a low resistance gate metal oxide semiconductor transistor according to claim 4, characterized in that: The method of integrating a polysilicon gate and a source / drain region on a semiconductor substrate comprises: forming an insulating gate dielectric layer on top of the active region on the semiconductor substrate; forming a polysilicon gate on the insulating gate dielectric layer; Using the polysilicon gate as a mask, impurities are injected into the active area to form a lightly doped extension area; forming spacers on sidewalls of the polysilicon gate; Using the spacer as a mask, dopants are implanted into the lightly doped extension region to form source / drain regions.
6. The method for manufacturing a low resistance gate metal oxide semiconductor transistor according to claim 4, characterized in that: The planarizing of the pre-metal dielectric layer on the top of the silicon nitride etch stop layer includes: taking the top contact point of the silicon nitride etch stop layer as an endpoint, and planarizing the pre-metal dielectric layer above the endpoint by chemical mechanical planarization process.
7. The method for manufacturing a low resistance gate metal oxide semiconductor transistor according to claim 4, characterized in that: The process of opening a gap in the interlayer dielectric layer and silicon nitride etching stop layer on the top of the polysilicon gate to the top surface of the polysilicon gate includes: using a mask to align the polysilicon gate, etching the interlayer dielectric layer and silicon nitride layer on the top of the polysilicon gate, and stopping etching on the top surface of the polysilicon gate.
8. The method for manufacturing a low resistance gate metal oxide semiconductor transistor according to claim 4, characterized in that: The back-end interconnection process is performed to make the polysilicon gate and the source / drain regions respectively conductive to the outer surface of the semiconductor transistor, including: Continue to deposit and planarize the interlayer dielectric layer on the interlayer dielectric layer after the top metal layer is removed; Etching the interlayer dielectric layer on the top of the polysilicon gate until the etching stops on the top surface of the metal block to form a gate contact hole, and etching the interlayer dielectric layer and the pre-metal dielectric layer on the top of the source / drain region until the etching stops on the top surface of the silicon layer in the source / drain region to form a source / drain contact hole; Filling the gate contact hole and the source / drain contact hole with conductive materials to form a gate contact plug and a source / drain contact plug respectively; Interconnect metal is formed on top of the gate contact plug and the source / drain contact plug.