Circuit board frame and preparation method thereof, and embedded packaging substrate and preparation method thereof

Abstract

The embodiment of the invention provides a circuit board frame and a preparation method thereof, and an embedded packaging substrate and a preparation method thereof, relates to the technical field of semiconductors, and is used for reducing the cost of the embedded packaging substrate. The circuit board frame comprises a frame base material, a plurality of first conductive columns and a plurality of conductive blocks, and the frame base material comprises a first surface; the plurality of first conductive columns and the plurality of conductive blocks are embedded in the frame base material, the plurality of conductive blocks are arranged at intervals, one conductive block is in contact with at least one first conductive column, and the surfaces, deviating from the plurality of conductive blocks, of the plurality of first conductive columns are exposed on the first surface; the frame base material further comprises a first device installation space, and a first opening of the first device installation space is located on the first surface. The circuit board frame is used for the embedded packaging substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a circuit board frame and a preparation method thereof, and an embedded packaging substrate and a preparation method thereof. Background Art

[0002] The embedded packaging substrate may include a circuit board frame and wiring located on one side of the circuit board frame. In the related art, before forming the wiring located on one side of the circuit board frame, an insulating layer needs to be formed on one side of the circuit board frame. Therefore, the cost of the embedded packaging substrate is relatively high. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a circuit board frame and a preparation method thereof and an embedded packaging substrate and a preparation method thereof, so as to reduce the cost of the embedded packaging substrate.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a circuit board frame is provided. The circuit board frame includes a frame substrate, a plurality of first conductive pillars and a plurality of conductive blocks. The frame substrate includes a first surface. The plurality of first conductive pillars and the plurality of conductive blocks are embedded in the frame substrate, the plurality of conductive blocks are arranged at intervals, one conductive block is in contact with at least one first conductive pillar, and the surfaces of the plurality of first conductive pillars facing away from the plurality of conductive blocks are exposed to the first surface. The frame substrate also includes a first device installation space, and the first opening of the first device installation space is located on the first surface.

[0006] In the above-mentioned circuit board frame, when the circuit board frame is applied to an embedded packaging substrate, the first device installation space can be used to install electronic devices (such as the first electronic device), and the routing layer (such as the first routing layer) of the embedded packaging substrate can be directly formed on the first surface of the frame substrate. At this time, the first routing layer can be larger than the first conductive column and contact and electrically connected, so that the first routing layer can be electrically connected to the conductive block through the first conductive column. In addition, the first routing layer can also contact and electrically connect to the electronic device in the first device installation space. Among them, the first routing layer is in direct contact with the first surface of the frame substrate, and there is no other insulating layer between the two. In other words, before forming the first routing layer, there is no need to form other insulating layers on the first surface, and there is no need to form vias in the "other insulating layers", and to form via connection parts for connecting the first routing layer and the conductive block in the vias, thereby reducing the cost of the embedded packaging substrate.

[0007] In some embodiments, the contacting conductive blocks and first conductive columns are arranged along a first direction, and the first direction is perpendicular to the first surface; the ratio of the thickness of the conductive blocks in the first direction to the thickness of the first conductive columns in the first direction is greater than or equal to 6.2 and less than or equal to 12.34.

[0008] Among them, by making the ratio of the thickness of the conductive block in the first direction to the thickness of the first conductive column in the first direction less than or equal to 12.34, the thickness of the first conductive column can be prevented from being too small. If the thickness of the first conductive column is too small, it may cause the resistance of the first conductive column to be too large, which is not conducive to the first conductive column transmitting high-power, high-current signals. Therefore, by making the ratio of the thickness of the conductive block in the first direction to the thickness of the first conductive column in the first direction less than or equal to 12.34, the thickness H2 of the first conductive column can be prevented from being too small, which can be beneficial to the first conductive column transmitting high-power, high-current signals and the heat dissipation of the first conductive column.

[0009] By making the ratio of the thickness of the conductive block in the first direction to the thickness of the first conductive column in the first direction greater than or equal to 6.2, the thickness of the first conductive column can be prevented from being too large. If the thickness of the first conductive column is too large, the thickness of the circuit board frame may be too large. Therefore, by making the ratio of the thickness of the conductive block in the first direction to the thickness of the first conductive column in the first direction greater than or equal to 6.2, the problem of the circuit board frame being too large can be reduced. When the circuit board frame is applied to electronic equipment, it is conducive to the miniaturization of the electronic equipment.

[0010] In some embodiments, the thickness of the first conductive pillar in the first direction is greater than or equal to 30 μm and less than or equal to 50 μm.

[0011] Among them, by making the thickness of the first conductive column in the first direction 30μm, the thickness of the first conductive column can be avoided from being too small. If the thickness of the first conductive column is too small, the resistance of the first conductive column may be too large, which is not conducive to the first conductive column transmitting high-power, high-current signals. In addition, if the thickness of the first conductive column is too small, it is not conducive to the heat dissipation of the first conductive column. Therefore, by making the thickness of the first conductive column in the first direction 30μm, the thickness of the first conductive column can be avoided from being too small, which can be conducive to the first conductive column transmitting high-power, high-current signals and the heat dissipation of the first conductive column.

[0012] In addition, by making the thickness of the first conductive column in the first direction less than or equal to 50 μm, the thickness of the first conductive column can be prevented from being too large, for example, greater than 50 μm. If the thickness of the first conductive column is too large, the thickness of the circuit board frame may be too large. Therefore, by making the thickness of the first conductive column in the first direction less than or equal to 50 μm, the problem of the circuit board frame being too large can be reduced.

[0013] In some embodiments, the first conductive pillar includes a first electrical connection surface contacting the conductive block, and a maximum width of the first electrical connection surface is greater than or equal to 80 μm and less than or equal to 100 μm.

[0014] By making the maximum width of the first electrical connection surface greater than or equal to 80 μm, it is possible to avoid the area of ​​the first electrical connection surface being too small, which would result in the volume of the first conductive column being too small. If the volume of the first conductive column is too small, the resistance of the first conductive column would be too large, which would affect the transmission of the signal. Therefore, by making the maximum width of the first electrical connection surface greater than or equal to 80 μm, the effect of the small volume of the first conductive column on the signal transmission can be reduced.

[0015] The maximum width of the first electrical connection surface is less than or equal to 100 μm, so as to avoid the area of ​​the first electrical connection surface being too large, thereby causing the area of ​​the second electrical connection surface to be too large. If the area of ​​the second electrical connection surface is too large, the width of the wiring in the first wiring layer will be too large, thereby affecting the wiring density in the first wiring layer. Therefore, by making the maximum width of the first electrical connection surface less than or equal to 100 μm, the problem of too small wiring density in the first wiring layer due to the excessive area of ​​the second electrical connection surface can be reduced.

[0016] In some embodiments, the contacting conductive blocks and first conductive columns are arranged along a first direction, and the conductive blocks include a third surface and a fourth surface arranged opposite to each other in the first direction; the circuit board frame also includes: a wire layer, the wire layer is embedded in the frame substrate, and the wire layer is connected to the side of the conductive block, wherein the wire layer is located between the plane where the third surface is located and the plane where the fourth surface is located.

[0017] Among them, by arranging a conductor layer between the plane where the third plane is located and the plane where the fourth plane is located, the wiring area in the circuit board frame can be increased, so that more wiring can be arranged in the circuit board frame, which is conducive to improving the wiring density. In addition, the wiring area outside the circuit board frame can be reduced.

[0018] In some embodiments, there are multiple conductive line layers, and the multiple conductive line layers are spaced apart along the first direction on the side of the conductive block.

[0019] Among them, by providing multiple conductor layers, more routing lines can be arranged in the circuit board frame, the routing density can be further improved, and the routing area outside the circuit board frame can be further reduced.

[0020] In some embodiments, the frame substrate further includes a second surface disposed opposite to the first surface. The circuit board frame further includes: a plurality of second conductive pillars, the plurality of second conductive pillars are embedded in the frame substrate, a surface of a conductive block facing away from the first conductive pillar is in contact with at least one second conductive pillar, and surfaces of the plurality of second conductive pillars facing away from the conductive block are exposed to the second surface.

[0021] Among them, the routing layer (for example, the second routing layer) of the embedded package substrate can be directly formed on the second surface of the frame substrate, that is, the second routing layer is in direct contact with the second surface of the frame substrate, and no other insulating layer is interposed therebetween. In other words, there is no need to form other insulating layers before forming the second routing layer, and there is no need to form vias in the "other insulating layers", and to form via connection portions in the vias for connecting the second routing layer and the conductive blocks, thereby reducing the cost of the embedded package substrate.

[0022] In some embodiments, the frame substrate further includes a second surface disposed opposite to the first surface; the circuit board frame further includes: a support block. The support block is embedded in the frame substrate and spaced apart from the conductive block; two surfaces of the support block opposite to each other in the first direction are covered by the frame substrate.

[0023] The support block can support the circuit board frame, and the strength of the circuit board frame can be improved by arranging the support block in the circuit board frame.

[0024] In some embodiments, the frame substrate further includes a second surface disposed opposite to the first surface; the first device mounting space further includes a second opening, and the second opening is located on the second surface.

[0025] Wherein, when the first device installation space also includes a second opening, the first electronic device can be loaded into the first device installation space from the second opening, and the first electronic device can be flush with the first electrical connection surface with the aid of a fixing film, thereby facilitating the installation of the first electronic device.

[0026] On the other hand, an embedded packaging substrate is provided, comprising: a circuit board frame provided in some of the above embodiments, a first electronic device and a first wiring layer. The first electronic device is located in a first device installation space of a frame substrate of the circuit board frame. The first wiring layer is located on a first surface of the frame substrate, the first wiring layer contacts a plurality of first conductive posts of the circuit board frame, and the first wiring layer contacts the first electronic device.

[0027] In the above-mentioned embedded packaging substrate, the first electronic device can be arranged in the first device installation space, and the first wiring layer can be directly formed on the first surface of the frame substrate. In this case, the first wiring layer can be electrically connected to the first electronic device and the first conductive column. The first wiring layer is in direct contact with the first surface of the frame substrate, and no other insulating layer is separated therebetween. In other words, before forming the first wiring layer, it is not necessary to form other insulating layers on the first surface, and it is not necessary to form vias in the "other insulating layers", and to form via connection parts in the vias for connecting the first wiring layer and the conductive blocks, thereby reducing the cost of the embedded packaging substrate.

[0028] In some embodiments, a ratio of a thickness of the first routing layer in the first direction to a thickness of the first conductive pillar in the first direction is greater than or equal to 0.36 and less than or equal to 2.

[0029] Wherein, the ratio of the thickness of the first routing layer in the first direction to the thickness of the first conductive column in the first direction is greater than or equal to 2, so that the thickness of the first routing layer can be avoided from being too large. Wherein, the thickness of the first routing layer will affect the thickness of the circuit board frame. If the thickness of the first routing layer is too large, the circuit board frame will be too thick. Therefore, by making the ratio of the thickness of the first routing layer in the first direction to the thickness of the first conductive column in the first direction greater than or equal to 2, the circuit board frame can be avoided from being too thick due to the excessive thickness of the first routing layer, which is beneficial to the miniaturization of the circuit board frame. When the circuit board frame is applied to electronic equipment, it is beneficial to the miniaturization of the electronic equipment.

[0030] In addition, the ratio of the thickness of the first routing layer in the first direction to the thickness of the first conductive column in the first direction is greater than or equal to 0.36, so that the thickness of the first routing layer can be prevented from being too small, so that the first routing layer can be ensured to have sufficient thickness, so that the first routing layer can shield interference signals. In addition, the greater the thickness of the first routing layer, the better the heat dissipation effect. Therefore, by making the ratio of the thickness of the first routing layer in the first direction to the thickness of the first conductive column in the first direction greater than or equal to 0.36, the heat dissipation effect of the first routing layer can be ensured.

[0031] In some embodiments, the embedded packaging substrate also includes: multiple first solder pads and multiple first connecting portions, the multiple first solder pads are located on the side of the first routing layer away from the multiple first conductive columns, the multiple first connecting portions are located between the multiple first solder pads and the first routing layer, and the first solder pads are electrically connected to the first routing layer through the first connecting portions.

[0032] Among them, the first pad can be connected to other electronic components, and then other electronic components can be electrically connected to the first wiring layer through the first pad and the first connecting part, and the first wiring layer is electrically connected to the first electronic device, and then the first electronic device can be electrically connected to the electronic component connected to the first pad.

[0033] In some embodiments, when the frame substrate also includes a second surface arranged opposite to the first surface; the circuit board frame also includes: a plurality of second conductive pillars, a surface of a conductive block facing away from the first conductive pillar is in contact with at least one second conductive pillar, and surfaces of the plurality of second conductive pillars facing away from the conductive block are exposed to the second surface: the embedded packaging substrate also includes: a second routing layer, the second routing layer is located on a side of the plurality of second conductive blocks of the circuit board frame facing away from the plurality of second conductive pillars, and the second routing layer is in contact with and electrically connected to the plurality of second conductive pillars.

[0034] The second wiring layer can be directly formed on the second surface of the frame substrate, that is, the second wiring layer is in direct contact with the second surface of the frame substrate, and no other insulating layer is interposed therebetween. In other words, there is no need to form other insulating layers before forming the second wiring layer, and there is no need to form vias in the "other insulating layers", and to form via connection portions in the vias for connecting the second wiring layer and the conductive blocks, thereby reducing the cost of the embedded package substrate.

[0035] In some embodiments, the embedded packaging substrate also includes: multiple second solder pads and multiple second connecting portions, the multiple second solder pads are located on the side of the second routing layer away from the multiple second conductive columns, the multiple second connecting portions are located between the multiple second solder pads and the second routing layer, and the second solder pads are electrically connected to the second routing layer through the second connecting portions.

[0036] Among them, the second functional element can be welded to the second pad, and the second pad can be electrically connected to the second conductive column through the second connecting portion, and the second conductive column can be electrically connected to the first electronic device through the conductive block and the first conductive column, and then the second functional element can be electrically connected to the first electronic device.

[0037] In another aspect, an electronic device is provided, comprising: the embedded package substrate provided in some of the above embodiments and a first functional element, wherein the first functional element is electrically connected to a first wiring layer of the embedded package substrate.

[0038] The above-mentioned electronic device has the same structure and beneficial technical effects as the embedded packaging substrate provided in some of the above-mentioned embodiments, which will not be described in detail here.

[0039] On the other hand, a method for preparing a circuit board frame is provided, the method for preparing the circuit board frame comprising: forming a plurality of conductive blocks, the plurality of conductive blocks being arranged at intervals; forming a plurality of first conductive columns on one side of the plurality of conductive blocks, wherein at least one first conductive column contact is arranged on one side of a conductive block; forming a frame substrate, the frame substrate covering the plurality of conductive blocks and the plurality of conductive blocks, the frame substrate comprising a first surface, the plurality of first conductive columns being exposed to the first surface away from the surfaces of the plurality of conductive blocks, the frame substrate further comprising a first device installation space, the first opening of the first device installation space being located on the first surface.

[0040] Among them, the circuit board frame formed based on the above preparation method has all the beneficial effects of the circuit board frames provided by some of the above embodiments, which will not be described in detail here.

[0041] In some embodiments, forming a frame substrate includes: forming a first dielectric layer, the first dielectric layer covers a first portion of a plurality of conductive blocks and a plurality of first conductive pillars, the first dielectric layer includes a first surface, and the first portion is a portion of the conductive block close to the first conductive pillar. Forming a second dielectric layer, the second dielectric layer covers a second portion of the plurality of conductive blocks, wherein the second portion is a portion of the conductive block not covered by the first dielectric layer. Removing a portion of the first dielectric layer, or removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a first device mounting space, the retained first dielectric layer and the retained second dielectric layer form the frame substrate.

[0042] The frame substrate is formed by forming a first dielectric layer and a second dielectric layer on both sides of the conductive block, and forming a first device installation space by removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer.

[0043] In some embodiments, before forming the second dielectric layer, the method further includes: forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, wherein at least one second conductive pillar is formed on a conductive block. When forming the second dielectric layer, the second dielectric layer also covers the plurality of second conductive pillars, and the second dielectric layer includes a second surface away from the first dielectric layer, and surfaces of the plurality of second conductive pillars away from the conductive blocks are exposed to the second surface.

[0044] The surface of the second conductive column facing away from the conductive block is exposed to the second surface, so the routing layer (e.g., the second routing layer) of the embedded package substrate can be directly formed on the second surface of the frame substrate, and the second routing layer can be directly in contact with and connected to the second conductive column, that is, the second routing layer is in direct contact with the second surface of the frame substrate, and no other insulating layer is interposed therebetween. In other words, there is no need to form other insulating layers before forming the second routing layer, and there is no need to form vias in the "other insulating layers", and to form via connection portions in the vias for connecting the second routing layer and the conductive block, thereby reducing the cost of the embedded package substrate.

[0045] In some embodiments, forming a plurality of conductive blocks includes: etching a target area of ​​a conductive substrate to thin the target area to form a connecting rib, and forming a conductive block outside the target area, wherein the connecting rib connects two conductive blocks. Before forming the second dielectric layer, the method further includes: removing the connecting rib.

[0046] The conductive block can be fixed by forming connecting ribs.

[0047] In some embodiments, in the step of forming a plurality of conductive blocks, support blocks are formed simultaneously; the support blocks and the conductive blocks are arranged in the same layer, and the support blocks and the conductive blocks are arranged at intervals.

[0048] The support block can support the circuit board frame, and the strength of the circuit board frame can be improved by arranging the support block in the circuit board frame.

[0049] In some embodiments, in the step of forming a plurality of conductive blocks, a sacrificial block is formed simultaneously, the sacrificial block is spaced apart from the conductive blocks, and is located between two adjacent conductive blocks. In the step of forming a plurality of first conductive pillars on one side of the plurality of conductive blocks, a first sacrificial pillar is formed simultaneously, wherein the direction in which the sacrificial block points to the first sacrificial pillar is the same as the direction in which the conductive block points to the first conductive pillar. Removing a portion of the first dielectric layer, or removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a first device mounting space, comprises: removing the sacrificial block through the first sacrificial pillar, and removing a portion of the first dielectric layer located on the fifth surface of the sacrificial block, wherein the fifth surface is the surface of the sacrificial block connected to the first sacrificial pillar.

[0050] Among them, by forming a first sacrificial column on the sacrificial block, after removing the first sacrificial column, the sacrificial block can be exposed, so that the sacrificial block can be removed. In addition, the first dielectric layer on the fifth surface of the sacrificial block is also removed. After removing the first sacrificial column, the sacrificial block and the first dielectric layer on the fifth surface, a first device installation space is formed. By forming the sacrificial block and the first sacrificial column, it is easy to form the first device installation space.

[0051] In some embodiments, in the step of forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, a second sacrificial pillar is simultaneously formed on a side of the sacrificial block away from the first sacrificial pillar. Removing a portion of the first dielectric layer, or removing a portion of the first dielectric layer and a portion of the second dielectric layer to form a first device mounting space, comprises: removing the sacrificial block through the first sacrificial pillar and the second sacrificial pillar, and removing a portion of the first dielectric layer located on the fifth surface of the sacrificial block and a portion of the second dielectric layer located on the sixth surface of the sacrificial block, wherein the fifth surface is a surface of the sacrificial block connected to the first sacrificial pillar, and the sixth surface is a surface of the sacrificial block connected to the second sacrificial pillar.

[0052] The first sacrificial column and the second sacrificial column are respectively formed on two opposite surfaces of the sacrificial block. After removing the first sacrificial column and the second sacrificial column, the sacrificial block can be removed, thereby forming a first device installation space that penetrates the frame substrate.

[0053] In some embodiments, forming a plurality of conductive blocks includes: forming a plurality of first conductive parts on a substrate. Forming a frame substrate includes: forming a third dielectric layer, the third dielectric layer is located on a side of the substrate provided with the first conductive parts, and the plurality of first conductive parts are embedded in the third dielectric layer. The method for preparing a circuit board frame also includes: removing the substrate; forming a conductive film layer, the conductive film layer is located on one side of the third dielectric layer, and the conductive film layer is in contact with the plurality of first conductive parts, the conductive film layer includes a first conductive part and a second conductive part connected to each other, the first conductive part overlaps with the first conductive part, and the second conductive part serves as a wire layer. Forming a plurality of conductive blocks also includes: forming a plurality of second conductive parts on a side of the conductive film layer away from the third dielectric layer, the second conductive parts overlap with the first conductive parts. Forming a plurality of first conductive pillars on one side of the plurality of conductive blocks includes: forming a plurality of first conductive pillars on a side of the second conductive parts of the plurality of conductive blocks away from the first conductive parts. The frame substrate is formed, and further includes: forming a fourth dielectric layer, the fourth dielectric layer is located on one side of the third dielectric layer, and the conductive film layer, multiple second conductive parts and multiple first conductive pillars are embedded in the fourth dielectric layer, and the fourth dielectric layer exposes the surface of the first conductive pillar away from the conductive block; removing part of the fourth dielectric layer, or removing part of the fourth dielectric layer and part of the third dielectric layer, and the retained third dielectric layer and the retained fourth dielectric layer form the frame substrate.

[0054] With such arrangement, a conductor layer can be formed in the frame substrate.

[0055] In another aspect, a method for preparing an embedded package substrate is provided. The method for preparing the embedded package substrate comprises: placing a first electronic device in a first device installation space of a frame substrate of a circuit board frame provided in some of the above embodiments. Forming a first wiring layer on a first surface of the frame substrate, wherein the first wiring layer contacts a plurality of first conductive pillars of the circuit board frame, and the first wiring layer contacts the first electronic device.

[0056] The embedded package substrate formed based on the above preparation method has all the beneficial effects of the embedded package substrate provided by some of the above embodiments, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0058] Figure 1 A structural diagram of an embedded package substrate provided according to some embodiments;

[0059] Figure 2 for Figure 1 The structural diagram of the circuit board frame in;

[0060] Figure 3 is another structural diagram of an embedded package substrate according to some embodiments;

[0061] Figure 4 for Figure 3 The structural diagram of the circuit board frame in;

[0062] Figure 5 is another structural diagram of a circuit board frame according to some embodiments;

[0063] Figure 6 for Figure 3 A structural diagram of installing a first electronic device in a first device installation space of a circuit board frame;

[0064] Figure 7 A structural diagram showing the connection between multiple conductor layers and conductive blocks;

[0065] Figure 8 A structural block diagram of an electronic device provided according to some embodiments;

[0066] Fig. 9is a flow chart of a method for preparing a circuit board frame according to some embodiments;

[0067] Figures 10 to 26 It is a structural diagram corresponding to each step of a method for preparing a circuit board frame according to some embodiments;

[0068] Fig. 27 is another structural diagram of a circuit board frame according to some embodiments;

[0069] Fig.28 is another flow chart of a method for preparing a circuit board frame according to some embodiments;

[0070] Fig.29 is another flow chart of a method for preparing a circuit board frame according to some embodiments;

[0071] Figures 30 to 39 It is a structural diagram corresponding to each step of another method for preparing a circuit board frame according to some embodiments;

[0072] Fig.40 is another flow chart of a method for preparing an embedded package substrate according to some embodiments;

[0073] Figure 41 to Figure 44 It is a structural diagram corresponding to each step of another method for preparing an embedded package substrate according to some embodiments;

[0074] Fig.45 and Fig.46 A structural diagram corresponding to steps of another method for preparing an embedded package substrate according to some embodiments;

[0075] Fig.47 is another structural diagram of an embedded package substrate according to some embodiments;

[0076] Fig.48 is another structural diagram of an embedded package substrate according to some embodiments;

[0077] Fig.49 and Fig.50 A structural diagram corresponding to steps of another method for preparing an embedded package substrate according to some embodiments;

[0078] Fig.51 is another structural diagram of an embedded package substrate according to some embodiments;

[0079] Fig.52 is another structural diagram of an embedded package substrate according to some embodiments. DETAILED DESCRIPTION

[0080] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0081] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0082] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0083] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0084] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0085] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0086] Figure 1 FIG. 1 is a structural diagram of an embedded package substrate provided according to some embodiments.

[0087] See also Figure 1 The embodiment of the present application provides an embedded package substrate 1000. The embedded package substrate 1000 may include a circuit board frame 100, a filling portion 200, a first electronic device 300, a first insulating layer 510, a via connection portion 411, a first routing layer 410, a plurality of first connection portions 620, a plurality of first pads 610 and a first protective layer 710.

[0088] The circuit board frame 100 includes a frame substrate 110 and a plurality of conductive blocks 120 . The plurality of conductive blocks 120 are embedded in the frame substrate 110 .

[0089] For example, the frame substrate 110 may include a first insulating material, such as polypropylene (PP), which has high impact resistance, strong mechanical properties, and resistance to corrosion by various organic solvents and acids and alkalis.

[0090] The plurality of conductive blocks 120 are arranged at intervals, so that the plurality of conductive blocks 120 are insulated from each other, thereby preventing the plurality of conductive blocks 120 from being short-circuited.

[0091] For example, the conductive block 120 may be made of a metal material, such as Cu (copper).

[0092] Figure 2 for Figure 1 Schematic diagram of the circuit board frame 100.

[0093] See also Figure 2The frame substrate 110 of the circuit board frame 100 includes a first surface 111 and a second surface 112 disposed opposite to each other in the thickness direction X of the frame substrate 110. One surface of the plurality of conductive blocks 120 is exposed to the first surface 111. Figure 2 As shown, the direction indicated by arrow X is the thickness direction.

[0094] The frame substrate 110 may further include a first device mounting space 113 , and an opening of the first device mounting space 113 is located at the first surface 111 . The first device mounting space 113 may be used to accommodate the first electronic device 300 .

[0095] For example, when preparing the embedded package substrate 1000, the first electronic device 300 can be placed in the first device installation space 113, wherein the first electronic device 300 can include a plurality of pins 310. The pins 310 of the first electronic device 300 can be located in the same plane as the first surface 111. Then, the second insulating material is filled in the first device installation space 113 to form a filling portion 200, wherein the filling portion 200 can fix the first electronic device 300.

[0096] In some examples, the filling portion 200 may include a first contact surface 210 , wherein the first contact surface 210 may expose the pins 310 of the first electronic device 300 . In some examples, the first contact surface 210 may be located in the same plane as the first surface 111 .

[0097] For example, the second insulating material may include ABF (Ajinomoto Build-Up Film) material.

[0098] See you later Figure 1 The buried package substrate 1000 may further include a first insulating layer 510 and a second insulating layer 520 .

[0099] After the first electronic device 300 is installed in the first device installation space 113, a first insulating layer 510 may be formed on the first surface 111 of the frame substrate 110. The first insulating layer 510 includes a plurality of vias. For example, the vias on the first insulating layer 510 may be formed by an etching process. Part of the vias in the first insulating layer 510 may expose the conductive blocks 120, and another part of the vias may expose the pins 310 of the first electronic device 300.

[0100] Then, a via connection portion 411 is formed in the via hole of the first insulating layer 510. Among them, one end of a part of the via connection portion 411 in the thickness direction X of the frame substrate 110 is connected to the conductive block 120, and then the via connection portion 411 can be electrically connected to the conductive block 120, and one end of another part of the via connection portion 411 in the thickness direction X of the frame substrate 110 is connected to the pin 310 of the first electronic device 300, and therefore, another part of the via connection portion 411 can be electrically connected to the pin 310 of the first electronic device 300.

[0101] The other end of the via connection portion 411 in the thickness direction X may be exposed to the surface of the first insulating layer 510 away from the frame substrate 110 .

[0102] Next, a first wiring layer 410 is formed on the surface of the first insulating layer 510 facing away from the frame substrate 110, wherein the first wiring layer 410 may cover the via connection portion 411, wherein a portion of the via connection portion 411 may be electrically connected to the conductive block 120, and another portion of the via connection portion 411 may be electrically connected to the pin 310 of the first electronic device 300. In this way, the first electronic device 300 may be electrically connected to the conductive block 120 through the first wiring layer 410.

[0103] Next, a second insulating layer 520 is formed, wherein the second insulating layer 520 may cover the first surface 111 of the frame substrate 110 and the side of the first wiring layer 410 away from the frame substrate 110. The second insulating layer 520 may include a plurality of second vias, and the second vias expose the first wiring layer 410.

[0104] Then, a first connection portion 620 is formed in the second via hole, wherein a surface of the first connection portion 620 facing away from the frame substrate 110 may be flush with a surface of the second insulating layer 520 .

[0105] Afterwards, a plurality of first pads 610 are formed on a side of the plurality of first connection portions 620 facing away from the frame substrate 110 , wherein one first pad 610 can be connected to one first connection portion 620 , and thus the first pad 610 can be electrically connected to the first connection portion 620 .

[0106] Finally, a first protective layer 710 is formed on the side of the plurality of first pads 610 facing away from the frame substrate 110 , wherein the first protective layer 710 may include a plurality of first pad openings, each first pad opening exposing a portion of a first pad 610 , so that the first pad 610 can be welded to other electronic components.

[0107] The first protective layer 710 may be made of an insulating material. For example, the first protective layer 710 may protect the circuit board frame 100 and reduce the intrusion of water and oxygen.

[0108] Among them, Figure 1 and Figure 2 In the provided embedded packaging substrate 1000, when forming the first routing layer 410 on the circuit board frame 100, it is necessary to first form the first insulating layer 510 on the first surface 111 of the frame substrate 110 of the circuit board frame 100, and form a via connection portion 411 in the first insulating layer 510, and then form the first routing layer 410. Therefore, the cost of the embedded packaging substrate 1000 is relatively high.

[0109] Based on this, an embodiment of the present application provides a circuit board frame.

[0110] Figure 3 FIG. 1 is another structural diagram of an embedded package substrate 1000 according to some embodiments.

[0111] See also Figure 3 In some embodiments, the embedded package substrate 1000 may include: a circuit board frame 100 , a first electronic device 300 and a first routing layer 410 .

[0112] Next, the structure of the circuit board frame 100 is exemplarily described.

[0113] Figure 4 for Figure 3 Schematic diagram of the circuit board frame 100.

[0114] See also Figure 4 The circuit board frame 100 includes: a frame substrate 110, a plurality of conductive blocks 120 and a plurality of first conductive pillars 130. The frame substrate 110 includes a first surface 111 and a second surface 112 arranged opposite to each other in the thickness direction X of the frame substrate 110. The plurality of first conductive pillars 130 and the plurality of conductive blocks 120 are embedded in the frame substrate 110, and the plurality of conductive blocks 120 are arranged at intervals. One conductive block 120 is in contact with at least one first conductive pillar 130, and the surfaces of the plurality of first conductive pillars 130 facing away from the plurality of conductive blocks 120 are exposed to the first surface 111. The frame substrate 110 also includes a first device mounting space 113, and a first opening 1131 of the first device mounting space 113 is located on the first surface 111.

[0115] The conductive block 120 contacts at least one first conductive column 130, so that the conductive block 120 is electrically connected to the first conductive column 130. The cross-sectional area of ​​the first conductive column 130 is smaller than the cross-sectional area of ​​the conductive block 120, wherein the cross-sectional area of ​​the first conductive column 130 is perpendicular to the thickness direction X of the frame substrate 110, and the cross-sectional area of ​​the conductive block 120 is perpendicular to the thickness direction X of the frame substrate 110.

[0116] Among them, the surface of the first conductive column 130 facing away from the conductive block 120 is exposed to the first surface 111. Therefore, when the first routing layer 410 is formed on the first surface 111, the first routing layer 410 can contact the side of the first conductive column 130 facing away from the conductive block 120, so that the first routing layer 410 can be electrically connected to the first conductive column 130.

[0117] See also Figure 4 In some examples, the first device installation space 113 may be a hollow structure, that is, the first device installation space 113 may penetrate the frame substrate 110. At this time, the first device installation space 113 may include a first opening 1131 and a second opening 1132 that are relatively arranged in the thickness direction X of the frame substrate 110, wherein the first opening 1131 is located on the first surface 111, and the second opening 1132 is located on the second surface 112.

[0118] Figure 5 FIG. 4 is another structural diagram of a circuit board frame 100 according to some embodiments.

[0119] See also Figure 5 In other examples, the first device installation space 113 may be a mounting groove, and in this case, the first device installation space 113 may include a first opening 1131. In this case, the depth of the first device installation space 113 in the thickness direction X of the frame substrate 110 may be greater than the thickness of the first electronic device 300 in the thickness direction X of the frame substrate 110, thereby preventing the pins 310 of the first electronic device 300 from protruding from the first surface 111 of the frame substrate 110, thereby reducing the impact on the first wiring layer 410.

[0120] Figure 6 for Figure 3 FIG. 1 is a structural diagram of a first electronic device 300 installed in a first device installation space 113 of a circuit board frame 100.

[0121] See also Figure 6 The embedded package substrate 1000 may further include: a first electronic device 300. The first electronic device 300 may be located in the first device installation space 113 of the circuit board frame 100.

[0122] Please refer again Figure 3 The embedded package substrate 1000 may further include: a first routing layer 410 .

[0123] The first routing layer 410 is located on the first surface 111 of the frame substrate 110 . The first routing layer 410 is in contact with the plurality of first conductive pillars 130 of the circuit board frame 100 , and the first routing layer 410 is in contact with the first electronic device 300 .

[0124] The first wiring layer 410 is electrically connected to the first electronic device 300. For example, the first electronic device 300 may include a plurality of pins 310 and a first electronic device body 320. The plurality of pins 310 may be disposed on a surface of the first electronic device body 320. The first wiring layer 410 may contact and be electrically connected to the plurality of pins 310 of the first electronic device 300.

[0125] After the first electronic device 300 is fixed in the first device installation space 113, a first routing layer 410 can be formed on the first surface 111 of the frame substrate 110. The first routing layer 410 can contact with the plurality of first conductive pillars 130, and then the first routing layer 410 can be electrically connected to the plurality of first conductive pillars 130, and the plurality of first conductive pillars 130 can contact and be electrically connected to the plurality of conductive blocks 120, so the first routing 410 can be electrically connected to the plurality of conductive blocks 120. In addition, the first routing layer 410 can also contact and be electrically connected to the pins 310 of the first electronic device 300, so the first electronic device 300 can be electrically connected to the first conductive pillar 130 through the first routing layer 410 and the first conductive pillar 130, so that the first conductive pillar 130 can be used to transmit the signal received or output by the first electronic device 300.

[0126] It should be noted that the first wiring layer 410 can be directly formed on the first surface 111 of the frame substrate 110, that is, the first wiring layer 410 is in direct contact with the first surface 111 of the frame substrate 110, and no other insulating layer is interposed therebetween. In other words, before forming the first wiring layer 410, it is not necessary to form other insulating layers on the first surface 111, and it is not necessary to form vias in the "other insulating layers", and to form via connection portions in the vias for connecting the first wiring layer 410 and the conductive blocks 120, thereby reducing the cost of the embedded package substrate 1000.

[0127] Please continue reading Figure 6 In some embodiments, the embedded package substrate 1000 may further include a filling portion 200. The filling portion 200 is filled in the first device installation space 113 of the frame substrate 110 of the circuit board frame 100, and the first electronic device 300 may be embedded in the filling portion 200. The filling portion 200 may fix the first electronic device 300.

[0128] The filling portion 200 may include a first contact surface 210, and the first contact surface 210 may be flush with the first surface 111. The filling portion 200 may wrap the first electronic device 300, and may cover a portion of the surface (e.g., the side) of the pin 310, wherein the surface of the pin 310 not covered by the filling portion 200 (e.g., the surface away from the first electronic device body 320) may be exposed to the first contact surface 210 of the filling portion 200.

[0129] When preparing the embedded packaging substrate 1000, the first electronic device 300 can be placed in the first device installation space 113, and the pin 310 of the first electronic device 300 is made flush with the first surface 111 of the frame substrate 110. Then, the first device installation space 113 is filled with filling material to form a filling portion 200 in the first device installation space 113. The filling portion 200 can fix the first electronic device 300 in the first device installation space 113.

[0130] After forming the filling portion 200 , a first wiring layer 410 may be formed on the first surface 111 of the frame substrate 110 . The first wiring layer 410 may also cover a portion of the first contact surface 210 of the filling portion 200 and the pins 310 of the first electronic device 300 .

[0131] Please refer again Figure 4 In some embodiments, the conductive blocks 120 and the first conductive pillars 130 that are in contact with each other are arranged along a first direction F1, and the first direction F1 is perpendicular to the first surface 111. Figure 4 As shown, the direction indicated by arrow F1 is the first direction.

[0132] Among the contacting conductive blocks 120 and first conductive pillars 130 , the direction from the conductive blocks 120 to the first conductive pillars 130 is the first direction F1 . The first direction F1 may be parallel to the thickness direction X of the frame substrate 110 .

[0133] In some examples, the thickness H1 of the conductive block 120 in the first direction F1 is greater than the thickness H2 of the first conductive pillar 130 in the first direction F1, thereby increasing the thickness H1 of the conductive block 120 in the first direction F1 and further reducing the resistance of the conductive block 120.

[0134] The ratio of the thickness H1 of the conductive block 120 in the first direction F1 to the thickness H2 of the first conductive column 130 in the first direction F1 is greater than or equal to 6.2 and less than or equal to 12.34, that is, 6.2≤H1 / H2≤12.34. In the following, for the convenience of description, the “thickness of the conductive block 120 in the first direction F1” is referred to as the “thickness of the conductive block 120”, and the “thickness of the first conductive column 130 in the first direction F1” is referred to as the “thickness of the first conductive column 130”.

[0135] By making H1 / H2≤12.34, the thickness H2 of the first conductive column 130 can be prevented from being too small, for example, H2 is less than H1 / 12.34. If the thickness H2 of the first conductive column 130 is too small, the resistance of the first conductive column 130 may be too large, which is not conducive to the first conductive column 130 transmitting a high-power, high-current signal. In addition, if the thickness H2 of the first conductive column 130 is too small, it is not conducive to the heat dissipation of the first conductive column 130. Therefore, by making H1 / H2≤12.34, the thickness H2 of the first conductive column 130 can be prevented from being too small, which can be conducive to the first conductive column 130 transmitting a high-power, high-current signal and the heat dissipation of the first conductive column 130.

[0136] By making H1 / H2≥6.2, the thickness H2 of the first conductive pillar 130 can be prevented from being too large, for example, H2 is greater than H1 / 6.2. If the thickness H2 of the first conductive pillar 130 is too large, the thickness of the circuit board frame 100 may be too large. Therefore, by making H1 / H2≥6.2, the problem of the circuit board frame 100 being too large can be reduced. When the circuit board frame 100 is applied to electronic equipment, it is conducive to the miniaturization of the electronic equipment.

[0137] See also Figure 4 In some embodiments, the thickness of the first conductive pillar 130 in the first direction F1 is greater than or equal to 30 μm and less than or equal to 50 μm, that is, 30 μm≤H2≤50 μm.

[0138] By making H2≥30μm, the thickness H2 of the first conductive column 130 can be prevented from being too small, for example, H2 is less than 30μm. If the thickness H2 of the first conductive column 130 is too small, the resistance of the first conductive column 130 may be too large, which is not conducive to the first conductive column 130 transmitting a high-power, high-current signal. In addition, if the thickness H2 of the first conductive column 130 is too small, it is not conducive to the heat dissipation of the first conductive column 130. Therefore, by making H2≥30μm, the thickness H2 of the first conductive column 130 can be prevented from being too small, which can be conducive to the first conductive column 130 transmitting a high-power, high-current signal and the heat dissipation of the first conductive column 130.

[0139] In addition, by making H2≤50μm, the thickness H2 of the first conductive pillar 130 can be prevented from being too large, for example, H2 is greater than 50μm. If the thickness H2 of the first conductive pillar 130 is too large, the thickness of the circuit board frame 100 may be too large. Therefore, by making H2≤50μm, the problem of the circuit board frame 100 being too large in thickness can be reduced.

[0140] For example, H2 = 40 μm. By setting H2 = 40 μm, the effect of the first conductive pillar 130 transmitting high-power and high-current signals and the heat dissipation of the first conductive pillar 130 due to the thickness H2 of the first conductive pillar 130 being too small can be reduced, and the problem of the circuit board frame 100 being too thick can also be reduced.

[0141] In some embodiments, the thickness H1 of the conductive block 120 is greater than or equal to 310 μm and less than or equal to 370 μm, that is, 310 μm≤H1≤370 μm.

[0142] Among them, the thickness of the frame substrate 110 mainly depends on the thickness H1 of the conductive block 120, and the maximum depth of the first device installation space 113 in the first direction F1 depends on the thickness of the frame substrate 110. In short, the maximum depth of the first device installation space 113 in the first direction F1 mainly depends on the thickness H1 of the conductive block 120.

[0143] By making H1≥310μm, the thickness H1 of the conductive block 120 can be prevented from being too small. For example, if H1 is less than 310μm, if the thickness of the conductive block 120 is too small, the depth of the first device installation space 113 in the first direction F1 may not be greater than the thickness of the first electronic device 300, that is, it is difficult for the first device installation space 113 to accommodate the first electronic device 300 in its entirety. At this time, part of the first electronic device 300 will be protruded from the first surface 111 of the frame substrate 110, thereby affecting the formation of the first wiring layer 410. Therefore, by making H1≥310μm, the adverse effects on the wiring of the first wiring layer 410 caused by the too small thickness of the conductive block 120 can be reduced.

[0144] In addition, by making H1 ≤ 370 μm, the thickness of the conductive block 120 can be prevented from being too large, for example, greater than 370 μm. By making H1 ≤ 370 μm, the thickness of the circuit board frame 100 can be prevented from being too large due to the thickness H1 of the conductive block 120 being too large.

[0145] For example, H1=340 μm. At this time, it can avoid that the thickness H1 of the conductive block 120 is too small, which will cause adverse effects on the wiring of the first wiring layer 410, and it can also avoid that the thickness of the circuit board frame 100 is too large due to the thickness H1 of the conductive block 120 being too large.

[0146] Please continue reading Figure 4 In some embodiments, the first conductive column 130 includes a first electrical connection surface 131 in contact with the conductive block 120, and a second electrical connection surface 132 away from the conductive block 120, wherein the first electrical connection surface 131 and the second electrical connection surface 132 are arranged opposite to each other in the first direction F1.

[0147] In some examples, the cross-sectional area of ​​the first conductive pillar 130 gradually increases along the first direction F1 , and at this time, the area of ​​the second electrical connection surface 132 is greater than the area of ​​the first electrical connection surface 131 .

[0148] The maximum width of the first electrical connection surface 131 is greater than or equal to 80 μm and less than or equal to 100 μm.

[0149] The first electrical connection surface 131 may be circular or rectangular, wherein the rectangle may include a standard rectangle or a quasi-rectangle, in which the angle between two adjacent sides is 90°, and the two sides are directly connected. In a quasi-rectangle, two sides perpendicular to each other may be connected by a chamfered straight line or a chamfered arc. The rectangle may include a rectangle or a square, and in the embodiments of the present application, the shape of the first electrical connection surface 131 is not limited.

[0150] The area of ​​the first electrical connection surface 131 is mainly determined by the maximum width of the first electrical connection surface 131 , and the volume of the first conductive pillar 130 is mainly determined by the area of ​​the first electrical connection surface 131 .

[0151] By making the maximum width of the first electrical connection surface 131 greater than or equal to 80 μm, it is possible to avoid the area of ​​the first electrical connection surface 131 being too small, which would result in the volume of the first conductive pillar 130 being too small. If the volume of the first conductive pillar 130 is too small, the resistance of the first conductive pillar 130 would be too large, which would affect the transmission of the signal. Therefore, by making the maximum width of the first electrical connection surface 131 greater than or equal to 80 μm, the effect of the small volume of the first conductive pillar 130 on the signal transmission can be reduced.

[0152] In addition, the first routing layer 410 needs to cover the second electrical connection surface 132 of the first conductive column 130, and the area of ​​the second electrical connection surface 132 is larger than the area of ​​the first electrical connection surface 131. Therefore, the larger the area of ​​the first electrical connection surface 131, the larger the area of ​​the second electrical connection surface 132.

[0153] The maximum width of the first electrical connection surface 131 is less than or equal to 100 μm, so that the area of ​​the first electrical connection surface 131 can be prevented from being too large, thereby causing the area of ​​the second electrical connection surface 132 to be too large. If the area of ​​the second electrical connection surface 132 is too large, the width of the wiring in the first wiring layer 410 will be too large, thereby affecting the wiring density in the first wiring layer 410. Therefore, by making the maximum width of the first electrical connection surface 131 less than or equal to 100 μm, the problem of reducing the wiring density in the first wiring 410 due to the excessive area of ​​the second electrical connection surface 132 can be reduced.

[0154] See you later Figure 3 In some embodiments, the ratio of the thickness H3 of the first routing layer 410 in the first direction F1 to the thickness H2 of the first conductive column 130 in the first direction F1 is greater than or equal to 0.36 and less than or equal to 2, that is, 0.36≤H3 / H2≤2.

[0155] For the convenience of description below, “the thickness of the first routing layer 410 in the first direction F1 ” is referred to as “the thickness of the first routing layer 410 ” for short.

[0156] Among them, H3 / H2≤2, therefore, H3≤2×H2, so that the thickness H3 of the first wiring layer 410 can be prevented from being too large, for example, H3 is greater than 2×H2. Among them, the thickness H3 of the first wiring layer 410 will affect the thickness of the circuit board frame 100. If the thickness H3 of the first wiring layer 410 is too large, the circuit board frame 100 will be too thick. Therefore, by making H3 / H2≤2, the circuit board frame 100 can be prevented from being too thick due to the excessive thickness H3 of the first wiring layer 410, which is conducive to the miniaturization of the circuit board frame 100. When the circuit board frame 100 is applied to electronic equipment, it is conducive to the miniaturization of the electronic equipment.

[0157] In addition, H3 / H2≥0.36, therefore, H3≥0.36×H2, so that the thickness H3 of the first routing layer 410 can be prevented from being too small, for example, H3 is less than 0.36×H2, so that the first routing layer 410 can be guaranteed to have a sufficient thickness, so that the first routing layer 410 can shield interference signals. In addition, the greater the thickness of the first routing layer 410, the better its heat dissipation effect, therefore, by making H3 / H2≥0.36, the heat dissipation effect of the first routing layer 410 can be guaranteed.

[0158] In some examples, the thickness H3 of the first routing layer 410 is greater than or equal to 18 μm and less than or equal to 60 μm.

[0159] For example, the thickness H3 of the first wiring layer 410 is equal to a first preset value, wherein the first preset value is greater than or equal to 18 μm and less than or equal to 42 μm.

[0160] For example, the first preset value is equal to 30 μm.

[0161] For example, the thickness H3 of the first wiring layer 410 is equal to a second preset value, wherein the second preset value is greater than or equal to 30 μm and less than or equal to 60 μm.

[0162] For example, the second preset value is equal to 45 μm.

[0163] Please refer again Figure 3 In some embodiments, the embedded packaging substrate 1000 may further include a plurality of first solder pads 610 and a plurality of first connecting portions 620, the plurality of first solder pads 610 being located on a side of the first routing layer 410 away from the plurality of first conductive pillars 130, the plurality of first connecting portions 620 being located between the plurality of first solder pads 610 and the first routing layer 410, and the first solder pads 610 being electrically connected to the first routing layer 410 through the first connecting portions 620.

[0164] Among them, the first solder pad 610 can be connected to other electronic components, and then the other electronic components can be electrically connected to the first routing layer 410 through the first solder pad 610 and the first connecting part 620, and the first routing layer 410 is electrically connected to the first electronic device 300, and then the first electronic device 300 can be electrically connected to the electronic components connected to the first solder pad 610.

[0165] By way of example, the electronic components may include chips, capacitors, resistors, etc. In the embodiments of the present application, the types of the electronic components are not limited.

[0166] In some embodiments, the thickness of the first pad 610 in the first direction F1 is greater than or equal to 18 μm and less than or equal to 42 μm.

[0167] For example, the thickness of the first pad 610 in the first direction F1 may be equal to 30 μm.

[0168] Please continue reading Figure 3 In some embodiments, the embedded package substrate 1000 may further include a fourth insulating layer 810, wherein the fourth insulating layer 810 covers the first surface 111 and the surface of the first wiring layer 410 away from the frame substrate 110. The first wiring layer 410 is embedded in the fourth insulating layer 810, and the first connecting portion 620 is embedded in the fourth insulating layer 810. The first pad is located on the surface of the fourth insulating layer 810 away from the frame substrate 110.

[0169] In some embodiments, the embedded package substrate 1000 may further include a first protective layer 710, which is located on a side of the fourth insulating layer 810 away from the frame substrate 110. The first protective layer 710 may include a plurality of first pad openings, each of which exposes a portion of a first pad 610, so that the first pad 610 can be soldered to other electronic components.

[0170] Please refer again Figure 4 In some embodiments, the frame substrate 110 further includes a second surface 112 disposed opposite to the first surface 111 . The first device mounting space 113 further includes a second opening 1132 , and the second opening 1132 is located on the second surface 112 .

[0171] Please refer again Figure 6 When installing the first electronic device 300 in the first device installation space 113, a fixing film can be used to cover the first surface 111, and the fixing film can cover the first opening 1131, and then the first electronic device 300 is placed into the first device installation space 113 from the second opening 1132, wherein the pins 310 of the first electronic device 300 can be connected to the fixing film, so that the pins 310 of the first electronic device 300 can be flush with the first surface 111. Then, the second insulating material can be filled in the first device installation space 113 to form the filling portion 200, and after the filling portion 200 is formed, the fixing film can be removed.

[0172] In summary, when the first device installation space 113 also includes a second opening 1132, the first electronic device 300 can be loaded into the first device installation space 113 from the second opening 1132, and the pin 310 of the first electronic device 300 can be flush with the first surface 111 with the aid of a fixing film, thereby facilitating the installation of the first electronic device 300.

[0173] Please continue reading Figure 6 In some examples, the filling portion 200 may further include a second contact surface 220 , wherein the second contact surface 220 may be flush with the second surface 112 of the frame substrate 110 .

[0174] In some embodiments, the circuit board frame 100 further includes: a plurality of second conductive pillars 140. The plurality of second conductive pillars 140 are embedded in the frame substrate 110, a surface of a conductive block 120 facing away from the first conductive pillar 130 contacts at least one second conductive pillar 140, and a surface of the plurality of second conductive pillars 140 facing away from the conductive block 120 is exposed to the second surface 112.

[0175] In some examples, at least one second conductive pillar 140 is disposed on a surface of a conductive block 120 facing away from the first conductive pillar 130. The cross-sectional area of ​​the second conductive pillar 140 is smaller than the cross-sectional area of ​​the conductive block 120, and the cross-sectional area of ​​the second conductive pillar 140 is perpendicular to the thickness direction X of the frame substrate 110.

[0176] In some examples, the thickness H1 of the conductive block 120 in the first direction F1 is greater than the thickness H4 of the second conductive pillar 140 in the first direction F1, thereby increasing the thickness H1 of the conductive block 120 in the first direction F1 and further reducing the resistance of the conductive block 120.

[0177] The ratio of the thickness H1 of the conductive block 120 in the first direction F1 to the thickness H4 of the second conductive pillar 140 in the first direction F1 is greater than or equal to 6.2 and less than or equal to 12.34, that is, 6.2≤H1 / H4≤12.34. In the following, for the convenience of description, the "thickness of the second conductive pillar 140 in the first direction F1" is referred to as the "thickness of the second conductive pillar 140".

[0178] Among them, by making H1 / H4≤12.34, the thickness H4 of the second conductive column 140 can be prevented from being too small, for example, H4 is less than H1 / 12.34. If the thickness H4 of the second conductive column 140 is too small, the resistance of the second conductive column 140 may be too large, which is not conducive to the second conductive column 140 transmitting a high-power, high-current signal. In addition, if the thickness H4 of the second conductive column 140 is too small, it is not conducive to the heat dissipation of the second conductive column 140. Therefore, by making H1 / H4≤12.34, the thickness H4 of the second conductive column 140 can be prevented from being too small, which can be conducive to the second conductive column 140 transmitting a high-power, high-current signal and the heat dissipation of the second conductive column 140.

[0179] By making H1 / H4≥6.2, the thickness H4 of the second conductive pillar 140 can be prevented from being too large, for example, H4 is greater than H1 / 6.2. If the thickness H4 of the second conductive pillar 140 is too large, the thickness of the circuit board frame 100 may be too large. Therefore, by making H1 / H4≥6.2, the problem of the circuit board frame 100 being too large can be reduced. When the circuit board frame 100 is applied to electronic equipment, it is conducive to the miniaturization of the electronic equipment.

[0180] See also Figure 4 In some embodiments, the thickness of the second conductive pillar 140 in the first direction F1 is greater than or equal to 30 μm and less than or equal to 50 μm, that is, 30 μm≤H4≤50 μm.

[0181] By making H4≥30μm, the thickness H4 of the second conductive column 140 can be prevented from being too small, for example, H4 is less than 30μm. If the thickness H4 of the second conductive column 140 is too small, the resistance of the second conductive column 140 may be too large, which is not conducive to the second conductive column 140 transmitting a high-power, high-current signal. In addition, if the thickness H4 of the second conductive column 140 is too small, it is not conducive to the heat dissipation of the second conductive column 140. Therefore, by making H4≥30μm, the thickness H4 of the second conductive column 140 can be prevented from being too small, which can be conducive to the second conductive column 140 transmitting a high-power, high-current signal and the heat dissipation of the second conductive column 140.

[0182] In addition, by making H4≤50μm, the thickness H4 of the second conductive pillar 140 can be prevented from being too large, for example, H4 is greater than 50μm. If the thickness H4 of the second conductive pillar 140 is too large, the thickness of the circuit board frame 100 may be too large. Therefore, by making H4≤50μm, the problem of the circuit board frame 100 being too large in thickness can be reduced.

[0183] For example, H4=40 μm. By setting H4=40 μm, the influence of the second conductive pillar 140 transmitting high-power and high-current signals and the heat dissipation of the second conductive pillar 140 due to the thickness H4 of the second conductive pillar 140 being too small can be reduced, and the problem of the circuit board frame 100 being too thick can also be reduced.

[0184] In some examples, the thickness H4 of the second conductive pillar 140 may be equal to the thickness H2 of the first conductive pillar 130 . Of course, the thickness H4 of the second conductive pillar 140 may also be different from the thickness H2 of the first conductive pillar 130 .

[0185] Please refer again Figure 3 In some embodiments, the embedded package substrate 1000 may further include a second routing layer 430 , which may cover the second surface 112 of the frame substrate 110 . In addition, the second routing layer 430 may also cover the second contact surface 220 of the filling portion 200 .

[0186] The second routing layer 430 may be in contact with an end of the second conductive pillar 140 facing away from the conductive block 120 , and thus the second routing layer 430 may be electrically connected to the conductive block 120 through the second conductive pillar 140 .

[0187] When the first device mounting space 113 of the circuit board frame 100 includes the first opening 1131 and the second opening 1132 , the pin 310 of the first electronic device 300 may be flush with the first surface 111 , and at this time, the first routing layer 410 may be electrically connected to the pin 310 of the first electronic device 300 .

[0188] Alternatively, the pin 310 of the first electronic device 300 may also be flush with the second surface 112, in which case the second routing layer 430 may contact and be electrically connected to the pin 310 of the first electronic device 300. The second routing layer 430 may contact a plurality of second conductive pillars 140, and then the second routing layer 430 may be electrically connected to the plurality of second conductive pillars 140, and the plurality of second conductive pillars 140 may contact and be electrically connected to the plurality of conductive blocks 120, and therefore, the second routing layer 430 may be electrically connected to the plurality of conductive blocks 120. In addition, the second routing layer 430 may also contact and be electrically connected to the pin 310 of the first electronic device 300, and therefore, the first electronic device 300 may be electrically connected to the second conductive pillar 140 through the second routing layer 430 and the second conductive pillar 140, so that the second conductive pillar 140 may be used to transmit the signal received or output by the first electronic device 300.

[0189] After the first electronic device 300 is fixed in the first device installation space 113, a second routing layer 430 can be formed on the second surface 112 of the frame substrate 110. It should be noted that the second routing layer 430 can be directly formed on the second surface 112 of the frame substrate 110, that is, the second routing layer 430 is in direct contact with the second surface 112 of the frame substrate 110, and there is no other insulating layer between the two. In other words, there is no need to form other insulating layers before forming the second routing layer 430, and there is no need to form vias in the "other insulating layers", and to form via connection parts in the vias for connecting the second routing layer 430 and the conductive block 120, thereby reducing the cost of the embedded packaging substrate 1000.

[0190] In some embodiments, a ratio of a thickness H5 of the second routing layer 430 in the first direction F1 to a thickness H4 of the second conductive pillar 140 in the first direction F1 is greater than or equal to 0.36 and less than or equal to 2, that is, 0.36≤H5 / H4≤2.

[0191] For the convenience of description below, “the thickness of the second routing layer 430 in the first direction F1 ” is referred to as “the thickness of the second routing layer 430 ”.

[0192] Among them, H5 / H4≤2, therefore, H5≤2×H4, so that the thickness H5 of the second wiring layer 430 can be prevented from being too large, for example, H5 is greater than 2×H4. Among them, the thickness H5 of the second wiring layer 430 will affect the thickness of the circuit board frame 100. If the thickness H5 of the second wiring layer 430 is too large, the circuit board frame 100 will be too thick. Therefore, by making H5 / H4≤2, the circuit board frame 100 can be prevented from being too thick due to the excessive thickness H5 of the second wiring layer 430, which is conducive to the miniaturization of the circuit board frame 100. When the circuit board frame 100 is applied to electronic equipment, it is conducive to the miniaturization of the electronic equipment.

[0193] In addition, H5 / H4≥0.36, therefore, H5≥0.36×H4, so that the thickness H5 of the second routing layer 430 can be prevented from being too small, for example, H5 is less than 0.36×H4, so that the second routing layer 430 can be guaranteed to have a sufficient thickness, so that the second routing layer 430 can shield the interference signal. In addition, the greater the thickness of the second routing layer 430, the better the heat dissipation effect thereof, so by making H5 / H4≥0.36, the heat dissipation effect of the second routing layer 430 can be guaranteed.

[0194] In some examples, the thickness H5 of the second routing layer 430 is greater than or equal to 18 μm and less than or equal to 60 μm.

[0195] For example, the thickness H5 of the second wiring layer 430 is equal to a first preset value, wherein the first preset value is greater than or equal to 18 μm and less than or equal to 42 μm.

[0196] For example, the first preset value is equal to 30 μm.

[0197] For example, the thickness H5 of the second wiring layer 430 is equal to a second preset value, wherein the second preset value is greater than or equal to 30 μm and less than or equal to 60 μm.

[0198] For example, the second preset value is equal to 45 μm.

[0199] In some examples, the thickness H5 of the second routing layer 430 may be equal to the thickness H3 of the first routing layer 410 . Of course, the thickness H5 of the second routing layer 430 may also be different from the thickness H3 of the first routing layer 410 .

[0200] See you later Figure 3In some embodiments, the embedded package substrate 1000 may further include: a plurality of second pads 630 and a plurality of second connecting portions 640. The plurality of second pads 630 are located on a side of the second wiring layer 430 away from the plurality of second conductive pillars 140, the plurality of second connecting portions 640 are located between the plurality of second pads 630 and the second wiring layer 430, and the second pads 630 are electrically connected to the second wiring layer 430 through the second connecting portions 640.

[0201] Among them, the second solder pad 630 can be connected to other electronic components, and then the other electronic components can be electrically connected to the second routing layer 430 through the second solder pad 630 and the second connecting part 640, and the second routing layer 430 is electrically connected to the first electronic device 300, and then the first electronic device 300 can be electrically connected to the electronic components connected to the second solder pad 630.

[0202] By way of example, the electronic components may include chips, capacitors, resistors, etc. In the embodiments of the present application, the types of the electronic components are not limited.

[0203] In some embodiments, the thickness of the second pad 630 in the first direction F1 is greater than or equal to 18 μm and less than or equal to 42 μm.

[0204] For example, the thickness of the second pad 630 in the first direction F1 may be equal to 30 μm.

[0205] Please continue reading Figure 3 In some embodiments, the embedded package substrate 1000 may further include a fifth insulating layer 820, wherein the fifth insulating layer 820 covers the second surface 112 and the surface of the second wiring layer 430 away from the frame substrate 110. The second wiring layer 430 is embedded in the fifth insulating layer 820, and the second connecting portion 640 is embedded in the fifth insulating layer 820. The first pad is located on the surface of the fifth insulating layer 820 away from the frame substrate 110.

[0206] In some embodiments, the embedded package substrate 1000 may further include a second protective layer 720, which is located on a side of the fifth insulating layer 820 away from the frame substrate 110. The second protective layer 720 may include a plurality of second pad openings, and a second pad opening exposes a portion of a second pad 630, so that the second pad 630 can be soldered to other electronic components.

[0207] See also Figures 4 to 6In some embodiments, the conductive block 120 includes a third surface 121 and a fourth surface 122 that are arranged opposite to each other in the first direction F1. The circuit board frame 100 further includes a wire layer 150. The wire layer 150 is embedded in the frame substrate 110, and the wire layer 150 is connected to the side of the conductive block 120, wherein the wire layer 150 is located between the plane where the third surface 121 is located and the plane where the fourth surface 122 is located.

[0208] The number of the wire layer 150 may be one or more, and the wire layer 150 may include multiple wires, and one conductive block 120 may be electrically connected to one wire. Figures 4 to 6 In the figure, the structure of the circuit board frame 100 is illustrated by taking the circuit board frame 100 including one conductor layer 150 as an example.

[0209] Among them, by setting a conductor layer 150 between the plane where the third surface 121 is located and the plane where the fourth surface 122 is located, the routing area in the circuit board frame 100 can be increased, so that more routing lines can be arranged in the circuit board frame 100, which is conducive to improving the routing density.

[0210] Figure 7 It is a structural diagram of the connection between multiple wire layers 150 and the conductive block 120.

[0211] See also Figure 7 In some examples, when there are multiple conductive line layers 150 , the multiple conductive line layers 150 may be arranged at intervals on the side of the conductive block 120 along the first direction F1 .

[0212] By providing a plurality of conductor layers 150 , more wirings can be arranged in the circuit board frame 100 , the wiring density can be further improved, and the wiring area outside the circuit board frame 100 can be further reduced.

[0213] In some examples, the thickness of the wire layer 150 may be greater than or equal to 25 μm, so that the wire layer 150 can shield interference signals.

[0214] Please continue reading Figures 4 to 6 In some embodiments, the circuit board frame 100 further includes a support block 160 . The support block 160 is embedded in the frame substrate 110 , and the support block 160 and the conductive block 120 are disposed on the same layer.

[0215] Among them, the support block 160 includes two surfaces arranged opposite to each other in the first direction F1, and the support block 160 and the conductive block 120 are arranged in the same layer. At this time, one of the two surfaces of the support block 160 arranged opposite to each other in the first direction F1 is located in the same plane as the third surface 121, and the other is located in the same plane as the fourth surface 122.

[0216] The support block 160 is spaced apart from the conductive block 120 , and the support block 160 is insulated from the conductive block 120 . Two surfaces of the support block 160 that are opposite to each other in the first direction F1 are covered by the frame substrate 110 .

[0217] The support block 160 can support the circuit board frame 100 . By arranging the support block 160 in the circuit board frame 100 , the strength of the circuit board frame 100 can be improved.

[0218] In some examples, the plurality of conductive blocks 120 may be sequentially arranged along the second direction F2. Figures 4 to 6 As shown, the direction indicated by the arrow F2 is the second direction F2.

[0219] Wherein, a conductive block 120 is disposed on each of two sides of the supporting block 160 in the second direction F2.

[0220] In some examples, the support block 160 may be located at one side of the first device mounting space 113 in the second direction F2, and at this time, the first device mounting space 113 is disposed adjacent to the support block 160 and a conductive block 120 on both sides in the second direction F2. At this time, the first device mounting space 113 is disposed between the support block 160 and the conductive block 120, and the support block 160 and the conductive block 120 can support the first device mounting space 113 to prevent the first device mounting space 113 from collapsing.

[0221] The embodiment of the present application also provides an electronic device 2000.

[0222] Figure 8 is a structural block diagram of an electronic device 2000 provided according to some embodiments.

[0223] See also Figure 8 The electronic device 2000 comprises: the embedded package substrate 1000 and the first functional element 3000 provided in some embodiments above. The first functional element 3000 is electrically connected to the first wiring layer 410 (such as Figure 3 shown).

[0224] See also Figure 8 , and combined with Figure 3 For example, the first functional element can be welded to the first pad 610 to be electrically connected to the first wiring layer 410, and the first wiring layer 410 can be electrically connected to the first electronic device 300, and then the first functional element can be electrically connected to the first electronic device 300.

[0225] In other examples, the electronic device may further include a second functional element, wherein the second functional element may be electrically connected to the second wiring layer 430. For example, the second functional element may be soldered to the second pad 630, and the second pad 630 may be electrically connected to the second conductive column 140 through the second connection portion 640, and the second conductive column 140 may be electrically connected to the first electronic device 300 through the conductive block 120 and the first conductive column 130, and the second functional element may be electrically connected to the first electronic device 300.

[0226] The first functional device may include electronic components such as capacitors and resistors.

[0227] The second functional device may include electronic components such as capacitors and resistors.

[0228] Among them, the above-mentioned electronic device can be a power supply, and the power supply can be applied to various products such as supercomputing servers, wireless, routers, etc.

[0229] exist Figures 3 to 8 In the embodiment, the circuit board frame 100, the embedded package substrate 1000 and the structure of the electronic device are introduced, and then the preparation method of the circuit board frame is introduced.

[0230] Fig. 9 is a flow chart of a method for preparing a circuit board frame according to some embodiments; Figures 10 to 26 It is a structural diagram corresponding to each step of a method for preparing a circuit board frame according to some embodiments.

[0231] See also Fig. 9 , an embodiment of the present application provides a method for preparing a circuit board frame, and the method for preparing the circuit board frame may include the following steps S10 to S30.

[0232] S10, forming a plurality of conductive blocks, wherein the plurality of conductive blocks are arranged at intervals.

[0233] See also Fig.10 Before step S10, a conductive substrate 910 may be provided. In step S10, the conductive substrate 910 may be etched to form a plurality of conductive blocks 120 (eg Figure 4 As shown). The conductive substrate 910 may be made of a metal material, for example, the conductive substrate 910 includes Cu.

[0234] For example, the first dry film 921 and the second dry film 922 are respectively covered on two surfaces of the conductive substrate 910 that are opposite to each other in the first direction F1.

[0235] See also Fig.11 Next, the first dry film 921 and the second dry film 922 are patterned.

[0236] See also Fig.12 Next, the conductive substrate 910 is etched according to the patterned first dry film 921 and the patterned second dry film 922 to form a plurality of conductive blocks 120 .

[0237] The thickness of the conductive block 120 in the first direction F1 may be equal to the thickness of the conductive substrate 910 in the first direction F1.

[0238] In some embodiments, step S10, forming a plurality of conductive blocks includes: S11, etching a target area of ​​a conductive substrate to thin the target area to form connecting ribs, and forming conductive blocks in portions outside the target area, wherein the connecting ribs connect two conductive blocks.

[0239] See also Fig.12 In step S11, the connecting rib 911 can be formed by connecting the conductive substrate 910 (such as Fig.10 The connection rib 911 and the conductive block 120 can be formed at the same time.

[0240] In some examples, two adjacent conductive blocks 120 may be connected via a connecting rib 911. The connecting rib 911 may be provided to fix a plurality of conductive blocks 120.

[0241] See also Fig.12 In some embodiments, in step S10, in the step of forming a plurality of conductive blocks, a support block 160 is formed simultaneously; the support block 160 and the conductive block 120 are arranged in the same layer, and the support block 160 and the conductive block 120 are arranged at intervals.

[0242] The support block 160 can be formed by contacting the conductive substrate 910 (such as Fig.10 The support block 160, the connecting rib 911 and the conductive block 120 can be formed at the same time.

[0243] The thickness of the support block 160 in the first direction F1 may be equal to the thickness of the conductive substrate 910 in the first direction F1.

[0244] In some examples, the two sides of the support block 160 in the second direction F2 may be adjacent to two conductive blocks 120 respectively. In this case, the two sides of the support block 160 in the second direction F2 are respectively connected to the adjacent conductive blocks 120 through the connecting ribs 911 .

[0245] In some other examples, one side of the support block 160 in the second direction F2 may be adjacent to a conductive block 120 . Adjacent support blocks 160 and conductive blocks 120 may be connected via a connecting rib 911 .

[0246] The structure of the support block 160 is the same as that of the conductive block 120. Fig.12 In FIG. 1 , only a portion of the support block 160 is shown.

[0247] See also Fig.12 In some embodiments, in step S10 , in the step of forming a plurality of conductive blocks, a sacrificial block 912 is formed simultaneously. The sacrificial block 912 is spaced apart from the conductive block 120 and is located between two adjacent conductive blocks 120 .

[0248] See also Fig.12 The sacrificial block 912 can be formed by applying a conductive substrate 910 (such as Fig.10 Obtained by etching (as shown).

[0249] In some examples, the sacrificial block 912 may be located between two adjacent conductive blocks 120, wherein both sides of the sacrificial block 912 in the second direction F2 may be connected to the two conductive blocks 120 respectively through two connecting ribs 911. At this time, the connecting ribs 911 may fix the conductive blocks 120 and the sacrificial block 912.

[0250] The thickness of the sacrificial block 912 in the first direction F1 may be equal to the thickness of the conductive block 120 in the first reverse direction F1.

[0251] After the support blocks 160 , the connection ribs 911 , the sacrificial blocks 912 , and the conductive blocks 120 are formed, the first dry film 921 and the second dry film 922 may be removed.

[0252] In some of the following embodiments, for the convenience of description, the structure formed after etching the conductive substrate 910 is defined as a conductive base frame, wherein the conductive base frame may include a support block 160 , a connecting rib 911 , a sacrificial block 912 and a conductive block 120 .

[0253] See also Fig. 9 The method for preparing a circuit board frame may include: S20, forming a plurality of first conductive pillars on one side of a plurality of conductive blocks, wherein at least one first conductive pillar contact is disposed on one side of a conductive block.

[0254] In step S20, refer to Fig.13 First, the third dry film 923 and the fourth dry film 924 may be respectively covered on both sides of the conductive base in the first direction F1.

[0255] Then, see Fig.14, the third dry film 923 is patterned, at this time, a plurality of vias are formed in the third dry film 923, and the vias in the third dry film 923 can expose a surface of the corresponding conductive block 120. Among them, one conductive block 120 can correspond to one or more vias in the third dry film 923.

[0256] See also Fig.15 , a first conductive pillar 130 is formed in the via hole in the third dry film 923 , and one end of the first conductive pillar 130 can contact the conductive block 120 .

[0257] It should be noted that in Fig.15 In the figure, only the first conductive pillar 130 formed on one conductive block 120 is illustrated, while the first conductive pillar 130 formed on another conductive block 120 is not illustrated.

[0258] See also Fig.15 In some embodiments, in step S20, in the step of forming multiple first conductive pillars on one side of multiple conductive blocks, a first sacrificial pillar 913 is formed simultaneously, wherein the direction in which the sacrificial block 912 points to the first sacrificial pillar 913 is the same as the direction in which the conductive block 120 points to the first conductive pillar 130.

[0259] See you later Fig.14 , some of the vias in the third dry film 923 may expose the sacrificial block 912, wherein one sacrificial block 912 may correspond to one or more vias, wherein the projection of the via corresponding to one sacrificial block 912 in the first direction F1 may cover the sacrificial block 912. Fig.14 As shown, one sacrificial block 912 may correspond to two via holes in the third dry film 923 .

[0260] See also Fig.15 A first sacrificial column 913 is formed in the via hole corresponding to the sacrificial block 912. The thickness of the first sacrificial column 913 in the first direction F1 may be equal to the thickness of the first conductive column 130 in the first direction F1.

[0261] The cross-sectional area of ​​the first sacrificial column 913 is smaller than that of the sacrificial block 912 , wherein the cross-sectional area of ​​the first sacrificial column 913 is perpendicular to the thickness direction X of the frame substrate 110 , and the cross-sectional area of ​​the sacrificial block 912 is perpendicular to the thickness direction X of the frame substrate 110 .

[0262] The first sacrificial pillar 913 and the first conductive pillar 130 may both be made of Cu.

[0263] See you later Fig. 9 , after step S20, step S30 may be executed.

[0264] S30, forming a frame substrate, the frame substrate covers a plurality of conductive blocks and a plurality of first conductive pillars, the frame substrate includes a first surface, the surfaces of the plurality of first conductive pillars facing away from the plurality of conductive blocks are exposed on the first surface, the frame substrate also includes a first device installation space, and a first opening of the first device installation space is located on the first surface.

[0265] See also Fig.26 After completing step S30, the preparation of the circuit board frame 100 is completed. The circuit board frame 100 formed based on the above preparation method has all the beneficial effects of the circuit board frame 100 provided by some of the above embodiments, which will not be described in detail here.

[0266] See also Fig.28 , step S30, forming a frame substrate, including: the following steps S31 to S33.

[0267] S31, forming a first dielectric layer, the first dielectric layer covering the first parts of the plurality of conductive blocks and the plurality of first conductive pillars, the first dielectric layer comprising a first surface, and the first part being a part of the conductive block close to the first conductive pillar.

[0268] See also Fig.16 In step S31, the first dielectric layer 114 may be used to replace the third dry film 923 (eg Fig.15 For example, the third dry film 923 may be removed first, and then the first dielectric layer 114 may be formed, wherein the first dielectric layer 114 may wrap the first portion 123 of the conductive block 120 and cover the third surface 121 of the conductive block 120 and the gap between two adjacent conductive blocks 120. At this time, it can be understood that the first portion 123 of the conductive block 120 is embedded in the first dielectric layer 114.

[0269] The first dielectric layer 114 may be formed by a lamination process.

[0270] The first dielectric layer may be made of a first insulating material, for example, the first insulating material may include PP.

[0271] In some examples, step S10 may include step S11 , that is, the conductive base may further include a connecting rib 911 , and in this case, the first dielectric layer 114 may cover a surface of the connecting rib 911 close to the first conductive column 130 .

[0272] In some examples, when the supporting block 160 is formed while the conductive block 120 is formed, the conductive base may further include the supporting block 160. When performing step S31 and forming the first dielectric layer, the first dielectric layer 114 also covers the third portion 161 of the supporting block 160, wherein the third portion 161 is a portion of the supporting block 160 close to the plane where the first conductive column 130 is located. At this time, the third portion 161 is embedded in the first dielectric layer 114.

[0273] In some examples, when the support block 160 is formed while the sacrificial block 912 is formed, the conductive base may further include the sacrificial block 912. When performing step S31 and forming the first dielectric layer, the first dielectric layer 114 also covers the portion of the sacrificial block 912 close to the first sacrificial column 913 and the first sacrificial column 913, and the first dielectric layer 114 exposes the surface of the first sacrificial column 913 away from the sacrificial block 912. At this time, the first sacrificial column 913 is embedded in the first dielectric layer 114.

[0274] See also Fig.28 In some embodiments, before step S32, the method for preparing the circuit board frame may further include: step S40, removing the connecting ribs.

[0275] See also Fig.17 In step S40 , the fourth dry film 924 may be patterned first. The patterned fourth dry film 924 may expose the connecting ribs 911 .

[0276] Next, see Fig.18 , the connecting ribs 911 are removed according to the patterned fourth dry film 924 (eg Fig.17 As shown). In step S40, the connecting rib 911 (as shown) Fig.17 After the first dielectric layer 114 is removed, the conductive block 120, the support block 160 and the sacrificial block 912 can be fixed.

[0277] See also Fig.28 In some embodiments, after step S40, step S32 may be performed to form a second dielectric layer, wherein the second dielectric layer covers a second portion of the plurality of conductive blocks, wherein the second portion is a portion of the conductive block that is not covered by the first dielectric layer.

[0278] like Fig.19 As shown, the second portion 124 is embedded in the second dielectric layer 115. It is understood that before forming the second dielectric layer 115, the fourth dry film 924 may be removed.

[0279] In step S40 , the second dielectric layer 115 may be formed on the first dielectric layer 114 by a lamination process.

[0280] In some examples, the second dielectric layer 115 may cover the fourth surface 122 of the conductive block 120 .

[0281] In some other examples, the second dielectric layer 115 may expose the fourth surface 122 of the conductive block 120 .

[0282] See also Fig.28 , after step S32, step S33 can be executed.

[0283] S33, removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form a first device mounting space, and the remaining first dielectric layer and the remaining second dielectric layer form a frame substrate.

[0284] In some examples, in step S33 , a portion of the first dielectric layer 114 may be removed, and in this case, the first device mounting space 113 may be a mounting groove.

[0285] See also Fig. 20 In other examples, in step S33, part of the first dielectric layer 114 and part of the second dielectric layer 115 may be removed. In this case, the first device mounting space 113 may be a mounting groove, or the first device mounting space 113 may be a hollow portion. Fig. 20 In the figure, the embodiment of the present application is schematically described by taking the first device installation space 113 as a hollow portion as an example.

[0286] In some embodiments, when the sacrificial block 912 and the first sacrificial column 913 are formed, step S33, removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form a first device mounting space, may include: S331, removing the sacrificial block through the first sacrificial column, and removing part of the first dielectric layer located on the fifth surface of the sacrificial block, wherein the fifth surface is the surface of the sacrificial block connected to the first sacrificial column.

[0287] See also Fig.19 In step S331 , after the first sacrificial column 913 is removed, the sacrificial block 912 may be exposed, and thus the sacrificial block 912 may be removed.

[0288] In addition, in step S331, the first dielectric layer 114 on the fifth surface 9121 of the sacrificial block 912 is also removed, and the first device mounting space 113 is formed after the first sacrificial pillar 913, the sacrificial block 912, and the first dielectric layer 114 on the fifth surface 9121 are removed. The formation of the sacrificial block 912 and the first sacrificial pillar 913 facilitates the formation of the first device mounting space.

[0289] In some examples, the sacrificial block 912 further includes a sixth surface 9122 disposed opposite to the fifth surface 9121. The second dielectric layer 115 may expose the sixth surface 9122 of the sacrificial block 912. At this time, in step S331, after removing the first sacrificial column 913, the sacrificial block 912, and the first dielectric layer 114 on the fifth surface 9121 of the sacrificial block 912, the formed first device mounting space 113 may be a hollow portion.

[0290] In other examples, the second dielectric layer 115 can cover the sixth surface 9122 of the sacrificial block 912. In this case, in step S331, after removing the first sacrificial column 913, the sacrificial block 912 and the first dielectric layer 114 on the fifth surface 9121 of the sacrificial block 912, the first device mounting space 113 formed can be a mounting groove.

[0291] In some other examples, when the second dielectric layer 115 can cover the sixth surface 9122 of the sacrificial block 912, in this case, in step S331, after removing the first sacrificial column 913, the sacrificial block 912, the first dielectric layer 114 on the fifth surface 9121 of the sacrificial block 912, and the second dielectric layer 115 on the sixth surface 9122 of the sacrificial block 912, the formed first device mounting space 113 can be a hollow portion.

[0292] In some examples, the sacrificial block 912 includes a first side surface 9123 and a second side surface 9124 that are oppositely disposed in the second direction F2. Two first sacrificial posts 913 are formed on one sacrificial block 912, and the two first sacrificial posts 913 are oppositely disposed in the second direction F2, wherein a surface of the first first sacrificial post 913 facing away from the second first sacrificial post 913 is flush with the first side surface 9123, and a surface of the second first sacrificial post 913 facing away from the first first sacrificial post 913 is flush with the second side surface 9124.

[0293] At this time, the first dielectric layer 114 located on the fifth surface 9121 may be located between the two first sacrificial pillars 913. In step S331, after the two first sacrificial pillars 913 and the sacrificial block 912 are removed, the first dielectric layer 114 located on the fifth surface 9121 may fall off automatically, so there is no need to remove the first dielectric layer 114 located on the fifth surface 9121 through an additional process, thereby simplifying the preparation process of the circuit board frame 100.

[0294] After step S331 , the remaining first dielectric layer 114 and the remaining second dielectric layer 115 may form the frame substrate 110 .

[0295] At this point, the circuit board frame 100 is completed.

[0296] The frame substrate 110 is formed by forming a first dielectric layer 114 and a second dielectric layer 115 on both sides of the conductive block 120, and forming a first device mounting space 113 by removing part of the first dielectric layer 114, or removing part of the first dielectric layer 114 and part of the second dielectric layer 115.

[0297] The circuit board frame 100 formed based on the above preparation methods has all the beneficial effects of the circuit board frame 100 provided by the above embodiments, which will not be elaborated here.

[0298] See you later Figure 4 In some embodiments, the circuit board frame 100 may further include: a plurality of second conductive pillars 140. Correspondingly, Fig.28 As shown, the method for preparing the circuit board frame may include the following step S50. Step S50 may be before step S32 and after step S40.

[0299] S50, forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, wherein at least one second conductive pillar is formed on one conductive block.

[0300] See also Fig.21 , can be based on Fig.18 The step diagram of the provided method for preparing a circuit board frame executes step S50.

[0301] Before step S50, the fourth dry film 924 (eg, Fig.18 shown).

[0302] Then, see Fig.21 , a fifth dry film 925 is formed on the side of the conductive frame away from the first dielectric layer 114, wherein the fifth dry film 925 can cover the fourth surface 122 of the conductive block 120 and fill the gap between two adjacent conductive blocks 120. At this time, the second portion 124 of the conductive block 120 is embedded in the fifth dry film 925. The second portion 124 is the portion of the conductive block 120 that is not covered by the first dielectric layer 114.

[0303] In step S50, first, refer to Fig. 22 The fifth dry film 925 may be patterned, and the patterned fifth dry film 925 may include a plurality of vias, wherein at least some of the vias in the fifth dry film 925 may expose a partial area of ​​the fourth surface 122 of the conductive block 120 .

[0304] Afterwards, see Fig.23, a second conductive column 140 is formed in the via hole corresponding to the conductive block 120 in the fifth dry film 925. The via hole corresponding to the conductive block 120 can expose the fourth surface 122 of the conductive block 120.

[0305] See also Fig.23 In some embodiments, in step 50, in the step of forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, a second sacrificial pillar 914 is simultaneously formed on a side of the sacrificial block 912 away from the first sacrificial pillar 913 .

[0306] See also Fig. 22 , part of the via holes in the fifth dry film 925 may expose a part of the surface of the sacrificial block 912 facing away from the first sacrificial pillar 913 .

[0307] See also Fig.23 , a second sacrificial column 914 may be formed in the via hole of the fifth dry film 925 exposing the sacrificial block 912 , and the second sacrificial column 914 may be connected to the sacrificial block 912 .

[0308] The cross-sectional area of ​​the second sacrificial column 914 is smaller than that of the sacrificial block 912 , wherein the cross-sectional area of ​​the second sacrificial column 914 is perpendicular to the thickness direction X of the frame substrate 110 , and the cross-sectional area of ​​the sacrificial block 912 is perpendicular to the thickness direction X of the frame substrate 110 .

[0309] The second conductive pillar 140 and the second sacrificial pillar 914 may both be made of Cu.

[0310] After the second conductive pillars 140 and the second sacrificial pillars 914 are formed, step S32 may be performed.

[0311] S32, forming a second dielectric layer, wherein the second dielectric layer covers a second portion of the conductive block, wherein the second portion is a portion of the conductive block away from the first conductive column.

[0312] See also Fig.24 Before step S32, the fifth dry film 925 (such as Fig.23 As shown), a second dielectric layer 115 is then formed on a side of the conductive base away from the first conductive column 130.

[0313] The second dielectric layer 115 may wrap the second portion 124 of the conductive block 120 and fill the gap between two adjacent conductive blocks 120 . At this time, it can also be understood that the second portion 124 is embedded in the second dielectric layer 115 .

[0314] In some examples, the material of the second dielectric layer 115 may be the same as the material of the first dielectric layer 114 , for example, the second dielectric layer 115 may be made of PP material.

[0315] See also Fig.24 , when the method for preparing the circuit board frame further includes step S50, that is, when the circuit board frame 100 further includes the second conductive pillar 140, in step S32, when the second dielectric layer is formed, the second dielectric layer 115 also covers a plurality of second conductive pillars 140, and the surfaces of the plurality of second conductive pillars away from the conductive block are exposed to the surface of the second dielectric layer 115 away from the first dielectric layer. At this time, it can be understood that the second conductive pillar 140 is embedded in the second dielectric layer 115. Among them, the surface of the second dielectric layer 115 away from the first dielectric layer is the second surface 112 of the frame substrate.

[0316] See also Fig.24 When the circuit board frame 100 further includes a support block 160 , in step S32 , when forming the second dielectric layer, the second dielectric layer 115 covers the fourth portion 162 of the support block 160 , wherein the fourth portion 162 is the portion of the support block 160 not covered by the first dielectric layer 114 .

[0317] The fourth portion 162 of the support block 160 may also be understood as the portion of the support block 160 excluding the third portion 161 .

[0318] See also Fig.24 In the case where the conductive base also includes a sacrificial block 912, when forming the second dielectric layer at S32, the second dielectric layer 115 covers the portion of the sacrificial block 912 that is not covered by the first dielectric layer 114. Part of the sacrificial block 912 is embedded in the first dielectric layer 114, and the other part is embedded in the second dielectric layer 115.

[0319] See also Fig.24 In the case where the second sacrificial pillar 914 is formed on the side of the sacrificial block 912 away from the first sacrificial pillar 913, when the second dielectric layer is formed in step S32, the second dielectric layer 115 covers the second sacrificial pillar 914, and the second dielectric layer 115 exposes the surface of the second sacrificial pillar 914 away from the sacrificial block 912. Part of the second sacrificial pillar 914 can be embedded in the first dielectric layer 114, and the other part of the second sacrificial pillar 914 can be embedded in the second dielectric layer 115.

[0320] See also Fig.26 After step S32, step S33 may be performed to remove part of the first dielectric layer, or to remove part of the first dielectric layer and part of the second dielectric layer to form a first device mounting space, and the retained first dielectric layer and the retained second dielectric layer form a frame substrate.

[0321] In some examples, in step S33 , a portion of the first dielectric layer 114 may be removed, and in this case, the first device mounting space 113 may be a mounting groove.

[0322] See also Fig.26 In other examples, in step S33, part of the first dielectric layer 114 and part of the second dielectric layer 115 may be removed. In this case, the first device mounting space 113 may be a mounting groove, or the first device mounting space 113 may be a hollow portion.

[0323] After step S33 , the remaining first dielectric layer 114 and the remaining second dielectric layer 115 may form the frame substrate 110 .

[0324] When the first sacrificial column 913 is formed, step S33, removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form a first device mounting space, includes: S331, removing the sacrificial block through the first sacrificial column, and removing part of the first dielectric layer located on the fifth surface of the sacrificial block, wherein the fifth surface is the surface of the sacrificial block connected to the first sacrificial column.

[0325] For example, in step S331, refer to Fig.25 A sixth dry film 926 can be formed on the surface of the first dielectric layer 114 facing away from the second dielectric layer 115, and the sixth dry film 926 can be patterned, wherein the patterned sixth dry film 926 includes a first notch, wherein the first notch can expose the first sacrificial column 913, and the projection of the sacrificial block 912 in the first direction F1 can completely overlap with the first notch.

[0326] A seventh dry film 927 is formed on the surface of the second dielectric layer 115 facing away from the first dielectric layer 114 . The seventh dry film 927 can protect the second dielectric layer 115 .

[0327] See also Fig.26 Then, the first sacrificial column 913 and the sacrificial block 912 and the fifth surface 9121 of the sacrificial block 912 are removed according to the patterned sixth dry film 926. At this time, the seventh dry film 927 can protect the sacrificial block 912, the second sacrificial column 914 and the second dielectric layer 115.

[0328] In summary, by forming the first sacrificial pillar 913 on the sacrificial block 912 , after removing the first sacrificial pillar 913 , the sacrificial block 912 may be exposed, and thus the sacrificial block 912 may be removed.

[0329] In addition, in step S331, the first dielectric layer 114 on the fifth surface 9121 of the sacrificial block 912 is also removed, and the first device mounting space 113 is formed after the first sacrificial pillar 913, the sacrificial block 912, and the first dielectric layer 114 on the fifth surface 9121 are removed. The formation of the sacrificial block 912 and the first sacrificial pillar 913 facilitates the formation of the first device mounting space.

[0330] In the case where a second sacrificial column 914 is formed on the surface of the sacrificial block 912 away from the first sacrificial column 913, S33, removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form a first device mounting space, including: S332, removing the sacrificial block through the first sacrificial column and the second sacrificial column, and removing part of the first dielectric on the fifth surface of the sacrificial block and part of the second dielectric layer on the sixth surface of the sacrificial block, wherein the fifth surface is the surface of the sacrificial block connected to the first sacrificial column, and the sixth surface is the surface of the sacrificial block connected to the second sacrificial column.

[0331] In step S332, please refer to Fig.25 , a sixth dry film 926 may be formed on a surface of the first dielectric layer 114 away from the second dielectric layer 115, and the sixth dry film 926 may be patterned. In addition, a seventh dry film 927 may be formed on a surface of the second dielectric layer 115 away from the first dielectric layer 114, and the seventh dry film 927 may be patterned. The patterned seventh dry film 927 may include a second notch, wherein the second notch may expose the second sacrificial column 914, wherein a projection of the sacrificial block 912 in the opposite direction of the first direction F1 may completely overlap with the second notch.

[0332] See also Fig.26 Then, the first sacrificial column 913 is removed according to the patterned sixth dry film 926, and the second sacrificial column 914 is removed according to the patterned seventh dry film 927. After the first sacrificial column 913 and the second sacrificial column 914 are removed, the sacrificial block 912 can be exposed, so that the first sacrificial column 913 can be removed according to the patterned sixth dry film 926 to remove the sacrificial block 912.

[0333] In some examples, two second sacrificial columns 914 are formed on a sacrificial block 912, and the two second sacrificial columns 914 are arranged opposite to each other in the second direction F2, wherein the surface of the first second sacrificial column 914 facing away from the second second sacrificial column 914 is flush with the first side surface 9123, and the surface of the second second sacrificial column 914 facing away from the first second sacrificial column 914 is flush with the second side surface 9124.

[0334] At this time, the second dielectric layer 115 located on the sixth surface 9122 may be located between the two second sacrificial pillars 914. In step S332, after the two second sacrificial pillars 914 and the sacrificial block 912 are removed, the second dielectric layer 115 located on the sixth surface 9122 may fall off automatically, so there is no need to remove the second dielectric layer 115 located on the sixth surface 9122 through an additional process, thereby simplifying the preparation process of the circuit board frame 100.

[0335] The first device mounting space 113 penetrating the frame substrate 110 can be formed by forming the first sacrificial column 913 on the fifth surface 9121 of the sacrificial block 912 and the second sacrificial column 914 on the sixth surface 9122 of the sacrificial block 912 .

[0336] Among them, Fig.26 In the provided embodiment, in step S332 , all of the sacrificial block 912 is removed, while in other embodiments, only a portion of the sacrificial block 912 may be removed.

[0337] Fig. 27 FIG. 4 is another structural diagram of a circuit board frame 100 according to some embodiments.

[0338] For example, Fig. 27 As shown, after a portion of the sacrificial block 912 is removed, the remaining sacrificial block 912 may be located at one or both sides of the first device mounting space 113 in the second direction F2 .

[0339] Part of the sacrificial block 912 is retained, and the retained sacrificial block 912 can support the circuit board frame 100, thereby improving the strength of the circuit board frame.

[0340] Fig.29 is another flow chart of a method for preparing a circuit board frame according to some embodiments; Figures 30 to 39 It is a structural diagram corresponding to each step of another method for preparing a circuit board frame according to some embodiments.

[0341] See also Fig.29 In some embodiments, S10, forming a plurality of conductive blocks includes: S01, forming a plurality of first conductive portions on a substrate.

[0342] See also Fig.30 In some examples, the substrate 930 may include a base layer 931 and a first metal layer 932 , a spacer metal layer 933 , and a second metal layer 934 sequentially stacked on the base layer 931 .

[0343] For example, the substrate layer 931 may be made of an insulating material, wherein the substrate layer 931 may support the first metal layer 932 , the spacer metal layer 933 , and the second metal layer 934 .

[0344] For example, the first metal layer 932 and the second metal layer 934 may both be made of Cu.

[0345] By way of example, the thickness of the first metal layer 932 may be 18 μm, and by way of example, the thickness of the second metal layer 934 may be 3 μm.

[0346] For example, the spacer metal layer 933 may be made of Ni (nickel).

[0347] In step S01, refer to Fig.31 A plurality of first conductive parts 125 may be formed on the second metal layer 934 of the substrate 930, wherein the first conductive parts 125 may be made of Cu. The plurality of first conductive parts 125 are arranged at intervals, so that the plurality of first conductive parts 125 are insulated from each other.

[0348] In some examples, a first metal layer 932, a spacer metal layer 933, and a second metal layer 934 are sequentially stacked on one side of the base layer 931. At this time, a plurality of first conductive portions 125 may be formed on one side of the substrate 930.

[0349] In some other examples, the first metal layer 932, the spacer metal layer 933 and the second metal layer 934 are sequentially stacked on the other side of the base layer 931. At this time, a plurality of first conductive parts 125 may also be formed on the other side of the substrate 930.

[0350] For example, the plurality of first conductive portions 125 may be arranged in sequence along the second direction F2.

[0351] In some embodiments, the method for preparing a circuit board frame may further include: step S03 , forming a plurality of first sacrificial portions on the substrate, wherein the first sacrificial portion is located between two adjacent first conductive portions 125 .

[0352] See also Fig.31 The number of the first sacrificial portion 951 may be one or more, for example, Fig.31 As shown, the number of the first sacrificial parts 951 may be 2. In the embodiment of the present application, the number of the first sacrificial parts 951 is not limited.

[0353] The plurality of first sacrificial portions 951 may be sequentially arranged along the second direction F2.

[0354] In the case where a plurality of first conductive portions 125 are disposed on both sides of the substrate 930 , first sacrificial portions 951 are also formed on both sides of the substrate 930 .

[0355] In some examples, step S03 and step S01 may be performed simultaneously, that is, the first sacrificial portion 951 and the first conductive portion 125 may be formed simultaneously.

[0356] S30, forming a frame substrate, including: S3.1, forming a third dielectric layer, the third dielectric layer is located on a side of the substrate where the first conductive parts are provided, and a plurality of first conductive parts are embedded in the third dielectric layer.

[0357] After step S01, step S3.1 may be performed.

[0358] See also Fig.32 In step S3.1, a third dielectric layer 116 may be formed on the second metal layer 934 of the substrate 930, wherein the third dielectric layer 116 may be made of PP material.

[0359] The third dielectric layer 116 may be formed on the second metal layer 934 by a lamination process.

[0360] In some examples, the third dielectric layer 116 may expose a surface of the first conductive portion 125 facing away from the substrate 930 .

[0361] See also Fig.32 In some other examples, the third dielectric layer 116 may also cover the surface of the first conductive portion 125 facing away from the substrate 930 .

[0362] In the case where the first conductive portion 125 is disposed on both sides of the substrate 930 , the third dielectric layer 116 may be formed on both sides of the substrate 930 .

[0363] When the method for preparing the circuit board frame further includes step S03 , the first sacrificial portion 951 is also embedded in the third dielectric layer 116 .

[0364] The method for preparing the circuit board frame further includes: the following steps S60 and S70, wherein steps S60 and S70 can be formed after step S3.1.

[0365] S60: removing the substrate.

[0366] See also Fig.33 In step S60, when removing the substrate 930, part of the film layer of the substrate 930 may be removed, or the entire film layer of the substrate 930 may be removed.

[0367] In step S60, the substrate layer 931 and the first metal layer 932 on the substrate layer 931 may be peeled off first, and one side of the third dielectric layer 116 is covered with the spacer metal layer 933 and the second metal layer 934. At this time, the third dielectric layers 116 on both sides of the substrate 930 are independent of each other.

[0368] See also Fig.34 , then the spacing metal layer 933 can be removed. Fig.34 In the embodiment of the present application, a third dielectric layer 116 and a plurality of first conductive parts 125 embedded in the third dielectric layer 116 are taken as an example to introduce the preparation process of the circuit board frame provided in the embodiment of the present application.

[0369] In some examples, the second metal layer 934 may be retained, in which case a portion of the film layer of the substrate 930 is removed.

[0370] In some other examples, the second metal layer 934 may also be removed, in which case all the film layers of the second metal layer 934 are removed. It should be noted that, at this time, one surface of the first conductive portion 125 is exposed to one surface of the third dielectric layer 116 .

[0371] S70, forming a conductive film layer, which is located on one side of the third dielectric layer and contacts the plurality of first conductive parts. The conductive film layer includes a first conductive part and a second conductive part connected to each other, the first conductive part overlaps the first conductive part, and the second conductive part serves as a wire layer.

[0372] See also Fig.35 In some examples, in step S60, the second metal layer 934 (eg Fig.34 As shown) can be retained, at this time, a Cu layer can be deposited on the second metal layer 934, and then part of the second metal layer 934 and part of the Cu layer are removed. At this time, the retained Cu layer and the retained second metal layer 934 can form a conductive film layer 940.

[0373] In some other examples, in step S60, the second metal layer 934 may be removed, and a Cu layer may be formed on one side of the third dielectric layer 116, and then the Cu layer may be etched, and the remaining Cu layer may be used as the conductive film layer 940. In this example, the Cu layer may directly contact the surface of the first conductive portion 125 exposed to the third dielectric layer 116.

[0374] The conductive film layer 940 may include a first conductive portion, and a projection of the first conductive portion in the third direction F3 overlaps with a projection of the first conductive portion 125 in the third direction F3.

[0375] The conductive film layer 940 includes a second conductive portion, and the second conductive portion can be used as a wire layer 150, and the projection of the wire layer 150 in the third direction F3 does not overlap with the projection of the first conductive portion 125 in the third direction F3. Fig.35 As shown, the direction indicated by arrow F3 is the third direction. The plurality of first conductive parts 125 and the conductive film layer 940 are sequentially arranged along the third direction F3.

[0376] When the method for preparing the circuit board frame also includes step S03, part of the conductive film layer 940 formed in step S70 also covers the surface of the first sacrificial part 951, wherein the edge of the conductive film layer 940 covering the first sacrificial part 951 can overlap with the edge of the first sacrificial part 951.

[0377] S10, forming a plurality of conductive blocks, further comprising: S02, forming a plurality of second conductive portions on a side of the conductive film layer away from the third dielectric layer, the second conductive portions overlapping the first conductive portions.

[0378] Wherein, step S02 may be performed after step S70.

[0379] See also Fig.36 The plurality of second conductive portions 126 may be located on a side of the conductive film layer 940 away from the third dielectric layer 116 , and the plurality of second conductive portions 126 are in contact with the first conductive portion of the conductive film layer 940 .

[0380] A conductive block 120 may include a first conductive portion 125 , a second conductive portion 126 , and a first conductive part located between the first conductive portion 125 and the second conductive portion 126 .

[0381] When the method for preparing the circuit board frame further includes step S03 , the conductive film layer 940 may further include a third conductive portion.

[0382] The method for preparing the circuit board frame may further include step S04, forming a second sacrificial portion, wherein the second sacrificial portion overlaps with the third conductive portion, wherein a second sacrificial portion, a first sacrificial portion and a third conductive portion located between the first sacrificial portion and the second sacrificial portion may form a sacrificial block 912.

[0383] One second sacrificial portion 952 corresponds to one first sacrificial portion 951 , and the projections of the first sacrificial portion 951 and the second sacrificial portion 952 corresponding to each other in the third direction F3 overlap.

[0384] The first sacrificial portion 951 and the second sacrificial portion 952 corresponding to each other, and the third conductive portion located between the first sacrificial portion 951 and the second sacrificial portion 952 corresponding to each other may form one sacrificial block 912 .

[0385] In some examples, step S04 and step S02 may be performed simultaneously, that is, the second sacrificial portion 952 and the second conductive portion 126 may be formed simultaneously.

[0386] S20, forming a plurality of first conductive pillars on one side of the plurality of conductive blocks, comprising:

[0387] S2.1. Form a plurality of first conductive pillars on a side of the second conductive portion of the plurality of conductive blocks away from the first conductive portion.

[0388] See also Fig.37 In step S2.1, at least one first conductive column 130 may be formed on the second conductive portion 126 of a conductive block 120 .

[0389] When the method for preparing the circuit board frame further includes steps S03 and S04, the method for preparing the circuit board frame may further include step S2.2, forming a third sacrificial column on a side of the second sacrificial portion away from the first sacrificial portion.

[0390] See also Fig.32 At least one third sacrificial column 953 may be formed on a second sacrificial portion 952 .

[0391] The third sacrificial pillar 953 , the second sacrificial portion 952 , the first sacrificial portion 951 and the conductive film layer 940 may be made of the same material, for example, all of them are made of Cu.

[0392] S30, forming a frame substrate, may also include: the following steps S3.2 and S3.3.

[0393] S3.2, forming a fourth dielectric layer, the fourth dielectric layer is located on one side of the third dielectric layer, and the conductive film layer, the plurality of second conductive parts and the plurality of first conductive pillars are embedded in the fourth dielectric layer, and the fourth dielectric layer exposes the surface of the first conductive pillar away from the conductive block.

[0394] See also Fig.38 The surface of the first conductive pillar 130 facing away from the conductive block 120 is exposed to the surface of the fourth dielectric layer 117 facing away from the third dielectric layer 116 .

[0395] For example, the fourth dielectric layer 117 may be made of PP material.

[0396] For example, the fourth dielectric layer 117 may be formed by a lamination process.

[0397] In the case where the method for preparing the circuit board frame further includes steps S03, S04 and S2.2, the second sacrificial portion 952 and the third sacrificial pillar 953 are both embedded in the fourth dielectric layer 117, and the surface of the third sacrificial pillar 953 away from the second sacrificial portion 952 is exposed to the surface of the fourth dielectric layer 117 away from the third dielectric layer 116. By forming the third sacrificial pillar 953 on the second sacrificial portion 952, the sacrificial block 912 can be easily removed.

[0398] S3.3. Remove part of the fourth dielectric layer to form a first device installation space; or remove part of the fourth dielectric layer and part of the third dielectric layer to form a first device installation space; wherein the retained third dielectric layer and the retained fourth dielectric layer form a frame substrate.

[0399] See also Fig.39 When part of the fourth dielectric layer 117 is removed, the first device mounting space 113 may be a mounting groove.

[0400] When part of the fourth dielectric layer 117 and part of the third dielectric layer 116 are removed, the first device mounting space 113 may be a mounting groove or a hollow portion. When the first device mounting space 113 is a hollow portion, the first device mounting space 113 may penetrate the frame substrate 110 .

[0401] The surface of the fourth dielectric layer 117 facing away from the third dielectric layer 116 is the first surface 111 of the frame substrate 110 .

[0402] In the case where the method for preparing the circuit board frame further includes steps S03, S04 and S2.2, step S3.3 may include the following step S3.31, removing the sacrificial block through the third sacrificial column to form a first device mounting space.

[0403] Among them, in step S03 and step S04, two sacrificial blocks 912 can be formed. In step S3.31, the two sacrificial blocks 912 can be removed through the third sacrificial columns 953 on the two sacrificial blocks 912, and the third dielectric layer 116 and the fourth dielectric layer 117 between the two sacrificial blocks 912 can be removed to form a first device installation space 113.

[0404] The embodiment of the present application also provides a method for preparing an embedded packaging substrate.

[0405] Fig.40 is another flow chart of a method for preparing an embedded package substrate according to some embodiments; Figure 41 to Figure 44 It is a structural diagram corresponding to each step of another method for preparing an embedded package substrate according to some embodiments.

[0406] See also Fig.40 The method for preparing the embedded package substrate includes: the following steps S100, S210, and S310.

[0407] S100, placing a first electronic component in a first component installation space of a frame substrate of a circuit board frame.

[0408] S210, forming a first routing layer on a first surface of the frame substrate, wherein the first routing layer contacts a plurality of first conductive pillars of the circuit board frame, and the first routing layer contacts a first electronic device.

[0409] See also Fig.41 After step S100 , the method for preparing an embedded package substrate may further include: forming a filling portion in the first device installation space, wherein the first electronic device is embedded in the charging portion. The filling portion 200 fixes the first electronic device 300 in the first device installation space 113 .

[0410] In step S210, the first routing layer 410 can be directly formed on the first surface 111 of the frame substrate 110, and the first electronic device 300 can be electrically connected to the first conductive column 130 through the first routing layer 410 and the first conductive column 130, so that the first conductive column 130 can be used to transmit the signal received or output by the first electronic device 300.

[0411] The first routing layer 410 can be directly formed on the first surface 111 of the frame substrate 110. Therefore, there is no need to form other insulating layers on the first surface 111 before forming the first routing layer 410, and there is no need to form vias in the "other insulating layers" and to form via connection portions in the vias for connecting the first routing layer 410 and the conductive blocks 120, thereby reducing the cost of the embedded packaging substrate 1000.

[0412] S310, forming a fourth insulating layer, wherein the fourth insulating layer covers the first surface and a surface of the first wiring layer away from the frame substrate, wherein the fourth insulating layer further comprises a plurality of vias, and the plurality of vias in the fourth insulating layer expose the first wiring layer.

[0413] For examples, see Fig.42 In step S310, the fourth insulating layer 810 can be made of PP material.

[0414] For example, a PP film layer is formed on the side of the first wiring layer 410 away from the frame substrate 110 , and the PP film layer is etched to form via holes, wherein the PP film layer provided with a plurality of via holes is the fourth insulating layer 810 .

[0415] The PP film layer may be formed on the first wiring layer 410 and the first surface 111 by a lamination process.

[0416] S410 , forming first connecting portions in a plurality of via holes in a fourth insulating layer.

[0417] See also Fig.43 , the first connection portion 620 formed in step S400 may be connected to the first routing layer 410 .

[0418] S510, forming a plurality of first pads on a surface of the fourth insulating layer facing away from the frame substrate, wherein the plurality of first pads are connected to first connecting portions formed in a plurality of via holes in the fourth insulating layer.

[0419] See also Fig.44 , one first pad 610 contacts one first connection portion 620 .

[0420] S610, forming a first protective layer, the first protective layer covering the surface of the fourth insulating layer away from the frame substrate and the surface of the first pad away from the frame substrate, the first protective layer comprising a plurality of first pad openings, the first pad openings exposing the first pads.

[0421] See you later Figure 3 , the first protection layer 710 is made of insulating material.

[0422] In some embodiments, the method for preparing the embedded package substrate further includes step S220, forming a second wiring layer on the second surface of the frame substrate, wherein the second wiring layer is in contact with a plurality of second conductive pillars of the circuit board frame.

[0423] Among them, in step S220, the second routing layer 430 can be directly formed on the second surface 112 of the frame substrate 110. Therefore, there is no need to form other insulating layers on the second surface 112 before forming the second routing layer 430, and there is no need to form vias in the "other insulating layers", and to form via connection parts in the vias for connecting the second routing layer 430 and the conductive blocks 120, thereby reducing the cost of the embedded packaging substrate 1000.

[0424] S320, forming a fifth insulating layer, wherein the fifth insulating layer covers the second surface and the surface of the second wiring layer facing away from the frame substrate, wherein the fifth insulating layer further comprises a plurality of vias, and the plurality of vias in the fifth insulating layer expose the second wiring layer.

[0425] For examples, see Fig.42 In step S320, the fifth insulating layer can be made of PP material.

[0426] For example, another PP film layer is formed on the side of the second wiring layer 430 away from the frame substrate 110 , and the PP film layer is etched to form via holes, wherein the PP film layer provided with a plurality of via holes is the fifth insulating layer 820 .

[0427] The PP film layer may be formed on the second wiring layer 430 and the second surface 112 by a lamination process.

[0428] S420 , forming second connection portions in a plurality of via holes in the fifth insulating layer.

[0429] The second connection portion 640 formed in step S420 may be connected to the second routing layer 430 .

[0430] S520, forming a plurality of second pads on a surface of the fifth insulating layer facing away from the frame substrate, wherein the plurality of pads are in contact with second connection portions formed in a plurality of via holes in the fifth insulating layer.

[0431] See also Fig.44 , a second pad 630 contacts a second connection portion 640 .

[0432] S620, forming a second protective layer, the second protective layer covering the surface of the fifth insulating layer away from the frame substrate and the surface of the second pad away from the frame substrate, the second protective layer comprising a plurality of second pad openings, the second pad openings exposing the second pads.

[0433] See you later Figure 3 , the second protection layer 720 is made of insulating material.

[0434] In the method for preparing the embedded package substrate provided in some of the above embodiments, the circuit board frame used in step S100 is Figure 4 The circuit board frame 100 is provided.

[0435] In some embodiments, the method for preparing an embedded package substrate may include the following steps S0.01 and S0.02. Fig.45 and Fig.46 The figure is a structural diagram corresponding to the steps of another method for preparing an embedded package substrate according to some embodiments.

[0436] S0.01. Remove the first conductive column on at least one conductive block and the frame substrate on the first surface of the conductive block to form a second device mounting space.

[0437] See also Fig.45 , can be based on Fig.18 and Fig.24 The provided circuit board frame 100 performs step S0.01. Fig.45 In Fig.18 The structure of the circuit board frame 100 is provided to illustrate the method for preparing the embedded package substrate.

[0438] Here, a depth of the second device mounting space 118 in the first direction F1 may be smaller than a depth of the first device mounting space 113 in the first direction F3 .

[0439] The second device installation space 118 may be used to install a second electronic device.

[0440] S0.02. Install a second electronic component in the second component installation space, and form a second filling portion in the second component installation space.

[0441] See also Fig.46 The second filling portion 303 can fix the second electronic device 301 , wherein the pins 302 of the second electronic device 301 can be flush with the first surface 111 .

[0442] The conductive block 120 can support the second electronic device 301 , thereby improving the support strength of the second electronic device 301 .

[0443] Fig.47 is another structural diagram of an embedded package substrate according to some embodiments.

[0444] In other embodiments, see Fig.47 In step S0.01, at least part of the conductive block 120 may be removed. For example, the thickness of the removed conductive block 120 may be adjusted to control the depth of the second device installation space 118 in the first direction F1, so that the second device installation space 118 can match the second electronic devices 301 of different thicknesses. Fig.47 The embodiment of the present application is illustrated by taking the entirety of one conductive block 120 as an example.

[0445] Fig.48 FIG. 4 is another structural diagram of an embedded package substrate according to some embodiments.

[0446] See also Fig.48 In some other embodiments, the circuit board frame 100 may further include a connecting rib 911, wherein the connecting rib 911 has been introduced in some of the above embodiments and will not be described in detail here. In the case where the circuit board frame 100 further includes the connecting rib 911, the connecting rib 911 may not be removed in the preparation method of the circuit board frame.

[0447] In some embodiments, the method for preparing the embedded package substrate may include the following steps S0.03 and S0.04. Fig.49 and Fig.50 The figure is a structural diagram corresponding to the steps of another method for preparing an embedded package substrate according to some embodiments.

[0448] S0.03. Remove the second conductive column on at least one conductive block and the frame substrate on the second surface of the conductive block to form a third device installation space.

[0449] See also Fig.49 , can be based on Fig.24The provided circuit board frame 100 performs step S0.03. The depth of the third device mounting space 119 in the first direction F1 may be smaller than the depth of the first device mounting space 113 in the first direction F3.

[0450] The third device installation space 119 may be used to install a third electronic device.

[0451] In some embodiments, in step S0.02, at least a portion of the conductive block 120 may be removed, thereby increasing the depth of the third device mounting space 119.

[0452] In some examples, a third device mounting space 119 and a second device mounting space 118 are respectively disposed at two sides of one conductive block 120 in the first direction F1 .

[0453] S0.04. Install a third electronic component in the third component installation space, and form a third filling portion in the third component installation space.

[0454] See also Fig.50 The third filling portion 306 can fix the third electronic device 304 , wherein the pins 305 of the third electronic device 304 can be flush with the second surface 112 .

[0455] The conductive block 120 can support the third electronic device 304 , thereby improving the support strength of the third electronic device 304 .

[0456] For example, the thickness of the removed conductive block 120 may be adjusted according to the thickness of the third electronic device 304 , so that the depth of the third device mounting space 119 can be adapted to the third electronic devices 304 of different thicknesses.

[0457] Fig.51 FIG. 4 is another structural diagram of an embedded package substrate according to some embodiments.

[0458] See also Fig.51 In some other embodiments, the above steps S0.03 and S0.04 can be performed based on a circuit board frame 100 that also includes connecting ribs 911.

[0459] Fig.52 is another structural diagram of an embedded package substrate according to some embodiments.

[0460] See also Fig.52In other embodiments, the above steps S0.01, S0.02, S0.03 and S0.04 can be performed based on the circuit board frame 100 in which part of the sacrificial block 912 can be retained. In this case, the retained sacrificial block 912 can be located on one side or both sides of the first device mounting space 113 in the second direction F2. In this case, the structure of the embedded package substrate 1000 can be as follows: Fig.52 shown.

[0461] In this example, the embedded package substrate 1000 may also include a connecting rib 911 .

[0462] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A circuit board frame, characterized in that: include: A frame substrate, a plurality of first conductive pillars and a plurality of conductive blocks, wherein the frame substrate comprises a first surface; The plurality of first conductive pillars and the plurality of conductive blocks are embedded in the frame substrate, the plurality of conductive blocks are arranged at intervals, one conductive block is in contact with at least one first conductive pillar, and the surfaces of the plurality of first conductive pillars facing away from the plurality of conductive blocks are exposed to the first surface; The frame substrate further includes a first device installation space, and a first opening of the first device installation space is located on the first surface.

2. The circuit board frame according to claim 1, characterized in that: The conductive blocks and the first conductive pillars in contact are arranged along a first direction, and the first direction is perpendicular to the first surface; A ratio of a thickness of the conductive block in the first direction to a thickness of the first conductive column in the first direction is greater than or equal to 6.2 and less than or equal to 12.

34.

3. The circuit board frame according to claim 1 or 2, characterized in that: The conductive block and the first conductive column in contact are arranged along a first direction, and the conductive block includes a third surface and a fourth surface arranged opposite to each other in the first direction; The circuit board frame further includes: a conductor layer, the conductor layer is embedded in the frame substrate, the conductor layer is connected to the side of the conductive block, wherein the conductor layer is located between the plane where the third surface is located and the plane where the fourth surface is located.

4. The circuit board frame according to claim 3, characterized in that: There are multiple wire layers, and the multiple wire layers are arranged at intervals on the side of the conductive block along the first direction.

5. The circuit board frame according to any one of claims 1 to 4, characterized in that: The frame substrate further includes a second surface disposed opposite to the first surface; The circuit board frame also includes: a plurality of second conductive pillars, the plurality of second conductive pillars are embedded in the frame substrate, a conductive block faces away from the first conductive pillar and contacts at least one second conductive pillar, and the plurality of second conductive pillars face away from the conductive block and are exposed to the second surface.

6. The circuit board frame according to any one of claims 1 to 5, characterized in that: The frame substrate further includes a second surface disposed opposite to the first surface; The circuit board frame further includes: a support block, which is embedded in the frame substrate and spaced apart from the conductive block; two surfaces of the support block that are opposite to each other in a first direction are covered by the frame substrate.

7. The circuit board frame according to any one of claims 1 to 6, characterized in that: The frame substrate further includes a second surface disposed opposite to the first surface; The first device mounting space further includes a second opening, and the second opening is located on the second surface.

8. An embedded packaging substrate, characterized in that: include: A circuit board frame as claimed in any one of claims 1 to 7; A first electronic device is located in a first device installation space of a frame substrate of the circuit board frame; A first routing layer, wherein the first routing layer is located on the first surface of the frame substrate, the first routing layer is in contact with a plurality of first conductive columns of the circuit board frame, and the first routing layer is in contact with the first electronic device.

9. The embedded package substrate according to claim 8, characterized in that: In the case where the frame substrate further includes a second surface disposed opposite to the first surface; and the circuit board frame further includes: a plurality of second conductive pillars, a surface of a conductive block facing away from the first conductive pillar is in contact with at least one second conductive pillar, and a surface of the plurality of second conductive pillars facing away from the conductive block is exposed to the second surface: The embedded packaging substrate further includes: a second routing layer, the second routing layer is located on a side of the plurality of second conductive blocks of the circuit board frame away from the plurality of second conductive pillars, and the second routing layer is in contact with the plurality of second conductive pillars.

10. An electronic device, characterized in that: include: The embedded packaging substrate as claimed in claim 8 or 9; A first functional element is electrically connected to a first wiring layer of the embedded package substrate.

11. A method for preparing a circuit board frame, characterized in that: include: forming a plurality of conductive blocks, wherein the plurality of conductive blocks are arranged at intervals; forming a plurality of first conductive pillars on one side of the plurality of conductive blocks, wherein at least one first conductive pillar contact is disposed on one side of one conductive block; A frame substrate is formed, wherein the frame substrate covers a plurality of conductive blocks and the plurality of first conductive pillars, the frame substrate includes a first surface, surfaces of the plurality of first conductive pillars facing away from the plurality of conductive blocks are exposed to the first surface, and the frame substrate also includes a first device mounting space, wherein a first opening of the first device mounting space is located on the first surface.

12. The method for preparing a circuit board frame according to claim 11, characterized in that: The forming of the frame substrate comprises: forming a first dielectric layer, wherein the first dielectric layer covers first portions of the plurality of conductive blocks and the plurality of first conductive pillars, the first dielectric layer includes the first surface, and the first portion is a portion of the conductive block close to the first conductive pillar; forming a second dielectric layer, wherein the second dielectric layer covers a second portion of the plurality of conductive blocks, wherein the second portion is a portion of the conductive block that is not covered by the first dielectric layer; A portion of the first dielectric layer is removed, or a portion of the first dielectric layer and a portion of the second dielectric layer are removed to form the first device mounting space, and the remaining first dielectric layer and the remaining second dielectric layer form the frame substrate.

13. The method for preparing a circuit board frame according to claim 12, characterized in that: Before forming the second dielectric layer, the method further comprises: forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, wherein at least one second conductive pillar is formed on one conductive block; When forming the second dielectric layer, the second dielectric layer further covers the plurality of second conductive pillars, and surfaces of the plurality of second conductive pillars facing away from the conductive block are exposed to a surface of the second dielectric layer facing away from the first dielectric layer.

14. The method for preparing a circuit board frame according to claim 12 or 13, characterized in that: The forming of the plurality of conductive blocks comprises: etching a target area of ​​a conductive substrate to thin the target area to form a connecting rib, and forming the conductive block in a portion other than the target area, wherein the connecting rib connects two conductive blocks; Before forming the second dielectric layer, the method further comprises: The connecting ribs are removed.

15. The method for preparing a circuit board frame according to any one of claims 12 to 14, characterized in that: In the step of forming a plurality of conductive blocks, a supporting block is formed simultaneously; the supporting block and the conductive block are arranged in the same layer, and the supporting block and the conductive block are arranged at intervals.

16. The method for preparing a circuit board frame according to any one of claims 12 to 15, characterized in that: In the step of forming a plurality of conductive blocks, a sacrificial block is formed simultaneously, wherein the sacrificial block is spaced apart from the conductive blocks and is located between two adjacent conductive blocks; In the step of forming a plurality of first conductive pillars on one side of the plurality of conductive blocks, a first sacrificial pillar is formed simultaneously, wherein the direction in which the sacrificial block points to the first sacrificial pillar is the same as the direction in which the conductive block points to the first conductive pillar; The removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form the first device mounting space includes: The sacrificial block is removed through the first sacrificial column, and a portion of the first dielectric layer located on a fifth surface of the sacrificial block is removed, wherein the fifth surface is a surface of the sacrificial block connected to the first sacrificial column.

17. The method for preparing a circuit board frame according to claim 16, characterized in that: In the step of forming a plurality of second conductive pillars on a side of the plurality of conductive blocks away from the plurality of first conductive pillars, a second sacrificial pillar is simultaneously formed on a side of the sacrificial block away from the first sacrificial pillars; The removing part of the first dielectric layer, or removing part of the first dielectric layer and part of the second dielectric layer to form the first device mounting space includes: The sacrificial block is removed through the first sacrificial column and the second sacrificial column, and a portion of the first medium located on the fifth surface of the sacrificial block and a portion of the second medium layer located on the sixth surface of the sacrificial block are removed, wherein the fifth surface is a surface of the sacrificial block connected to the first sacrificial column, and the sixth surface is a surface of the sacrificial block connected to the second sacrificial column.

18. The method for preparing a circuit board frame according to claim 11, characterized in that: The forming of a plurality of conductive blocks comprises: forming a plurality of first conductive portions on a substrate; The forming of the frame substrate comprises: forming a third dielectric layer, wherein the third dielectric layer is located at a side of the substrate where the first conductive part is provided, and the plurality of first conductive parts are embedded in the third dielectric layer; The method for preparing the circuit board frame further includes: removing the substrate; forming a conductive film layer, the conductive film layer being located on one side of the third dielectric layer and in contact with the plurality of first conductive portions, the conductive film layer comprising a first conductive portion and a second conductive portion connected to each other, the first conductive portion overlapping the first conductive portion, and the second conductive portion serving as a wire layer; The forming of a plurality of conductive blocks further comprises: forming a plurality of second conductive portions on a side of the conductive film layer away from the third dielectric layer, wherein the second conductive portions overlap with the first conductive portions; The forming of a plurality of first conductive pillars on one side of the plurality of conductive blocks comprises: forming a plurality of first conductive pillars on a side of the second conductive portion of the plurality of conductive blocks away from the first conductive portion; The forming of the frame substrate further comprises: forming a fourth dielectric layer, wherein the fourth dielectric layer is located on one side of the third dielectric layer, and the conductive film layer, the plurality of second conductive portions and the plurality of first conductive pillars are embedded in the fourth dielectric layer, and the fourth dielectric layer exposes a surface of the first conductive pillar away from the conductive block; A portion of the fourth dielectric layer is removed, or a portion of the fourth dielectric layer and a portion of the third dielectric layer are removed, and the remaining third dielectric layer and the remaining fourth dielectric layer form the frame substrate.

19. A method for preparing an embedded packaging substrate, characterized in that: Placing a first electronic device in a first device mounting space of a frame substrate of a circuit board frame as described in any one of claims 1 to 7; A first wiring layer is formed on the first surface of the frame substrate, wherein the first wiring layer is in contact with a plurality of first conductive pillars of the circuit board frame, and the first wiring layer is in contact with the first electronic device.

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