Interconnection via hole structure for improving wafer level packaging interconnection density

Abstract

The invention discloses an interconnection via hole structure for improving wafer level packaging interconnection density, which comprises a via hole and a bonding pad, and is characterized in that in the cross section of the via hole, the length in the normal direction is greater than the length in the transverse direction; the bonding pad and the via hole are arranged and assembled in a profiling manner, and the bonding pad is connected between the via hole and the circuit in the layer; the minimum distance (D) between the edge of the bonding pad and the via hole is 2-10 [mu] m; by changing the shape of the cross section of the via hole, the normal length is greater than the transverse length, so that the size in the transverse direction can be effectively reduced under the condition that the cross section area of the via hole is not reduced, namely the exposure area during forming of the via hole is not reduced and the requirement of the current process on the development area is met; therefore, more wiring space is reserved in the effective space, and the improvement of the wiring density of the circuit is greatly facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to an interconnection via structure for improving the interconnection density of wafer-level packaging. Background Art

[0002] As the industry develops, the integration density of packages continues to increase, and the circuits and devices within the package become increasingly dense, which in turn reduces the available wiring space. Vias are connected to the circuits within the layer through redistribution pads. Vias serve as interconnects between layers within the package. This via-pad structure plays a vital role in transmitting electrical signals between layers.

[0003] Further improving the packaging integration density has become an important direction for the development of the industry. In the existing technology, due to the limitation of process capability, the size of circular vias in existing wafer-level packaging ranges from a few microns to tens of microns, and the distance between the pad and the edge of the via is usually 2 to 10 microns, while the wiring width of modern wafer-level packaging is only a few microns. Therefore, compared with the line width, the existing via size is larger, such as Figure 1 As shown in , L1 reaches 20μm. However, if the via size is directly reduced, the exposure area will be too small to meet the current process requirements for the development area, limiting the further improvement of the interconnection density within the package. Summary of the Invention

[0004] To solve the above problems, the present invention provides a rationally structured interconnect via structure for improving the interconnect density of wafer-level packaging, thereby leaving more wiring space in the effective space, greatly contributing to improving the line wiring density.

[0005] The technical solutions adopted in the present invention are as follows:

[0006] An interconnect via structure for improving the interconnect density of wafer-level packaging includes a via and a pad. In the cross section of the via, the length in the normal direction is greater than the length in the lateral direction. The pad is arranged and assembled with the via in a contoured manner, and the pad is connected between the via and a circuit within a layer.

[0007] As a further improvement of the above technical solution:

[0008] The cross-sectional shape of the via hole includes but is not limited to an ellipse, a circular groove, an octagon, a hexagon, and a rounded prism.

[0009] A single via is composed of a conductive material and an insulating material. The insulating material fills the hole in the center of the via, and the conductive material covers the circumference of the hole. The via is connected to the pad by the conductive material.

[0010] The conductive material is a conductor, including but not limited to copper, silver, gold, and tin.

[0011] The insulating material includes but is not limited to photoresist and resin.

[0012] The material of the pad is consistent with the conductive material in the via hole.

[0013] The ratio of the length of the via hole in the transverse direction to the length in the normal direction is 0.75-0.9.

[0014] The longitudinal cross section of the via hole in the longitudinal direction is a tapered structure that is larger at the top and smaller at the bottom, and pads of the same shape are respectively provided at both ends of the via hole.

[0015] The circuit includes a plurality of circuits arranged in parallel, and the plurality of circuits are arranged at intervals along the transverse direction; the length direction of the circuit is in the normal direction.

[0016] The minimum distance (D) between the edge of the pad and the via hole is 2-10 μm.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention changes the cross-sectional shape of the via so that the normal length is greater than the lateral length. This allows the size in the lateral direction to be effectively reduced without reducing the cross-sectional area of ​​the via, that is, without reducing the exposure area during via formation, while meeting the current process requirements for the development area. This leaves more wiring space in the effective space, greatly contributing to improving the line wiring density and matching the wiring width in modern wafer-level packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the existing vias and solder tabs.

[0020] Figure 2 This is a schematic diagram of the via and pad assembly of the present invention.

[0021] Figure 3 This is a cross-sectional view of the via hole and pad assembly of the present invention.

[0022] Figure 4 Schematic diagram of the shape of the via hole of the present invention.

[0023] Among them: 1. Circuit; 2. Pad; 3. Via. DETAILED DESCRIPTION

[0024] The specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0025] like Figure 2 and Figure 3As shown, an interconnection via structure for improving the interconnection density of wafer-level packaging in this embodiment includes a via 3 and a pad 2. In the cross section of the via 3, the length in the normal direction is greater than the length in the lateral direction; the pad 2 and the via 3 are arranged and assembled in a contoured manner, and the pad 2 is connected between the via 3 and the circuit 1 in the layer.

[0026] In this embodiment, by changing the cross-sectional shape of the via 3 so that the normal length is greater than the lateral length, the cross-sectional area of ​​the via 3 is not reduced, that is, the exposure area when the via 3 is formed is not reduced. While meeting the current process requirements for the development area, the size in the lateral direction can be effectively reduced, thereby leaving more wiring space in the effective space, which can match the wiring width in modern wafer-level packaging.

[0027] The via hole 3 in this embodiment can meet and facilitate the implementation and requirements of the development process.

[0028] In this embodiment, the pads 2 serve as the interconnection between the circuits 1 within a layer and the vias 3 , while the vias 3 serve as the interconnection between the pads 2 between adjacent layers.

[0029] like Figure 4 As shown, the cross-sectional shape of the via hole 3 includes but is not limited to an ellipse, a circular groove, an octagon, a hexagon, and a rounded prism.

[0030] In this embodiment, in actual implementation, the via 3 and the pad 2 adopt the same cross-sectional shape. The via 3 and the pad 2 can both be one of elliptical, circular groove, octagonal, hexagonal, and rounded prism-shaped. Their lateral length can be appropriately reduced, while their normal length can be increased.

[0031] A single via 3 is composed of conductive material and insulating material. The insulating material fills the hole in the center of the via 3, and the conductive material covers the circumference of the hole. The via 3 is connected to the pad 2 by the conductive material to achieve interconnection between layers and transmit electrical signals.

[0032] The conductive material is a conductor, including but not limited to copper, silver, gold, and tin.

[0033] Insulating materials include but are not limited to photoresist and resin.

[0034] In this embodiment, the conductive material or the insulating material in the via hole 3 can be selected according to actual packaging requirements.

[0035] The material of the pad 2 is consistent with the conductive material in the via 3, effectively ensuring the interconnection effect.

[0036] The ratio of the length of the via 3 in the lateral direction to the length in the normal direction is 0.75-0.9, which can effectively meet the existing development process while reasonably and effectively improving the wiring density.

[0037] The longitudinal cross-section of the via hole 3 in the longitudinal direction is a tapered structure that is larger at the top and smaller at the bottom. Both ends of the via hole 3 are respectively provided with pads 2 of the same shape.

[0038] The line 1 includes a plurality of lines arranged in parallel, and the plurality of lines 1 are arranged at intervals along the transverse direction; the length direction of the line 1 is in the normal direction.

[0039] The minimum distance (D) between the edge of the pad 2 and the via 3 is 2-10 μm.

[0040] In this embodiment, wafer-level packaging, especially advanced packaging, is specifically considered and set, taking into account that the interconnection area between chips has a high line density and the lines have strong directionality; for example, the high-density interconnection area within the package is usually parallel lines, and the space in the direction perpendicular to the lines is more compact, while the space in the direction parallel to the lines is relatively loose.

[0041] In this embodiment, by modifying the shape of the via 3, the size of the via 3 in the direction parallel to the line 2 can be appropriately increased while the exposure area remains unchanged or even larger, so that the wiring space occupied by the via 3 in the direction perpendicular to the line 2 is reduced, thereby effectively saving valuable wiring space in the high-density interconnection area within the package without excessively increasing the process cost.

[0042] In this embodiment, the process flow for manufacturing the via 3 is as follows:

[0043] Step 1: Coating: A layer of photoresist is applied to the target substrate. The target substrate includes but is not limited to silicon wafers, PCBs, passivation layers, redistribution layers, and other functional layers or passivation layers that appear in semiconductor process flows.

[0044] Step 2: Exposure: Place the target substrate coated with photoresist into the photolithography machine for exposure, so that the photoresist in the non-via opening area is solidified and the soluble area in the via opening area is retained. During exposure, a mask with a corresponding pattern is used to make the via opening shape into a preset shape, such as Figure 2 The octagon shown in .

[0045] Step 3: Development: The exposed target substrate is taken to a developing machine and the photoresist-soluble areas are dissolved with a developer.

[0046] Step 4: Baking: Place the developed material in an oven and bake until it is fully solidified, thereby producing a Figure 2 The via area of ​​the octagonal structure shown in .

[0047] The present invention leaves more wiring space in an effective space, greatly helps to improve the line wiring density, and can match the wiring width in modern wafer-level packaging.

[0048] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0049] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. Any modifications may be made within the scope of protection of the present invention.

Claims

1. An interconnection via structure for improving the interconnection density of wafer-level packaging, comprising a via (3) and a pad (2), characterized in that: In the cross section of the via hole (3), the length in the normal direction is greater than the length in the transverse direction; the pad (2) and the via hole (3) are arranged and assembled in a contoured manner, and the pad (2) is connected between the via hole (3) and the circuit (1) in the layer.

2. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: The cross-sectional shape of the via hole (3) includes, but is not limited to, an ellipse, a circular groove, an octagon, a hexagon, or a rounded prism.

3. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: A single via hole (3) is composed of a conductive material and an insulating material. The insulating material fills the hole in the center of the via hole (3), and the conductive material covers the circumference of the hole. The via hole (3) is connected to the pad (2) by the conductive material.

4. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 3, characterized in that: The conductive material is a conductor, including but not limited to copper, silver, gold, and tin.

5. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 3, characterized in that: The insulating material includes but is not limited to photoresist and resin.

6. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 3, characterized in that: The material of the pad (2) is consistent with the conductive material in the via hole (3).

7. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: The ratio of the length of the via hole (3) in the transverse direction to the length in the normal direction is 0.75-0.

9.

8. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: The longitudinal cross-section of the via hole (3) in the longitudinal direction presents a conical structure that is larger at the top and smaller at the bottom, and solder pads (2) of the same shape are respectively provided at both ends of the via hole (3).

9. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: The line (1) comprises a plurality of lines arranged in parallel, and the plurality of lines (1) are arranged at intervals along the transverse direction; the length direction of the line (1) is in the normal direction.

10. The interconnection via structure for improving the interconnection density of wafer-level packaging according to claim 1, characterized in that: The minimum distance (D) between the edge of the pad (2) and the via hole (3) is 2-10 μm.

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