A via resistance de-embedding structure and a via resistance detection method

Abstract

The present invention provides a via resistance de-embedding structure and a via resistance detection method. The via resistance de-embedding structure includes: a via detection structure, which includes a first lower metal layer, a via metal layer, and a first upper metal layer stacked in sequence; a lower metal surface test structure, which includes a second lower metal layer and is connected to a second lower metal surface test pad through a second lower metal surface test arm; an upper metal surface test structure, which includes a second upper metal layer and is connected to a second upper metal surface test pad through a second upper metal surface test arm; a test arm test structure, which includes a third metal surface test arm and a third metal surface test pad connected to each other. The present invention can calculate and remove the resistance of the test arm and the test pad, thereby improving the detection accuracy of the via resistance.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a via resistance de-embedding structure and a via resistance detection method. Background Art

[0002] In an integrated circuit, by forming wirings and vias in one step, a closer wiring pitch can be achieved, which helps to improve the integration and performance of the chip. An integrated circuit usually contains millions to over one hundred million vias, and the failure of any one via may cause the function of the integrated circuit to fail to meet the expectation. Therefore, it is necessary to detect the via resistance to determine whether it is qualified.

[0003] Currently, there are mainly the following two via resistance detection methods:

[0004] First, prepare a via chain including vias and interconnect lines; test the sheet resistance of the interconnect lines and the resistance of the via chain, then calculate the interconnect line resistance, and further calculate the via resistance. When testing the sheet resistance of a semiconductor material, the contact resistance of the test Pad is small for the resistance value of the semiconductor material, so the influence of the contact resistance on the result is not considered when calculating the sheet resistance. However, in the back-end process of a logic circuit, the width of the copper interconnect line is dozens of nm, so it is necessary to lead out test arms and test Pads to test and calculate the sheet resistance and via resistance. Since the resistance of the copper wire is low, the test Pad resistance has a serious influence on the test results of the sheet resistance and via resistance.

[0005] Second, prepare a via chain structure with multiple different numbers of vias plus interconnect lines; test the resistance of each via chain structure. Then draw a curve between the resistance and the reciprocal of the number of vias. Fit the slope R 0 is the resistance of the via chain structure with the number of vias being 1, and further calculate the via resistance. For the via chain structures with different numbers of vias obtained by this solution, when the via resistance is low and the interconnect line resistance is large, the fitting data error is large, and the contact resistance of the test Pad is not removed when calculating the interconnect line resistance. Summary of the Invention

[0006] The technical problem to be solved by the present invention is: to provide a via resistance de-embedding structure and a via resistance detection method, which can improve the detection accuracy of the via resistance.

[0007] The technical solution adopted by the present invention to solve the above technical problem is:

[0008] In the first aspect, the present invention provides a via resistance de-embedding structure, including:

[0009] Through-hole detection structure, including a first lower metal layer, a through-hole metal layer, and a first upper metal layer stacked in sequence; wherein, the first lower metal layer is connected to a first lower metal surface test pad through a first lower metal surface test arm, and the first upper metal layer is connected to a first upper metal surface test pad through a first upper metal surface test arm;

[0010] Lower metal surface test structure, including a second lower metal layer, and the second lower metal layer is connected to a second lower metal surface test pad through a second lower metal surface test arm;

[0011] Upper metal surface test structure, including a second upper metal layer, and the second upper metal layer is connected to a second upper metal surface test pad through a second upper metal surface test arm;

[0012] Test arm test structure, including a third metal surface test arm and a third metal surface test pad connected to each other;

[0013] Wherein, the structures and dimensions of the first and second lower metal layers are the same, the structures and dimensions of the first and second upper metal layers are the same, the structures and dimensions of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same, and the structures and dimensions of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same.

[0014] According to the above solution, the forming processes of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same; the forming processes of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same.

[0015] According to the above solution, the first lower metal layer and the second lower metal layer are formed on the same substrate under the same process; the first upper metal layer and the second upper metal layer are formed on the same layer under the same process.

[0016] According to the above solution, the substrate is an insulating silicon substrate or a stacked structure with an insulating layer on its upper surface.

[0017] According to the above solution, the through-hole metal layer includes an insulating dielectric layer and a plurality of through-hole metals of equal size in the insulating dielectric layer; the first lower metal layer and the first upper metal layer are connected through the through-hole metals.

[0018] According to the above solution, the numbers of the second lower metal surface test arm, the second upper metal surface test arm, and the third metal surface test arm are the same, all being 4; the number of the first lower metal surface test arm is 2, and the number of the first upper metal surface test arm is 2.

[0019] As the second aspect of the present invention, the present invention also provides a through-hole resistance detection method completed by using the through-hole resistance de-embedding structure described above,

[0020] Adopt a via hole detection structure to detect the total resistance value of the first upper metal layer, the via hole metal layer, the first lower metal layer, the first upper metal surface test arm, the first upper metal surface test pad, the first lower metal surface test arm, and the first lower metal surface test pad;

[0021] Adopt a lower metal surface test structure to detect the total resistance value of the second lower metal layer, the second lower metal surface test arm, and the second lower metal surface test pad;

[0022] Adopt an upper metal surface test structure to detect the total resistance value of the second upper metal layer, the second upper metal surface test arm, and the second upper metal surface test pad;

[0023] Adopt a test arm test structure to detect the total resistance value of the third metal surface test arm and the third metal surface test pad;

[0024] Based on the fact that the resistance values of the first and second upper metal layers are the same, the resistance values of the first and second lower metal layers are the same, the resistance values of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same, and the resistance values of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same, use the detected resistance values above to calculate the resistance value of the via hole metal layer.

[0025] According to the above method, the calculation formula for the resistance value R of the via hole metal layer is: R = R1 - R2 - R3 + R4;

[0026] Among them, R1 is the total resistance value of the first upper metal layer, the via hole metal layer, the first lower metal layer, 2 first upper metal surface test arms, 2 first upper metal surface test pads, 2 first lower metal surface test arms, and 2 first lower metal surface test pads; R2 is the total resistance value of the second lower metal layer, 4 second lower metal surface test arms, and 4 second lower metal surface test pads; R3 is the total resistance value of the second upper metal layer, 4 second upper metal surface test arms, and 4 second upper metal surface test pads; R4 is the total resistance value of 4 third metal surface test arms and 4 third metal surface test pads.

[0027] According to the above method, after obtaining the resistance value of the via hole metal layer, then according to the number of via hole metals in the via hole metal layer, obtain the average resistance value of each via hole metal.

[0028] According to the above method, the detection of the resistance value all adopts the Van der Pauw method; for each total resistance value, at least 2 detections are carried out, and the average value is obtained.

[0029] The beneficial effects of the present invention are:

[0030] 1. Design a set of through-hole resistor de-embedding structures, use the resistance relationship between different structures for addition and subtraction, so as to obtain the through-hole resistance value. The unexpected effect is that the resistance of the test arm and the test pad can be calculated and removed, thereby improving the detection accuracy of the through-hole resistance, and the calculation method is simple.

[0031] 2. The parts with the same resistance value in the through-hole detection structure, the lower metal surface test structure, the upper metal surface test structure and the test arm test structure are formed in the same process, eliminating the resistance value error caused by the process batch and further improving the calculation accuracy of the through-hole resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. is a schematic structural diagram of a through-hole detection structure according to an embodiment of the present invention.

[0033] Figure 2 is Figure 1 partial cross-sectional view of

[0034] Figure 3 FIG. is a schematic structural diagram of an upper metal surface test structure according to an embodiment of the present invention.

[0035] Figure 4 FIG. is a schematic structural diagram of a lower metal surface test structure according to an embodiment of the present invention.

[0036] Figure 5 FIG. is a schematic structural diagram of a test arm test structure according to an embodiment of the present invention.

[0037] Figure 6 FIG. is a flowchart of a method according to an embodiment of the present invention.

[0038] In the figure:

[0039] 1010 - First upper metal layer, 1011 - First upper metal surface test pad, 1012 - First upper metal surface test arm;

[0040] 1020 - Through-hole metal layer, 1021 - Insulating dielectric layer;

[0041] 1030 - First lower metal layer, 1031 - First lower metal surface test pad, 1032 - First lower metal surface test arm;

[0042] 1040 - Substrate;

[0043] 2010 - Second upper metal layer, 2011 - Second upper metal surface test pad, 2012 - Second upper metal surface test arm;

[0044] 3010 - Second lower metal layer, 3011 - Second lower metal surface test pad, 3012 - Second lower metal surface test arm;

[0045] 4011 - Third metal surface test pad, 4012 - Third metal surface test arm. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0048] In the present invention, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be understood as indicating or implying relative importance.

[0049] Glossary:

[0050] Van der Pauw method: VanDePauW, a technique for measuring resistivity and Hall coefficient.

[0051] As a first aspect of the present invention, the present invention provides a via resistance de-embedding structure, including a via detection structure for detecting the resistance values of the upper metal layer, the via metal layer, the lower metal surface, as well as the test arm and the test pad; a lower metal surface test structure for detecting the resistance values of the lower metal layer, as well as the test arm and the test pad; an upper metal surface test structure for detecting the resistance values of the upper metal layer, as well as the test arm and the test pad; and a test arm test structure for detecting the resistance values of the test arm and the test pad. The present invention uses the VanDePauW method to measure the resistance values of the via resistance detection structure, the lower metal layer test structure, the upper metal surface test structure, and the test arm test structure, only for detecting the total resistance value of each test structure and calculating the via resistance value, rather than solving equations and calculating the sheet resistance value of the conductive film.

[0052] Specifically, the via hole detection structure includes a first lower metal layer, a via hole metal layer, and a first upper metal layer stacked in sequence; wherein, the first lower metal layer is connected to a first lower metal surface test pad through a first lower metal surface test arm, and the first upper metal layer is connected to a first upper metal surface test pad through a first upper metal surface test arm.

[0053] The lower metal surface test structure includes a second lower metal layer, and the second lower metal layer is connected to a second lower metal surface test pad through a second lower metal surface test arm.

[0054] The upper metal surface test structure includes a second upper metal layer, and the second upper metal layer is connected to a second upper metal surface test pad through a second upper metal surface test arm.

[0055] The test arm test structure includes a third metal surface test arm and a third metal surface test pad that are connected to each other.

[0056] Wherein, the structures and sizes of the first and second lower metal layers are the same, the structures and sizes of the first and second upper metal layers are the same, the structures and sizes of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same, and the structures and sizes of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same.

[0057] As a second aspect of the present invention, the present invention also provides a via hole resistance detection method completed by using the via hole resistance de-embedding structure as Figure 6 shown, specifically including the following steps:

[0058] S1. Use the via hole detection structure to detect the total resistance value R1 of the first upper metal layer, the via hole metal layer, the first lower metal surface, the first upper metal surface test arm, the first upper metal surface test pad, the first lower metal surface test arm, and the first lower metal surface test pad;

[0059] S2. Use the lower metal surface test structure to detect the total resistance value R2 of the second lower metal layer, the second lower metal surface test arm, and the second lower metal surface test pad;

[0060] S3. Use the upper metal surface test structure to detect the total resistance value R3 of the second upper metal layer, the second upper metal surface test arm, and the second upper metal surface test pad;

[0061] S4. Use the test arm test structure to detect the total resistance value R4 of the third metal surface test arm and the third metal surface test pad;

[0062] S5. Based on the same resistance values of the first and second upper metal layers, the same resistance values of the first and second lower metal layers, the same resistance values of the first upper, first lower, second lower, second upper, and third metal surface test arms, and the same resistance values of the first upper, first lower, second lower, second upper, and third metal surface test pads, use the detected resistance values above to calculate the resistance value of the via metal layer, and then obtain the average resistance value Rv of each via metal according to the number of via metals, that is: Rv = (R1 - R2 - R3 + R4) / N, where N is the number of vias.

[0063] Among them, the order of the above S1 - S4 can be arbitrarily exchanged.

[0064] The present invention can calculate the average value of multiple via resistances by using the de-embedding method, thereby solving the problem of large test errors of via resistances.

[0065] The following will illustrate the present invention with a specific embodiment.

[0066] The via detection structure is as Figure 1 and Figure 2 shown, including a first lower metal layer 1030, a via metal layer 1020, and a first upper metal layer 1010 stacked in sequence on a substrate 1040. The first lower metal layer 1030 leads out a first lower metal surface test arm 1032 and a first lower metal surface test pad 1031, and the first upper metal layer 1010 leads out a first upper metal surface test arm 1012 and a first upper metal surface test pad 1011.

[0067] The number and setting positions of the test arms and test pads are set according to the test method. In this embodiment, the Van der Pauw method is adopted, so 2 test arms and test pads are respectively led out from the first lower metal layer 1030 and the first upper metal layer 1010, for a total of 4 test arms and test pads.

[0068] The via metal layer 1020 contains multiple via metals with approximately equal sizes, and the first lower metal layer 1030 and the first upper metal layer 1010 are connected through the via metals. In this embodiment, the material of the via metal is Cu, Au, or Ti / Au alloy, etc., and the metal thickness is 120 - 180 nm. In this embodiment, the via metals are arranged in a 6·6 matrix, and other quantities and arrangements can also be selected according to actual situations such as test requirements and sensitivity, such as 4·4, etc. In the via metal layer 1020, except for the via metals, other places are filled with an insulating dielectric layer 1021, and the insulating dielectric layer 1021 is Si3N4 or SiO2.

[0069] The via detection structure in this embodiment is obtained by using the conventional Logic IC BEOL process, and will not be repeated here.

[0070] The described lower metal surface test structure is as follows Figure 4 shown, including a second lower metal layer 3010, a second lower metal surface test arm 3012, and a second lower metal surface test pad 3011, which have the same structural dimensions and formation processes as those of the first lower metal layer, the first lower metal surface test arm, and the first lower metal surface test pad. To simplify the process and time, and reduce the errors caused by the process, the lower metal surface test structure and the first lower metal layer 1030 of the via detection structure can be formed on the same substrate simultaneously under the same process.

[0071] The described upper metal surface test structure is as follows Figure 3 shown, including a second upper metal layer 2010, a second upper metal surface test arm 2012, and a second upper metal surface test pad 2011, which have the same structural dimensions and formation processes as those of the first upper metal layer, the first upper metal surface test arm, and the first upper metal surface test pad. Similarly, the upper metal surface test structure and the first upper metal layer 1010 of the via detection structure can be formed on the same layer simultaneously under the same process.

[0072] The described test arm test structure is as follows Figure 5 shown, including a third metal surface test arm 4012 and a third metal surface test pad 4011 that are connected to each other. Similarly, the test arm test structure and the first lower metal layer 1030 of the via detection structure can be formed on the same substrate simultaneously under the same process, or the test arm test structure and the first upper metal layer 1010 of the via detection structure can be formed on the same layer simultaneously under the same process. Since the resistance values of the test arm and the test pad themselves are very small, the test arm test structure in this embodiment connects 4 test arms together for detection, which can improve the detection accuracy. Of course, according to the actual situation, the test arm test structure can also be divided into 2 or more, and the resistance values of one test arm and one test pad are detected respectively, and then added together to obtain the total resistance value of the test arm test structure. Multiple test arms and test pads can also be formed, and after detecting the total resistance value of multiple test arms and test pads, conversion is performed to obtain the total resistance value of 4 test arms and 4 test pads.

[0073] For the convenience of calculation, the structures, shapes, sizes, thicknesses and processes of the test arms and test pads in the through-hole detection structure, lower metal surface test structure, upper metal surface test structure and test arm test structure are the same. That is: the structures, shapes, sizes, thicknesses and processes of the first upper metal surface test pad 1011, the first lower metal surface test pad 1031, the second upper metal surface test pad 2011, the second lower metal surface test pad 3011 and the third metal surface test pad 4011 are the same; the structures, shapes, sizes, thicknesses and processes of the first upper metal surface test arm 1012, the first lower metal surface test arm 1032, the second upper metal surface test arm 2012, the second lower metal surface test arm 3012 and the third metal surface test arm 4012 are the same.

[0074] Since the above test structure needs to be formed on an insulating substrate, a substrate is required. The substrate is an insulating silicon substrate or a stacked structure with an insulating layer on its upper surface. However, the substrate itself does not participate in the resistance test and calculation, so there is no limitation on it.

[0075] For the convenience of structure preparation, in this embodiment, the first upper metal layer 1010, the first lower metal layer 1030, the second upper metal layer 2010 and the second lower metal layer 3010 are made into metal layers with the same materials, shapes, sizes and thicknesses.

[0076] Furthermore, to further ensure accuracy and reduce errors, all upper metal layers are completed in the same batch process, and all lower metal layers are completed in the same batch process. That is: when forming the first lower metal layer 1030, the first lower metal surface test pad 1031 and the first lower metal surface test arm 1032, the second lower metal layer 3010, the second lower metal surface test pad 3011, the second lower metal surface test arm 3012, the third metal surface test pad 4011 and the third metal surface test arm 4012 are simultaneously formed on the substrate 1040. When forming the first upper metal layer 1010, the first upper metal surface test pad 1011 and the first upper metal surface test arm 1012, the second upper metal layer 2010, the second upper metal surface test pad 2011 and the second upper metal surface test arm 2012 are synchronously formed. Of course, the third metal surface test pad 4011 and the third metal surface test arm 4012 can also be synchronously formed when forming the first upper metal layer 1010, the first upper metal surface test pad 1011 and the first upper metal surface test arm 1012.

[0077] Taking the through-hole detection structure as an example, the specific steps of resistance detection are described below.

[0078] Using the Van der Pauw method, two first upper metal surface test pads 1011 and two first lower metal surface test pads 1031 respectively correspond to a total of 4 test modules of SMU1 - SMU4. A variable current of -10 mA to 10 mA is applied to the two first lower metal surface test pads 1031, the voltage value is detected at the two first upper metal surface test pads 1011, and then the first detection resistance value of the via hole detection structure is calculated. A variable current of -10 mA to 10 mA is applied to the two first upper metal surface test pads 1011, the voltage value is detected at the two first lower metal surface test pads 1031, and then the second detection resistance value of the via hole detection structure is calculated. Then, a variable current of -10 mA to 10 mA is applied to one first lower metal surface test pad 1031 and one first upper metal surface test pad 1011, the voltage value is detected at the other first lower metal surface test pad 1031 and the other first upper metal surface test pad 1011, and then the third detection resistance value of the via hole detection structure is calculated. Then, the detections are exchanged to obtain the fourth detection resistance value of the via hole detection structure. Finally, the total resistance value R1 of the via hole detection structure (including the upper and lower metal layers, via hole metal, and 4 test arms and pads) is obtained as the average value of the four detection resistance values.

[0079] Using the same idea as above, the total resistance values R2 of the lower metal layer and the test arms and test pads, R3 of the upper metal layer and the test arms and test pads, and R4 of the test arms and test pads are obtained respectively. Finally, according to the number N of via hole metals, the average resistance value Rv of each via hole metal is obtained.

[0080] In this embodiment, the total resistance value R2 of the lower metal layer and the test arms and test pads is the total resistance value of the second lower metal layer, the second lower metal surface test arms, and the second lower metal surface test pads. The total resistance value R3 of the upper metal layer and the test arms and test pads is the total resistance value of the second upper metal layer, the second upper metal surface test arms, and the second upper metal surface test pads. The total resistance value R4 of the test arms and test pads is the total resistance value of the third upper metal surface test arms, the third upper metal surface test pads, the third lower metal surface test arms, and the third lower metal surface test pads.

[0081] Since the structural dimensions and the formed process batches of the first and second upper metal layers are the same, it can be considered that the resistance values of the first and second upper metal layers are the same. Similarly, the resistance values of the first and second lower metal layers are the same. The resistance values of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same, and the resistance values of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same. Then, through simple mathematical addition and subtraction, the calculation formula for the resistance value R of the via hole metal layer can be obtained. Specifically expressed by the formula as:

[0082] R1 = R11 +R 13 +4R b +4R p +NR v ;

[0083] R2 = R 21 +4R b +4R p ;

[0084] R3 = R 31 +4R b +4R p ;

[0085] R4 = 4R b +4R p ;

[0086] R 11 = R 21 、R 13 = R 31 ;

[0087] Furthermore, the via resistance R = R1 - R2 - R3 + R4 is obtained.

[0088] In the formula, R 11 is the resistance value of the first lower metal layer, R 13 is the resistance value of the first upper metal layer, R 21 is the resistance value of the second lower metal layer, R 31 is the resistance value of the second upper metal layer, R b is the resistance value of a test arm, and R p is the resistance value of a test pad. Then, according to the number N of via metals in the via metal layer, the average resistance value Rv of each via metal is obtained as Rv = (R1 - R2 - R3 + R4) / N. In this embodiment, N = 6 * 6 = 36.

[0089] In summary, the present invention adopts a set of via resistance de-embedding structures including a via detection structure, a lower metal surface test structure, an upper metal surface test structure, and a test arm test structure, and uses the de-embedding method to calculate the average value of multiple via resistances. The unexpected effect is that the resistances of the test arm and the test pad are calculated and removed, thereby improving the detection accuracy of the via resistance and solving the error problem of via resistance testing.

[0090] It should be noted that according to the needs of implementation, each step / component described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0091] The sequence numbers of the steps in the above embodiments do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0092] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A via resistor de-embedding structure, characterized in that: Comprising: A via hole detection structure, including a first lower metal layer, a via hole metal layer, and a first upper metal layer stacked in sequence; wherein, the first lower metal layer is connected to a first lower metal surface test pad through a first lower metal surface test arm, and the first upper metal layer is connected to a first upper metal surface test pad through a first upper metal surface test arm; A lower metal surface test structure, including a second lower metal layer, and the second lower metal layer is connected to a second lower metal surface test pad through a second lower metal surface test arm; An upper metal surface test structure, including a second upper metal layer, and the second upper metal layer is connected to a second upper metal surface test pad through a second upper metal surface test arm; A test arm test structure, including a third metal surface test arm and a third metal surface test pad connected to each other; Wherein, the structures and dimensions of the first and second lower metal layers are the same, the structures and dimensions of the first and second upper metal layers are the same, the structures and dimensions of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same, and the structures and dimensions of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same.

2. The via resistance de-embedding structure according to claim 1, wherein: The forming processes of the first upper, first lower, second lower, second upper, and third metal surface test arms are the same; the forming processes of the first upper, first lower, second lower, second upper, and third metal surface test pads are the same.

3. The via resistance de-embedding structure according to claim 1, wherein: The first lower metal layer and the second lower metal layer are formed on the same substrate under the same process; the first upper metal layer and the second upper metal layer are formed on the same layer under the same process.

4. The via resistance de-embedding structure according to claim 3, wherein: The substrate is an insulating silicon substrate or a stacked structure with an insulating layer on its upper surface.

5. The via resistance de-embedding structure according to claim 1, wherein: The via hole metal layer includes an insulating dielectric layer and a plurality of via hole metals of equal size in the insulating dielectric layer; the first lower metal layer and the first upper metal layer are connected through the via hole metals.

6. The via resistance de-embedding structure according to claim 1, wherein: The number of the second lower metal surface test arms, the second upper metal surface test arms, and the third metal surface test arms is the same, all being 4; the number of the first lower metal surface test arms is 2, and the number of the first upper metal surface test arms is 2.

7. A via hole resistance detection method completed by using the via hole resistance de-embedding structure according to any one of claims 1 to 6, characterized in that: Adopting the via hole detection structure to detect the total resistance value of the first upper metal layer, the via hole metal layer, the first lower metal surface, the first upper metal surface test arm, the first upper metal surface test pad, the first lower metal surface test arm, and the first lower metal surface test pad; Adopting the lower metal surface test structure to detect the total resistance value of the second lower metal layer, the second lower metal surface test arm, and the second lower metal surface test pad; Adopting the upper metal surface test structure to detect the total resistance value of the second upper metal layer, the second upper metal surface test arm, and the second upper metal surface test pad; Adopting the test arm test structure to detect the total resistance value of the third metal surface test arm and the third metal surface test pad; Based on the same resistance values of the first and second upper metal layers, the same resistance values of the first and second lower metal layers, the same resistance values of the first upper, first lower, second lower, second upper, and third metal surface test arms, and the same resistance values of the first upper, first lower, second lower, second upper, and third metal surface test pads, the resistance value of the via metal layer is calculated using the above detected resistance values.

8. The via resistance detection method according to claim 7, wherein: The calculation formula for the resistance value R of the via metal layer is: R = R1 - R2 - R3 + R4; Wherein, R1 is the total resistance value of the first upper metal layer, the via metal layer, the first lower metal surface, 2 first upper metal surface test arms, 2 first upper metal surface test pads, 2 first lower metal surface test arms, and 2 first lower metal surface test pads; R2 is the total resistance value of the second lower metal layer, 4 second lower metal surface test arms, and 4 second lower metal surface test pads; R3 is the total resistance value of the second upper metal layer, 4 second upper metal surface test arms, and 4 second upper metal surface test pads; R4 is the total resistance value of 4 third metal surface test arms and 4 third metal surface test pads.

9. The through-hole resistance detection method according to claim 7, characterized in that: After obtaining the resistance value of the via metal layer, the average resistance value of each via metal is obtained based on the number of via metals in the via metal layer.

10. The through-hole resistance detection method according to claim 7, wherein: The detection of the resistance value is all carried out using the Van der Pauw method; for each total resistance value, at least 2 detections are made and the average value is obtained.

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