Semiconductor package and method of manufacturing the same

Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The method includes providing a package substrate having a first surface and a second surface opposite the first surface; mounting a plurality of conductive blocks onto the first surface of the package substrate; forming at least one conductive bump on each of the plurality of conductive blocks; forming a first encapsulant on a first surface of the package substrate to encapsulate the plurality of conductive blocks, and the conductive bumps on each of the plurality of conductive blocks; and grinding the first encapsulant to remove an upper portion of the first encapsulant and an upper portion of the conductive bump on each of the plurality of conductive blocks such that an exposed surface of the conductive bump on each of the plurality of conductive blocks is at the same height relative to a first surface of the package substrate.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology, and more particularly, to a semiconductor package and a method of forming the same. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic devices to be smaller, faster, and higher performing, and to pack more and more functions into a single device. In recent years, semiconductor packages have been manufactured in smaller sizes to increase the density of electronic components. Generally, a semiconductor package may include major functional modules, such as a semiconductor chip and an interconnect structure. However, it should be noted that the formation process of certain interconnects, such as stacking multiple layers of solder balls in a single through-hole to achieve a higher interconnect structure, may be complex and not cost-effective. In addition, such complex processes may adversely affect the yield of semiconductor packages incorporating such interconnect structures.

[0003] Therefore, a method for forming a semiconductor package with simple process and higher yield is needed. Summary of the invention

[0004] An object of the present application is to provide a method for forming a semiconductor package with a simple process and improved yield.

[0005] According to one aspect of the present application, a method for forming a semiconductor package is provided. The method may include: providing a package substrate having a first surface and a second surface opposite to the first surface; mounting a plurality of conductive blocks on the first surface of the package substrate; forming at least one conductive bump on each of the plurality of conductive blocks; forming a first sealant on the first surface of the package substrate to seal the conductive blocks and the conductive bumps on each of the plurality of conductive blocks; and grinding the first sealant to remove an upper portion of the first sealant and an upper portion of the conductive bumps on each of the plurality of conductive blocks, so that an exposed surface of the conductive bumps on each of the plurality of conductive blocks is at the same height relative to the first surface of the package substrate.

[0006] According to another aspect of the present application, a semiconductor package is provided, which can be formed using the above method.

[0007] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in this specification and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings cited herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless the detailed description explicitly indicates otherwise, and the reader of this specification should not infer otherwise.

[0009] Figure 1A is a cross-sectional view of a conventional semiconductor package.

[0010] Figure 1B for Figure 1A A partial enlarged view of the semiconductor package shown in FIG.

[0011] Figures 2A to 2J The present invention is a cross-sectional view showing various steps of a method for manufacturing a semiconductor package according to an embodiment of the present application.

[0012] Figure 3 for Figure 2C Scanning electron microscope (SEM) image of the conductive blocks shown in FIG.

[0013] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0014] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of this specification. The accompanying drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the accompanying drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0015] In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "includes" and other forms such as "includes" and "comprising" are not limiting. In addition, terms such as "element" or "component" encompass elements and components comprising one unit and elements and components comprising more than one subunit, unless specifically stated otherwise. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0016] As used herein, for ease of description, spatially relative terms such as "below", "below", "above", "up", "upper", "lower", "left", "right", "vertical", "horizontal", "side", etc. may be used herein to describe the relationship of an element or feature to another element (or elements) or feature (or features) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or there can be intermediate elements.

[0017] As mentioned above, one way to form a taller interconnect structure in a semiconductor package (e.g., in a molded cover layer of such a semiconductor package) is to stack multiple layers of solder balls in a single through hole. However, the process of such an approach may be complicated. As an alternative, pre-formed conductive blocks (e.g., electrical function column (e-bar) modules) each having one or more conductive columns built therein may be installed in a through hole or cavity on a package substrate to form a thicker interconnect structure.

[0018] For example, Figure 1A A semiconductor package 100 is shown, in which a preformed conductive block 130 is formed on a package substrate 110 to couple electronic components in the semiconductor package 100 to solder bumps. However, the inventors of the present application have noticed that the yield of the semiconductor package 100 incorporating the conductive block 110 is relatively low and the reliability is low. After studying samples of the semiconductor package 100, the inventors found that due to differences in the size and height of the solder bumps 115 that mount the conductive block 130 to the package substrate 110, there may be a significant height difference between two or more conductive blocks 130 on the package substrate 110. For example, Figure 1B Show Figure 1A FIG. 1 is a partial enlarged view of the semiconductor package 100 shown in FIG. 1 , and the sealant 120 is omitted to more clearly show the two conductive blocks 130. Figure 1B There is a significant height difference D between the two conductive blocks 130 - 1 and 130 - 2 shown in FIG. Therefore, when other electronic components or circuit boards are mounted on the two conductive blocks 130 - 1 and 130 - 2 , the height difference D may cause tilted mounting or even open circuit, which reduces the reliability of the semiconductor package 100 .

[0019] In order to solve at least one of the above problems, a new method for forming a semiconductor package is provided in one aspect of the present application. In this method, additional conductive bumps are formed on a plurality of conductive blocks, and then the conductive bumps are ground to remove their upper portions so that the top surfaces of the plurality of conductive bumps can be at the same height relative to the package substrate. In other words, a height difference between the conductive bumps can be introduced in the grinding process to compensate for the height difference between the conductive blocks. In this way, the yield and reliability of the semiconductor package can be improved.

[0020] See also Figures 2A to 2J , which shows various steps of a method for forming a semiconductor package according to an embodiment of the present application. Figures 2A to 2J The method is described in more detail.

[0021] See also Figure 2A , a package substrate 210 is provided. The package substrate 210 has a first surface 210 a and a second surface 210 b opposite to the first surface 210 a , and a plurality of interconnect structures 212 are formed in the package substrate 210 .

[0022] Specifically, the package substrate 210 can provide support and connectivity for the electronic components and devices mounted thereon. For example, the package substrate 210 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, or a ceramic substrate. However, the package substrate 210 is not limited to these examples. In other examples, the package substrate 210 may include a laminated interposer, a strip interposer, a lead frame, or other suitable substrates. In order to increase manufacturing output, the package substrate 210 may include a plurality of predefined substrate units arranged in a strip manner, thereby allowing some manufacturing processes to be performed on all of these substrate units in parallel.

[0023] The interconnect structure 212 may provide connectivity for electronic components mounted on the package substrate 210. The interconnect structure 212 may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the package substrate 210. For example, Figure 2A As shown in FIG. 2 , some of the interconnect structures 212 may provide a plurality of first contact pads 212 a on the first surface 210 a and a plurality of second contact pads 212 b on the second surface 210 b.

[0024] See also Figure 2B , a plurality of conductive blocks 230 are mounted on the first surface 210 a of the package substrate 210 .

[0025] In some embodiments, solder material may be deposited onto the first contact pad 212a on the first surface 210a of the package substrate 210 to form a plurality of solder bumps 215 on the first contact pad 212a. For example, the solder material may include eutectic Sn / Pb, high lead solder, lead-free solder, or other suitable materials.

[0026] Next, a plurality of conductive blocks 230 are placed on the first surface 210a of the package substrate 210 and in contact with some of the solder bumps 215, and the solder bumps 215 may be reflowed to mount the conductive blocks 230 on the first surface 210a of the package substrate 210 via the solder bumps 215, thereby forming an electrical connection between the interconnect structure 212 and the conductive blocks 230. Similarly, at least one first electronic component 240 is also mounted on the first surface 210a of the package substrate 210 via some of the solder bumps 215, thereby forming an electrical connection between the interconnect structure 212 and the first electronic component 240. In some embodiments, the first electronic component 240 may be a semiconductor chip or a smaller semiconductor package. In some embodiments, the conductive blocks 230 are thicker than the first electronic components 240. In other words, the top surface of the first electronic component 240 may be lower than the top surface of the conductive blocks 230. In this way, the semiconductor package may be electrically connected to other external electronic devices via the conductive blocks 230 while keeping the first electronic components 240 isolated from other devices. In some embodiments, the conductive block 230 and the first electronic component 240 may be attached to the first surface 210a of the packaging substrate 210 simultaneously, while in some other embodiments, the conductive block 230 may be attached to the first surface 210a of the packaging substrate 210 before or after attaching the first electronic component 240.

[0027] In some embodiments, the conductive block 230 may be an e-bar module, which includes built-in conductive posts such as copper posts, and an insulating base material separating the copper posts from each other. Figure 2B As shown in , each electrical functional column module 230 includes two conductive columns 232 surrounded by a dielectric layer 234 (e.g., an insulating polymeric material or a composite). More specifically, the bottom surface of the conductive column 232 is exposed relative to the bottom surface of the dielectric layer 234 for contacting the solder bump 215. Similarly, the top surface of the conductive column 232 is exposed relative to the top surface of the dielectric layer 234 for purposes such as electrical contact with an external device. In some embodiments, the conductive columns 232 in some conductive blocks 230 are electrically connected to each other. In some other embodiments, the conductive columns 232 in some conductive blocks 230 are not electrically connected to each other, but are electrically isolated from each other to form separate electrical paths. It can be understood that the number of conductive columns 232 included in each conductive block 230 can vary according to the actual needs of the semiconductor package.

[0028] exist Figure 2B In the example shown in , the plurality of conductive blocks 230 include a first conductive block 230-1 mounted on the right side portion of the package substrate 210 and a second conductive block 230-2 mounted on the left side portion of the package substrate 210. As previously described, due to, for example, the unevenness of the first surface 210a of the package substrate 210, the inconsistency of the formation process of the solder bump 215, and / or the inconsistency of the attachment process of the conductive block 230 to the package substrate 210, the conductive blocks 230 at different locations on the package substrate 210 may have different heights. For example, the height of the solder bump 215 under the first conductive block 230-1 may be different from the height of the solder bump 215 under the second conductive block 230-2, resulting in a height difference between the top surface of the first conductive block 230-1 and the top surface of the second conductive block 230-2. Specifically, the top surface of the first conductive block 230-1 is higher than the top surface of the second conductive block 230-2, as shown in FIG. Figure 2B As shown in .

[0029] See also Figure 2C , at least one conductive bump 235 is formed on each of the plurality of conductive blocks 230 .

[0030] In some embodiments, the conductive bump 235 may be a solder bump. For example, a solder material may be printed or deposited onto the top surface of the conductive bump 230. The solder material may then be reflowed by heating it above its melting point to form the solder bump 235.

[0031] exist Figure 2C In the example shown in FIG. 2 , two first solder bumps 235-1 are formed on the first conductive block 230-1, and two second solder bumps 235-2 are formed on the second conductive block 230-2. Since the top surface of the first conductive block 230-1 is higher than the top surface of the second conductive block 230-2, the top surface of the first solder bump 235-1 may be higher than the top surface of the second solder bump 235-2. Figure 2C , each of the two first solder bumps 235-1 and the second solder bump 235-2 may have an oval cross-section. In other examples, the solder bumps may have a semicircular cross-section, etc.

[0032] See also Figure 2D , a first sealant 250 is formed on the first surface 210 a of the package substrate 210 to seal the conductive blocks 230 , the conductive bumps 235 on the conductive blocks 230 , and the first electronic components 240 .

[0033] In some embodiments, a molding material is formed on the first surface 210a of the package substrate 210 to form a first sealant 250, and the first sealant 250 seals the conductive block 230, the conductive bump 235 on the conductive block 230, and the first electronic component 240. The molding material may include epoxy resin, epoxy resin with filler, epoxy acrylate with filler, or a polymer with a suitable filler, but the scope of the present application is not limited thereto. In some embodiments, the first sealant 250 may be formed by using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes.

[0034] See also Figure 2D and Figure 2E , grinding the first sealant 250 to remove an upper portion of the first sealant 250 and an upper portion of the conductive bump 235 on each of the conductive blocks 230, so that the exposed surface of the conductive bump 235 on each of the conductive blocks 230 is at the same height relative to the first surface 210a of the packaging substrate 210.

[0035] In some embodiments, a grinder may be used to grind the top surface of the first encapsulant 250 until an upper portion of the first encapsulant 250 and an upper portion of the conductive bump 235 on each of the conductive blocks 230 are removed. Because the grinding process may also planarize the top surface of the first encapsulant 250, the exposed surfaces of the conductive bump 235 on each of the conductive blocks 230 may be substantially flush or coplanar with each other.

[0036] like Figure 2E As shown in , after the grinding process, the upper portion of the first solder bump 235-1 and the upper portion of the second solder bump 235-2 are both removed, but the first electronic component 240 is still covered by the first sealant 250. Since the top surface of the first solder bump 235-1 is higher than the top surface of the second solder bump 235-2, the removed portion of the first solder bump 235-1 can be thicker than the removed portion of the second solder bump 235-2. Figure 2F , showing Figure 2E A top view of the structure shown in FIG. Figure 2E For along Figure 2F A cross-sectional view of the structure shown in FIG. Figure 2F As shown in FIG. 1 , the exposed surfaces of the first solder bump 235-1 and the second solder bump 235-2 may have substantially the same size and / or shape. Figure 3 More details about the configuration of the solder bumps are described.

[0037] See also Figure 2G, the package substrate 210 is turned over, and at least one second electronic component 260 is mounted on the second surface 210 b of the package substrate 210 .

[0038] In some embodiments, solder material may be deposited onto the second contact pad 212b on the second surface 210b of the package substrate 210 to form a plurality of solder bumps. For example, the solder material may include eutectic Sn / Pb, high lead solder, lead-free solder or other suitable materials. Next, at least one second electronic component 260 is placed on the second surface 210b of the package substrate 210 and in contact with the solder bumps, and the solder bumps may be reflowed to mount the second electronic component 260 to the second surface 210b of the package substrate 210 via the solder bumps. In this way, the first electronic component 240 mounted on the first surface 210a of the package substrate 210, the second electronic component 260 mounted on the second surface 210b of the package substrate 210, and the conductive block 230 may be electrically connected to each other to form an integrated package. The integrated package may be further connected to an external circuit via the conductive block 230.

[0039] In some embodiments, the second electronic component 260 may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory controller, a memory device, an application-specific integrated circuit (ASIC), a discrete device, etc. In some embodiments, the second electronic component 260 may be a small IC chip that contains different well-defined functional subsets and allows a variety of different architectures, different process nodes, and even dedicated silicon modules or intellectual property (IP) modules from different manufacturers to be integrated into a single package. In some other embodiments, it is understood that the second electronic component 260 can be arranged and sized according to the actual needs of the semiconductor package.

[0040] See also Figure 2H , a second sealant 270 is formed on the second surface 210 b of the package substrate 210 to seal the second electronic component 260 .

[0041] In some embodiments, a molding material is formed on the second surface 210b of the packaging substrate 210 to form a second sealant 270 that seals the second electronic component 260. The molding material may include an epoxy resin, an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with an appropriate filler, but the scope of the present application is not limited thereto. In some embodiments, the second sealant 270 may be formed by using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes. Therefore, a double-sided molded package is formed by attaching and encapsulating the electronic components to both the first surface 210a and the second surface 210b of the packaging substrate 210.

[0042] See also Fig.2I , solder bumps 236 are formed on the exposed surfaces of the conductive bumps 235 on each of the conductive bumps 230 .

[0043] In some embodiments, solder material may be printed or deposited onto the exposed surfaces of the first solder bump 235-1 and the second solder bump 235-2, and then the solder material may be reflowed by heating the solder material above its melting point to form the solder bump 236. The solder material may include eutectic Sn / Pb, high lead solder, lead-free solder, or other suitable materials. In some other embodiments, the solder bump 236 may be compression bonded or thermocompression bonded onto the exposed surfaces of the first solder bump 235-1 and the second solder bump 235-2. Fig.2I The solder bump 236 shown in FIG. 2 may represent one type of external conductive bump that may be formed on the exposed surfaces of the first solder bump 235-1 and the second solder bump 235-2. In other examples, the external conductive bump may be a stud bump, a micro bump, or other electrical interconnect.

[0044] Finally, see Figure 2J , an electromagnetic interference (EMI) shield 280 may be formed to cover the top surface and side surfaces of the second sealant 270 , and side surfaces of the package substrate 210 and the first sealant 250 .

[0045] EMI shield 280 may be formed of copper, aluminum, iron, or any other suitable material for EMI shielding. In some embodiments, EMI shield 280 may be formed by spraying, electroplating, sputtering, or any other suitable metal deposition process. EMI shield 280 may follow the shape and / or contour of second encapsulant 270, as well as the side surfaces of package substrate 210 and first encapsulant 250.

[0046] In some embodiments, when the package substrate 210 is arranged in a strip including a plurality of predefined substrate units, a singulation process may be performed to singulate each individual package from the package strip along a singulation channel before the step of forming the EMI shield 280. For example, a saw blade may be used to singulate the package strip into individual packages via the singulation channel. In some other examples, a laser cutting tool may also be used to singulate the package strip.

[0047] Although combined Figures 2A to 2J Various processes for forming semiconductor packages are shown, but those skilled in the art will appreciate that modifications and adaptations may be made to the processes without departing from the scope of the present invention.

[0048] Figure 3 A portion of a conductive block is shown (eg, Figure 2B 2) and the conductive bumps (eg, Figure 2C 23. A scanning electron microscope (SEM) image of solder bumps or balls 235 formed in FIG.

[0049] The inventors of the present application have found that when the diameter of the solder ball 235 is larger than the width of the top surface of the conductive pillar 232 exposed from the solder resist opening (SRO) of the dielectric layer 234 of the conductive block 230, the solder ball 235 may have an oval cross-section after the reflow process. Figure 3 As shown in , the solder ball 235 may have an upper portion 235U, a lower portion 235L, and a middle portion 235M, and the width "W" of the solder ball 235 may not vary much in the middle portion 235M. Figure 2D For example, the first solder bump 235-1 and the second solder bump 235-2 both have an oval cross-section after the reflow process, and due to the height variation between the first conductive block 230-1 and the second conductive block 230-2, there may be a height difference between the first solder bump 235-1 and the second solder bump 235-2. Figure 2E and Figure 3 , the grinding process can be controlled to stop at the middle portion 235M of the first solder bump 235-1 and the second solder bump 23.5-2. For example, the first solder bump 235-1 is ground until the lower portion of the middle portion 235M, and the second solder bump 235-2 is ground until the upper portion of the middle portion 235M. Since the width "W" of the first solder bump 235-1 and the second solder bump 23.5-2 varies little in the middle portion 235M, the exposed area of ​​the first solder bump 235-1 and the exposed area of ​​the second solder bump 235-2 are substantially the same as each other, as shown in FIG. Figure 2E shown.

[0050] On the other hand, when the diameter of the solder ball 235 is smaller than the width of the top surface of the conductive pillar 232, the solder ball 235 may have a semicircular cross-section after the reflow process, and the width of the solder ball 235 may vary greatly in the middle portion 235M. Figure 2F The exposed areas of the first solder bump 235 - 1 and the second solder bump 23 . 5 - 2 shown in FIG. 1 are the same after the grinding process, thereby reducing the reliability of the semiconductor package to be formed.

[0051] Therefore, in the present application, it is preferred that the diameter of the solder ball 235 is larger than the width of the top surface of the conductive pillar 232. Figure 2C In the step shown in , a solder ball having a diameter of 280 μm can be formed on the conductive pillar 232 having a width of 210 μm.

[0052] According to another aspect of the present application, a semiconductor package prepared by the method described above is provided. The details of the semiconductor package can refer to the method described above, and are not described in detail herein.

[0053] The discussion herein includes many illustrative drawings showing various parts of semiconductor packages and methods of making the same. For clarity of illustration, such drawings do not show all aspects of each example package. Any example package and / or method provided herein may share any or all characteristics with any or all other devices and / or methods provided herein.

[0054] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and variations may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by consideration of the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A method for forming a semiconductor package, characterized in that: The method comprises: Providing a packaging substrate, the packaging substrate having a first surface and a second surface opposite to the first surface; mounting a plurality of conductive bumps on the first surface of the packaging substrate; forming at least one conductive bump on each of the plurality of conductive blocks; forming a first sealant on a first surface of the package substrate to seal the plurality of conductive blocks and the conductive bump on each of the plurality of conductive blocks; and The first sealant is ground to remove an upper portion of the first sealant and an upper portion of the conductive bump on each of the plurality of conductive blocks so that an exposed surface of the conductive bump on each of the plurality of conductive blocks is at the same height relative to the first surface of the packaging substrate.

2. The method according to claim 1, characterized in that: The method further comprises: A solder bump is formed on the exposed surface of the conductive bump on each of the plurality of conductive blocks.

3. The method according to claim 1, characterized in that The package substrate includes a plurality of conductive pads formed on a first surface of the package substrate, and mounting the plurality of conductive pads on the first surface of the package substrate includes: depositing solder material onto the plurality of conductive pads formed on the first surface of the package substrate; placing the plurality of conductive bumps on the first surface of the package substrate so as to contact the solder material; and The solder material is reflowed to mount the plurality of conductive bumps on the first surface of the package substrate.

4. The method according to claim 1, characterized in that: The plurality of conductive blocks include a first conductive block and a second conductive block, and a top surface of the first conductive block is higher than a top surface of the second conductive block.

5. The method according to claim 4, characterized in that Forming at least one conductive bump on each of the plurality of conductive blocks comprises: forming a first conductive bump on the first conductive block; and A second conductive bump is formed on the second conductive block, wherein a top surface of the first conductive bump is higher than a top surface of the second conductive bump.

6. The method according to claim 1, characterized in that Before forming the first sealant on the first surface of the package substrate, the method further includes: At least one first electronic component is mounted on the first surface of the packaging substrate.

7. The method according to claim 6, characterized in that A top surface of the first electronic component is lower than top surfaces of the plurality of conductive blocks.

8. The method according to claim 1, characterized in that After grinding the first sealant, the method further comprises: At least one second electronic component is mounted on the second surface of the packaging substrate.

9. The method according to claim 8, characterized in that The method further comprises: A second sealant is formed on the second surface of the package substrate to seal the second electronic component.

10. The method according to claim 9, characterized in that The method further comprises: An electromagnetic interference shield is formed to cover a top surface and side surfaces of the second encapsulant, and side surfaces of the package substrate and the first encapsulant.

11. The method according to claim 1, characterized in that: The conductive bumps include solder bumps.

12. The method according to claim 1, characterized in that The plurality of conductive blocks include electrical functional column modules.

13. A semiconductor package, characterized in that: The semiconductor package is formed using the method of any one of claims 1 to 12 .

Images