Multi-phase integrated phase shifting unit and phase shifter for realizing 22.5-degree, 45-degree and 67.5-degree phase shifting

Abstract

The invention relates to a multi-phase integrated phase shifting unit for realizing 22.5-degree, 45-degree and 67.5-degree phase shifting and a phase shifter, belongs to the technical field of radio frequency integrated circuits, and solves the problem of large occupied volume of a phase shifting unit for realizing 22.5-degree, 45-degree and 67.5-degree phase shifting in the prior art. The multi-phase integrated phase shifting unit comprises a high-pass circuit, a first low-pass circuit and a second low-pass circuit which are connected in parallel; the on-off states of the first low-pass circuit and the second low-pass circuit are opposite; by controlling the on-off states of the high-pass circuit, the first low-pass circuit and the second low-pass circuit, the multi-phase integrated phase shifting unit realizes the following four phase shifting states: a reference phase shifting state, a 22.5-degree phase shifting state, a 45-degree phase shifting state and a 67.5-degree phase shifting state. The phase shifting unit for realizing 22.5-degree phase shifting, 45-degree phase shifting and 67.5-degree phase shifting is small in occupied volume, and the cost is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a multi-phase integrated phase shift unit and a phase shifter for achieving 22.5°, 45° and 67.5° phase shifts. Background Art

[0002] With the continuous development of communication technology, at the military level, phased array radars are gradually replacing traditional mechanical radars with slow scanning speeds and inflexible scanning directions due to their strong anti-interference capabilities and high reliability. At the same time, with the continuous breakthroughs in 5G technology, the application of automotive radar systems in driverless technology is becoming more and more popular. Among these technologies, phased array radar systems are a very important link. In phased array radar systems, T / R (Transmitter and Receiver) transceiver components are the core architecture, among which the phase shifter is an important component of the T / R transceiver component, which directly affects the performance of the entire phased array system, such as phase accuracy, insertion loss, etc. The entire phased array system has thousands of T / R transceiver components, and each T / R transceiver component requires at least one phase shifter, and the phase shifter also occupies a considerable area in the T / R transceiver component.

[0003] In the prior art, the phase shift units for realizing 22.5° and 45° are usually realized by using a T-shaped structure based on capacitors or inductors. When 67.5° is needed, two phase shift units of 22.5° and 45° are connected in series to realize a phase shift of 67.5°. However, this implementation method occupies a large volume and is increasingly unable to meet the needs of the current development of miniaturization of science and technology.

[0004] Therefore, there is an urgent need for a phase shifting unit that occupies a small volume and is used to achieve 22.5°, 45° and 67.5°. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a multi-phase integrated phase shifting unit and a phase shifter for achieving 22.5°, 45° and 67.5° phase shifting, so as to solve the problem that the phase shifting unit for achieving 22.5°, 45° and 67.5° phase shifting in the prior art occupies a large volume.

[0006] On the one hand, an embodiment of the present invention provides a multi-phase integrated phase shift unit for achieving 22.5°, 45° and 67.5° phase shifts, the multi-phase integrated phase shift unit comprising a high-pass circuit, a first low-pass circuit and a second low-pass circuit connected in parallel with each other;

[0007] The on-off states of the first low-pass circuit and the second low-pass circuit are opposite; by controlling the on-off states of the high-pass circuit, the first low-pass circuit and the second low-pass circuit, the multi-phase integrated phase shifting unit realizes the following four phase shift states:

[0008] When only the first low-pass circuit is in the on state, a reference phase shift state of the multi-phase integrated phase shift unit is formed;

[0009] When only the second low-pass circuit is in the on state, a 22.5° phase shift state of the multi-phase integrated phase shift unit is formed;

[0010] When only the high-pass circuit and the first low-pass circuit are in the on state, a 45° phase shift state of the multi-phase integrated phase shift unit is formed;

[0011] When only the high-pass circuit and the second low-pass circuit are in the on state, a 67.5° phase shift state of the multi-phase integrated phase shift unit is formed.

[0012] Based on the further improvement of the above multi-phase integrated phase shifting unit, the high-pass circuit includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor and a second NMOS transistor connected in series;

[0013] The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage, and the first voltage is used to control the on-off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on-off state of the high-pass circuit;

[0014] The source of the first NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit;

[0015] The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor at the same time; the other end of the first inductor is grounded;

[0016] The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output end of the multi-phase integrated phase shift unit.

[0017] Based on a further improvement of the above multi-phase integrated phase shifting unit, the capacitances of the first capacitor and the second capacitor are equal.

[0018] Based on the further improvement of the above multi-phase integrated phase shifting unit, the first low-pass circuit and the second low-pass circuit have the same structure, and both include a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series;

[0019] The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage, and the second voltage is used to control the on-off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on-off state of the first low-pass circuit and the second low-pass circuit;

[0020] The source of the third NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit;

[0021] The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor at the same time, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor at the same time, and the other end of the fourth capacitor is grounded;

[0022] The drain of the fourth NMOS transistor serves as a signal output terminal of the multi-phase integrated phase shifting unit.

[0023] Based on the further improvement of the above multi-phase integrated phase shifting unit, the capacitance of the third capacitor and the fourth capacitor in the first low-pass circuit are equal, and the capacitance of the third capacitor and the fourth capacitor in the second low-pass circuit are equal;

[0024] The inductive reactance values ​​of the second inductors of the first low-pass circuit and the second low-pass circuit are not equal;

[0025] The capacitances of the third capacitors of the first low-pass circuit and the second low-pass circuit are not equal;

[0026] The capacitances of the fourth capacitors of the first low-pass circuit and the second low-pass circuit are not equal.

[0027] Based on the further improvement of the above multi-phase integrated phase shifting unit, the multi-phase integrated phase shifting unit further includes an inverter;

[0028] One end of the inverter is connected to the gates of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit;

[0029] The other end of the inverter is connected to gates of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

[0030] Based on the further improvement of the above multi-phase integrated phase shifting unit, the capacitances of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactances of the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit are determined by the following method:

[0031] Determine the circuit equivalent models of the multi-phase integrated phase shift unit in four phase shift states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0032] Construct constraint equations under four phase shift states, and solve the constraint equations to obtain the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit.

[0033] Based on the further improvement of the above multi-phase integrated phase shifting unit, the method of determining the amplitude ratio of the output signal to the input signal in each state and the phase change of the output signal to the input signal in each state according to the circuit equivalent model in each state includes:

[0034] Determine the cascade matrix of the circuit equivalent model in each state respectively, and convert the cascade matrix into an admittance matrix in the state;

[0035] Determine the insertion loss in this state according to the admittance matrix in this state;

[0036] According to the insertion loss in this state, the amplitude ratio of the output signal to the input signal in this state and the phase change amount of the output signal to the input signal are determined.

[0037] Based on the further improvement of the above multi-phase integrated phase shift unit, the constraint equations under the four phase shift states are constructed, including:

[0038] Phase LP2 -Phase LP1 =22.5°;

[0039] Phase HP+LP1 -Phase LP1 =45°;

[0040] phase HP+LP2 -Phase LP1 =67.5°;

[0041]

[0042]

[0043]

[0044]

[0045] Among them, Phase LP1 Phaswe LP2 、Phase HP+LP1 and phase HP+LP2 Respectively represent the phase changes of the output signal and the input signal in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state;

[0046] real(S21 LP1 )、real(S21 LP2 )、real(S21 HP+LP1 ) and real(S21 HP+LP2 ) represent the real parts of the insertion losses in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state and the 67.5° phase shift state respectively;

[0047] imag(S21 LP1 )、imag(S21 LP2 )、imag(S21 HP+LP1 ) and imag(S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state, respectively.

[0048] On the other hand, an embodiment of the present invention provides a phase shifter, the phase shifter comprising the above-mentioned multi-phase integrated phase shifting unit, and the phase shifter further comprising one or more of the following phase shifting units:

[0049] 5.625° phase shift unit;

[0050] 11.25° phase shift unit;

[0051] 90° phase shift unit;

[0052] 180° phase shift unit;

[0053] The phase shift unit is connected in series with the multi-phase integrated phase shift unit.

[0054] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0055] 1. Through a high-pass circuit and two low-pass circuits, combined with a double-pole triple-throw switch, a phase shift unit of 22.5°, 45° and 67.5° is formed, which occupies a small volume and saves costs;

[0056] 2. By determining the circuit equivalent model of the multi-phase integrated phase-shifting unit in four phase-shifting states, further determining the amplitude ratio of the output signal to the input signal in each state, and the phase change between the output signal and the input signal, constructing constraint equations in the four phase-shifting states, solving the constraint equations to obtain the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit and the fourth capacitor in the second low-pass circuit, and the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit, further reducing the volume of the multi-phase integrated phase-shifting unit and saving costs.

[0057] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0059] Figure 1 A schematic diagram of the structure of a multi-phase integrated phase shifting unit for achieving 22.5°, 45° and 67.5° phase shifting provided by an embodiment of the present invention;

[0060] Figure 2 A comparison diagram of the occupied volumes of the multi-phase integrated phase shifting unit for achieving 22.5°, 45° and 67.5° phase shifting provided in an embodiment of the present invention and the 22.5° and 45° combined phase shifting unit in the prior art.

[0061] Reference numerals:

[0062] ① High-pass circuit; ②- First low-pass circuit; ③ Second low-pass circuit. DETAILED DESCRIPTION

[0063] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0064] In a first aspect, a specific embodiment of the present invention discloses a multi-phase integrated phase shifting unit for achieving 22.5°, 45° and 67.5° phase shifting, such as Figure 1 As shown, the multi-phase integrated phase shifting unit includes a high-pass circuit ①, a first low-pass circuit ② and a second low-pass circuit ③ connected in parallel with each other;

[0065] The on-off states of the first low-pass circuit ② and the second low-pass circuit ③ are opposite; by controlling the on-off states of the high-pass circuit ①, the first low-pass circuit ② and the second low-pass circuit ③, the multi-phase integrated phase shifting unit realizes the following four phase shift states:

[0066] When only the first low-pass circuit ② is in the on state, a reference phase shift state of the multi-phase integrated phase shift unit is formed;

[0067] When only the second low-pass circuit ③ is in the on state, a 22.5° phase shift state of the multi-phase integrated phase shift unit is formed;

[0068] When only the high-pass circuit ① and the first low-pass circuit ② are in the on state, a 45° phase shift state of the multi-phase integrated phase shift unit is formed;

[0069] When only the high-pass circuit ① and the second low-pass circuit ③ are in the on state, a 67.5° phase shift state of the multi-phase integrated phase shift unit is formed.

[0070] Specifically, Figure 1 As shown, the multi-phase integrated phase shift unit for realizing 22.5°, 45° and 67.5° phase shift provided by the embodiment of the present invention has the IN terminal on the left serving as the signal input terminal of the multi-phase integrated phase shift unit, and the OUT terminal on the right serving as the signal output terminal of the multi-phase integrated phase shift unit. The signal is input from the IN terminal, passes through the high-pass circuit ①, the first low-pass circuit ② and the second low-pass circuit ③ connected in parallel, and is finally output from the OUT terminal.

[0071] Specifically, the on-off states of the first low-pass circuit ② and the second low-pass circuit ③ are opposite, that is, if the first low-pass circuit ② is in the on state, the second low-pass circuit ③ is in the off state; if the first low-pass circuit ② is in the off state, the second low-pass circuit ③ is in the on state.

[0072] Specifically, the on and off states of the high-pass circuit ① are independently controlled.

[0073] It is worth noting that by controlling the on-off states of the high-pass circuit ①, the first low-pass circuit ② and the second low-pass circuit ③, the multi-phase integrated phase shifting unit realizes four on-off states, which belongs to a 2-bit phase shifter:

[0074] The first type: when the first low-pass circuit ② is in the on state, and the high-pass circuit ① and the second low-pass circuit ③ are in the off state, this state is used as the reference phase shift state of the multi-phase integrated phase shift unit;

[0075] The second type: when the second low-pass circuit ③ is in the on state, and the high-pass circuit ① and the first low-pass circuit ② are in the off state, the state at this time serves as the 22.5° phase shift state of the multi-phase integrated phase shift unit;

[0076] The third type: when the high-pass circuit ① and the first low-pass circuit ② are in the on state, and the second low-pass circuit ③ is in the off state, the state at this time is used as the 45° phase shift state of the multi-phase integrated phase shift unit;

[0077] The fourth type: when the high-pass circuit ① and the second low-pass circuit ③ are in the on state, and the first low-pass circuit ② is in the off state, the state at this time serves as the 67.5° phase shift state of the multi-phase integrated phase shift unit.

[0078] It is worth noting that when using the multi-phase integrated phase shift unit for realizing 22.5°, 45° and 67.5° phase shift provided by the embodiment of the present invention, the number of multi-phase integrated phase shift units can be selected according to actual needs. For example, when only 22.5°, 45° or 67.5° phase shift is needed, two multi-phase integrated phase shift units can be selected, and one of the multi-phase integrated phase shift units can be kept in the reference phase shift state, while the other multi-phase integrated phase shift unit can be kept in the 22.5° phase shift state, 45° phase shift state or 67.5° phase shift state, that is, the phase difference of the output signals of the two multi-phase integrated phase shift units can be realized to be 22.5°, 45° or 67.5°, that is, the phase difference is relative to the reference phase shift state.

[0079] Preferably, if Figure 1 As shown, the high-pass circuit ① includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor and a second NMOS transistor connected in series;

[0080] The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage, and the first voltage is used to control the on-off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on-off state of the high-pass circuit ①;

[0081] The source of the first NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit;

[0082] The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor at the same time; the other end of the first inductor is grounded;

[0083] The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output end of the multi-phase integrated phase shift unit.

[0084] Preferably, if Figure 1 As shown, the capacitance of the first capacitor is equal to that of the second capacitor.

[0085] Specifically, Figure 1 As shown, the high-pass circuit ① includes, from left to right, a first NMOS transistor M51, a first capacitor C51, a first inductor L51, a second capacitor C51, and a second NMOS transistor M51. It is worth noting that the first NMOS transistor and the second NMOS transistor can be the same or different, as long as the first voltage VA can simultaneously control the on-off state of the two NMOS transistors. Figure 1 As shown, the two first NMOS transistors and the second NMOS transistors are the same. When the first voltage VA is at a high level, the first NMOS transistor and the second NMOS transistor are turned on at the same time. When the first voltage VA is at a low level, the first NMOS transistor and the second NMOS transistor are turned off at the same time.

[0086] Specifically, the capacitance of the first capacitor and the second capacitor are equal, that is, Figure 1 As shown, the first capacitor C51 and the second capacitor C51 are the same.

[0087] Specifically, when the first voltage VA is at a high level, the first NMOS transistor and the second NMOS transistor are turned on at the same time, so that the high-pass circuit ① is turned on, and the signal is output from the left side to the high-pass circuit ①, and is output from the right side through the high-pass circuit ①. When the first voltage VA is at a low level, the first NMOS transistor and the second NMOS transistor are turned off at the same time, so that the high-pass circuit ① is turned off, and the signal cannot pass through the high-pass circuit ①.

[0088] Preferably, if Figure 1 As shown, the first low-pass circuit and the second low-pass circuit have the same structure, and both include a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series;

[0089] The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage, and the second voltage is used to control the on-off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on-off state of the first low-pass circuit and the second low-pass circuit;

[0090] The source of the third NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit;

[0091] The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor at the same time, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor at the same time, and the other end of the fourth capacitor is grounded;

[0092] The drain of the fourth NMOS transistor serves as a signal output terminal of the multi-phase integrated phase shifting unit.

[0093] Preferably, the third capacitor and the fourth capacitor in the first low-pass circuit have the same capacitance, and the third capacitor and the fourth capacitor in the second low-pass circuit have the same capacitance;

[0094] The inductive reactance values ​​of the second inductors of the first low-pass circuit and the second low-pass circuit are not equal;

[0095] The capacitances of the third capacitors of the first low-pass circuit and the second low-pass circuit are not equal;

[0096] The capacitances of the fourth capacitors of the first low-pass circuit and the second low-pass circuit are not equal.

[0097] Specifically, Figure 1 As shown, the first low-pass circuit ② and the second low-pass circuit ③ include, from left to right, a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series with each other, that is, the first low-pass circuit ② and the second low-pass circuit ③ have the same composition structure.

[0098] It is worth noting that if Figure 1 As shown, the capacitance of the third capacitor C52 and the fourth capacitor C52 in the first low-pass circuit ② are equal, and the capacitance of the third capacitor C53 and the fourth capacitor C53 in the second low-pass circuit ③ are equal. That is, the third capacitor C52 and the fourth capacitor C52 in the first low-pass circuit ② are the same, and the third capacitor C53 and the fourth capacitor C53 in the second low-pass circuit ③ are the same.

[0099] It is worth noting that if Figure 1 As shown, the inductive reactance values ​​of the second inductors of the first low-pass circuit ② and the second low-pass circuit ③ are not equal;

[0100] The capacitance values ​​of the third capacitors of the first low-pass circuit ② and the second low-pass circuit ③ are not equal;

[0101] The capacitances of the fourth capacitors of the first low-pass circuit ② and the second low-pass circuit ③ are not equal.

[0102] That is, the second inductor L52 of the first low-pass circuit ② and the second inductor L53 of the second low-pass circuit ③ are different, the third capacitor C52 of the first low-pass circuit ② and the third capacitor C53 of the second low-pass circuit ③ are different, and the fourth capacitor C52 of the first low-pass circuit ② and the fourth capacitor C53 of the second low-pass circuit ③ are different.

[0103] Specifically, Figure 1As shown, the first low-pass circuit ② includes, from left to right, a third NMOS transistor, a third capacitor C52, a second inductor L52, a fourth capacitor C52 and a fourth NMOS transistor connected in series. It is worth noting that the third NMOS transistor and the fourth NMOS transistor can be the same or different, as long as the second voltage VB can simultaneously control the on-off state of the two NMOS transistors. Figure 1 As shown, the third NMOS transistor and the fourth NMOS transistor are the same. When the first voltage VB is at a high level, the third NMOS transistor and the fourth NMOS transistor are turned on at the same time. When the first voltage VB is at a low level, the third NMOS transistor and the fourth NMOS transistor are turned off at the same time. Specifically, when the second voltage VB is at a high level, the third NMOS transistor and the fourth NMOS transistor are turned on at the same time, so that the first low-pass circuit ② is turned on, and the signal is output from the left side to the first low-pass circuit ②, and is output from the right side through the first low-pass circuit ②. When the second voltage VB is at a low level, the third NMOS transistor and the fourth NMOS transistor are turned off at the same time, so that the first low-pass circuit ② is turned off, and the signal cannot pass through the first low-pass circuit ②.

[0104] Specifically, Figure 1 As shown, the second low-pass circuit ③ includes, from left to right, a third NMOS transistor, a third capacitor C53, a second inductor L53, a fourth capacitor C53 and a fourth NMOS transistor connected in series. It is worth noting that the third NMOS transistor and the fourth NMOS transistor can be the same or different, as long as the second voltage VB can simultaneously control the on-off state of the two NMOS transistors. Figure 1 As shown, the third NMOS transistor and the fourth NMOS transistor are the same. When the first voltage VB is at a high level, the third NMOS transistor and the fourth NMOS transistor are turned off at the same time. When the first voltage VB is at a low level, the third NMOS transistor and the fourth NMOS transistor are turned on at the same time. Specifically, when the second voltage VB is at a low level, the third NMOS transistor and the fourth NMOS transistor are turned on at the same time, so that the second low-pass circuit ③ is turned on, and the signal is output from the left side to the second low-pass circuit ③, and is output from the right side through the second low-pass circuit ③. When the second voltage VB is at a high level, the third NMOS transistor and the fourth NMOS transistor are turned off at the same time, so that the second low-pass circuit ③ is turned off, and the signal cannot pass through the second low-pass circuit ③.

[0105] Preferably, the multi-phase integrated phase shift unit further includes an inverter;

[0106] One end of the inverter is connected to the gates of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit;

[0107] The other end of the inverter is connected to gates of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

[0108] Specifically, one end of the inverter is connected to the gates of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit ②, and the other end is connected to the gates of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit ③, so that the second voltage VB can simultaneously control the on-off state of the first low-pass circuit ② and the second low-pass circuit ③, and make the on-off state of the first low-pass circuit ② and the second low-pass circuit ③ opposite.

[0109] Preferably, the capacitances of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit are determined in the following manner:

[0110] Determine the circuit equivalent models of the multi-phase integrated phase shift unit in four phase shift states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0111] Construct constraint equations under four phase shift states, and solve the constraint equations to obtain the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit.

[0112] Preferably, determining the amplitude ratio of the output signal to the input signal in each state, and the phase change amount between the output signal and the input signal in each state according to the circuit equivalent model in each state includes:

[0113] Determine the cascade matrix of the circuit equivalent model in each state respectively, and convert the cascade matrix into an admittance matrix in the state;

[0114] Determine the insertion loss in this state according to the admittance matrix in this state;

[0115] According to the insertion loss in this state, the amplitude ratio of the output signal to the input signal in this state and the phase change amount of the output signal to the input signal are determined.

[0116] Specifically, the multi-phase integrated phase shift unit includes four phase shift states:

[0117] The first type: when the first low-pass circuit ② is in the on state, and the high-pass circuit ① and the second low-pass circuit ③ are in the off state, this state is used as the reference phase shift state of the multi-phase integrated phase shift unit;

[0118] The second type: when the second low-pass circuit ③ is in the on state, and the high-pass circuit ① and the first low-pass circuit ② are in the off state, the state at this time serves as the 22.5° phase shift state of the multi-phase integrated phase shift unit;

[0119] The third type: when the high-pass circuit ① and the first low-pass circuit ② are in the on state, and the second low-pass circuit ③ is in the off state, the state at this time is used as the 45° phase shift state of the multi-phase integrated phase shift unit;

[0120] The fourth type: when the high-pass circuit ① and the second low-pass circuit ③ are in the on state, and the first low-pass circuit ② is in the off state, the state at this time serves as the 67.5° phase shift state of the multi-phase integrated phase shift unit.

[0121] The circuit equivalent model under each phase shift state is determined respectively, the cascade matrix of the circuit equivalent model under each state is determined according to the circuit equivalent model under the state, and the cascade matrix of the circuit equivalent model under the state is converted into the admittance matrix under the state.

[0122] Specifically, Figure 1 As shown, the cascade matrix of the first capacitor C51, the first inductor L51, and the second capacitor C51 in the multi-phase integrated phase shift unit is respectively:

[0123] The cascade matrix of the first capacitor C51 is:

[0124] The cascade matrix of the first inductor L51 is:

[0125] The cascade matrix of the second capacitor C51 is:

[0126] That is, the cascade matrix of the high-pass circuit is: A HP =HP1*HP2*HP3.

[0127] Specifically, Figure 1 As shown, the cascade matrix of the third capacitor C52, the second inductor L52, and the fourth capacitor C52 of the first low-pass circuit in the multi-phase integrated phase shift unit is respectively:

[0128] The cascade matrix of the third capacitor C52 of the first low-pass circuit is:

[0129]

[0130] The cascade matrix of the second inductor L52 of the first low-pass circuit is:

[0131]

[0132] The cascade matrix of the fourth capacitor C52 of the first low-pass circuit is:

[0133]

[0134] That is, the cascade matrix of the first low-pass circuit is: A LP1 =LP1*LP2*LP3.

[0135] Specifically, Figure 1 As shown, the cascade matrix of the third capacitor C53, the second inductor L53, and the fourth capacitor C53 of the second low-pass circuit in the multi-phase integrated phase shift unit is respectively:

[0136] The cascade matrix of the third capacitor C53 of the second low-pass circuit is:

[0137]

[0138] The cascade matrix of the second inductor L53 of the second low-pass circuit is:

[0139]

[0140] The cascade matrix of the fourth capacitor C53 of the second low-pass circuit is:

[0141]

[0142] That is, the cascade matrix of the second low-pass circuit is: A LP2 =LP4*LP5*LP6.

[0143] Where j is the imaginary unit and w is the angular frequency of the input signal.

[0144] Specifically, the cascade matrix of the high-pass circuit, the first low-pass circuit, and the second low-pass circuit is converted into an admittance matrix:

[0145] The admittance matrix of the high-pass circuit is:

[0146]

[0147] The admittance matrix of the first low-pass circuit is:

[0148]

[0149] The admittance matrix of the second low-pass circuit is:

[0150]

[0151] Then the admittance matrix of the multi-phase integrated phase shift unit in four phase shift states is:

[0152] In the first reference phase shift state, only the first low-pass circuit is turned on, and the circuit equivalent model only contains the first low-pass circuit. The admittance matrix of the first reference phase shift state is:

[0153]

[0154] In the second 22.5° phase shift state, only the second low-pass circuit is turned on, and the circuit equivalent model only includes the second low-pass circuit. The admittance matrix of the second 22.5° phase shift state is:

[0155]

[0156] In the third 45° phase shift state, only the high-pass circuit and the first low-pass circuit are turned on. The circuit equivalent model only contains the high-pass circuit and the first low-pass circuit. The admittance matrix of the third 45° phase shift state is:

[0157]

[0158] In the fourth 67.5° phase-shifted state, only the high-pass circuit and the second low-pass circuit are turned on. The circuit equivalent model only contains the high-pass circuit and the second low-pass circuit. The admittance matrix of the fourth 67.5° phase-shifted state is:

[0159]

[0160] Specifically, according to the admittance matrix in this state, the insertion loss in this state is determined:

[0161]

[0162] Among them, S21 represents the insertion loss, Y (1，1) , Y (1，2) , Y (2，1) and Y (2，2) They represent the elements in the admittance matrix under each phase shift state, and Z represents the characteristic impedance parameter of the circuit network.

[0163] Preferably, the constructing of constraint equations under four phase shift states includes:

[0164] Phase LP2 -Phase LP1 =22.5°;

[0165] Phase HP+LP1 -Phase LP1 =45°;

[0166] Phase HP+LP2 -Phase LP1 =67.5°;

[0167]

[0168]

[0169]

[0170]

[0171] Among them, Phase LP1 、Phase LP2 、Phase HP+LP1 and Phase HP+LP2 Respectively represent the phase changes of the output signal and the input signal in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state;

[0172] real(S21 LP1 )、real(S21 LP2 )、real(S21 HP+LP1 ) and real(S21 HP+LP2 ) represent the real parts of the insertion losses in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state and the 67.5° phase shift state respectively;

[0173] imag(S21 LP1 )、imag(S21 LP2 )、imag(S21 HP+LP1 ) and imag(S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state, respectively.

[0174] Specifically, the process of solving the constraint equation is to solve the multi-objective problem. The particle swarm algorithm can be used to select the final solution of the problem from the non-inferior solution set according to the actual problem. In addition, the ant colony algorithm, distribution estimation algorithm, co-evolution algorithm or evolutionary algorithm can also be used to solve the constraint equation.

[0175] Specifically, Figure 2 As shown, the left figure shows the volume of the combination of the 22.5° phase shift unit and the 45° phase shift unit in the prior art, and the right figure shows the volume of the multi-phase integrated phase shift unit for achieving 22.5°, 45° and 67.5° phase shifts provided by an embodiment of the present invention. It can be seen that the occupied volume is greatly reduced.

[0176] In a second aspect, a specific embodiment of the present invention discloses a phase shifter, wherein the phase shifter comprises the above-mentioned multi-phase integrated phase shifting unit, and the phase shifter further comprises one or more of the following phase shifting units:

[0177] 5.625° phase shift unit;

[0178] 11.25° phase shift unit;

[0179] 90° phase shift unit;

[0180] 180° phase shift unit;

[0181] The phase shift unit is connected in series with the multi-phase integrated phase shift unit.

[0182] Specifically, the phase shifter may include one or more phase shift units, and the phase shift unit may be a 5.625° phase shift unit, a 11.25° phase shift unit, a 90° phase shift unit or a 180° phase shift unit, as well as the multi-phase integrated phase shift unit provided in the first aspect of the present invention.

[0183] It is worth noting that the phase shifter provided in the embodiment of the second aspect of the present invention includes the multi-phase integrated phase shifter provided in the first aspect of the present invention, and the phase shifter provided in the embodiment of the second aspect of the present invention may also include a 5.625° phase shifter, a 11.25° phase shifter, a 90° phase shifter or a 180° phase shifter in the prior art. The specific phase shifter to be used is selected according to specific needs. For example, when it is necessary to achieve a 28.125° phase shift, a 50.625° phase shift or a 73.125° phase shift, the phase shifter includes the multi-phase integrated phase shifter provided in the first aspect of the present invention, and a 5.625° phase shifter.

[0184] Specifically, the multi-phase integrated phase shift unit for achieving 22.5°, 45° and 67.5° phase shifts provided in the embodiment of the present invention can be used in combination with one or more other phase shift units, such as a 5.625° phase shift unit, an 11.25° phase shift unit, a 90° phase shift unit and a 180° phase shift unit. The multi-phase integrated phase shift unit is connected in series with the other phase shift units to realize a multi-bit phase shifter.

[0185] When a 2-bit multi-phase integrated phase shift unit is connected in series with a 5.625° phase shift unit, an 11.25° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit, a 6-bit phase shifter can be formed. The 6-bit phase shifter can achieve a phase shift from 5.625° to 354.375°, 64 phase shift states, and each phase shift state is spaced 5.625° apart.

[0186] Exemplary: In a 6-bit phase shifter, a multi-phase integrated phase shift unit, a 5.625° phase shift unit, a 11.25° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit are connected in series. In this case, in the 6-bit phase shifter:

[0187] The multi-phase integrated phase shift unit has a 0° reference phase shift state, a 22.5° phase shift state, a 45° phase shift state and a 67.5° phase shift state;

[0188] The 5.625° phase shift unit has a 0° reference phase shift state and a 5.625° phase shift state;

[0189] The 11.25° phase shift unit° has a 0° reference phase shift state and an 11.25° phase shift state;

[0190] The 90° phase shift unit has a 0° reference phase shift state and a 90° phase shift state;

[0191] The 180° phase shift unit has a 0° reference phase shift state and a 180° phase shift state.

[0192] By controlling the states of each phase shift unit, phase shifts from 5.625° to 354.375° are achieved:

[0193] When a 5.625° phase shift needs to be achieved, a 5.625° phase shift unit in a 6-bit phase shifter is controlled to be in a 5.625° phase shift state, and other phase shift units are controlled to be in a 0° reference phase shift state, and all phase shift units in another 6-bit phase shifter are controlled to be in a 0° reference phase shift state to achieve a 5.625° phase shift;

[0194] When a 11.25° phase shift is required, the 11.25° phase shift unit in one 6-bit phase shifter is controlled to be in a 11.25° phase shift state, and the other phase shift units are controlled to be in a 0° reference phase shift state, and all phase shift units in another 6-bit phase shifter are controlled to be in a 0° reference phase shift state to achieve a 11.25° phase shift;

[0195] When a 16.875° phase shift is required, the 11.25° phase shift unit in one 6-bit phase shifter is controlled to be in a 11.25° phase shift state and the 5.625° phase shift unit is controlled to be in a 5.625° phase shift state, and the other phase shift units are controlled to be in a 0° reference phase shift state. All phase shift units in another 6-bit phase shifter are controlled to be in a 0° reference phase shift state to achieve a 16.875° phase shift.

[0196] …

[0197] Similarly, when a 354.375° phase shift needs to be achieved, the multi-phase integrated phase shift unit in a 6-bit phase shifter is controlled to be in a 67.5-degree phase shift state, the 5.625° phase shift unit is in a 5.625° phase shift state, the 11.25° phase shift unit is in a 11.25° phase shift state, the 90° phase shift unit is in a 90° phase shift state, and the 180° phase shift unit is in a 180° phase shift state, and all the phase shift units in another 6-bit phase shifter are controlled to be in a 0° reference phase shift state to achieve a 354.375° phase shift.

[0198] Compared with the prior art, the multi-phase integrated phase shift unit for realizing phase shifts of 22.5°, 45° and 67.5° provided in the embodiment of the present invention uses a high-pass circuit and two low-pass circuits, combined with a double-pole triple-throw switch to form a phase shift unit realizing 22.5°, 45° and 67.5°, which occupies a small volume and saves costs; at the same time, by determining the circuit equivalent model of the multi-phase integrated phase shift unit in four phase shift states, further determining the amplitude ratio of the output signal to the input signal in each state, and the phase change of the output signal to the input signal, constructing constraint equations in the four phase shift states, solving the constraint equations to obtain the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit, further reducing the volume of the multi-phase integrated phase shift unit and saving costs.

[0199] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-phase integrated phase shifting unit for achieving 22.5°, 45° and 67.5° phase shifting, characterized in that: The multi-phase integrated phase shifting unit comprises a high-pass circuit, a first low-pass circuit and a second low-pass circuit connected in parallel with each other; The on-off states of the first low-pass circuit and the second low-pass circuit are opposite; by controlling the on-off states of the high-pass circuit, the first low-pass circuit and the second low-pass circuit, the multi-phase integrated phase shifting unit realizes the following four phase shift states: When only the first low-pass circuit is in the on state, a reference phase shift state of the multi-phase integrated phase shift unit is formed; When only the second low-pass circuit is in the on state, a 22.5° phase shift state of the multi-phase integrated phase shift unit is formed; When only the high-pass circuit and the first low-pass circuit are in the on state, a 45° phase shift state of the multi-phase integrated phase shift unit is formed; When only the high-pass circuit and the second low-pass circuit are in the on state, a 67.5° phase shift state of the multi-phase integrated phase shift unit is formed.

2. The multi-phase integrated phase shifting unit according to claim 1, characterized in that: The high-pass circuit includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor and a second NMOS transistor connected in series; The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage, and the first voltage is used to control the on-off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on-off state of the high-pass circuit; The source of the first NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit; The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor at the same time; the other end of the first inductor is grounded; The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output end of the multi-phase integrated phase shift unit.

3. The multi-phase integrated phase shifting unit according to claim 2, characterized in that: The capacitance of the first capacitor is equal to that of the second capacitor.

4. The multi-phase integrated phase shifting unit according to claim 2, characterized in that: The first low-pass circuit and the second low-pass circuit have the same structure, and both include a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series; The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage, and the second voltage is used to control the on-off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on-off state of the first low-pass circuit and the second low-pass circuit; The source of the third NMOS transistor serves as a signal input terminal of the multi-phase integrated phase shift unit; The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor at the same time, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor at the same time, and the other end of the fourth capacitor is grounded; The drain of the fourth NMOS transistor serves as a signal output terminal of the multi-phase integrated phase shifting unit.

5. The multi-phase integrated phase shifting unit according to claim 4, characterized in that: The third capacitor and the fourth capacitor in the first low-pass circuit have the same capacitance, and the third capacitor and the fourth capacitor in the second low-pass circuit have the same capacitance; The inductive reactance values ​​of the second inductors of the first low-pass circuit and the second low-pass circuit are not equal; The capacitances of the third capacitors of the first low-pass circuit and the second low-pass circuit are not equal; The capacitances of the fourth capacitors of the first low-pass circuit and the second low-pass circuit are not equal.

6. The multi-phase integrated phase shifting unit according to claim 4, characterized in that: The multi-phase integrated phase shifting unit also includes an inverter; One end of the inverter is connected to the gates of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit; The other end of the inverter is connected to gates of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

7. The multi-phase integrated phase shifting unit according to claim 5, characterized in that: The capacitances of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactances of the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit are determined in the following manner: Determine the circuit equivalent models of the multi-phase integrated phase shift unit in four phase shift states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state; Construct constraint equations under four phase shift states, and solve the constraint equations to obtain the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the first inductor, the second inductor of the first low-pass circuit and the second inductor of the second low-pass circuit.

8. The multi-phase integrated phase shifting unit according to claim 7, characterized in that: The determining of the amplitude ratio of the output signal to the input signal in each state and the phase change between the output signal and the input signal in each state according to the circuit equivalent model in each state includes: Determine the cascade matrix of the circuit equivalent model in each state respectively, and convert the cascade matrix into an admittance matrix in the state; Determine the insertion loss in this state according to the admittance matrix in this state; According to the insertion loss in this state, the amplitude ratio of the output signal to the input signal in this state and the phase change amount of the output signal to the input signal are determined.

9. The multi-phase integrated phase shifting unit according to claim 8, characterized in that: The construction of constraint equations under four phase shift states includes: Phase LP2 -Phase LP1 =22.5°; Phase HP+LP1 -Phase LP1 =45°; phase HP+LP2 -Phase LP1 =67.5°; Among them, Phase LP1 、Phase LP2 、Phase HP+LP1 and phase HP+LP2 Respectively represent the phase changes of the output signal and the input signal in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state; real(S21 LP1 )、real(S21 LP2 )、real(S21 HP+LP1 ) and real(S21 HP+LP2 ) represent the real parts of the insertion losses in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state and the 67.5° phase shift state respectively; imag(S21 LP1 )、imag(S21 LP2 )、imag(S21 HP+LP1 ) and imag(S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state and 67.5° phase shift state, respectively.

10. A phase shifter, characterized in that: The phase shifter comprises the multi-phase integrated phase shifting unit according to any one of claims 1 to 9, and the phase shifter further comprises one or more of the following phase shifting units: 5.625° phase shift unit; 11.25° phase shift unit; 90° phase shift unit; 180° phase shift unit; The phase shift unit is connected in series with the multi-phase integrated phase shift unit.

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