Semiconductor circuit and intelligent power module

Abstract

The invention provides a semiconductor circuit and an intelligent power module. Comprising a first input stage circuit, a dead zone generation circuit, a pulse generation circuit, a level shift circuit, a first output circuit, a two-stage charge pump bootstrap circuit, a second input stage circuit, a low-side delay circuit, a second output circuit, an ITRIP protection circuit, a fault output circuit, an under-voltage protection circuit and a fault logic control circuit. The input end of the two-stage charge pump bootstrap circuit is used for being connected with a power supply, the output end of the two-stage charge pump bootstrap circuit is connected with the dead zone generation circuit, and the two-stage charge pump bootstrap circuit is used for providing a continuous power supply function; the ITRIP protection circuit and the under-voltage protection circuit are respectively connected with the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the fault output circuit, the first output circuit and the second output circuit. According to the semiconductor circuit, the applicability, reliability and market competitiveness of the intelligent power module can be improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a semiconductor circuit and an intelligent power module. Background Art

[0002] Intelligent Power Module, or IPM (Intelligent Power Module), is a power drive product that combines power electronics and integrated circuit technology. The intelligent power module integrates power switching devices and high-voltage drive circuits, and has built-in fault detection circuits such as overvoltage, overcurrent and overheating. On the one hand, the intelligent power module receives the control signal of the MCU to drive the subsequent circuit to work, and on the other hand, it sends the system status detection signal back to the MCU. Compared with traditional discrete solutions, the intelligent power module has won an increasingly large market with its advantages such as high integration and high reliability. It is especially suitable for frequency converters and various inverter power supplies that drive motors. It is an ideal power electronic device for variable frequency speed regulation, metallurgical machinery, electric traction, servo drive, and variable frequency home appliances.

[0003] The high-voltage side power supply of traditional intelligent power modules is floating, and the voltage changes with the bus voltage (V BUS ) increases. The voltage drop between the high-voltage side floating power supply and the floating ground must remain constant, and the potential of the high-voltage side floating ground will increase between zero and V BUS Therefore, the high-voltage side power supply of the chip needs to adopt an isolated power supply solution, and the high-voltage side power supply of the chip needs to have a certain ability to resist voltage transients. As we all know, batteries are the most commonly used isolated power supply, but the battery power is limited and cannot meet the long-term working requirements of the chip. At present, the bootstrap power supply method is the most commonly used power supply method on the high-voltage side of the intelligent power module, such as Figure 1 When the low-voltage side power tube Q2 is turned on, the potential of VS is pulled to zero potential. At this time, VCC is connected to the power supply through the bootstrap diode D boot To supply power to the bootstrap capacitor, when charging stops, C boot The voltage above is approximately equal to the voltage of VCC. When the low-voltage side power tube is turned off and the high-voltage side power tube is turned on, the potential of the Vs terminal will be quickly pulled to VBUS due to the opening of Q1. Since the voltage across the capacitor cannot change suddenly, the voltage of VCCA at this time is approximately equal to (V BUS +VCC), the capacitor acts as the power supply for the high voltage circuit of the battery. In the next cycle, when the lower tube Q2 is turned on, C boot It will be charged again to meet the power supply requirement when the high-voltage side power tube is turned on in the next cycle, and this process is repeated.

[0004] Therefore, the bootstrap power supply method can meet the continuous power supply of the high-voltage side circuit. In some applications, the power devices in the high-voltage area may be turned on for a long time, which will lead to insufficient voltage on the power supply capacitor in the high-voltage area, increase the size of the bootstrap capacitor, but increase the startup time of the system. During the normal operation of the system using the intelligent power module, due to the freewheeling effect of the inductive load, the source-drain voltage difference potential of the high-voltage side switch tube device is less than the output negative voltage. At this time, the bootstrap capacitor will be continuously charged by the bootstrap diode, and the voltage at both ends of it is very easy to exceed the maximum gate-source voltage value of the switch tube device, resulting in excessive gate-source voltage and damage to the switch tube, and poor reliability. Summary of the invention

[0005] The present invention provides a semiconductor circuit, aiming to solve the problem of poor reliability of the existing semiconductor circuit.

[0006] An embodiment of the present invention provides a semiconductor circuit, including: a first input stage circuit, a dead zone generating circuit, a pulse generating circuit, a level shifting circuit, a first output circuit, a two-stage charge pump bootstrap circuit, a second input stage circuit, a low-side delay circuit, a second output circuit, an ITRIP protection circuit, a fault output circuit, an undervoltage protection circuit, and a fault logic control circuit;

[0007] The first input stage circuit is used to receive a first input drive signal, the first input drive signal passes through the first input stage circuit, the dead zone generating circuit, the pulse generating circuit, the level shifting circuit and the first output circuit in sequence, and the first output circuit is used to output a high-side drive pulse signal;

[0008] The second input stage circuit is used to receive a second input drive signal, the second input drive signal passes through the second input stage circuit, the dead zone generating circuit, the low-side delay circuit and the second output circuit in sequence, and the second output circuit is used to output a low-side drive pulse signal;

[0009] The input end of the two-stage charge pump bootstrap circuit is used to connect to the power supply, the output end of the two-stage charge pump bootstrap circuit is connected to the dead zone generating circuit, and the two-stage charge pump bootstrap circuit is used to provide a continuous power supply function;

[0010] The ITRIP protection circuit and the undervoltage protection circuit are respectively connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the fault output circuit, the first output circuit and the second output circuit.

[0011] Preferably, the two-stage charge pump bootstrap circuit comprises: a bootstrap circuit, a third input stage circuit, a pulse generator, a low-side delay matching circuit, a high-voltage level shift circuit and a drive output circuit;

[0012] The input end of the bootstrap circuit is connected to the power supply, and the output end of the bootstrap circuit is connected to the high-voltage level shift circuit and the drive output circuit in sequence;

[0013] The input end of the third input stage circuit, the input end of the pulse generator and the input end of the low-side delay matching circuit are respectively connected to the power supply; the output end of the third input stage circuit is connected to the pulse generator, the low-side delay matching circuit and the drive output circuit in sequence; the pulse generator is also connected to the high-voltage level shifting circuit.

[0014] Preferably, the bootstrap circuit comprises: a first diode, a second diode, a third diode, a first capacitor, a second capacitor, a first resistor, a first MOS transistor and a second MOS transistor;

[0015] The anode of the first diode is connected to the power supply, and the cathode of the first diode is respectively connected to the first end of the first capacitor, the first end of the first resistor, and the anode of the second diode; the second end of the first capacitor is respectively connected to the anode of the third diode and the source of the second MOS tube, and the cathode of the third diode is respectively connected to the drain of the first MOS tube, the second end of the first resistor, and the gate of the second MOS tube, the source of the first MOS tube is grounded, and the gate of the first MOS tube is used to connect to the VPULSE port;

[0016] The drain of the second MOS tube is respectively connected to the first end of the second capacitor and the input end of the drive output circuit; the second end of the second capacitor is connected to the cathode of the second diode and the high-voltage level shift circuit.

[0017] Preferably, the drive output circuit comprises: a third capacitor, a voltage stabilizing diode, a third MOS transistor and a fourth MOS transistor;

[0018] The first end of the third capacitor is respectively connected to the cathode of the second diode and the cathode of the voltage regulator diode, and the second end of the third capacitor is respectively connected to the anode of the voltage regulator diode, the source of the third MOS tube and the drain of the fourth MOS tube; the gate of the third MOS tube is connected to the high-voltage level shifting circuit, and the drain of the third MOS tube is connected to the bus voltage; the gate of the fourth MOS tube is connected to the output end of the low-side delay matching circuit, and the source of the fourth MOS tube is grounded.

[0019] Compared with the prior art, the beneficial effect of the present invention lies in that, by using the first input stage circuit to receive the first input drive signal, the first input drive signal passes through the first input stage circuit, the dead zone generating circuit, the pulse generating circuit, the level shifting circuit and the first output circuit in sequence, and the first output circuit is used to output the high-side drive pulse signal; the second input stage circuit is used to receive the second input drive signal, the second input drive signal passes through the second input stage circuit, the dead zone generating circuit, the low-side delay circuit and the second output circuit in sequence, and the second output circuit is used to output the low-side drive pulse signal; the input end of the two-stage charge pump bootstrap circuit is used to connect to the power supply, the output end of the two-stage charge pump bootstrap circuit is connected to the dead zone generating circuit, and the two-stage charge pump bootstrap circuit is used to provide a continuous power supply function; the ITRIP protection circuit and the undervoltage protection circuit are respectively connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the fault output circuit, the first output circuit and the second output circuit. In this way, the intelligent power module integrating the two-stage charge pump bootstrap circuit HVIC and the upper bridge output clamp circuit can replenish the bootstrap capacitor when the high-voltage side circuit is continuously working, thereby achieving the purpose of long-term operation of the high-voltage side. The upper bridge output clamp circuit adds a clamp circuit at the upper bridge drive output stage to avoid damage caused by excessive gate-source voltage of the switching device, thereby protecting the switching device. This improves the applicability, reliability and market competitiveness of the intelligent power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0021] Figure 1 This is the circuit diagram of the traditional bootstrap power supply method;

[0022] Figure 2 is a circuit diagram of a semiconductor circuit provided by an embodiment of the present invention;

[0023] Figure 3 is a circuit diagram of a two-stage charge pump bootstrap circuit provided by an embodiment of the present invention;

[0024] Figure 4a is a schematic diagram of a charging mode of a two-stage charge pump bootstrap circuit provided by an embodiment of the present invention;

[0025] Figure 4b is a schematic diagram of a boost mode of a two-stage charge pump bootstrap circuit provided by an embodiment of the present invention;

[0026] Figure 4c It is a schematic diagram of a pumping mode of a two-stage charge pump bootstrap circuit provided in an embodiment of the present invention.

[0027] In the figure, 1. first input stage circuit, 2. dead zone generating circuit, 3. pulse generating circuit, 4. level shifting circuit, 5. first output circuit, 6. two-stage charge pump bootstrap circuit, 7. second input stage circuit, 8. low-side delay circuit, 9. second output circuit, 10. ITRIP protection circuit, 11. fault output circuit, 12. undervoltage protection circuit, 13. fault logic control circuit, 14. bootstrap circuit, 15. third input stage circuit, 16. pulse generator, 17. low-side delay matching circuit, 18. high-voltage level shifting circuit, 19. drive output circuit. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] Combined with Figure 2-Figure 3 As shown, an embodiment of the present invention provides a semiconductor circuit, including: a first input stage circuit 1, a dead zone generating circuit 2, a pulse generating circuit 3, a level shifting circuit 4, a first output circuit 5, a two-stage charge pump bootstrap circuit 6, a second input stage circuit 7, a low-side delay circuit 8, a second output circuit 9, an ITRIP protection circuit 10, a fault output circuit 11, an undervoltage protection circuit 12 and a fault logic control circuit 13;

[0030] The first input stage circuit 1 is used to receive a first input drive signal, and the first input drive signal passes through the first input stage circuit 1, the dead zone generating circuit 2, the pulse generating circuit 3, the level shifting circuit 4 and the first output circuit 5 in sequence, and the first output circuit 5 is used to output a high-side drive pulse signal;

[0031] The second input stage circuit 7 is used to receive a second input drive signal, the second input drive signal passes through the second input stage circuit 7, the dead zone generating circuit 2, the low-side delay circuit 8 and the second output circuit 9 in sequence, and the second output circuit 9 is used to output a low-side drive pulse signal;

[0032] The input end of the two-stage charge pump bootstrap circuit 6 is used to connect to the power supply VCC, the output end of the two-stage charge pump bootstrap circuit 6 is connected to the dead zone generating circuit 2, and the two-stage charge pump bootstrap circuit 6 is used to provide a continuous power supply function;

[0033] The ITRIP protection circuit 10 and the undervoltage protection circuit 12 are respectively connected to the input end of the fault logic control circuit 13, and the output end of the fault logic control circuit 13 is respectively connected to the fault output circuit 11, the first output circuit 5 and the second output circuit 9. The ITRIP protection circuit 10 is used for overcurrent protection.

[0034] Specifically, the input drive signals of HIN1, HIN2, and HIN3 (3-channel high-side drive circuits) pass through the first input stage circuit 1, the dead zone generating circuit 2, and the output OUT_H pulse signal. The pulse generating circuit 3 outputs SET and RESET short pulse signals respectively through the rising edge and falling edge of the OUT_H pulse signal, and realizes low-to-high voltage conversion through the level shifting circuit 4. The output circuit outputs the high-side drive pulse signal HO.

[0035] The input drive signals of LIN1, LIN2, and LIN3 (3-channel high-side drive circuits) pass through the second input stage circuit 7, the dead zone generating circuit 2, and the output OUT_L pulse signal; through the low-side delay circuit 8, the consistency of the high-side and low-side drive signals is achieved, and the output circuit outputs the low-side drive pulse signal LO.

[0036] VPULSE is the control signal of the two-stage charge pump bootstrap circuit 6. The control signal of the two-stage charge pump circuit is independent of the chip input signal, and its refresh frequency does not change with the input of the high-voltage gate driver chip of the switching tube. It can replenish the power of the bootstrap capacitor on the high-voltage side when VS is at a high level, ensuring that the high-voltage side power supply will not be exhausted due to the static current of the high-voltage side circuit.

[0037] The outputs of the driving signals HO and LO are protected by an undervoltage protection circuit 12, an ITRIP protection circuit 10, and a fault logic circuit. The fault output circuit 11 is used to output a fault signal.

[0038] Specifically, the first input stage circuit 1 is used to receive the first input drive signal, the first input drive signal passes through the first input stage circuit 1, the dead zone generating circuit 2, the pulse generating circuit 3, the level shifting circuit 4 and the first output circuit 5 in sequence, and the first output circuit 5 is used to output a high-side drive pulse signal; the second input stage circuit 7 is used to receive the second input drive signal, the second input drive signal passes through the second input stage circuit 7, the dead zone generating circuit 2, the low-side delay circuit 8 and the second output circuit 9 in sequence, and the second output circuit 9 is used to output a low-side drive pulse signal; the input end of the two-stage charge pump bootstrap circuit 6 is used to connect to the power supply VCC, the output end of the two-stage charge pump bootstrap circuit 6 is connected to the dead zone generating circuit 2, and the two-stage charge pump bootstrap circuit 6 is used to provide a continuous power supply function; the ITRIP protection circuit 10 and the undervoltage protection circuit 12 are respectively connected to the input end of the fault logic control circuit 13, and the output end of the fault logic control circuit 13 is respectively connected to the fault output circuit 11, the first output circuit 5 and the second output circuit 9. In this way, the intelligent power module integrating the two-stage charge pump bootstrap circuit 6HVIC and the upper bridge output clamp circuit can replenish the bootstrap capacitor when the high-voltage side circuit is continuously working, thereby achieving the purpose of long-term operation of the high-voltage side. The upper bridge output clamp circuit adds a clamp circuit at the upper bridge drive output stage to avoid damage caused by excessive gate-source voltage of the switching device, thereby protecting the switching device. This improves the applicability, reliability and market competitiveness of the intelligent power module.

[0039] In this embodiment, the two-stage charge pump bootstrap circuit 6 includes: a bootstrap circuit 14, a third input stage circuit 15, a pulse generator 16, a low-side delay matching circuit 17, a high-voltage level shift circuit 18 and a drive output circuit 19;

[0040] The input end of the bootstrap circuit 14 is connected to the power supply VCC, and the output end of the bootstrap circuit is connected to the high-voltage level shift circuit 18 and the drive output circuit 19 in sequence;

[0041] The input end of the third input stage circuit 15, the input end of the pulse generator 16 and the input end of the low-side delay matching circuit 17 are respectively connected to the power supply VCC; the output end of the third input stage circuit 15 is connected to the pulse generator 16, the low-side delay matching circuit 17 and the drive output circuit 19 in sequence; the pulse generator 16 is also connected to the high-voltage level shifting circuit 18.

[0042] In this embodiment, the bootstrap circuit 14 includes: a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a first resistor R1, a first MOS transistor S1 and a second MOS transistor S2;

[0043] The anode of the first diode D1 is connected to the power supply VCC, and the cathode of the first diode D1 is respectively connected to the first end of the first capacitor C1, the first end of the first resistor R1, and the anode of the second diode D2; the second end of the first capacitor C1 is respectively connected to the anode of the third diode D3 and the source of the second MOS transistor S2, and the cathode of the third diode D3 is respectively connected to the drain of the first MOS transistor S1, the second end of the first resistor R1, and the gate of the second MOS transistor S2; the source of the first MOS transistor S1 is grounded, and the gate of the first MOS transistor S1 is used to connect to the VPULSE port;

[0044] The drain of the second MOS transistor S2 is connected to the first end of the second capacitor C2 and the input end of the drive output circuit 19 respectively; the second end of the second capacitor C2 is connected to the cathode of the second diode D2 and the high-voltage level shift circuit 18.

[0045] In this embodiment, the driving output circuit 19 includes: a third capacitor C3, a voltage stabilizing diode ZD1, a third MOS transistor GaN FET1 and a fourth MOS transistor GaN FET2;

[0046] The first end of the third capacitor C3 is respectively connected to the cathode of the second diode D2 and the cathode of the voltage stabilizing diode ZD1, and the second end of the third capacitor C3 is respectively connected to the anode of the voltage stabilizing diode ZD1, the source of the third MOS tube GaN FET1 and the drain of the fourth MOS tube GaN FET2; the gate of the third MOS tube GaN FET1 is connected to the high-voltage level shift circuit 18, and the drain of the third MOS tube GaN FET1 is connected to the bus voltage V BUS ; The gate of the fourth MOS tube GaN FET2 is connected to the output end of the low-side delay matching circuit 17, and the source of the fourth MOS tube GaN FET2 is grounded.

[0047] Among them, the gates of the GaN power devices of the third MOS tube GaN FET1 and the fourth MOS tube GaN FET2 are extremely fragile, and excessive gate voltage can easily cause excessive leakage of the GaN device or even permanent damage. However, significantly reducing its gate drive voltage cannot give full play to the excellent characteristics of the GaN power device. Therefore, to prevent the gate breakdown of the GaN device caused by overcharging of the bootstrap capacitor, the high-voltage side power supply circuit needs a corresponding clamping protection circuit to ensure that when the VS negative voltage comes, the voltage on the bootstrap capacitor will not increase, so as to ensure that the gate of the GaN power device is not broken down.

[0048] In specific implementation, the two-stage charge pump bootstrap circuit 6 replenishes the bootstrap capacitor when the high-voltage side circuit continues to work. Thereby achieving the purpose of long-term operation of the high-voltage side. Its basic principle consists of two stages. In the first stage, the charge pump circuit charges the capacitor therein and stores energy on the capacitor; the second stage is to connect the capacitor to the part that needs power supply. Since its basic principle is to use the capacitor to act as a battery, it can also be floating to meet the power supply requirements of the high-voltage side of the driver chip.

[0049] The power supply VCC of HVIC is connected to the anode of the first diode D1, the cathode of the first diode D1, one end of the first capacitor C1, one end of the first resistor R1 and the anode of the second diode D2 are connected, and the cathode of the second diode D2 is connected to one end of the second capacitor C2, which is recorded as VCCA.

[0050] The other end of the first capacitor C1, the anode of the third diode D3 and the S pole of the second MOS tube S2 are connected together, and the D pole of the second MOS tube is connected to the other end of the second capacitor C2 and connected to VS.

[0051] The cathode of the third diode D3, the other end of the first resistor R1, the B pole of the second MOS transistor S2 and the D pole of the first MOS transistor S1 are connected.

[0052] The S pole of the first MOS tube S1 is connected to GND, and the B pole of the first MOS tube S1 is led out as VPULSE.

[0053] The two-stage charge pump bootstrap circuit 6 is mainly composed of a high-voltage first MOS tube S1, a second MOS tube S2, a first capacitor C1, a second capacitor C2, a first resistor R1, a high-voltage first diode D1, a second diode D2 and a common third diode D3; its working process can be divided into the following three modes: charging, boosting and pumping mode, Figure 4a-4c A simplified model showing the charge, boost and pump modes and how each stage works:

[0054] (1) Charging mode Figure 4a : In this mode, the high-voltage first MOS transistor S1 is turned on, and VCC charges the first capacitor C1 through the first diode D1 and the third diode D3. At this time, since the gate-source voltage of the second MOS transistor S2 is clamped to a negative value by the third diode D3, the second MOS transistor S2 is in a cut-off state. The third diode D3 can use a Schottky diode to minimize its voltage drop and conduction loss.

[0055] (2) Boost mode such as Figure 4b: When the first MOS tube S1 is turned off, the charging loop of the first capacitor C1 is disconnected, and the first capacitor C1 starts to charge the gate of the second MOS tube S2 through the first resistor R1. Since the capacitance value of the first capacitor C1 is much larger than the gate capacitance of the second MOS tube S2, the voltage change on the first capacitor C1 can be ignored. As the gate-source voltage of the second MOS tube S2 rises, the second MOS tube S2 is turned on, and the lower plate of the first capacitor C1 is connected to the floating ground of the high-voltage side. Since the voltage across the capacitor cannot change suddenly, the voltage of the upper plate of the first capacitor C1 will be higher than the voltage of VS by about VCC. The turn-on delay time of the second MOS tube S2 can be controlled by controlling the size of the first resistor R1, and when the gate capacitance of the second MOS tube S2 is charged, there will be no more current flowing through the first resistor R1, so the loss on the first resistor R1 is extremely small.

[0056] Pumping mode Figure 4c : When the second MOS tube S2 is fully turned on, the charge on the first capacitor C1 is transferred to the second capacitor C2, which serves as the high-voltage side power supply for the GaN high-voltage gate driver chip. When the external signal controls the first MOS tube S1 to turn on, due to the clamping effect of the third diode D3, the gate-source voltage of the second MOS tube S2 becomes negative, and the second MOS tube S2 is turned off, and then it returns to the charging mode.

[0057] The control signal VPULSE of the two-stage charge pump circuit is independent of the chip input signal, and its refresh frequency does not change with the input of the switching tube (GaN) high-voltage gate driver chip. It can replenish the power of the bootstrap capacitor on the high-voltage side when VS is at a high level, ensuring that the high-voltage side power supply will not be exhausted due to the static current of the high-voltage side circuit.

[0058] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0059] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A semiconductor circuit, characterized in that: include: A first input stage circuit, a dead zone generating circuit, a pulse generating circuit, a level shifting circuit, a first output circuit, a two-stage charge pump bootstrap circuit, a second input stage circuit, a low-side delay circuit, a second output circuit, an ITRIP protection circuit, a fault output circuit, an undervoltage protection circuit, and a fault logic control circuit; The first input stage circuit is used to receive a first input drive signal, the first input drive signal passes through the first input stage circuit, the dead zone generating circuit, the pulse generating circuit, the level shifting circuit and the first output circuit in sequence, and the first output circuit is used to output a high-side drive pulse signal; The second input stage circuit is used to receive a second input drive signal, the second input drive signal passes through the second input stage circuit, the dead zone generating circuit, the low-side delay circuit and the second output circuit in sequence, and the second output circuit is used to output a low-side drive pulse signal; The input end of the two-stage charge pump bootstrap circuit is used to connect to the power supply, the output end of the two-stage charge pump bootstrap circuit is connected to the dead zone generating circuit, and the two-stage charge pump bootstrap circuit is used to provide a continuous power supply function; The ITRIP protection circuit and the undervoltage protection circuit are respectively connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the fault output circuit, the first output circuit and the second output circuit.

2. The semiconductor circuit according to claim 1, wherein: The two-stage charge pump bootstrap circuit comprises: a bootstrap circuit, a third input stage circuit, a pulse generator, a low-side delay matching circuit, a high-voltage level shift circuit and a drive output circuit; The input end of the bootstrap circuit is connected to the power supply, and the output end of the bootstrap circuit is connected to the high-voltage level shift circuit and the drive output circuit in sequence; The input end of the third input stage circuit, the input end of the pulse generator and the input end of the low-side delay matching circuit are respectively connected to the power supply; the output end of the third input stage circuit is connected to the pulse generator, the low-side delay matching circuit and the drive output circuit in sequence; the pulse generator is also connected to the high-voltage level shifting circuit.

3. The semiconductor circuit according to claim 2, wherein: The bootstrap circuit comprises: a first diode, a second diode, a third diode, a first capacitor, a second capacitor, a first resistor, a first MOS transistor and a second MOS transistor; The anode of the first diode is connected to the power supply, and the cathode of the first diode is respectively connected to the first end of the first capacitor, the first end of the first resistor, and the anode of the second diode; the second end of the first capacitor is respectively connected to the anode of the third diode and the source of the second MOS tube, and the cathode of the third diode is respectively connected to the drain of the first MOS tube, the second end of the first resistor, and the gate of the second MOS tube, the source of the first MOS tube is grounded, and the gate of the first MOS tube is used to connect to the VPULSE port; The drain of the second MOS tube is respectively connected to the first end of the second capacitor and the input end of the drive output circuit; the second end of the second capacitor is connected to the cathode of the second diode and the high-voltage level shift circuit.

4. The semiconductor circuit according to claim 3, wherein: The drive output circuit comprises: a third capacitor, a voltage stabilizing diode, a third MOS transistor and a fourth MOS transistor; The first end of the third capacitor is respectively connected to the cathode of the second diode and the cathode of the voltage regulator diode, and the second end of the third capacitor is respectively connected to the anode of the voltage regulator diode, the source of the third MOS tube and the drain of the fourth MOS tube; the gate of the third MOS tube is connected to the high-voltage level shifting circuit, and the drain of the third MOS tube is connected to the bus voltage; the gate of the fourth MOS tube is connected to the output end of the low-side delay matching circuit, and the source of the fourth MOS tube is grounded.

5. An intelligent power module, characterized in that: Comprising a semiconductor circuit as claimed in any one of claims 1 to 4.

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