Demodulator circuit and rotary digital converter

Abstract

The invention discloses a demodulation circuit and a rotary digital converter, and relates to the technical field of rotary digital converters, and the demodulation circuit is composed of a peak detection circuit and a phase discrimination loop. The peak detection circuit is used for extracting an envelope waveform in an input rotary transformer input signal and demodulating the envelope waveform to obtain rotor information; and the phase discrimination loop is used for identifying phase information of the accessed rotary transformer input signal, determining an offset error, generating a sampling clock and a synchronous clock according to the offset error, transmitting the sampling clock and the synchronous clock into the peak detection circuit, correcting an envelope waveform, assisting the peak detection circuit through the phase discrimination loop, and outputting the corrected envelope waveform. Therefore, the gain of the envelope waveform extracted by the peak detection circuit is improved, the signal-to-noise ratio is improved, and the demodulation effect and demodulation accuracy of the envelope waveform are improved.

Description

Technical Field

[0001] The present application relates to the technical field of rotary digital converters, and in particular to a demodulation circuit and a rotary digital converter. Background Art

[0002] To achieve demodulation inside the rotary digital converter, the maximum amplitude of the sine signal and the cosine signal within one excitation cycle are extracted to obtain an envelope signal with the best signal-to-noise ratio. The input shaft angle related to the demodulation result is obtained through the envelope signal.

[0003] However, extracting the maximum amplitude of the signal of the excitation cycle is related to the position of the zero-crossing point of an excitation cycle. If there is an excitation cycle whose zero-crossing data at time zero is positive or negative, that is, the zero-crossing data obtained in an excitation cycle corresponds to a position on the excitation cycle that is not the zero point of the excitation cycle, then it means that there is a deviation in the excitation cycle, and the acquisition of the sine signal and cosine signal corresponding to the excitation cycle has the problem of low signal-to-noise ratio of the extracted envelope signal and inaccurate demodulation result. Summary of the invention

[0004] The main purpose of the present application is to provide a demodulation circuit and a rotary digital converter, aiming to solve the technical problem that when there is a deviation in an excitation cycle, the signal-to-noise ratio of the extracted envelope signal is low.

[0005] To achieve the above object, the present application proposes a demodulation circuit, which is composed of a peak detection circuit and a phase detection loop; The peak detection circuit is used to extract the envelope waveform of the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; The phase detection loop is used to identify the phase information of the input signal of the connected resolver. After determining the offset error, the sampling clock and the synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are transmitted to the peak detection circuit to correct the envelope waveform. Wherein, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor and a four-quadrant inverse tangent module; The input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor; and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor; The envelope extractor outputs a sine envelope waveform based on the connected sine resolver input digital signal, and outputs a cosine envelope waveform based on the connected cosine resolver input digital signal; The four-quadrant inverse tangent module outputs the quadrant phases of the sine envelope waveform and the cosine envelope waveform according to the connected sine envelope waveform and the cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phases; The phase detection loop includes a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator and a clock generation module; The first phase detector and the second phase detector are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to perform phase identification on the sine resolver input digital signal and the cosine resolver input signal, and output phase information; The first phase detector and the second phase detector are connected to a four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; The first phase detector and the second phase detector are also connected to a sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; The sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs the sampling clock and the synchronization clock to the envelope extractor according to the phase offset connected.

[0006] In one embodiment, the four-quadrant adder includes a multiplexer, a first inverter, a second inverter, a first adder, and a gain device; The first input end of the multiplexer is connected to the output end of the first phase detector, and the second input end of the multiplexer is connected to the output end of the first phase detector via the first inverter; The third input terminal of the multiplexer is connected to the output terminal of the second phase detector, and the fourth input terminal of the multiplexer is connected to the output terminal of the second phase detector via the second inverter; The output end of the multiplexer is connected to the first adder, and the output end of the first adder is connected to the gain device.

[0007] In one embodiment, the sampling phase accumulator includes a second adder and a unit delay; The input end of the second adder is connected to the output end of the gain device, and the output end of the second adder is connected to the input end of the unit delay device; The output end of the unit delayer is connected to the input end of the clock generation module and the input end of the second adder respectively.

[0008] In one embodiment, the clock generation module includes a plurality of phase branches and an OR gate, and the plurality of phase branches constitute an excitation cycle; Each phase branch is respectively connected to a phase offset, and the phase offset is compared with the phase point in each phase branch. When the comparison shows that the phase offset is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset belongs is output as a sampling clock through an OR gate.

[0009] In one embodiment, if there is a phase offset equal to any zero-crossing point, the comparison result of the phase branch where any zero-crossing point is located is output as the synchronous clock.

[0010] In one embodiment, the demodulation circuit is specifically used for: Performing equal-interval sampling operation or non-equal-interval sampling operation on a magnetizing cycle according to a sampling clock through a peak detection circuit to obtain a plurality of initial sampling signals, wherein the plurality of initial sampling signals include a sampling signal at zero time; Based on the phase detection loop, the sampling signal at zero time is subtracted to obtain phase information, and according to the positive and negative conditions reflected by the phase information, the position information between the sampling position corresponding to the sampling signal at zero time and the zero point position on an excitation cycle is obtained; The sampling clock is adjusted according to the position information to obtain the target sampling clock. Based on the target sampling clock, multiple samplings are performed on an excitation cycle to obtain multiple target sampling signals. Then, the sine envelope waveform and cosine envelope waveform of the electromagnetic induction differential output signal belonging to an excitation cycle are extracted according to the target sampling signal.

[0011] In one embodiment, the demodulation circuit is specifically used for: When the phase information is determined to be a positive difference based on the positive and negative conditions, a first position relationship in which the sampling position lags behind the zero-crossing position of an excitation cycle is obtained based on the positive difference, and a first distance relationship between the sampling position and the zero-crossing position is obtained based on the first absolute value of the positive difference, wherein the first position relationship and the first distance relationship are position information.

[0012] According to the first position relationship and the first distance relationship, the time period reflected by the first time interval is adjusted earlier on the basis of the sampling clock to obtain a sine envelope waveform and a cosine envelope waveform.

[0013] In one embodiment, the demodulation circuit is specifically used for: When the phase information is determined to be a negative difference based on the positive and negative conditions, a second position relationship in which the sampling position is ahead of the zero-crossing position by one excitation cycle is obtained based on the negative difference, and a second distance relationship between the sampling position and the zero-crossing position is obtained based on the second absolute value of the negative difference, wherein the second position relationship and the second distance relationship are position information.

[0014] According to the second position relationship and the second distance relationship, the time period reflected by the second time interval is delayed on the basis of the sampling clock to obtain a sine envelope waveform and a cosine envelope waveform.

[0015] In one embodiment, the demodulation circuit is specifically used for: The sum of the sampling signal at the target zero point and the sampling signal at the target non-zero point is calculated, and the sine envelope waveform and the cosine envelope waveform are output; or the sum of the sampling signals at the target non-zero point is calculated, and the sine envelope waveform and the cosine envelope waveform are output.

[0016] In addition, to achieve the above objective, the present application also proposes a rotational digital converter, which includes the demodulation circuit as described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: A demodulation circuit is proposed, which consists of a peak detection circuit and a phase detection loop; the peak detection circuit is used to extract the envelope waveform from the incoming resolver input signal, and demodulate the envelope waveform to obtain rotor information; the phase detection loop is used to identify the phase information of the connected resolver input signal, and after determining the offset error, generate a sampling clock and a synchronization clock according to the offset error, and transmit the sampling clock and the synchronization clock to the peak detection circuit to correct the envelope waveform; wherein the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor and a four-quadrant inverse tangent module; the input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor, and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor; the envelope extractor outputs a sine envelope waveform based on the connected sine resolver input digital signal, and outputs a cosine envelope waveform based on the connected cosine resolver input digital signal; the four-quadrant inverse tangent module The limited inverse tangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the connected sine envelope waveform and the cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phase; the phase detection loop comprises a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator and a clock generation module; the first phase detector and the second phase detector are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to perform phase identification on the sine resolver input digital signal and the cosine resolver input signal, and output phase information; the first phase detector and the second phase detector are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; the first phase detector and the second phase detector are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output the phase offset according to the phase information and the phase error information; the sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs the sampling clock and the synchronization clock to the envelope extractor according to the connected phase offset.

[0018] A demodulation circuit designed in the present application uses a phase-locked loop to assist a peak detection circuit, thereby improving the gain of the envelope waveform extracted by the peak detection circuit, thereby improving the signal-to-noise ratio, and further improving the demodulation effect and demodulation accuracy of the envelope waveform. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 This is a schematic diagram of the structure of the demodulation circuit of this application; Figure 2 Schematic diagram of the correct waveform output for rotor position phase detection; Figure 3 This is a schematic diagram of the correct waveform of the detection output after the rotor position phase is corrected; Figure 4 This is a schematic diagram of the structure of the four-quadrant adder of the present application; Figure 5 This is a schematic diagram of the structure of the sampling phase accumulator of this application; Figure 6 This is a schematic diagram of the structure of the clock generation module of this application; Figure 7 It is a waveform diagram of equally spaced sampling in one excitation cycle; Figure 8 It is a waveform diagram of non-equal interval sampling in one excitation cycle; Fig. 9 Schematic diagram of the waveform of an excitation cycle with different phases on the coordinate axis.

[0022] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0024] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0025] The main solution of the embodiment of the present application is: a demodulation circuit is proposed, which consists of a peak detection circuit and a phase detection loop; the peak detection circuit is used to extract the envelope waveform in the incoming resolver input signal, and demodulate the envelope waveform to obtain rotor information; the phase detection loop is used to identify the phase information of the connected resolver input signal, and after determining the offset error, generate a sampling clock and a synchronization clock according to the offset error, and transmit the sampling clock and the synchronization clock to the peak detection circuit to correct the envelope waveform; wherein the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor and a four-quadrant inverse tangent module; the input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor, and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor; the envelope extractor outputs a sine envelope waveform based on the connected sine resolver input digital signal, and outputs a cosine resolver input digital signal based on the connected cosine resolver input digital signal. The four-quadrant inverse tangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the connected sine envelope waveform and the cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phase; the phase detection loop includes a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator and a clock generation module; the first phase detector and the second phase detector are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to phase the sine resolver input digital signal and the cosine resolver input signal. identification, and outputting phase information; the first phase detector and the second phase detector are connected to a four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; the first phase detector and the second phase detector are also connected to a sampling phase accumulator, and the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; the sampling phase accumulator is connected to a clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the connected phase offset.

[0026] To achieve demodulation inside the rotary digital converter, the maximum amplitude of the sine signal and cosine signal in each excitation cycle is extracted to extract the envelope signal with the best signal-to-noise ratio, and the input shaft angle related to the demodulation result is obtained through the envelope signal. However, the maximum amplitude of the signal in the excitation cycle is extracted, which is related to the position of the zero point of an excitation cycle. If there is an excitation cycle with a zero-crossing data at zero time that is positive or negative, that is, the zero-crossing data obtained in an excitation cycle corresponds to a position on the excitation cycle that is not the zero point position of the excitation cycle, it means that there is a deviation in an excitation cycle. The acquisition of the sine signal and cosine signal corresponding to the excitation cycle has the problem of low signal-to-noise ratio of the extracted envelope signal and inaccurate demodulation results.

[0027] The present application provides a solution, which improves the gain of the envelope waveform extracted by the peak detection circuit through a phase-locked loop, thereby improving the signal-to-noise ratio and further improving the demodulation effect and demodulation accuracy of the envelope waveform.

[0028] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, etc. The following takes the rotation digitizer as an example to illustrate this embodiment and the following embodiments.

[0029] The present application embodiment proposes a method for extracting an envelope signal, referring to Figure 1 As shown, Figure 1 The demodulation circuit for this application is composed of a peak detection circuit and a phase detection loop; The peak detection circuit is used to extract the envelope waveform of the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; the phase detection loop is used to identify the phase information of the connected resolver input signal, and after determining the offset error, generate a sampling clock and a synchronization clock according to the offset error, and transmit the sampling clock and the synchronization clock to the peak detection circuit to correct the envelope waveform.

[0030] The peak detection circuit includes a first analog-to-digital converter (i.e. Figure 1 ADC1 in the second analog-to-digital converter (i.e. Figure 1ADC2 in the embodiment, envelope extractor and four-quadrant inverse tangent module; the input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor, and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor; the envelope extractor outputs a sine envelope waveform based on the connected sine resolver input digital signal, and outputs a cosine envelope waveform based on the connected cosine resolver input digital signal; the four-quadrant inverse tangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the connected sine envelope waveform and the cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phase. Among them, in addition to SAR ADC (Successive Approximation Register Analog-to-Digital Converter, successive approximation register analog-to-digital converter), the first analog-to-digital converter and the second analog-to-digital converter can also use Incremental Delta-Sigma ADC (incremental triangle modulation analog-to-digital converter) and the like. The four-quadrant inverse tangent module can be implemented by quadrant judgment plus inverse tangent CORDIC (Coordinate Rotation Digital Computer), or by four-quadrant inverse tangent CORDIC. This application does not limit the implementation method of the four-quadrant inverse tangent module.

[0031] The phase detection loop comprises a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator and a clock generation module; the first phase detector and the second phase detector are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to perform phase identification on the sine resolver input digital signal and the cosine resolver input signal, and output phase information; the first phase detector and the second phase detector are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; the first phase detector and the second phase detector are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; the sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the connected phase offset.

[0032] according to Figure 1 It can be seen from the demodulation circuit shown that the demodulation circuit proposed in the present application is composed of a peak detection circuit and a phase detection loop, wherein the peak detection circuit can demodulate the rotor information such as the phase and speed of the rotor by extracting the envelope waveform of the resolver input signal. The phase detection loop identifies the offset error of the phase information such as the zero crossing point, and generates a sampling clock and a synchronization clock for correcting the envelope waveform in the peak detection circuit.

[0033] It should be noted that the resolver input signal includes a sinusoidal signal and cosine signal , whose expressions correspond to expression ① and expression ② respectively.

[0034] ————Expression ① ————Expression ② in, is the input shaft angle, The two electromagnetic induction differential output signals generated on the secondary winding are modulated by the corresponding input shaft angle, specifically, the sine signal, cosine signal, excitation signal, and the sine envelope signal extracted based on the sine signal and cosine signal. and cosine envelope signal like Figure 2 and Figure 3 shown.

[0035] in, Figure 2 When the excitation phase is 0°, the rotor position phase output is correct. As can be seen from the top figure, since the position of the zero crossing point is relatively accurate, the output amplitude of the analog-to-digital converter can match the input amplitude of the analog-to-digital converter at this time, so the amplitude of the envelope signal obtained is large and the signal-to-noise ratio is high (middle figure). The rotor position phase detection output obtained in this way is correct, that is, the demodulation effect is good. It should be noted that Figure 2 The top figure is the ADC input / output amplitude matching verification diagram when the excitation phase is 0°; Figure 2 The middle figure is the demodulation effect diagram of high signal-to-noise ratio envelope signal; Figure 2 The bottom figure is the discrete feedback diagram of the rotor position phase correctness.

[0036] Figure 3 When the excitation phase is 90°, the initial rotor position phase is wrong, and the detection output is normal after correction. As can be seen from the top figure, due to the position error of the initial zero-crossing point, the output amplitude of the analog-to-digital converter is much smaller than the input amplitude of the analog-to-digital converter at this time, so the amplitude of the obtained envelope signal is small, and the rotor position phase is wrong. The second half is to open the phase-locked loop, which can determine the relevant information of the excitation phase and correct the zero-crossing point. Thereby, the output amplitude of the analog-to-digital converter can match the input amplitude of the analog-to-digital converter, so the amplitude of the corrected envelope signal becomes larger. The corrected rotor position phase detection output obtained in this way is correct. It should be noted that Figure 3 The top graph is a comparison of ADC input / output amplitude mismatch and recovery when the excitation phase is 90°; Figure 3 The middle figure is a verification figure of the dynamic correction effect of the envelope signal; Figure 3The bottom figure is a comparison diagram of rotor phase closed-loop correction.

[0037] Reference Figure 4 As shown, the four-quadrant adder includes a multiplexer, a first inverter (i.e. Figure 4 ① in the figure), the second inverter (i.e. Figure 4 ② in the first adder (i.e. Figure 4 ③) and gain device (i.e. Figure 4 ④ in the above); The first input end of the multiplexer is connected to the output end of the first phase detector, and the second input end of the multiplexer is connected to the output end of the first phase detector via the first inverter; the third input end of the multiplexer is connected to the output end of the second phase detector, and the fourth input end of the multiplexer is connected to the output end of the second phase detector via the second inverter; the output end of the multiplexer is connected to the first adder, and the output end of the first adder is connected to the gain device.

[0038] according to Figure 4 It can be seen that the multiplexer included in the four-quadrant adder in the present application will respectively access the phase information output by the first phase detector and the second phase detector, and will also input the inverted phase information of the phase information to the multiplexer via the first inverter and the second inverter.

[0039] according to Figure 1 It can be seen that the quadrant signal output by the four-quadrant inverse tangent module will be transmitted to the four-quadrant adder and used as the control switch of the multiplexer in the four-quadrant adder. The multiplexer performs output superposition according to the phase information and inverted phase information received, and then after being scaled by the amplifier, an adjustable gain factor is superimposed on it through the gain device to adjust the phase error output by the multiplexer, thereby affecting the final phase error detection result.

[0040] Reference Figure 5 As shown, the sampling phase accumulator includes a second adder (i.e. Figure 5 ⑤ in the figure) and the unit delay (i.e. Figure 5 ⑥ in the above); The input end of the second adder is connected to the output end of the gain device, and the output end of the second adder is connected to the input end of the unit delayer; the output end of the unit delayer is connected to the input end of the clock generation module and the input end of the second adder respectively. That is, the phase error can be obtained by shift addition to obtain the phase offset.

[0041] Reference Figure 6 As shown, the clock generation module includes multiple phase branches (i.e. Figure 6 In ,..., , and ) and the OR gate (i.e. Figure 6 ⑦), multiple phase branches form an excitation cycle, where: The total number of segments representing the phase offset.

[0042] Each phase branch is respectively connected to a phase offset, and the phase offset is compared with the phase point in each phase branch. When the comparison shows that the phase offset is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset belongs is output as a sampling clock through an OR gate.

[0043] If there is a phase offset equal to any zero-crossing point, the comparison result of the phase branch where any zero-crossing point is located is output as a synchronous clock.

[0044] The clock generation module divides the signal of an excitation cycle into n equally divided phase branches and compares the phase offset with the n equally divided phase points. The output of the n phase branches will be used as the input of the OR gate, and the output of the OR gate is the sampling clock. Among them, the output of the phase branch at the 0° phase point is the synchronization clock.

[0045] It is worth noting that since both the 0° phase point and the 180° phase point are zero-crossing points. If synchronization is performed once within an excitation cycle, the output of the phase branch at the 0° phase point can be taken as the synchronization clock; the output of the phase branch at the 180° phase point can also be taken as the synchronization clock. If synchronization is performed twice within an excitation cycle, the output of the phase branch at the 0° phase point and the output of the phase branch at the 180° phase point can be taken as the synchronization clock. The present invention does not limit the selection of the synchronization clock.

[0046] The embodiment of the clock generation module mainly compares the phase offset with the n equally divided phase points of the n phase branches. When the phase offset is equal to a certain phase point of the n equally divided phases, the branch will output a high level, and the OR gate will also output a high level. At this time, the sampling clock becomes a high level, so the signal in one excitation cycle will be sampled at equal intervals of the n equally divided phases.

[0047] When n=8, the phase offset needs to be compared with 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°. When the phase offset is exactly equal to the above 8 phase points, the sampling clock will be output to sample the signal within one excitation cycle, such as Figure 7 When the phase offset is equal to 0° and 180°, the corresponding S0 and S4 are zero-crossing signals.

[0048] It is worth noting that it is not necessary for the sampling intervals to be equal. The sampling can be concentrated near 0°, 90°, 180°, and 270°; or the sampling can be concentrated near 90° and 270°, such as Figure 8The present invention is not limited thereto.

[0049] Furthermore, the demodulation circuit is specifically used for: Performing equal-interval sampling operation or non-equal-interval sampling operation on a magnetizing cycle according to a sampling clock through a peak detection circuit to obtain a plurality of initial sampling signals, wherein the plurality of initial sampling signals include a sampling signal at zero time; Based on the phase detection loop, the sampling signal at zero time is subtracted to obtain phase information, and according to the positive and negative conditions reflected by the phase information, the position information between the sampling position corresponding to the sampling signal at zero time and the zero point position on an excitation cycle is obtained; The sampling clock is adjusted according to the position information to obtain the target sampling clock. Based on the target sampling clock, multiple samplings are performed on an excitation cycle to obtain multiple target sampling signals. Then, the sine envelope waveform and cosine envelope waveform of the electromagnetic induction differential output signal belonging to an excitation cycle are extracted according to the target sampling signal.

[0050] In order to facilitate subsequent explanation and understanding, the principle of the rotary digitizer and information related to extraction of the envelope signal based on the rotary digitizer are first explained.

[0051] First, the rotary digital converter implements the interface between the resolver and the system microprocessor, and demodulates the sine and cosine signals to obtain the angular position and rotation speed of the motor shaft.

[0052] For the resolver, an excitation signal is used to excite the Exciting the primary winding will generate two electromagnetic induction differential output signals on the secondary winding, i.e. sinusoidal signals. and cosine signal , whose expressions correspond to expression ① and expression ② respectively.

[0053] ————Expression ① ————Expression ② in, is the input shaft angle, The two electromagnetic induction differential output signals generated on the secondary winding are modulated by the corresponding input shaft angle, specifically, the sine signal, cosine signal, excitation signal, and envelope signals extracted based on the sine signal and cosine signal. and like Figure 1 shown.

[0054] Please refer to Figure 7As shown, in the early stage, a plurality of samples are sampled for one excitation cycle directly based on the sampling clock to obtain a plurality of initial sampling signals. This embodiment samples 8 times in one excitation cycle to obtain the initial sampling signal shown in expression ③.

[0055] ————Expression ③ in, represents the set of initial sampling signals, s represents the initial sampling signal, and its subscript represents the number of sampling points. Figure 7 It can be seen that and is the signal at the zero point of an excitation cycle, that is, the sampling signal at the zero point of an excitation cycle. ~ and ~ It is the sampling signal at the non-zero point of an excitation cycle.

[0056] Based on the sampling clock, a magnetizing cycle is directly sampled to obtain a sampling signal at the zero point of the magnetizing cycle, so as to determine the corresponding relationship between the sampling signal at the zero point and the zero-crossing position of the magnetizing cycle.

[0057] It should be noted that the zero time in the sampling signal of the zero time of an excitation cycle refers to the zero time on an excitation cycle, and the zero time is related to the sampling clock.

[0058] Furthermore, expression ③ only expresses the case where the number of initial sampling signals is 8, and it can also be other sampling times as shown in expression ④.

[0059] ————Expression ④ in, represents the set of initial sampling signals, s represents the initial sampling signal, and its subscript represents the number of sampling points.

[0060] It should be noted that, because the excitation signal of an excitation cycle Exciting the primary winding generates a sinusoidal signal on the secondary winding and cosine signal , while the sinusoidal signal and cosine signal There are corresponding input shaft angles, so this application needs to be respectively matched with the sinusoidal signal according to the sampling clock The corresponding first excitation cycle and the cosine signal The corresponding second excitation cycle is sampled multiple times. A sampling signal at zero time on the first excitation cycle and a sampling signal at zero time on the second excitation cycle are obtained, and the sampling clocks of the first excitation cycle and the second excitation cycle are adjusted accordingly based on the sampling signal at zero time, so that the envelope signals extracted based on the first excitation cycle and the second excitation cycle can improve the accuracy of demodulation.

[0061] Referring to expression ⑤, expression ⑤ is the calculation formula for phase information.

[0062] ————Expression ⑤ in, represents phase information, and Indicates the initial sampling signal of the 4th sampling number, It represents the sampling signal at zero time. In the specific implementation process, it can be set to the sampling signal at zero time of other subscripts.

[0063] Because within one half of an excitation cycle, and The magnitudes are equal but the directions are opposite, so if we want to and To extract effective phase information, a subtraction operation needs to be performed, based on which The positional relationship and distance with the zero-crossing position in an excitation cycle can be used to determine whether the sampling signal at the zero point obtained based on the sampling clock is a signal at the zero-crossing position in an excitation cycle.

[0064] The reason why the judgment is based on the sampling signal at the zero point instead of the sampling signal at the non-zero point is that the sampling signal at the zero point can better determine the position than the sampling signal at the non-zero point. It only needs to determine that the sampling signal at the zero point corresponds to the zero-crossing position of an excitation cycle, and then it can be directly deduced that the sampling signal at the non-zero point does not correspond to the zero-crossing position of an excitation cycle. Subsequently, the envelope signal with a higher signal-to-noise ratio can be directly extracted based on the sampling signal at the non-zero point.

[0065] In other implementation processes, the calculation formula for the phase information can be further expressed as Expression ⑥.

[0066] ————Expression ⑥ in, represents phase information, and Indicates the initial sampling signal of the 2nth sampling point number, Represents the sampling signal at zero time.

[0067] In this embodiment, the first phase information obtained by subtracting the sampling signal at the first zero point in the first excitation cycle, and the second phase information obtained by subtracting the sampling signal at the second zero point in the second excitation cycle, can both reflect whether the sampling signal at the zero point in the first excitation cycle and the second excitation cycle obtained based on the sampling clock is a signal at the zero-crossing position of an excitation cycle, so that the sampling clock of the first excitation cycle and the sampling clock of the second excitation cycle are adjusted accordingly, ensuring that the envelope signals extracted in the first excitation cycle and the second excitation cycle have a good signal-to-noise ratio.

[0068] After obtaining the position information of the sampling signal at the zero point of an excitation cycle mapped between the sampling position on an excitation cycle and the zero-crossing position on an excitation cycle, the sampling clock can be adjusted according to the position information to change the sampling time of the sampling signal on an excitation cycle based on the sampling clock, so that the target sampling signal obtained by sampling on an excitation cycle based on the adjusted sampling clock, that is, the target sampling clock, includes the signal located at the zero-crossing position of an excitation cycle. Therefore, other signals in the target sampling signal will definitely not be located at the zero-crossing position of an excitation cycle. Therefore, the target envelope signal (that is, the sine envelope waveform and the cosine envelope waveform) extracted based on other signals in the target sampling signal will definitely have a better signal-to-noise ratio and can achieve a high-accuracy demodulation effect.

[0069] The demodulation circuit is also used for: when the phase information is determined to be a positive difference according to the positive and negative conditions, obtaining a first position relationship in which the sampling position lags behind the zero-crossing position of an excitation cycle according to the positive difference, and obtaining a first distance relationship between the sampling position and the zero-crossing position according to the first absolute value of the positive difference, wherein the first position relationship and the first distance relationship are position information.

[0070] According to the first position relationship and the first distance relationship, the time period reflected by the first time interval is adjusted earlier on the basis of the sampling clock to obtain a sine envelope waveform and a cosine envelope waveform.

[0071] Specifically, Fig. 9 As shown, an excitation cycle is taken as an example for explanation.

[0072] Fig. 9 One excitation cycle As a control group, it is used to represent the standard wave, whose phase is neither advanced nor delayed. The zero-crossing position on the magnetizing cycle is exactly the same as the zero-point position on the magnetizing cycle (i.e. Fig. 9 The mark “0” in the figure overlaps.

[0073] When the phase information is determined to be a positive difference value according to the positive and negative conditions, the phase condition reflected in an excitation cycle is such as an excitation cycle shown. Fig. 9 The 0 moment in the figure (i.e., the zero position of an excitation cycle) is a sampling moment in the sampling clock. As can be seen from the figure, when the phase information is a positive difference, it means that an excitation cycle is obtained by sampling at the 0 moment. The sampling signal at the zero point on the magnetizing cycle is located in In the second half of the cycle, the phase advances and the sampling clock lags, making an excitation cycle The sampling position of the zero-time sampling signal mapped on an excitation cycle lags behind an excitation cycle. The first position relationship of the zero-crossing position.

[0074] Because an excitation cycle is repeated periodically at a certain frequency, The difference between the sampling signals at zero time obtained by upsampling, that is, the absolute value of the positive difference reflected by the phase information, can reflect the difference between the sampling position and an excitation cycle. The first distance relationship between the zero-crossing positions.

[0075] After determining the first position relationship and the first distance relationship, the sampling clock can be adjusted accordingly. According to the first position relationship obtained above, it can be known that the sampling time of the sampling clock is delayed, so it is necessary to perform an operation of adjusting the sampling clock earlier. According to the first distance relationship obtained above, it can be known that the distance relationship between the sampling position and the zero-crossing position is reflected on the X-axis (i.e., the time axis) of an excitation cycle, so the adjustment operation of the initial sampling clock at this time is to adjust the sampling clock earlier by the first time interval.

[0076] The first time interval corresponds to the first distance relationship, and the first distance relationship can reflect the time interval between the sampling moment of the sampling position in an excitation cycle and the first moment of the zero-crossing position in an excitation cycle.

[0077] The demodulation circuit is also used for: when the phase information is determined to be a negative difference according to the positive and negative conditions, obtaining a second position relationship in which the sampling position is ahead of the zero-crossing position of an excitation cycle according to the negative difference, and obtaining a second distance relationship between the sampling position and the zero-crossing position according to the second absolute value of the negative difference, wherein the second position relationship and the second distance relationship are position information.

[0078] According to the second position relationship and the second distance relationship, the time period reflected by the second time interval is delayed on the basis of the sampling clock to obtain a sine envelope waveform and a cosine envelope waveform.

[0079] When the phase information is determined to be a negative difference value based on the positive and negative conditions, it reflects the phase situation in an excitation cycle, such as an excitation cycle shown. Fig. 9 The 0 moment in the figure (i.e., the zero moment of an excitation cycle) is a sampling moment in the sampling clock. As can be seen from the figure, when the phase information is a negative difference, it means that an excitation cycle is obtained by sampling at the 0 moment. The sampling signal at the zero point on the magnetizing cycle is located in In the first half of the cycle, after the phase occurs, the sampling clock advances, making an excitation cycle The sampling position of the zero-time sampling signal mapped on an excitation cycle is ahead of an excitation cycle. The second position relationship of the zero-crossing position.

[0080] Because an excitation cycle is repeated periodically at a certain frequency, The difference between the sampling signals at zero time obtained by upsampling, that is, the absolute value of the negative difference reflected by the phase information, can reflect the difference between the sampling position and an excitation cycle. The second distance relationship between the zero-crossing positions.

[0081] After determining the second position relationship and the second distance relationship, the sampling clock can be adjusted accordingly. According to the second position relationship obtained above, it can be known that the sampling time of the sampling clock is ahead, so it is necessary to perform an operation of delaying the sampling clock. According to the second distance relationship obtained above, it can be known that the distance relationship between the sampling position and the zero-crossing point position reflected on the X-axis (i.e., the time axis) of an excitation cycle, so the adjustment operation of the initial sampling clock at this time is to delay the sampling clock by the second time interval.

[0082] The second time interval corresponds to the second distance relationship, and the second distance relationship can reflect the time interval between the sampling moment of the sampling position in an excitation cycle and the second moment of the zero-crossing position in an excitation cycle.

[0083] It should be noted that based on Figure 2 and Figure 3 It can be seen that the envelope signal has sine and cosine characteristics, so when the amplitude of the sine envelope signal is minimum, the amplitude of the cosine envelope signal is maximum; when the amplitude of the cosine envelope signal is minimum, the amplitude of the sine envelope signal is maximum, and when the amplitude difference is too large, the extracted phase information has a large error. Therefore, in order to avoid this situation, this embodiment proposes to superimpose the phase information of the sine envelope signal and the cosine envelope signal to solve the problem of large phase information error caused by the small amplitude of a single sine envelope signal or a cosine envelope signal.

[0084] Specifically, still according to Figure 2 and Figure 3 It can be seen that in the phase range of 0°~90°, the amplitudes of the sine envelope signal and the cosine envelope signal are both positive; in the phase range of 90°~180°, the amplitude of the sine envelope signal is positive, and the amplitude of the cosine envelope signal is negative; in the phase range of 180°~270°, the amplitudes of the sine envelope signal and the cosine envelope signal are both negative; in the phase range of 270°~360°, the amplitude of the sine envelope signal is negative, and the amplitude of the cosine envelope signal is positive. Therefore, the sine envelope signal and the cosine envelope signal can be divided into four quadrants. The first quadrant is the phase range of 0°~90°; the second quadrant is the phase range of 90°~180°; the third quadrant is the phase range of 180°~270°; the fourth quadrant is the phase range of 270°~360°, thereby obtaining the superposition formula of the phase information of the sine envelope signal and the phase information of the cosine envelope signal as shown in Expression ⑦.

[0085] ————Expression ⑦ in, is the target phase information of the sine envelope signal and the cosine envelope signal in the first quadrant, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the second quadrant, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the third quadrant, is the target phase information of the sine envelope signal and the cosine envelope signal in the fourth quadrant, Represents the phase information of the sine envelope signal and the cosine envelope signal in the first quadrant, Represents the phase information of the sine envelope signal and the cosine envelope signal in the second quadrant, Represents the phase information of the sine envelope signal and the cosine envelope signal in the third quadrant, Indicates the phase information of the sine envelope signal and the cosine envelope signal in the fourth quadrant.

[0086] After the corresponding target phase information is obtained according to expression ⑦, the arc tangent of the target phase information is calculated to obtain the specific degree of the target phase information within the phase range of 0°~360° (i.e., one excitation cycle).

[0087] It should be noted that the inverse tangent operation in this embodiment is performed using the CORDIC method.

[0088] In order to further improve the accuracy of the obtained phase information, and thereby further improve the accuracy of the extracted envelope signal, this embodiment proposes to adjust the sampling clock based on the obtained degree and position information, so as to reduce the large phase information error caused by the small amplitude of a single sine envelope signal or a cosine envelope signal, and thus the problem of low accuracy of the position information, so that the target sampling clock obtained after adjustment still has a low signal-to-noise ratio of the extracted envelope signal.

[0089] Furthermore, the demodulation circuit is specifically used for: The sum of the sampling signal at the target zero point and the sampling signal at the target non-zero point is calculated, and the sine envelope waveform and the cosine envelope waveform are output; or the sum of the sampling signals at the target non-zero point is calculated, and the sine envelope waveform and the cosine envelope waveform are output.

[0090] Specifically, expression ⑧ calculates the sum of the sampling signal at the target zero point and the sampling signal at the target non-zero point, and outputs the target envelope signal.

[0091] ————Expression⑧ in, The sum of the signals representing the sampling signal at the first target zero point to the sampling signal at the second target zero point before the sampling signal at the target non-zero point. The sum of the signals representing the sampling signal from the second target zero point to the last target non-zero point, Represents the target envelope signal.

[0092] Expression ⑨ calculates the sum of the sampling signals at the target non-zero time points, and outputs the target envelope signal.

[0093] ————Expression ⑨ in, The sum of the signals representing the sampling signal at the target non-zero time point after the first target zero time point sampling signal to the sampling signal at the target non-zero time point before the second target zero time point sampling signal, The sum of the signals representing the sampling signal at the next non-zero point after the second target zero point sampling signal to the last target non-zero point sampling signal, Represents the target envelope signal.

[0094] Because the target zero-point sampling signal obtained by sampling in an excitation cycle based on the target sampling clock must be located at the zero-crossing position of an excitation cycle, it can be determined that the target non-zero-point sampling signal includes not only the peak value of an excitation cycle, but also other amplitude components. Therefore, the signal-to-noise ratio of the envelope signal calculated based on this is improved.

[0095] It should be noted that the reason why expression ⑧ includes the sampling signal at the target zero point is that although the sampling signal at the target zero point is a useless signal, it will not affect the calculation result. Therefore, calculating the sampling signal at the target zero point and the sampling signal at the non-target zero point will not have a negative impact on the output envelope signal.

[0096] The present application also provides a rotational digitizer, which includes the demodulation circuit as described above.

[0097] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A demodulation circuit, characterized in that: The demodulation circuit is composed of a peak detection circuit and a phase detection loop; The peak detection circuit is used to extract the envelope waveform of the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; The phase detection loop is used to identify the phase information of the input signal of the resolver, and after determining the offset error, generate a sampling clock and a synchronization clock according to the offset error, and transmit the sampling clock and the synchronization clock to the peak detection circuit to correct the envelope waveform; Wherein, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor and a four-quadrant inverse tangent module; The input end of the first analog-to-digital converter is connected to a sine resolver input signal, and outputs a sine resolver input digital signal to the envelope extractor; and the input end of the second analog-to-digital converter is connected to a cosine resolver input signal, and outputs a cosine resolver input digital signal to the envelope extractor; The envelope extractor outputs a sine envelope waveform based on the connected sine resolver input digital signal, and outputs a cosine envelope waveform based on the connected cosine resolver input digital signal; The four-quadrant inverse tangent module outputs the quadrant phases of the sine envelope waveform and the cosine envelope waveform according to the connected sine envelope waveform and the cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phases; The phase detection loop includes a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator and a clock generation module; The first phase detector and the second phase detector are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to perform phase identification on the sine resolver input digital signal and the cosine resolver input signal, and output the phase information; The first phase detector and the second phase detector are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; The first phase detector and the second phase detector are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; The sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs the sampling clock and the synchronization clock to the envelope extractor according to the phase offset input.

2. The demodulation circuit according to claim 1, characterized in that: The four-quadrant adder includes a multiplexer, a first inverter, a second inverter, a first adder and a gain device; The first input end of the multiplexer is connected to the output end of the first phase detector, and the second input end of the multiplexer is connected to the output end of the first phase detector via the first inverter; The third input terminal of the multiplexer is connected to the output terminal of the second phase detector, and the fourth input terminal of the multiplexer is connected to the output terminal of the second phase detector via the second inverter; The output end of the multiplexer is connected to the first adder, and the output end of the first adder is connected to the gain device.

3. The demodulation circuit according to claim 2, characterized in that: The sampling phase accumulator includes a second adder and a unit delayer; The input end of the second adder is connected to the output end of the gain device, and the output end of the second adder is connected to the input end of the unit delay device; The output end of the unit delayer is connected to the input end of the clock generation module and the input end of the second adder respectively.

4. The demodulation circuit according to claim 3, characterized in that: The clock generation module includes a plurality of phase branches and an OR gate, and the plurality of phase branches constitute an excitation cycle; Each of the phase branches is respectively connected to the phase offset, and the phase offset is compared with the phase point in each of the phase branches. When the comparison shows that the phase offset is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset belongs is output as a sampling clock through an OR gate.

5. The demodulation circuit according to claim 4, characterized in that: If there is a phase offset equal to any zero-crossing point, the comparison result of the phase branch where any zero-crossing point is located is output as the synchronous clock.

6. The demodulation circuit according to claim 5, characterized in that: The demodulation circuit is specifically used for: By means of the peak detection circuit, an equal-interval sampling operation or a non-equal-interval sampling operation is performed on the one excitation cycle according to the sampling clock to obtain a plurality of initial sampling signals, wherein the plurality of initial sampling signals include a sampling signal at the zero point; The phase information is obtained by subtracting the sampling signal at the zero time based on the phase detection loop, and the position information between the sampling position corresponding to the sampling signal at the zero time and the zero point position on the excitation cycle is obtained according to the positive and negative conditions reflected by the phase information; The sampling clock is adjusted according to the position information to obtain a target sampling clock. Based on the target sampling clock, multiple samplings are performed on the one excitation cycle to obtain multiple target sampling signals. Then, the sine envelope waveform and the cosine envelope waveform of the electromagnetic induction differential output signal belonging to the one excitation cycle are extracted according to the target sampling signals.

7. The demodulation circuit according to claim 6, characterized in that: The demodulation circuit is specifically used for: In the case where the phase information is determined to be a positive difference according to the positive and negative conditions, a first position relationship in which the sampling position lags behind the zero-crossing position of the one excitation cycle is obtained according to the positive difference, and a first distance relationship between the sampling position and the zero-crossing position is obtained according to a first absolute value of the positive difference, wherein the first position relationship and the first distance relationship are the position information; According to the first position relationship and the first distance relationship, the time period reflected by the first time interval is adjusted earlier on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

8. The demodulation circuit according to claim 7, characterized in that: The demodulation circuit is specifically used for: In the case where the phase information is determined to be a negative difference according to the positive and negative conditions, a second position relationship in which the sampling position is ahead of the zero-crossing position of the one excitation cycle is obtained according to the negative difference, and a second distance relationship between the sampling position and the zero-crossing position is obtained according to a second absolute value of the negative difference, wherein the second position relationship and the second distance relationship are the position information; According to the second position relationship and the second distance relationship, the time period reflected by the second time interval is delayed on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

9. The demodulation circuit according to claim 6, characterized in that: The demodulation circuit is specifically used for: Calculate the sum of the target zero-point sampling signal and the target non-zero-point sampling signal, and output the sine envelope waveform and the cosine envelope waveform; or, The sum of the sampling signals at the target non-zero point is calculated, and the sine envelope waveform and the cosine envelope waveform are outputted.

10. A rotation digitizer, characterized in that: The rotational digitizer comprises a demodulation circuit as claimed in any one of claims 1 to 9.

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