Digital filter with configurable extraction rate applied to BMS (Battery Management System)

Abstract

The invention discloses a decimation rate configurable digital filter applied to a BMS (Battery Management System). The decimation rate configurable digital filter comprises a decimation filter, a compensation filter, a half-band filter and an SPI (Serial Peripheral Interface) configuration interface circuit, the decimation filter, the compensation filter and the half-band filter are sequentially connected in series, and the SPI configuration interface circuit is respectively connected with clock control ends of the decimation filter, the compensation filter and the half-band filter; the decimation filter is used for performing multiple extraction on the input signal to obtain a density wave; the compensation filter is used for compensating the density wave by adopting amplitude-frequency characteristics opposite to those of the decimation filter to obtain the compensated density wave; the half-band filter is used for carrying out frequency-doubled reduction operation on the compensated density wave to obtain a digital signal; the SPI configuration interface circuit is used for respectively configuring decimation factors of the decimation filter, the compensation filter and the half-band filter according to an input clock input signal SCLK and an externally input control instruction. The method can flexibly adapt to the requirements of different application scenes.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital filtering, and in particular relates to a configurable decimation rate digital filter applied to a BMS. Background Art

[0002] Battery Management System (BMS) is an important technology for monitoring and managing battery pack performance. To ensure the safety and performance of the battery pack, BMS needs to accurately measure and analyze the voltage, current, and temperature of the battery. However, these measurement signals are often interfered by high-frequency noise, affecting the accuracy of the data. Therefore, an effective digital filter is needed to process these signals.

[0003] Traditional analog filters have limitations in filtering effect and flexibility, and are difficult to meet the complex BMS application requirements. Digital filters have gradually become an important part of BMS due to their high precision, configurability and flexibility. However, the application scenarios of existing digital filters are not flexible enough and the system power consumption is high. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a configurable decimation rate digital filter applied to a BMS.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a configurable decimation rate digital filter for BMS, comprising: a decimation filter, a compensation filter, a half-band filter and an SPI configuration interface circuit, wherein the decimation filter, the compensation filter and the half-band filter are sequentially connected in series, and the SPI configuration interface circuit is respectively connected to the clock control terminals of the decimation filter, the compensation filter and the half-band filter;

[0007] The decimation filter is used to perform multiple decimation on the input signal to obtain a density wave;

[0008] The compensation filter is used to compensate the density wave by using an amplitude-frequency characteristic opposite to that of the extraction filter to obtain a compensated density wave;

[0009] The half-band filter is used to perform a frequency-reduction operation on the compensated density wave to obtain a digital signal;

[0010] The SPI configuration interface circuit is used to configure the decimation factors of the decimation filter, the compensation filter, and the half-band filter respectively according to the input clock input signal SCLK and the external input control instruction.

[0011] In some embodiments, the decimation filter is a 4-stage CIC decimation filter with a recursive structure.

[0012] In some embodiments, the compensation filter is an ISOP compensation filter.

[0013] In some embodiments, the half-band filter is a half-band filter of improved insensitive structure.

[0014] In some embodiments, the SPI configuration interface circuit is specifically used to change the assignment of the D register according to an external control instruction, and generate the clock division signals required for the operation of the decimation filter, the compensation filter and the half-band filter according to the changed assignment of the D register and the input clock input signal SCLK, and the clock division signals required for the operation of the decimation filter, the compensation filter and the half-band filter are used to control the decimation factors of the decimation filter, the compensation filter and the half-band filter respectively.

[0015] In some embodiments, the clock division signal required for the decimation filter to operate is used to configure the decimation factor of the decimation filter to one of 32, 64, 128, 256, 512, and 1024, and the clock division signal required for the compensation filter and the half-band filter to operate is used to configure the decimation factors of the compensation filter and the half-band filter to 2.

[0016] In some embodiments, when the changed value of the D register is 5, the decimation factors of the decimation filter, the compensation filter, and the half-band filter are 32, 2, and 2, respectively, and the total decimation factor of the configurable decimation rate digital filter is 128;

[0017] When the value of the D register after the change is 6, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 64, 2, and 2 respectively, and the total decimation factor of the configurable decimation rate digital filter is 256;

[0018] When the value of the D register after the change is 7, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 128, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 512;

[0019] When the value of the D register after the change is 8, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 256, 2, and 2 respectively, and the total decimation factor of the configurable decimation rate digital filter is 1024;

[0020] When the value of the D register after the change is 9, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 512, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 2048;

[0021] When the value of the D register after the change is 10, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 1024, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 4096.

[0022] In some embodiments, the SPI configuration interface circuit includes a status register, a data register and a D register, and the SPI configuration interface circuit is also used to implement the function of a clock division circuit; in SPI mode, the SPI configuration interface circuit is the host, and the filter module composed of the extraction filter, the compensation filter and the half-band filter is the slave.

[0023] In some embodiments, the input sampling frequency of the ISOP compensation filter is 96 kHz, the passband cutoff frequency is 10 kHz, the stopband cutoff frequency is 86 kHz, the passband ripple is 0.01 dB, and the stopband attenuation is -110 dB.

[0024] In some embodiments, the input sampling frequency of the half-band filter is 48kHz, the output signal frequency is 24kHz, the passband cutoff frequency is 10kHz, the stopband cutoff frequency is 20kHz, the passband ripple is 0.01dB, and the stopband attenuation is -110dB.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention proposes a configurable digital filter for extraction rate applied to BMS. The digital filter can reduce hardware consumption through the combination of extraction filter, compensation filter and half-band filter, thereby effectively reducing system power consumption. Moreover, the extraction rate of the digital filter is adjusted by configuring the extraction factor of the extraction filter, compensation filter and half-band filter through the extraction rate control module, which can flexibly adapt to the needs of different application scenarios, thereby improving the accuracy of the signal and the overall performance of the system. In addition, the high precision of the measurement is guaranteed by the multi-stage extraction structure and advanced digital filtering technology, which is suitable for various applications such as voltage, current and temperature measurement in battery management systems.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 11 is a schematic diagram of the internal structure of a configurable decimation rate digital filter applied to a BMS provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of the amplitude-frequency response of a 4-stage CIC decimation filter with a recursive structure provided in an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of the amplitude-frequency response of the ISOP compensation filter provided by an embodiment of the present invention;

[0031] Figure 4 It is a schematic diagram of the amplitude-frequency response before and after the passband roll-off compensation of a 4-level CIC decimation filter using an ISOP compensation filter provided by an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of the amplitude-frequency response of a half-band filter provided by an embodiment of the present invention;

[0033] Figure 6 It is a schematic diagram of the connection relationship between the SPI configuration interface circuit provided by an embodiment of the present invention and the extraction filter, the compensation filter and the half-band filter;

[0034] Figure 7 It is a schematic diagram of a signal spectrum obtained by a configurable decimation rate digital filter applied to a BMS provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0036] Figure 1 FIG. 1 is a schematic diagram of the internal structure of a configurable decimation rate digital filter applied to a BMS according to an embodiment of the present invention. Figure 1 As shown, the digital filter includes: a decimation filter, a compensation filter, a half-band filter and an SPI configuration interface circuit; wherein the decimation filter, the compensation filter and the half-band filter are connected in series in sequence, and the SPI configuration interface circuit is respectively connected to the clock control terminals of the decimation filter, the compensation filter and the half-band filter. The decimation filter is used to perform multiple decimation on the input signal to obtain a density wave; the compensation filter is used to compensate the density wave with an amplitude-frequency characteristic opposite to that of the decimation filter to obtain a compensated density wave; the half-band filter is used to perform a frequency-reducing operation on the compensated density wave to obtain a digital signal; the SPI configuration interface circuit is used to respectively configure the decimation factors of the decimation filter, the compensation filter and the half-band filter according to an external input control instruction.

[0037] In some embodiments, when the modulator in the first stage of the decimation rate configurable digital filter is a 3rd order structure, the decimation filter is a 4-stage CIC decimation filter using a recursive structure. By using a 4-stage CIC decimation filter, the number of stages of the CIC decimation filter can be one stage more than the number of stages of the modulator, thereby reducing the interference of high-frequency quantization noise on low-frequency signals, not affecting the noise spectrum within the signal bandwidth, and not consuming hardware. In addition, the CIC filter structure can be divided into a recursive structure, a non-recursive structure, and a combination of a recursive structure and a non-recursive structure. The decimation factor of the non-recursive structure can only be a power of 2, and in order to achieve a variable rate, the compensation filter can only be a variable coefficient filter, especially when the decimation factor is relatively large, this structure lacks flexibility in practical applications. The decimation factor of the recursive structure can be any positive integer value, and there is no multiplier in the structure, and the cascade integrator and the differentiator work at different clock frequencies, reducing the power consumption of the circuit. In addition, the recursive structure can flexibly configure the decimation factor MCIC of the filter, and no matter how the decimation factor changes, the number of integral structures and comb structures does not need to be changed. Therefore, the 4-stage CIC decimation filter of the present invention adopts a recursive structure.

[0038] In the present invention, the downsampling rate of the 4-stage CIC decimation filter using a recursive structure is 32, the input signal frequency is 3.072MHz, the output signal frequency is 192K, the passband cutoff frequency is 20K, and the amplitude-frequency response of the 4-stage CIC decimation filter using a recursive structure is as follows: Figure 2 As shown, obviously, Figure 2 The attenuation of the first side lobe shown in is about -80dB, which shows that it has a good noise suppression effect. The amplitude-frequency characteristic expression of the multi-stage CIC filter is: R represents the decimation factor of the 4-stage CIC decimation filter, ω represents the angular frequency, and L represents the number of stages of the 4-stage CIC decimation filter. The attenuation value of the first sidelobe calculated according to the above formula is: When the amplitude value is determined, as the decimation factor increases, the corresponding normalized bandwidth will also decrease exponentially. Therefore, the variable rate filter can be implemented with the same structure only by adjusting the word length of the register. The decimation factor R of the CIC decimation filter is configurable. This model can be used for different decimation factors by simply adjusting the value of R. Here, if the data in the digital circuit uses double precision, the word length of the register will increase dramatically, which will consume a lot of chip area. Therefore, under the premise of ensuring that the data in the register of the 4-level CIC decimation filter will not overflow, the word length of the internal register of the 4-level CIC decimation filter needs to be fixed-point. The number of bits required for the register of the 4-level CIC decimation filter can be estimated by the following formula, B max =Nlog2RM+B in, M is the differential delay of the 4-stage CIC decimation filter, N is the number of stages of the 4-stage CIC decimation filter, B in is the number of bits of the input signal of the 4-stage CIC decimation filter. For an N-stage CIC decimation filter, its essence is a cascade of N single-stage CIC filters, and its system transfer function is: Its frequency response is: M1 is the decimation rate of the 4-stage CIC decimation filter, M2 is the number of stages of the 4-stage CIC decimation filter, and Z represents the Z domain.

[0039] The CIC decimation filter has obvious passband attenuation, which will deteriorate the signal-to-noise ratio of the circuit. Therefore, it is necessary to design a special filter to compensate for this amplitude attenuation to improve system performance. The CIC decimation filter can be designed using the filter designer tool in Matlab. In the present invention, the 4-stage CIC decimation filter can provide a maximum attenuation of 42dB. The greater the attenuation, the more serious the passband roll-off will be, which will make the passband less than 1. In this regard, the present invention uses an ISOP compensation filter to compensate for the density wave obtained by the 4-stage CIC decimation filter. Compared with the traditional FIR compensation filter, the ISOP compensation filter has a simple structure and good passband attenuation compensation performance. The compensation method of the ISOP compensation filter adopts the interpolation second-order polynomial method (ISOP). The system function of the ISOP compensation filter can generally be expressed as: Where I is a positive integer, c is a real number, and the amplitude-frequency response of the ISOP compensation filter is: In the present invention, as shown in Table 1, the input sampling frequency of the ISOP compensation filter is 96 kHz, the passband cutoff frequency is 10 kHz, the stopband cutoff frequency is 86 kHz, the passband ripple is 0.01 dB, and the stopband attenuation is -110 dB.

[0040] Table 1 ISOP compensation filter design indicators

[0041] Input sampling frequency 96kHz Passband cutoff frequency 10kHz Stopband cutoff frequency 86kHz Passband ripple 0.01dB Stopband Attenuation -110dB

[0042] According to the index of ISOP compensation filter, its amplitude-frequency response is as follows: Figure 3 As shown, and Figure 4 The amplitude-frequency response of the 4-level CIC decimation filter before and after passband roll-off compensation using the ISOP compensation filter. Figure 4It can be seen that the passband fluctuation of the CIC+ISOP filter at the passband cutoff frequency is reduced to ±0.005dB, which shows that the ISOP compensation filter used in the present invention can well compensate for the attenuation of the 4-level CIC extraction filter at the passband cutoff frequency, and the required hardware resources are much smaller than the traditional FIR compensator, which can meet the design requirements.

[0043] Here, in the half-band filter (HBF), half of the filter coefficients are zero, so the number of memories required to store the filter coefficients will be reduced by half, and the corresponding addition and multiplication operations will also be reduced, which is beneficial to reduce the power consumption of the filter and reduce the chip area. The frequency response of the half-band filter is: Wherein, Q represents the order of the half-band filter, H(jf) represents the frequency response of the half-band filter, and k represents a discrete integer sequence. In the present invention, an improved insensitive structure half-band filter can be used. The improved insensitive structure half-band filter can reduce the dependence of the filter frequency response on the number of coefficient quantization bits, so that a smaller number of coefficient quantization bits can be used to obtain a larger stopband attenuation. Moreover, the stopband attenuation of the improved insensitive structure half-band filter is about 9dB lower than that of the traditional filter. The greater the stopband attenuation, the stronger the noise suppression ability. Therefore, the improved insensitive structure half-band filter has better performance. The system transfer function of the improved insensitive structure half-band filter is expressed as: a i Represents the coefficient of the i-th level. The half-band filter can be designed using the medium ripple method in the filter designer tool in Matlab. In the present invention, as shown in Table 2, the input sampling frequency of the half-band filter is 48kHz, the output signal frequency is 24kHz, the passband cutoff frequency is 10kHz, the stopband cutoff frequency is 20kHz, the passband ripple is 0.01dB, and the stopband attenuation is -110dB. According to the indicators of the half-band filter, its amplitude-frequency response is obtained as follows Figure 5 shown.

[0044] Table 2 Half-band filter design indicators

[0045] Input sampling frequency 48kHz Output signal frequency 24kHz Passband cutoff frequency 10kHz Stopband cutoff frequency 20kHz Passband ripple 0.01dB Stopband Attenuation -110dB

[0046] In the present invention, the SPI configuration interface circuit includes a status register, a data register and a D register, and the SPI configuration interface circuit is also used to realize the function of a clock frequency division circuit; in the SPI mode, the SPI configuration interface circuit is a host, and a filter module composed of a decimation filter, a compensation filter and a half-band filter is a slave. The SPI configuration interface circuit can be implemented by an FPGA development board, and the specific circuit structure is known, and the present invention will not repeat it. Specifically, the SPI configuration interface circuit is used to change the assignment of the D register according to an external input control instruction, and according to the changed assignment of the D register and the input clock input signal SCLK, respectively generate the clock frequency division signals required for the decimation filter, the compensation filter and the half-band filter to work, and the clock frequency division signals required for the decimation filter, the compensation filter and the half-band filter to work are respectively used to control the decimation factors of the decimation filter, the compensation filter and the half-band filter. Exemplarily, the clock division signal required for the decimation filter to operate is used to configure the decimation factor of the decimation filter to one of 32, 64, 128, 256, 512, and 1024, and the clock division signal required for the compensation filter and the half-band filter to operate is used to configure the decimation factors of the compensation filter and the half-band filter to 2.

[0047] Exemplarily, the correspondence between the changed assignment of the D register and the decimation factors of the decimation filter, the compensation filter and the half-band filter, and the total decimation factor of the digital filter is shown in Table 3.

[0048] Table 3D register value and the corresponding relationship between the extraction factor

[0049] D Decimation filter Compensation filter Half-band filter Total decimation factor 5 32 2 2 128 6 64 2 2 256 7 128 2 2 512 8 256 2 2 1024 9 512 2 2 2048 10 1024 2 2 4096

[0050] For example, Figure 6 Figure 1 is a schematic diagram of the connection relationship between the SPI configuration interface circuit and the decimation filter, compensation filter, and half-band filter. Figure 6As shown, the SPI configuration interface circuit has an SPI interface structure, and the SPI configuration interface circuit has the function of a clock frequency division circuit. The three output ends of the SPI configuration interface circuit are respectively connected to the clock control ends of the extraction filter, the compensation filter and the half-band filter. The SPI interface structure is used to receive the input clock signal SCLK and the external input control instruction CSn for changing the assignment of the D register. The SPI interface structure contains a write byte function submodule, a read byte function submodule, a read filter output data function submodule, a host control module and a selector. The enable signals of the write byte function submodule, the read byte function submodule and the read filter output data function submodule are all provided by the host control module in a time-sharing manner. When each function submodule runs a preset program, it will send a completion signal to the host control module respectively. After the host control module detects the stop signal, it will stop enabling; the data selector will select the working function submodule and output data. Through the write byte function submodule, the read byte function submodule, the read filter output data function submodule, the host control module and the selector, the input clock signal SCLK can be processed according to CSn to generate the clock division signals required for the operation of the extraction filter, the compensation filter and the half-band filter respectively.

[0051] The present invention adopts a 4-level CIC filter structure, and can configure a variety of decimation rates according to requirements, which is suitable for signal processing scenarios with different sampling rates; the interpolation second-order polynomial method can effectively compensate for the signal distortion introduced by the decimation filter, thereby improving the signal processing accuracy of the entire system; the half-band filter adopts an improved insensitive structure, which has better stability and anti-interference ability, can effectively reduce high-frequency noise, realizes a digital filter applied to the BMS system, and configures the decimation rate of the digital filter through the SPI configuration interface circuit, enriches the digital interface function, and can increase the effective number of bits by adjusting the output rate of the data, and can be flexibly adjusted according to actual needs, and can adapt to the needs of different application scenarios.

[0052] The design indicators of the decimation rate configurable digital filter applied to BMS provided by the present invention are shown in Table 4.

[0053] Table 4 Design indicators of configurable digital filter with decimation rate

[0054]

[0055]

[0056] Exemplarily, the decimation rate configurable digital filter applied to BMS of the present invention adopts Smic 0.18ummmrf process, the operating voltage is 3.3V, the input swing is ±1.5V, the input signal frequency is 2.56KHz, the obtained signal-to-noise ratio and signal-to-noise-distortion ratio are 108.1dB and 119.9dB respectively, and the effective number of bits (ENOB) is 19.62bit, which can meet the requirements of Sigma delta ADC in BMS system. In addition, the signal spectrum obtained by the decimation rate configurable digital filter applied to BMS provided by the present invention is as follows: Figure 7 shown.

[0057] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0058] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0059] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0060] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A configurable decimation rate digital filter for BMS, characterized in that: include: A decimation filter, a compensation filter, a half-band filter and an SPI configuration interface circuit, wherein the decimation filter, the compensation filter and the half-band filter are sequentially connected in series, and the SPI configuration interface circuit is respectively connected to the clock control terminals of the decimation filter, the compensation filter and the half-band filter; The decimation filter is used to perform multiple decimation on the input signal to obtain a density wave; The compensation filter is used to compensate the density wave by using an amplitude-frequency characteristic opposite to that of the extraction filter to obtain a compensated density wave; The half-band filter is used to perform a frequency-reduction operation on the compensated density wave to obtain a digital signal; The SPI configuration interface circuit is used to configure the decimation factors of the decimation filter, the compensation filter, and the half-band filter respectively according to the input clock input signal SCLK and the external input control instruction.

2. The decimation rate configurable digital filter for BMS according to claim 1, characterized in that: The decimation filter is a 4-stage CIC decimation filter with a recursive structure.

3. The decimation rate configurable digital filter for BMS according to claim 1, characterized in that: The compensation filter is an ISOP compensation filter.

4. The decimation rate configurable digital filter for BMS according to claim 1, characterized in that: The half-band filter is a half-band filter with an improved insensitive structure.

5. The decimation rate configurable digital filter for BMS according to claim 1, characterized in that: The SPI configuration interface circuit is specifically used to change the assignment of the D register according to an external control instruction, and to generate clock frequency division signals required for the operation of the decimation filter, the compensation filter and the half-band filter according to the changed assignment of the D register and the input clock input signal SCLK, and the clock frequency division signals required for the operation of the decimation filter, the compensation filter and the half-band filter are used to control the decimation factors of the decimation filter, the compensation filter and the half-band filter respectively.

6. The decimation rate configurable digital filter applied to BMS according to claim 5, characterized in that: The clock division signal required for the decimation filter to work is used to configure the decimation factor of the decimation filter to one of 32, 64, 128, 256, 512, and 1024. The clock division signal required for the compensation filter and the half-band filter to work is used to configure the decimation factors of the compensation filter and the half-band filter to 2.

7. The decimation rate configurable digital filter for BMS according to claim 5, characterized in that: When the value of the D register after the change is 5, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 32, 2, and 2 respectively, and the total decimation factor of the configurable decimation rate digital filter is 128; When the value of the D register after the change is 6, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 64, 2, and 2 respectively, and the total decimation factor of the configurable decimation rate digital filter is 256; When the value of the D register after the change is 7, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 128, 2, and 2 respectively, and the total decimation factor of the configurable decimation rate digital filter is 512; When the value of the D register after the change is 8, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 256, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 1024; When the value of the D register after the change is 9, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 512, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 2048; When the value of the D register after the change is 10, the decimation factors of the decimation filter, the compensation filter and the half-band filter are 1024, 2, and 2 respectively, and the total decimation factor of the configurable digital filter is 4096.

8. The decimation rate configurable digital filter for BMS according to claim 1, characterized in that: The SPI configuration interface circuit includes a status register, a data register and a D register, and the SPI configuration interface circuit is also used to realize the function of a clock frequency division circuit; in the SPI mode, the SPI configuration interface circuit is a host, and the filter module composed of the extraction filter, the compensation filter and the half-band filter is a slave.

9. The decimation rate configurable digital filter applied to BMS according to claim 3, characterized in that: The input sampling frequency of the ISOP compensation filter is 96 kHz, the passband cutoff frequency is 10 kHz, the stopband cutoff frequency is 86 kHz, the passband ripple is 0.01 dB, and the stopband attenuation is -110 dB.

10. The decimation rate configurable digital filter applied to BMS according to claim 4, characterized in that: The input sampling frequency of the half-band filter is 48kHz, the output signal frequency is 24kHz, the passband cutoff frequency is 10kHz, the stopband cutoff frequency is 20kHz, the passband ripple is 0.01dB, and the stopband attenuation is -110dB.

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