Cascode semiconductor device

Abstract

A cascode semiconductor device includes a normally on type high voltage (HV) silicon carbide (SiC) junction field effect transistor (JFET), a normally off type low voltage (LV) gallium nitride (GaN) high electron mobility transistor (HEMT), and a clamp circuit. The SiC JFET has a first gate terminal, a first drain terminal, and a first source terminal. The GaN HEMT has a second gate terminal, a second drain terminal, and a second source terminal. The second drain terminal is connected to the first source terminal. The second source terminal is connected to the first gate terminal. The clamp circuit is connected between the second drain terminal and the second gate terminal and has a clamp voltage. The clamp voltage is greater than a magnitude of a threshold voltage of the SiC JFET and less than a reverse gate voltage limit of the SiC JFET.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 589,027, filed on October 10, 2023, and the invention name of the application is "Cascode GaN / SiC Device Integrated with a Clamping Circuit for the Gate Protection of SiC JFET", the entire contents of which are hereby incorporated by reference into this document. Technical Field

[0003] The present disclosure relates generally to semiconductor devices, and more particularly to cascode semiconductor devices. Background Art

[0004] Any discussion of the prior art throughout the specification should not be considered as an admission that such prior art is widely known or forms part of the common general knowledge in the field.

[0005] Power devices based on wide bandgap (WBG) semiconductors such as gallium nitride (GaN) and silicon carbide (SiC) are suitable for the next generation of high-efficiency and high-power density converters, mainly because they have superior performance than silicon (Si) based power devices, such as higher operating temperature, faster switching speed and lower specific on-resistance.

[0006] SiC-based power devices, such as SiC metal oxide semiconductor field effect transistors (MOSFETs) and SiC junction field effect transistors (JFETs), have been intensively developed with the goal of being applied to high voltage levels. For SiC MOSFETs, the gate oxide is made of silicon dioxide (SiO 2 The high trap density at the SiC / SiC interface significantly reduces the channel mobility, thereby increasing the channel resistance and conduction losses. SiC JFETs do not have the high channel resistance problem, but their depletion mode (D-type) gate control is not ideal in power electronics applications that require fail-safe operation. Summary of the invention

[0007] According to an embodiment of the present disclosure, a cascode semiconductor device includes a normally-on high voltage (HV) silicon carbide (SiC) junction field effect transistor (JFET), a normally-off low voltage (LV) gallium nitride (GaN) high electron mobility transistor (HEMT), and a clamping circuit. The SiC JFET has a first gate terminal, a first drain terminal, and a first source terminal. The GaN HEMT has a second gate terminal, a second drain terminal, and a second source terminal. The second drain terminal is connected to the first source terminal. The second source terminal is connected to the first gate terminal. The clamping circuit is connected between the second drain terminal and the second gate terminal and has a clamping voltage. The clamping voltage is greater than the magnitude of the threshold voltage of the SiC JFET and less than the reverse gate voltage limit of the SiC JFET.

[0008] According to certain embodiments, the GaN HEMT and the SiC JFET have substantially the same current rating.

[0009] According to certain embodiments, SiC JFETs have significantly higher blocking voltage ratings than GaN HEMTs.

[0010] According to certain embodiments, the clamping circuit is monolithically integrated with the GaN HEMT.

[0011] According to some embodiments, the clamping circuit includes a plurality of diodes connected in series.

[0012] According to certain embodiments, the clamping circuit includes a plurality of lateral field effect rectifiers (L-FERs) connected in series. In some embodiments, each of the plurality of L-FERs is implemented by connecting a gate contact and a source contact of another LV GaN HEMT. The number of the plurality of L-FERs may be based on the clamping voltage.

[0013] According to some embodiments, the clamping circuit includes a bidirectional Zener diode.

[0014] According to some embodiments, the clamping circuit includes a Zener diode connected in series with a diode.

[0015] According to some embodiments, the diode is selected from the group consisting of a PN diode, a Schottky barrier diode, and a lateral field effect rectifier. In some embodiments, the diode may be implemented by connecting the source terminal and the gate terminal of another LV GaN HEMT.

[0016] According to some embodiments, the clamping voltage is greater than 7V and less than 30V.

[0017] According to an embodiment of the present disclosure, a cascode semiconductor circuit includes a cascode semiconductor device and a driving circuit connected between a second gate terminal and a second source terminal of a GaN HEMT for applying a gate signal to the second gate terminal.

[0018] According to some embodiments, the gate-source voltage of the SiC JFET is clamped below 30V.

[0019] According to an embodiment of the present disclosure, a method of operating a cascode semiconductor device includes applying a turn-off signal to a second gate terminal of a GaN HEMT through a driving circuit, and in response to the turn-off signal, a current flowing through the GaN HEMT is transferred to a capacitor connected between a second drain terminal and a second source terminal of the GaN HEMT.

[0020] According to some embodiments, the method further includes: in response to the shutdown signal, the current flowing through the SiC JFET is transferred to a capacitor connected between the first gate terminal and the first drain terminal of the SiC JFET, thereby increasing the voltage between the first drain terminal and the second source terminal.

[0021] According to some embodiments, the method further includes, in response to the shutdown signal, if a voltage between the second drain terminal and the second source terminal exceeds a clamping voltage, flowing a current into the second gate terminal of the GaN HEMT through the clamping circuit.

[0022] According to some embodiments, the method further includes: in response to the turn-off signal, increasing a voltage at a second gate terminal of the GaN HEMT, thereby increasing a channel conductivity of the GaN HEMT.

[0023] According to some embodiments, the method further includes: in response to the turn-off signal, a portion of the current flows through a channel of the GaN HEMT and charges stored in a capacitance of the GaN HEMT are discharged, thereby suppressing a drain-source overvoltage of the GaN HEMT.

[0024] Other example embodiments are discussed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The detailed description is described with reference to the accompanying drawings. The drawings are for illustration purposes only and depict only example embodiments of the present disclosure. The drawings are provided to aid in understanding the present disclosure and should not be considered to limit the breadth, scope, or applicability of the present disclosure. The drawings are not drawn to scale unless otherwise noted. Certain portions of the drawings may be exaggerated for explanation purposes, which should not be considered limiting unless otherwise noted.

[0026] Figure 1 A cascode semiconductor device according to some embodiments of the present disclosure is shown.

[0027] Figure 2 Shows Figure 1 A first specific embodiment of the cascode semiconductor device, wherein the clamping circuit includes a plurality of diodes.

[0028] Figure 3 Shows Figure 1 In a second specific embodiment of the cascode semiconductor device, the clamping circuit includes a plurality of lateral field effect rectifiers (L-FERs).

[0029] Figure 4 Shows Figure 1 A third specific implementation of the cascode semiconductor device, wherein the clamping circuit includes a bidirectional Zener diode.

[0030] Figure 5 Shows Figure 1 A fourth specific embodiment of the cascode semiconductor device, wherein the clamping circuit includes a Zener diode connected in series with a diode, and the diode may be a PN diode, a Schottky barrier diode or an L-FER.

[0031] Figure 6 A cascode semiconductor circuit is shown according to some embodiments of the present disclosure.

[0032] Figure 7 An operating method of a cascode semiconductor device according to some embodiments of the present disclosure is shown.

[0033] Fig. 8A The first stage (stage 1) of the operating principle of a cascode semiconductor device according to some embodiments of the present disclosure is shown.

[0034] Figure 8B Shows Fig. 8A The second stage (stage 2) of the working principle of the cascode semiconductor device.

[0035] Fig. 9 A test circuit for characterizing the switching process of a cascode semiconductor device with and without a clamping circuit according to some embodiments of the present invention is shown.

[0036] Fig. 10A FIG. 1 shows that according to some embodiments of the present invention, a common-source common-gate semiconductor device without a clamp circuit is respectively D = V during the shutdown process at 8A and 24A DS ~Time curve.

[0037] Fig. 10B Shows Fig. 10A The common source and common gate semiconductor devices are respectively in I D = I during the shutdown process at 8A and 24ADS ~Time curve.

[0038] Fig. 10C Shows Fig. 10A The common source and common gate semiconductor devices are respectively in I D = -V at 8A and 24A during its shutdown process GS-JFET ~Time curve.

[0039] Fig.11A FIG. 1 shows a common-source common-gate semiconductor device with a clamp circuit according to some embodiments of the present invention. D = V during the shutdown process at 8A and 24A DS ~Time curve.

[0040] Fig. 11B Shows Fig.11A The common source and common gate semiconductor devices are respectively in I D = I during the shutdown process at 8A and 24A DS ~Time curve.

[0041] Fig. 11C Shows Fig.11A The common source and common gate semiconductor devices are respectively in I D = -V at 8A and 24A during its shutdown process GS-JFET ~Time curve. DETAILED DESCRIPTION

[0042] The present disclosure will now be described with reference to the following examples, which are to be considered in all respects as illustrative and non-restrictive.

[0043] Throughout the specification and claims, the words "include", "comprising", etc. should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0044] Furthermore, as used herein, unless otherwise indicated, the use of ordinal adjectives "first," "second," etc., to describe common objects merely indicates that different instances of similar objects are being referred to and is not intended to imply that the objects so described must be arranged in a given order, whether temporally, spatially, in ranking, or in any other manner.

[0045] Example embodiments relate to cascode semiconductor devices, circuits, and methods thereof.

[0046] Combining a low voltage (LV) enhancement mode (E-mode) Si MOSFET with a high voltage (HV) depletion mode (D-mode) SiC JFET into a cascode Si / SiC configuration can realize HV E-mode power devices with low conduction losses. In addition, GaN E-mode high electron mobility transistors (HEMTs) have been widely used and commercialized, with products ranging from low voltage to medium voltage levels from 15V to 650V. The advantages of LV E-mode GaN HEMTs and HV D-mode SiC JFETs can be combined to realize HV cascode GaN / SiC devices. Compared with cascode Si / SiC devices, LV Si MOSFETs are replaced by LV GaN HEMTs. This results in faster switching speeds, higher operating temperatures, thermally stable threshold voltages (V TH ) and zero reverse recovery charge (Q rr )’s benefits.

[0047] However, replacing LV Si MOSFETs with LV GaN HEMTs can lead to some challenging issues. These issues include gate overstress of the HV SiC JFET during switching. Since LV GaN HEMTs lack avalanche capability, it is not possible to clamp the drain-source voltage (V) of the GaN HEMT during switching. DS-HEMT As a result, the gate of the HV SiC JFET may be overstressed because the gate-source voltage (V GS-JFET ) is equal to V with opposite polarity DS-HEMT In contrast, the JFET gate in a cascode Si / SiC device is protected from overstress because V GS-JFET Can be clamped by avalanche capable LV Si MOSFET.

[0048] To protect the gate of the HV SiC JFET in a cascode GaN / SiC device, a flip-chip co-packaging structure can be used to reduce the parasitic interconnect inductance between the SiC JFET and the GaN HEMT to suppress oscillation and reduce V during switching. DS-HEMT However, in addition to the parasitic inductance, the capacitance mismatch between the HV JFET and the LV HEMT also causes V DS-HEMT overshoot and the associated JFET gate overstress. Therefore, a Zener diode (ZD) can be used for reliable V DS-HEMTclamp, thereby protecting the SiC JFET from gate overstress even after co-packaging. ZD is a heavily doped Si PN junction with a forward conduction voltage of ~0.7V, which is lower than the reverse conduction turn-on voltage of GaN HEMT. Therefore, during the reverse conduction stage of the cascode GaN / SiC device, the current flows through the forward biased Si PN junction of ZD. Therefore, when the cascode device switches from reverse conduction mode to forward blocking mode, ZD undergoes a reverse recovery process to clear the excess minority carriers in the Si PN junction, resulting in a prolonged switching process and increased switching losses.

[0049] Example embodiments overcome or ameliorate at least one of the disadvantages of the prior art by providing a new structural design with improved device performance.

[0050] Example embodiments include a cascode semiconductor device including a GaN / SiC device integrated with a clamp circuit. According to one or more embodiments, a gate of a SiC JFET may be protected from overstress without compromising the switching performance of the cascode GaN / SiC device.

[0051] According to one or more embodiments, a cascode semiconductor device includes a cascode GaN / SiC power device integrated with a clamping circuit for protecting the SiC JFET from gate overstress during switching. The cascode GaN / SiC power device includes an HV normally-on SiC JFET, a LV normally-off GaN HEMT, and a clamping circuit. The gate and source of the HV SiC JFET are connected to the source and drain of the LV GaN HEMT, respectively. The clamping circuit is electrically arranged between the drain and the gate of the LV GaN HEMT. The gate and source of the LV GaN HEMT are the gate and source of the cascode GaN / SiC device, respectively, and the drain of the HVSiC JFET is the drain of the cascode GaN / SiC device. The integrated clamping circuit can clamp or suppress the drain-source overvoltage of the LV GaN HEMT during switching, thereby protecting the HV SiC JFET from gate overstress.

[0052] One or more embodiments include a cascode semiconductor device, which includes a SiC JFET, a GaN HEMT, and a clamping circuit. The gate and source of the SiC JFET are connected to the source and drain of the GaN HEMT, respectively, thereby forming a current path through the SiC JFET and the GaN HEMT. The clamping circuit is connected between the drain and the gate of the GaN HEMT. The SiC JFET can be protected from gate overstress without affecting the switching performance of the cascode GaN / SiC device. Through the clamping circuit, the gate voltage of the SiC JFET can be effectively clamped, thereby protecting the SiC JFET from gate overstress during the switching process. Compared with the above-mentioned ZD protection scheme, the reverse conduction current of the cascode semiconductor device flows through the GaN HEMT, and when operating in the reverse conduction mode, the Q of the GaN HEMT rr is zero. Therefore, since Q is not introduced rr , so the reverse recovery performance of the cascode semiconductor device is not affected. In addition, since the clamp circuit only needs to conduct a small current of several amperes during the short switching transient duration of less than a few hundred nanoseconds, the parasitic capacitance of the clamp circuit can be very small. Therefore, the switching speed of the cascode semiconductor device is not significantly affected.

[0053] Figure 1 A cascode semiconductor device 100 according to some embodiments of the present disclosure is shown. The cascode semiconductor device 100 includes a normally-on HV SiC JFET 110 , a normally-off LV GaN HEMT 120 , and a clamping circuit 130 .

[0054] The SiC JFET 110 includes a first gate terminal G1, a first drain terminal D1, and a first source terminal S1. The LV GaNHEMT 120 includes a second gate terminal G2, a second drain terminal D2, and a second source terminal S2. The second drain terminal D2 is connected to the first source terminal S1, and the second source terminal S2 is connected to the first gate terminal G1.

[0055] The clamp circuit 130 is connected between the second drain terminal D2 (which is connected to the first source terminal S1) and the second gate terminal G2. The clamp circuit 130 has a clamp voltage. The clamp voltage is greater than the threshold voltage (V TH ) and is below the reverse gate voltage limit of the SiC JFET.

[0056] The threshold voltage is a key parameter that defines the gate-source voltage at which the transistor starts to turn off. For normally-on SiC JFETs, the threshold voltage is usually negative. This means that a negative gate-source voltage is required to turn the device off. V THThe exact value of may vary depending on the specific device and manufacturer, but is typically in the range of -2V to -30V. The magnitude of the threshold voltage is its absolute value, i.e. |V TH |.

[0057] The reverse gate voltage limit of a normally-on SiC JFET specifies the maximum allowable negative gate-source voltage that can be applied without damaging the device. This parameter is critical to ensuring the reliability and lifetime of the device. As an example, the reverse gate voltage limit of a SiC JFET may be around 30V. In some embodiments, the clamping voltage may be greater than 7V and less than 30V. In some embodiments, the clamping voltage may be other values, depending on the specific application in which the device is used.

[0058] In some embodiments, the GaN HEMT 120 and the SiC JFET 110 have substantially the same (e.g., the same or similar) rated current. The rated current specifies the maximum amount of continuous drain current that the device can handle without suffering damage or performance degradation. The rated current may depend on the specific device, its application conditions, and its manufacturer. For example, the rated currents of the GaN HEMT 120 and the SiC JFET 110 may be in the range of 1A to 100A. In a common source and common gate device, having substantially the same rated current in the GaN HEMT 120 and the SiC JFET 110 optimizes performance, improves reliability, and simplifies design. This balanced approach takes full advantage of the advantages of both materials—GaN for high-speed switching and SiC for high-voltage processing—while suppressing overstress in both transistors, thereby improving overall device efficiency and life.

[0059] In some embodiments, the rated blocking voltage of the SiC JFET 110 can be significantly higher than the rated blocking voltage of the GaN HEMT 120. The rated blocking voltage is the maximum voltage that a device can withstand in the off state without breakdown. This parameter is critical to ensure that the device can handle high voltage conditions in various power electronics applications. In some embodiments, the rated blocking voltage of the SiC JFET 110 is in the range of 200V to 3000V, while the rated blocking voltage of the GaN HEMT 120 is in the range of 10V to 50V, which is significantly lower than the rated blocking voltage of the SiC JFET 110.

[0060] The design of the present application provides several significant benefits. SiC JFETs have a higher blocking voltage and can handle higher voltages than GaN HEMTs. This enables cascode devices to operate effectively in high voltage applications while maintaining safety and reliability. Since SiC JFETs have a higher blocking voltage, GaN HEMTs are protected from high voltages. This reduces the voltage stress on the GaN HEMT, allowing it to focus on its strengths - high-speed switching. Therefore, this enhances the device's ability to handle high voltages while taking full advantage of the high-speed switching capabilities of the GaN HEMT. This improves efficiency, reliability and flexibility in high voltage and high-frequency applications, making the cascode device very effective for modern power electronics and switching applications.

[0061] In some embodiments, the clamp circuit 130 may be formed as a separate module that is separate from the SiC JFET 110 and / or the GaN HEMT 120. In some embodiments, the clamp circuit 130 may be monolithically integrated with the GaN HEMT 120. That is, during the manufacturing process, the clamp circuit 130 and the GaN HEMT 120 are manufactured together on the same semiconductor substrate. This can be achieved by integrating different elements in a coordinated manner using advanced semiconductor manufacturing techniques. This integration allows both the clamp circuit and the GaN HEMT to operate as a single unified device rather than separate components. Therefore, this results in a compact device arrangement with improved performance, such as faster response time and better protection against transient events.

[0062] The cascode semiconductor device 100 can be considered as a three-terminal device having a gate terminal G, a drain terminal D, and a source terminal S. Figure 1 As shown, the first drain terminal D1, the second source terminal S2, and the second gate terminal G2 are respectively used as the drain terminal D, the source terminal S, and the gate terminal G of the cascode semiconductor device 100. The cascode semiconductor device 100 can be driven on or off by applying a driving signal (e.g., a voltage) to the gate terminal G. In some embodiments, the combination of the SiC JFET 110 and the GaN HEMT 120 is referred to as a cascode GaN / SiC device, and thus the cascode semiconductor device 100 includes a cascode GaN / SiC device and a clamping circuit.

[0063] The clamping circuit can be implemented in a variety of ways. Figures 2 to 5 Some examples are explained in detail.

[0064] like Figure 2As shown, the clamp circuit 230 includes a plurality of diodes 231 ... 23N connected in series. N is an integer greater than 1. That is, the total number of diodes is N. The plurality of diodes form a diode chain starting from the first diode 231 and ending at the last diode 23N. The anode 23a of the diode 231 is connected to the second drain terminal D2 of the GaN HEMT 120 (or the first source terminal S1 of the SiC JFET 110, because the terminals D2 and S1 are connected). The cathode 23b of the diode 23N is connected to the second gate terminal G2 of the GaN HEMT 120. Each diode may be a PN diode, such as a Si PN diode or a GaN PN diode. It is preferred that the plurality of diodes be implemented as GaN PN diodes, because this will be compatible with the GaN HEMT during device manufacturing.

[0065] like Figure 3 As shown, the clamping circuit 330 includes a plurality of lateral field effect rectifiers (L-FER) 331 ... 33N connected in series. N is an integer greater than 1. That is, the total number of L-FERs is N. The plurality of L-FERs form an L-FER chain, starting from the first L-FER 331 and ending at the last L-FER 33N. For the first L-FER 331, its source terminal and gate terminal are both connected to the second drain terminal D2 of the GaN HEMT 120 (or the first source terminal S1 of the SiC JFET 110). For the last L-FER 33N, its drain terminal is connected to the second gate terminal G2 of the GaN HEMT 120.

[0066] L-FER has the characteristics of both field effect transistor and rectifier, and is suitable for specific applications that require both high-speed switching and rectification. Each L-FER can be realized or formed or implemented by connecting the gate and source contacts of LV GaN HEMT to form an anode terminal, such as Figure 3 As shown. Take the first L-FER 331 as an example. It is implemented by connecting the gate terminal or contact G0 and the source terminal or contact S0 of the LV GaN HEMT, and the LV GaN HEMT can have the same or different electrical properties compared with the LV GaN HEMT 120, depending on actual needs. Depending on actual needs, the geometric dimensions and / or electrical properties of the LV GaNHEMT used to form multiple L-FERs can be the same or different. The clamping circuit can be an independent module or can be monolithically integrated with the GaNHEMT 120. The parasitic capacitance of the clamping circuit can be designed to be negligible because the circuit only needs to conduct a small current into the gate terminal of the GaN HEMT during the turn-off transient. The number of L-FERs connected in series in the clamping circuit can be determined by or based on a predetermined or preset target clamping voltage. The clamping voltage can be greater than the V of the SiC JFETTH The magnitude of the clamp voltage can be 7V, for example, to ensure that the cascode device can be turned off during the switching process. In addition, the clamp voltage can be lower than the reverse gate voltage limit of the SiC JFET, for example, 30V, to protect the SiC JFET from gate overstress.

[0067] like Figure 4 As shown, the clamping circuit 430 includes a bidirectional Zener diode. The bidirectional Zener diode includes two Zener diodes 432 and 434 connected in series but oriented in opposite directions. The anode of the Zener diode 432 is connected to the second drain terminal D2 of the GaN HEMT 120 (or the first source terminal S1 of the SiC JFET 110). The anode of the Zener diode 434 is connected to the second gate terminal G2 of the GaN HEMT 120. The bidirectional Zener diode provides positive and negative voltage spike protection, so that the device can clamp overvoltages of both polarities to prevent damage caused by positive and negative transients.

[0068] like Figure 5 As shown, the clamp circuit may be a clamp circuit 530-1, a clamp circuit 530-2, or a clamp circuit 530-3. The clamp circuit 530-1 includes a Zener diode 531 connected in series with a PN diode 532. The clamp circuit 530-2 includes a Zener diode 533 connected in series with a Schottky barrier diode 534. The clamp circuit 530-3 includes a Zener diode 535 connected in series with a lateral field effect rectifier 536. The anodes of the Zener diodes 531, 533, and 535 are connected to the second gate terminal G2 of the GaN HEMT 120. The anodes of the PN diode 532, the Schottky barrier diode 534, and the lateral field effect rectifier 536 are connected to the second drain terminal D2 of the GaN HEMT 120 (or the first source terminal S1 of the SiC JFET 110). In this embodiment, a lateral field effect rectifier 536 is shown implemented by connecting the gate and source contacts of a LV GaN HEMT (not GaN HEMT 120) to form an anode terminal.

[0069] Figure 6A cascode semiconductor circuit according to some embodiments of the present disclosure is shown. The cascode semiconductor circuit includes a cascode semiconductor device and a drive circuit 640. The cascode semiconductor device may be any cascode semiconductor device as described above with reference to one or more figures. For example, the cascode semiconductor device includes a normally-on HV SiC JFET 110, a normally-off LV GaN HEMT 120, and a clamp circuit 630. The clamp circuit 630 may be any clamp circuit as described above with reference to one or more figures. The drive circuit 640 is connected between the second gate terminal G2 and the second source terminal S2 of the GaN HEMT 120, and is used to apply a drive signal or a gate signal to the second gate terminal G2. The drive circuit is a circuit that generates a gate signal. The gate signal includes one or more signals for driving the cascode semiconductor device. For example, the gate signal may include a turn-off signal to turn off the cascode semiconductor device. For example, the gate signal may include a turn-on signal to turn on the cascode semiconductor device. The gate signal may include one or more voltage signals.

[0070] refer to Figure 7 , Fig. 8A and Figure 8B , showing a method of operating a common-source common-gate semiconductor device according to some embodiments of the present disclosure. The common-source common-gate semiconductor device may be as described above with reference to Figures 1 to 6 Any common-source and common-gate semiconductor device described above. For example, Figure 6 A cascode semiconductor circuit or a cascode semiconductor circuit comprising Figure 6 A circuit of a cascode semiconductor circuit can implement one or more of the methods.

[0071] refer to Figure 7 , at block 710, a shutdown signal is applied to a second gate of the GaN HEMT. The GaN HEMT may be any of the GaN HEMTs 120 described above with reference to one or more of the figures. The shutdown signal may be a voltage signal that turns off the GaN HEMT. In some embodiments, the shutdown signal may be a termination of applying the voltage signal to the second gate of the GaN HEMT, thereby turning off the GaN HEMT.

[0072] At block 720, in response to the shutdown signal, the current flowing through the GaN HEMT is transferred to a capacitor connected between the second drain terminal and the second source terminal of the GaN HEMT. This will be referred to below. Fig. 8A and Figure 8B This is further described by way of examples.

[0073] Due to the turn-off signal, the GaN HEMT 120 is turned off and enters the saturation region. The current will be transferred to the output capacitor C2 provided between the second drain terminal and the source terminal of the GaN HEMT 120 (see Fig. 8A The output capacitor C2 is a parasitic capacitor generated during the manufacturing process of the GaN HEMT 120, so the drain-source voltage (V DS-HEMT ) will increase. The SiC JFET 110 is then pinched off. The current will then transfer to the gate-drain capacitance (not shown) of the SiC JFET 110, and the drain-source voltage of the cascode GaN / SiC device will increase and block the current (see Figure 8B During the shutdown process, if V DS-HEMT If the clamping voltage of the clamping circuit 830 is exceeded, a small current will be injected into the second gate terminal of the GaN HEMT 120 through the clamping circuit 830 (see Fig. 8A and Figure 8B As a result, the gate voltage of the GaN HEMT 120 in the saturation region is slightly increased, and accordingly, the channel conductivity of the GaN HEMT 120 is enhanced. Therefore, part of the current can flow through the channel of the GaN HEMT 120 instead of charging the output capacitor C2 of the GaN HEMT 120 (see Figure 8B The charge stored in the output capacitor of the GaN HEMT can also be discharged by process (iii) in Figure 8B The turn-off process of this cascode GaN / SiC device suppresses the drain-source overvoltage of the GaN HEMT 120, thereby providing gate overstress protection for the SiC JFET.

[0074] exist Fig. 8A and Figure 8B In the embodiment, the clamping circuit 830 includes a plurality of diodes connected in series. It should be understood that this is for illustration purposes only, and the clamping circuit can be implemented in different ways, including but not limited to the above referenced Figures 3 to 5 Any one of the clamping circuits described above.

[0075] Fig. 9 A test circuit for characterizing the switching process of a cascode semiconductor device with and without a clamping circuit according to certain embodiments of the present disclosure is shown. The device under test (DUT) is a 1200V / 30A cascode GaN / SiC device built using a SPICE simulation model of a commercial device.

[0076] The test circuit includes a rated voltage V DC900, a driving circuit 940 for driving the cascode semiconductor device 900, a Schottky barrier diode 902, and a load 904 in the form of a resistor. The cascode semiconductor device 900 includes a HV SiC JFET 910 and a LV GaN HEMT 920. The source terminal of the SiC JFET 910 is connected to the drain terminal of the GaN HEMT 920 to form a current path. The drain terminal D, the source terminal S and the gate terminal G of the cascode semiconductor device 900, and the drain-source voltage V DS , drain-source current I DS , the gate-source voltage (V GS-JFET ), and load current I D Also there Fig. 9 For comparison purposes, some common-source and common-gate semiconductor devices each include the same Figures 1 to 5 The clamping circuit of any one of the above, while the other cascode semiconductor devices each do not include any clamping circuit.

[0077] FIG. 10A to FIG. 10C Test results of a cascode semiconductor device that does not include any clamping circuit are shown. FIG. 11A to FIG. 11C Test results of a cascode semiconductor device including a clamping circuit are shown.

[0078] It can be seen that without the clamp circuit, the gate voltage (V GS-JFET ) exceeds the safety limit during the turn-off process, thus overstressing the gate of the SiC JFET. In addition, at higher load currents, V DS ,I DS and V GS-JFET The oscillation is very obvious.

[0079] In contrast, when a clamping circuit is used, the gate voltage of the JFET is well clamped in a safe area (i.e., an area below the safety limit), thereby providing protection for the gate of the JFET. In addition, the use of a clamping circuit can also significantly suppress switching process oscillations, which is beneficial in power electronic systems.

[0080] According to the above embodiments, one or more cascode semiconductor devices, circuits and methods thereof are provided. By incorporating a clamping circuit, the cascode semiconductor device or circuit can alleviate or avoid gate overstress of the HV SiC JFET without compromising switching performance. This is particularly advantageous in applications requiring high voltage and rapid acceleration.

[0081] According to one or more embodiments, the clamping circuit can be monolithically integrated with the GaN HEMT. For example, when the clamping circuit includes a plurality of diodes connected in series or a plurality of lateral field effect rectifiers (L-FERs) connected in series, as described and shown above, the clamping circuit and the GaN HEMT can be manufactured together on the same semiconductor substrate. This provides multiple technical advantages. For example, such monolithic integration reduces the parasitic inductance and resistance associated with external wiring and packaging, thereby improving switching performance and efficiency. Lower parasitic elements can achieve faster switching speeds, which is particularly advantageous in high-frequency applications. As another example, monolithic integration allows for a more compact design, thereby reducing the overall size and weight of the power module. This is particularly advantageous in applications where space and weight are critical factors. Integration also reduces the number of discrete components required, thereby reducing assembly and material costs. Fewer components means a lower probability of failure and lower maintenance requirements, further reducing long-term costs. In addition, the monolithic integration solution simplifies the design process because the clamping circuit is already built into the device, reducing the need for additional design steps and verification.

[0082] The inventors have further recognized that when the clamping circuit includes one or more Zener diodes, it cannot be monolithically integrated with the GaN HEMT of the cascode GaN / SiC device because the Zener diode cannot be realized with GaN material at this stage. Therefore, those skilled in the art will understand after reading this disclosure that certain embodiments are superior to others.

[0083] It will also be understood that the clamp circuit described above is illustrative. Modifications or variations to the clamp circuit described are possible and still within the conceptual scope of the present disclosure.

[0084] As used herein, the term "high voltage," "high voltage," or "HV" refers to a breakdown voltage of 400V or above.

[0085] As used herein, the term "low voltage," "low voltage," or "LV" refers to a breakdown voltage between 30V and 60V, inclusive.

[0086] As used herein, the term "connected" or "connected" refers to an electrical connection.

[0087] As used herein, the "channel" of a field effect transistor refers to the path or region through which charge carriers (electrons or holes) flow from the source terminal of the transistor to the drain terminal of the transistor when the transistor is operating. The conductivity of this path or region is controlled by the voltage applied to the gate terminal of the transistor.

[0088] As used herein, the term "independent module" refers to a self-contained module or functional unit that is formed separately and independently.

[0089] It should also be understood that any features in the above embodiments of the present disclosure can be combined together, and do not have to be applied in isolation from each other. Those skilled in the art can easily make similar combinations of two or more features in the above embodiments or preferred forms of the present disclosure.

[0090] Unless otherwise defined, technical and scientific terms used herein have the simple meanings commonly understood by those skilled in the art in connection with the example embodiments. It will be appreciated by those skilled in the art that many variations and / or modifications may be made to the above-described embodiments without departing from the broad general scope of the present disclosure. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive.

Claims

1. A common-source common-gate semiconductor device, comprising: a normally-on high voltage (HV) silicon carbide (SiC) junction field effect transistor (JFET) having a first gate terminal, a first drain terminal, and a first source terminal; a normally-off low voltage (LV) gallium nitride (GaN) high electron mobility transistor (HEMT) having a second gate terminal, a second drain terminal, and a second source terminal, the second drain terminal being connected to the first source terminal, the second source terminal being connected to the first gate terminal; and A clamp circuit is connected between the second drain terminal and the second gate terminal and has a clamp voltage that is greater than a magnitude of a threshold voltage of the SiC JFET and less than a reverse gate voltage extreme value of the SiC JFET. 2 . The cascode semiconductor device of claim 1 , wherein the GaN HEMT and the SiC JFET have substantially the same current rating. 3 . The cascode semiconductor device according to claim 1 , wherein a rated blocking voltage of the SiC JFET is significantly higher than a rated blocking voltage of the GaN HEMT. 4 . The cascode semiconductor device according to claim 1 , wherein the clamping circuit can be monolithically integrated with the GaN HEMT or connected to the GaN HEMT as an independent module. 5 . The cascode semiconductor device according to claim 1 , wherein the clamping circuit comprises a plurality of diodes connected in series. 6 . The cascode semiconductor device of claim 1 , wherein the clamping circuit comprises a plurality of lateral field effect rectifiers (L-FERs) connected in series. 7 . The cascode semiconductor device according to claim 6 , wherein each of the plurality of L-FERs is implemented by connecting a source contact and a gate contact of another LV GaN HEMT. 8 . The cascode semiconductor device of claim 7 , wherein a number of the plurality of L-FERs is based on the clamping voltage. 9 . The cascode semiconductor device of claim 1 , wherein the clamping circuit comprises a bidirectional Zener diode. 10 . The cascode semiconductor device of claim 1 , wherein the clamping circuit comprises a Zener diode connected in series with a diode.

11. The cascode semiconductor device of claim 10, wherein the diode is selected from the group consisting of a PN diode, a Schottky barrier diode, and a lateral field effect rectifier. 12 . The cascode semiconductor device according to claim 10 , wherein the diode can be implemented by connecting a source terminal and a gate terminal of another LV GaN HEMT. 13 . The cascode semiconductor device according to claim 1 , wherein the clamping voltage is greater than 7V and less than 30V.

14. A common-source common-gate semiconductor circuit, comprising: The cascode semiconductor device according to claim 1; as well as A driving circuit is connected between the second gate terminal and the second source terminal of the GaN HEMT and is used to apply a gate signal to the second gate terminal.

15. The cascode semiconductor circuit of claim 14, wherein the gate-source voltage of the SiC JFET is clamped below 30V.

16. A method of operating the cascode semiconductor device according to claim 14, the method comprising: applying a turn-off signal to the second gate terminal of the GaN HEMT through the driving circuit; as well as In response to the turn-off signal, the current flowing through the GaN HEMT is transferred to an output capacitor connected between a second drain terminal and a second source terminal of the GaN HEMT.

17. The method according to claim 16, further comprising: In response to the turn-off signal, current flowing through the SiC JFET is transferred to a capacitor connected between a first drain terminal and a first gate terminal of the SiC JFET, thereby increasing a voltage between the first drain terminal and the second source terminal.

18. The method according to claim 17, further comprising: In response to the turn-off signal, if a voltage between the second drain terminal and the second source terminal exceeds the clamping voltage, a current flows into the second gate terminal of the GaN HEMT through the clamping circuit.

19. The method according to claim 18, further comprising: In response to the turn-off signal, a voltage at the second gate terminal of the GaN HEMT increases, thereby improving channel conductivity of the GaN HEMT.

20. The method according to claim 19, further comprising: In response to the turn-off signal, a portion of the current flows through the channel of the GaN HEMT, and charges stored in an output capacitance of the GaN HEMT are discharged, thereby suppressing a drain-source overvoltage of the GaN HEMT.

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