Reconfigurable ffe equalization circuit based on multi-phase clock serialization, serdes transmitter and chip

Abstract

The application provides a reconfigurable FFE equalization circuit based on multi-phase clock serialization, a Serdes transmitter and a chip. The reconfigurable FFE equalization circuit based on multi-phase clock serialization comprises a multi-phase clock generation circuit configured to receive a differential voltage signal of an external clock source and generate a plurality of voltage signals with different phases, and the generated plurality of voltage signals with different phases are input to a reconfigurable FFE tap generation circuit as clock signals. The reconfigurable FFE tap generation module is configured to receive a plurality of parallel data signals input by an external signal source, serialize the plurality of parallel data signals based on the clock signals to generate a reconfigurable multi-tap signal. The generated multi-tap signal is input to a multiplexing-driving circuit. The multiplexing-driving circuit is configured to serialize and transmit the plurality of parallel multi-tap signals to a channel. The application provides a reconfigurable tap number for different application scenarios, and does not require an additional delay unit.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a reconfigurable FFE (Feed Forward Equalization) equalization circuit based on multi-phase clock serialization, a SerDes transmitter and a chip. Background Art

[0002] With the rapid development of applications such as artificial intelligence, big data, and autonomous driving, the demand for high-performance computing and high-bandwidth density data centers across various application scenarios is increasing. High-speed SerDes (Serializer-Reserializer) is widely used in data centers and high-performance computing. The transmitter, located at the transmitting end of the SerDes system, serializes low-speed parallel data into high-speed serial data and transmits it onto the channel through a driver circuit. While SerDes technology significantly increases data communication rates, it is still affected by many factors, such as skin effect, dielectric loss, reflections, noise, and crosstalk. These non-ideal factors can cause data transmission distortion, increase bit error rates, and lead to signal integrity issues. To ensure signal transmission quality, transmitters typically perform pre-distortion equalization on the signal before transmission. This pre-amplifies high-frequency components to offset attenuation caused by channel loss.

[0003] Transmitter equalization usually adopts the Feed-Forward Equalization (FFE) architecture, which is implemented as follows Figure 1 As shown. Its essence can be regarded as a finite impulse response filter (FIR), which delays the input data multiple times (T) during operation and treats the delayed data with different weights (α -1 ,α0,α1,…,α n ) are summed, the number of delayed data to be summed is called the number of taps, and the delay length T is called the tap interval. T is usually set to a fixed unit code element length 1UI (Unit Interval, code element length) so that the compensation point is set at the Nyquist frequency.

[0004] Usually, different delayed data are generated by the delay unit in the circuit, and the number of taps of the Serdes transmitter is determined during the circuit design, such as Figure 1 As shown in the figure, when applied to channels with varying loss, the number of taps may be excessive or insufficient, significantly limiting its scope of application. Furthermore, multiple delays for high-rate data result in significant power consumption and hardware overhead. Summary of the Invention

[0005] The application aims at the technical problem of generating different delay data based on a delay unit in the prior art, and provides a reconfigurable FFE equalization circuit based on multi-phase clock serialization, a Serdes transmitter and a chip, aiming at providing a reconfigurable tap number for different application scenarios without additional delay units, reducing system clock frequency, reducing full-rate nodes in the circuit and reducing overall system power consumption.

[0006] The application is implemented by the following technical solutions:

[0007] A reconfigurable FFE equalization circuit based on multi-phase clock serialization, comprising:

[0008] A multi-phase clock generation circuit is configured to receive a differential voltage signal of an external clock source and generate a plurality of voltage signals with different phases, and the generated plurality of voltage signals with different phases are input to a reconfigurable FFE tap generation circuit as clock signals.

[0009] A reconfigurable FFE tap generation module is configured to receive a plurality of parallel data signals input by an external signal source, serialize the plurality of parallel data signals based on the clock signals to generate a reconfigurable multi-tap signal, and input the generated multi-tap signal to a multiplexing-driving circuit.

[0010] The multiplexing-driving circuit is configured to serialize and transmit the plurality of parallel multi-tap signals to a channel.

[0011] Preferably, the multi-phase clock generation circuit comprises a multi-phase delay generation module, a multi-phase injection-locked ring oscillator, a frequency discriminator and a operational amplifier Gm.

[0012] The differential voltage signal V INJ,P and V INJ,N provided by the external clock source are respectively connected to differential clock input ends V INJP and V INJN of the multi-phase delay generation module, first, second, third, fourth, fifth, sixth, seventh and eighth output ends CKDL0, CKDL1, CKDL2, CKDL3, CKDL4, CKDL5, CKDL6 and CKDL7 of the multi-phase delay generation module are respectively connected to first, second, third, fourth, fifth, sixth, seventh and eighth input ends CKDL0, CKDL1, CKDL2, CKDL3, CKDL4, CKDL5, CKDL6 and CKDL7 of the multi-phase injection-locked ring oscillator; first, second and third output ends CKR 45 , CKR 90, fourth output terminal CKR 135 , fifth output terminal CKR 180 , sixth output terminal CKR 225 , seventh output terminal CKR 270 , eighth output terminal CKR 315 respectively connected with the first output terminal CK0, second output terminal CK 45 , third output terminal CK 90 , fourth output terminal CK 135 , fifth output terminal CK 180 , sixth output terminal CK 225 , seventh output terminal CK 270 , eighth output terminal CK 315 of the multi-phase clock generation circuit;

[0013] The first output terminal CKDL0, second output terminal CKDL1, third output terminal CKDL2, fourth output terminal CKDL3, fifth output terminal CKDL4, sixth output terminal CKDL5, seventh output terminal CKDL6, eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected with the first input terminal CKDL0, second input terminal CKDL1, third input terminal CKDL2, fourth input terminal CKDL3, fifth input terminal CKDL4, sixth input terminal CKDL5, seventh input terminal CKDL6, eighth input terminal CKDL7 of the frequency discriminator; the first differential output terminal V IP and second differential output terminal V IN of the frequency discriminator are respectively connected with the first differential input terminal V IP and second differential input terminal V IN of the operational amplifier Gm, and the output terminal of the operational amplifier Gm is respectively connected with the bias voltage input terminal V ctrl of the multi-phase delay generation module and the bias voltage input terminal V ctrl of the multi-phase injection-locked ring oscillator.

[0014] Further, the reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of 8 slices with the same structure, and the slice of the reconfigurable FFE tap generation module is one-to-one corresponding signal connection with the slice of the multiplexing-driving circuit.

[0015] Further, any reconfigurable FFE tap generation module slice includes a first reconfigurable serialization unit, a second reconfigurable serialization unit, and a third reconfigurable serialization unit; eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input from an external signal source are connected to the first input end MSB0, the second input end MSB1, the third input end MSB2, the fourth input end MSB3, the fifth input end MSB4, the sixth input end MSB5, the seventh input end MSB6, and the eighth input end MSB7 of the first reconfigurable serialization unit, respectively; meanwhile, the eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input from the external signal source are connected to the first input end MSB0, the second input end MSB1, the third input end MSB2, the fourth input end MSB3, the fifth input end MSB4, the sixth input end MSB5, the seventh input end MSB6, and the eighth input end MSB7 of the second reconfigurable serialization unit, respectively; eight parallel data LSB0, LSB1, LSB2, LSB3, LSB4, LSB5, LSB6, and LSB7 input from the external signal source are connected to the first input end LSB0, the second input end LSB1, the third input end LSB2, the fourth input end LSB3, the fifth input end LSB4, the sixth input end LSB5, the seventh input end LSB6, and the eighth input end LSB7 of the third reconfigurable serialization unit, respectively; the ninth input end CK0, the tenth input end CK 45 , the eleventh input end CK 90 , the twelfth input end CK 135 , the thirteenth input end CK 180 , the fourteenth input end CK 225 , the fifteenth input end CK 270 , the sixteenth input end CK 315 , and the seventeenth input end CK 45 of any reconfigurable serialization unit are connected to the first output end CK0, the second output end CK 90 , the third output end CK 135 , the fourth output end CK 180 , the fifth output end CK 225 , the sixth output end CK 270 , the seventh output end CK 315 , and the eighth output end CK AP of the multi-phase clock generation circuit, respectively; any reconfigurable serialization unit has output ends T BP , T CP , T DP , T AN , T BN , T CN , T DN .

[0016] Further, any reconfigurable serialization unit comprises: first to eighth 4:1 multiplexers, first to eighth single pulse generation modules, first to eighth 2:1 multiplexers; the input ends of the first to eighth 4:1 multiplexers receive eight parallel data input by an external signal source in turn; the output of the first 4:1 multiplexer is connected with the input end of the first single pulse generation module, the output of the second 4:1 multiplexer is connected with the input end of the second single pulse generation module, the output of the third 4:1 multiplexer is connected with the input end of the third single pulse generation module, the output of the fourth 4:1 multiplexer is connected with the input end of the fourth single pulse generation module, the output of the fifth 4:1 multiplexer is connected with the input end of the fifth single pulse generation module, the output of the sixth 4:1 multiplexer is connected with the input end of the sixth single pulse generation module, the output of the seventh 4:1 multiplexer is connected with the input end of the seventh single pulse generation module, and the output of the eighth 4:1 multiplexer is connected with the input end of the eighth single pulse generation module; the output ends DP <0> and DN <0> of the first single pulse generation module are connected with the first input end of the first 2:1 multiplexer and the first input end of the fifth 2:1 multiplexer respectively; the output ends DP <1> and DN <1> of the second single pulse generation module are connected with the first input end of the second 2:1 multiplexer and the first input end of the sixth 2:1 multiplexer respectively; the output ends DP <2> and DN <2> of the third single pulse generation module are connected with the first input end of the third 2:1 multiplexer and the first input end of the seventh 2:1 multiplexer respectively; the output ends DP <3> and DN <3> of the fourth single pulse generation module are connected with the first input end of the fourth 2:1 multiplexer and the first input end of the eighth 2:1 multiplexer respectively; the output ends DP <4> and DN <4> of the fifth single pulse generation module are connected with the second input end of the first 2:1 multiplexer and the second input end of the fifth 2:1 multiplexer respectively; the output ends DP <5> and DN <5> of the sixth single pulse generation module are connected with the second input end of the second 2:1 multiplexer and the second input end of the sixth 2:1 multiplexer respectively; the output ends DP <6> and DN <6> of the seventh single pulse generation module are connected with the second input end of the third 2:1 multiplexer and the second input end of the seventh 2:1 multiplexer respectively; the output ends DP <7> and DN <7>respectively; the first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, the fourth 2:1 multiplexer have output terminals T AP , T BP , T CP , T DP , the fifth 2:1 multiplexer, the sixth 2:1 multiplexer, the seventh 2:1 multiplexer, the eighth 2:1 multiplexer have output terminals T AN , T BN , T CN , T DN .

[0017] Further, any multiplexing-driving circuit slice contains three groups of driving circuits with the same structure, and the three groups of driving circuits correspond to the first reconfigurable serialization unit, the second reconfigurable serialization unit, and the third reconfigurable serialization unit one by one; any driving circuit includes: a first MOS tube P1, a second MOS tube P2, a third MOS tube P3, a fourth MOS tube P4, a fifth MOS tube P5, a sixth MOS tube P6, a seventh MOS tube P7, an eighth MOS tube P8, and a tail current source; the sources of the first MOS tube P1, the second MOS tube P2, the third MOS tube P3, the fourth MOS tube P4, the fifth MOS tube P5, the sixth MOS tube P6, the seventh MOS tube P7, and the eighth MOS tube P8 are connected to the current source; the drains of the first MOS tube P1, the third MOS tube P3, the fifth MOS tube P5, and the seventh MOS tube P7 are connected to the first output terminal OUT P of the FFE equalization circuit, and the drains of the second MOS tube P2, the fourth MOS tube P4, the sixth MOS tube P6, and the eighth MOS tube P8 are connected to the second output terminal OUT N of the FFE equalization circuit; the gates of the first MOS tube P1, the third MOS tube P3, the fifth MOS tube P5, and the seventh MOS tube P7 are connected to the output terminals T AP , T BP , T CP , T DP of the corresponding reconfigurable serialization unit one by one, and the gates of the second MOS tube P2, the fourth MOS tube P4, the sixth MOS tube P6, and the eighth MOS tube P8 are connected to the output terminals T AN , T BN , T CN , T DN of the corresponding reconfigurable serialization unit one by one.

[0018] Further, the current mode FFE equalization circuit further includes a first resistor R1, a second resistor R2, and a load 2R LThe drain of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5 and the seventh MOS transistor P7 is connected with the first end of the first resistor R1; the drain of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6 and the eighth MOS transistor P8 is connected with the first end of the second resistor R2; the first end of the first resistor R1 is connected with the first end of the load 2R L , and the first end of the second resistor R2 is connected with the second end of the load 2R L ; the second end of the first resistor R1 and the second end of the second resistor R2 are grounded.

[0019] Further, the output resistor formed by the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5 and the seventh MOS transistor P7 in parallel with the first resistor R1 is R, and the output resistor formed by the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6 and the eighth MOS transistor P8 in parallel with the second resistor R2 is R', and R is equal to R'.

[0020] The application further provides a reconfigurable FFE equalization circuit based on multi-phase clock serialization.

[0021] The application further provides a chip comprising the reconfigurable FFE equalization circuit based on multi-phase clock serialization.

[0022] Compared with the prior art, the application has the following beneficial effects:

[0023] Compared with the Serdes transmitter equalization circuit with fixed FFE tap number, the application has the advantages of reconfigurable feedforward equalization tap number and large equalization strength adjustment range. Specifically, unlike the Serdes transmitter equalization circuit with fixed tap number, the application can reconfigure the input data of a plurality of drivers, realize single tap with maximum output swing, and realize FFE setting with at least two taps to at most six taps.

[0024] Further, compared with the existing Serdes transmitter equalization circuit, the application significantly reduces the system clock frequency and reduces the difficulty of circuit design. Specifically, with the gradual increase of the wired communication rate, the current most full-rate, half-rate or quarter-rate architecture faces the problem of high required system clock frequency and high design difficulty. The application adopts an eighth-rate architecture and samples serialization through a multi-phase clock, reduces the highest required system clock frequency to one-eighth of the Nyquist frequency, and significantly reduces the circuit design and manufacturing costs.

[0025] Further, compared with the existing Serdes transmitter equalization circuit, the application has the advantage of low power consumption. Specifically, unlike the current most full-rate, half-rate or quarter-rate architecture, the application adopts an eighth-rate architecture, reduces the highest system clock frequency, and thus reduces the system power consumption; at the same time, the application integrates the last stage serialization in the driving circuit, eliminates the high-speed junction inside the system, and further reduces the system power consumption.

[0026] The reconfigurable Serdes transmitter based on multi-phase clock serialization of the application realizes a high signal rate while having high energy efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0028] Figure 1 It is a schematic diagram of a traditional feedforward equalizer structure;

[0029] Figure 2 It is a schematic diagram of the reconfigurable FFE equalization circuit based on multi-phase clock serialization of the application;

[0030] Figure 3 It is a schematic diagram of the multi-phase clock generation circuit in the application;

[0031] Figure 4 It is a schematic diagram of the reconfigurable FFE tap generation module in the application;

[0032] Figure 5 It is a schematic diagram of the reconfigurable serialization unit circuit in the application;

[0033] Figure 6 It is a signal timing diagram of an embodiment of the application;

[0034] Figure 7The connection relationship between the reconfigurable FFE tap generation module and the multiplexing-driving circuit in the application is shown in the schematic diagram.

[0035] Figure 8 The principle diagram of the multiplexing-driving circuit in the application is shown in the schematic diagram. DETAILED DESCRIPTION

[0036] The above embodiments of the present application are described with reference to specific examples. However, a person skilled in the art will readily understand that other advantages and benefits of the present application can be achieved from the description of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0037] It should be noted that the process equipment or device not specifically mentioned in the following examples is the conventional equipment or device in the art.

[0038] It should be noted that the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device. Moreover, unless otherwise specified, the numbering of the method steps is only a convenient tool for identifying the method steps, and is not a limitation on the arrangement order of the method steps or a limitation on the scope of the implementation of the present application, and the change or adjustment of the relative relationship, without substantial change of the technical content, is also considered as the scope of the implementation of the present application.

[0039] In addition, it should be noted that the terms "first", "second", etc. in the present application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application; in addition, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be a fixed connection, or a detachable connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication between two elements inside.

[0040] REFERENCE Figure 2The reconfigurable FFE equalization circuit based on multi-phase clock serialization adopts a current mode structure and comprises a multi-phase clock generation circuit, a reconfigurable FFE tap generation module, a multiplexing-driving module, a first resistor R1, a second resistor R2, and a load 2R L .

[0041] The multi-phase clock generation circuit is configured to receive a differential voltage signal of an external clock source and generate a plurality of voltage signals of different phases to generate accurate multi-phase clocks.

[0042] The reconfigurable FFE tap generation module is configured to receive a plurality of parallel data signals input by an external signal source, serialize and adjust the relative delay of the plurality of parallel data signals based on the clock signals, and generate a reconfigurable multi-tap signal.

[0043] The multiplexing-driving module is configured to serialize and transmit the plurality of parallel multi-tap signals to a channel.

[0044] The multi-phase clock generation circuit has external differential clock signal input ends V INJP 、V INJN The reconfigurable FFE tap generation module has external parallel data input ends MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, MSB7, LSB0, LSB1, LSB2, LSB3, LSB4, LSB5, LSB6, LSB7, the multiplexing-driving module, the first resistor R1, the second resistor R2, and the load 2R L The multiplexing-driving module, the first resistor R1, the second resistor R2, and the load 2R L The two ends of the load 2R P are differential signal output ends OUT N .

[0045] The differential voltage signals V INJ,P and V INJ,N provided by the external clock source are respectively connected to the external differential clock signal input ends V INJP and V INJNThe 16 parallel data provided by the external signal source are connected to the first input end MSB0, the second input end MSB1, the third input end MSB2, the fourth input end MSB3, the fifth input end MSB4, the sixth input end MSB5, the seventh input end MSB6, the eighth input end MSB7, the ninth input end LSB0, the tenth input end LSB1, the eleventh input end LSB2, the twelfth input end LSB3, the thirteenth input end LSB4, the fourteenth input end LSB5, the fifteenth input end LSB6, and the sixteenth input end LSB7 of the reconfigurable FFE tap generation module. 45 The first output end CK0, the second output end CK 90 , the third output end CK 135 , the fourth output end CK 180 , the fifth output end CK 225 , the sixth output end CK 270 , the seventh output end CK 315 , the eighth output end CK 45 of the multi-phase clock generation circuit are connected to the seventeenth input end CK0, the eighteenth input end CK 90 , the nineteenth input end CK 135 , the twentieth input end CK 180 , the twenty-first input end CK 225 , the twenty-second input end CK 270 , the twenty-third input end CK 315 , and the twenty-fourth input end CK

[0046] The reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of a plurality of slices with the same structure, and any reconfigurable FFE tap generation module slice corresponds to a multiplexing-driving circuit slice. Taking any slice as an example, the first output end T1 A(B、C、D)P , the second output end T1 A(B、C、D)N , the third output end T2 A(B、C、D)P , the fourth output end T2 A(B、C、D)N , the fifth output end T3 A(B、C、D)P , the sixth output end T3 A(B、C、D)N of the reconfigurable FFE tap generation module slice are connected to the first input end T1 A(B、C、D)P , the second input end T1 A(B、C、D)N , the third input end T2 A(B、C、D)P , the fourth input end T2 A(B、C、D)N , the fifth input end T3 A(B、C、D)P , and the sixth input end T3 A(B、C、D)NThe first output end of the first drive circuit Drv1, the first output end of the second drive circuit Drv2, and the first output end of the third drive circuit Drv3 are connected with the first end of the first resistor R1; the second output end of the first drive circuit Drv1, the second output end of the second drive circuit Drv2, and the second output end of the third drive circuit Drv3 are connected with the first end of the second resistor R2. The first end of the first resistor R1 is also connected with the first end of the load 2R L , and the first end of the second resistor R2 is also connected with the second end of the load 2R L ; the second end of the first resistor R1 and the second end of the second resistor R2 are grounded. The first output end of the first drive circuit Drv1, the first output end of the second drive circuit Drv2, and the first output end of the third drive circuit Drv3 of all the slices are connected in parallel and then connected in series with the first resistor R1 to form an output resistor R, and the second output end of the first drive circuit Drv1, the second output end of the second drive circuit Drv2, and the second output end of the third drive circuit Drv3 of all the slices are connected in parallel and then connected in series with the second resistor R2 to form an output resistor R', and R is equal to R'.

[0047] The specific resistance values of the first resistor R1 and the second resistor R2 are selected according to actual conditions to realize impedance matching. In one specific embodiment of the present application, the output resistor R formed by connecting the first output end of the first drive circuit Drv1, the first output end of the second drive circuit Drv2, and the first output end of the third drive circuit Drv3 of all the slices in series with the first resistor R1, and the output resistor R' formed by connecting the second output end of the first drive circuit Drv1, the second output end of the second drive circuit Drv2, and the second output end of the third drive circuit Drv3 of all the slices in series with the second resistor R2 are both 50 ohms, and the load 2R L is 100 ohms.

[0048] Reference Figure 3 , the multi-phase clock generation circuit comprises a multi-phase delay generation module, a multi-phase injection-locked ring oscillator, a frequency discriminator, and an operational amplifier Gm.

[0049] The differential voltage signals V INJ,P and V INJ,N provided by an external clock source are respectively connected with the differential clock input ends V INJP and V INJNThe first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6, and the eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6, and the eighth input terminal CKDL7 of the multi-phase injection locked ring oscillator; the first output terminal CKR0, the second output terminal CKR 45 , the third output terminal CKR 90 , the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 After passing through the first buffer B0, the second buffer B1, the third buffer B2, the fourth buffer B3, the fifth buffer B4, the sixth buffer B5, the seventh buffer B6 and the eighth buffer B7, the first output terminal CK0, the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 are connected.

[0050] Furthermore, the first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6, and the eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6, and the eighth input terminal CKDL7 of the phase frequency detector. The first differential output terminal V IP and the second differential output terminal V IN and the first differential input terminal V IP and the second differential input terminal V IN The output terminals of the operational amplifier Gm are connected to the bias voltage input terminals Vctrl and the bias voltage input end V of the multi-phase injection locking ring oscillator ctrl are connected.

[0051] In the locked state, the output signal frequency of the multi-phase injection locking ring oscillator is the same as the output clock frequency of the external clock source, and the oscillation frequency information of the multi-phase injection locking ring oscillator itself is lost. In the multi-phase delay generation module, there is a large phase error between adjacent voltage signals. The frequency discriminator and phase detector respectively phase detects the signals CKDL0 and CKDL1, CKDL2 and CKDL3, CKDL4 and CKDL5, and CKDL6 and CKDL7. If there is a phase error in the eight-way output signal, the output voltages of the first differential output end V IP and the second differential output end V IN of the frequency discriminator and phase detector are different. At this time, the operational amplifier charges and discharges the first capacitor C1 according to the difference between the input ends V IP and V IN , changes the size of the output end V ctrl of the operational amplifier, and feeds back the change of V ctrl to the multi-phase delay generation module and the multi-phase injection locking ring oscillator, adjusts the current size injected into the multi-phase delay generation module and the multi-phase injection locking ring oscillator, thereby changing the output signal frequency of the multi-phase delay generation module and the multi-phase injection locking ring oscillator, so that the intrinsic output signal frequency of the multi-phase delay generation module and the multi-phase injection locking ring oscillator is the same as the injection signal frequency of the external signal source. When the feedback system makes the phase differences between CKDL0, CKDL1, CKDL2, CKDL3, CKDL4, CKDL5, CKDL6, and CKDL7 the same, the output voltage V ctrl of the operational amplifier remains unchanged, and at this time, the multi-phase delay generation module and the multi-phase injection locking ring oscillator generate output signals with high phase accuracy. Further, due to the closed loop of the multi-phase injection locking ring oscillator, the output signals CKR0, CKR1, CKR2, CKRL3, CKR4, CKR5, CKR6, and CKR7 have high phase accuracy; at the same time, since the multi-phase delay generation module does not form a closed loop, there is no accumulation of phase noise in the module, and the output signals CKDL0, CKDL1, CKDL2, CKDL3, CKDL4, CKDL5, CKDL6, and CKDL7 of the multi-phase delay generation module are injected into the multi-phase injection locking ring oscillator, which further dithers the multi-phase injection locking ring oscillator and reduces the phase noise of the output signal of the multi-phase injection locking ring oscillator. The first output end CKR0, the second output end CKR 45 , and the third output end CKR 90, fourth output terminal CKR 135 , fifth output terminal CKR 180 , sixth output terminal CKR 225 , seventh output terminal CKR 270 , eighth output terminal CKR 315 After passing through the AC-coupled first buffer B0, second buffer B1, third buffer B2, fourth buffer B3, fifth buffer B4, sixth buffer B5, seventh buffer B6 and eighth buffer B7, the signal duty cycle of 50% is restored, and the first output terminal CK0, second output terminal CK 45 , third output terminal CK 90 , fourth output terminal CK 135 , fifth output terminal CK 180 , sixth output terminal CK 225 , seventh output terminal CK 270 , eighth output terminal CK 315 of the multi-phase clock generation circuit are connected respectively.

[0052] Further, referring to Figure 4 , the reconfigurable FFE tap generation module is composed of 8 slices of the same structure. For any slice, the 16-way parallel data input by the external signal source is connected with the first input terminal MSB0, second input terminal MSB1, third input terminal MSB2, fourth input terminal MSB3, fifth input terminal MSB4, sixth input terminal MSB5, seventh input terminal MSB6, eighth input terminal MSB7, ninth input terminal LSB0, tenth input terminal LSB1, eleventh input terminal LSB2, twelfth input terminal LSB3, thirteenth input terminal LSB4, fourteenth input terminal LSB5, fifteenth input terminal LSB6, sixteenth input terminal LSB7 of the slice. The output terminals CK0, CK 45 , CK 90 , CK 135 , CK 180 , CK 225 , CK 270 , CK 315 of the multi-phase clock generation circuit are connected respectively with the seventeenth input terminal CK0, eighteenth input terminal CK 45 , nineteenth input terminal CK 90 , twentieth input terminal CK 135 , twenty-first input terminal CK 180 , twenty-second input terminal CK 225 , twenty-third input terminal CK 270 , twenty-fourth input terminal CK 315 of the reconfigurable FFE tap generation module slice.

[0053] Further, each slice of the reconfigurable FFE tap generation module is composed of three reconfigurable serialization units. The parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, MSB7 are connected to the first input end MSB0, the second input end MSB1, the third input end MSB2, the fourth input end MSB3, the fifth input end MSB4, the sixth input end MSB5, the seventh input end MSB6, and the eighth input end MSB7 of the first reconfigurable serialization unit respectively; meanwhile, the parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, MSB7 are connected to the first input end MSB0, the second input end MSB1, the third input end MSB2, the fourth input end MSB3, the fifth input end MSB4, the sixth input end MSB5, the seventh input end MSB6, and the eighth input end MSB7 of the second reconfigurable serialization unit respectively. The parallel data LSB0, LSB1, LSB2, LSB3, LSB4, LSB5, LSB6, LSB7 are connected to the first input end LSB0, the second input end LSB1, the third input end LSB2, the fourth input end LSB3, the fifth input end LSB4, the sixth input end LSB5, the seventh input end LSB6, and the eighth input end LSB7 of the third reconfigurable serialization unit respectively. The ninth input end CK0, the tenth input end CK 45 , the eleventh input end CK 90 , the twelfth input end CK 135 , the thirteenth input end CK 180 , the fourteenth input end CK 225 , the fifteenth input end CK 270 , the sixteenth input end CK 315 of each reconfigurable serialization unit are connected to the first output end CK0, the second output end CK 45 , the third output end CK 90 , the fourth output end CK 135 , the fifth output end CK 180 , the sixth output end CK 225 , the seventh output end CK 270 , the eighth output end CK 315 of the multi-phase clock generation circuit respectively; each reconfigurable serialization unit has the output end T AP , T BP , T CP , T DP , T AN , T BN , T CN , T DN .

[0054] Reference Figure 5, the eighth input end D <0> , the ninth input end CK0, the tenth input end CK <1> , the eleventh input end CK <2> , the twelfth input end CK <3> , the thirteenth input end CK <4> , the fourteenth input end CK <5> , the fifteenth input end CK <6> , the sixteenth input end CK <7> , the seventeenth input end CK 45 , the eighteenth input end CK 90 , the nineteenth input end CK 135 , the twentieth input end CK 180 , the twenty-first input end CK 225 , the twenty-second input end CK 270 , the twenty-third input end CK 315 . Any 4:1 multiplexer has four input ends, wherein: the input ends of the first to fourth 4:1 multiplexers are connected with the first input end D <0> , the second input end D <1> , the third input end D <2> , the fourth input end D <3> respectively; the input ends of the fifth to eighth 4:1 multiplexers are connected with the fifth input end D <4> , the sixth input end D <5> , the seventh input end D <6> , the eighth input end D <7> respectively. Any single pulse generation module has eight input ends, wherein the input ends of any single pulse generation module are connected with the ninth input end CK0, the tenth input end CK 45 , the eleventh input end CK 90 , the twelfth input end CK 135 , the thirteenth input end CK 180 , the fourteenth input end CK 225 , the fifteenth input end CK 270 , the sixteenth input end CK 315 respectively. External input control signals S0, S1. Parallel data MSB0 (LSB0), MSB1 (LSB1), MSB2 (LSB2), MSB3 (LSB3), MSB4 (LSB4), MSB5 (LSB5), MSB6 (LSB6), MSB7 (LSB7) are sequentially connected with the first input end D <0> , the second input end D <1> , the third input end D<2> , fourth input terminal D <3> , fifth input terminal D <4> , sixth input terminal D <5> , seventh input terminal D <6> , eighth input terminal D <7> are connected. Control signals S0, S1 are used to select different signals for operation. The output of the first 4:1 multiplexer is connected with the input terminal of the first single pulse generation module, the output of the second 4:1 multiplexer is connected with the input terminal of the second single pulse generation module, the output of the third 4:1 multiplexer is connected with the input terminal of the third single pulse generation module, the output of the fourth 4:1 multiplexer is connected with the input terminal of the fourth single pulse generation module, the output of the fifth 4:1 multiplexer is connected with the input terminal of the fifth single pulse generation module, the output of the sixth 4:1 multiplexer is connected with the input terminal of the sixth single pulse generation module, the output of the seventh 4:1 multiplexer is connected with the input terminal of the seventh single pulse generation module, and the output of the eighth 4:1 multiplexer is connected with the input terminal of the eighth single pulse generation module. The output terminals DP <0> and DN <0> of the first single pulse generation module are connected with the first input terminal of the first 2:1 multiplexer and the first input terminal of the fifth 2:1 multiplexer respectively; the output terminals DP <1> and DN <1> of the second single pulse generation module are connected with the first input terminal of the second 2:1 multiplexer and the first input terminal of the sixth 2:1 multiplexer respectively; the output terminals DP <2> and DN <2> of the third single pulse generation module are connected with the first input terminal of the third 2:1 multiplexer and the first input terminal of the seventh 2:1 multiplexer respectively; the output terminals DP <3> and DN <3> of the fourth single pulse generation module are connected with the first input terminal of the fourth 2:1 multiplexer and the first input terminal of the eighth 2:1 multiplexer respectively; the output terminals DP <4> and DN <4> of the fifth single pulse generation module are connected with the second input terminal of the first 2:1 multiplexer and the second input terminal of the fifth 2:1 multiplexer respectively; the output terminals DP <5> and DN <5> of the sixth single pulse generation module are connected with the second input terminal of the second 2:1 multiplexer and the second input terminal of the sixth 2:1 multiplexer respectively; the output terminals DP <6> and DN <6> of the seventh single pulse generation module are connected with the second input terminal of the third 2:1 multiplexer and the second input terminal of the seventh 2:1 multiplexer respectively; the output terminals DP <7>and DN <7> respectively connected with the second input end of the fourth 2:1 multiplexer and the second input end of the eighth 2:1 multiplexer.

[0055] Reference Figure 6 In one embodiment of the present application, the control signals S0 and S1 are low. The reconfigurable serialization unit selects the first (fifth) input end D <0> The first (fifth) single pulse generation module outputs signals DP0 and DN0 (DP4 and DN4) whose rising edges are aligned with the rising edge of the input signal CK0 and whose falling edges are aligned with the falling edge of the input signal CK 180 Under the control of the above signals, the output result of the single pulse generation module is single pulse signals with a width of one unit pulse width and an interval of seven unit pulse widths. Similarly to the present embodiment, the rising and falling edges of the output signals DP1 and DN1 (DP5 and DN5), DP2 and DN2 (DP6 and DN6), and DP3 and DN3 (DP7 and DN7) of the second (sixth), third (seventh), and fourth (eighth) single pulse generation modules are respectively aligned with CK 45 and CK 225 , CK 90 and CK 270 , and CK 135 and CK 315 The output ends DP <0:7> and DN <0:7> of the single pulse generation module are respectively connected with the input ends DP <0:7> and DN <0:7> of the 8:4 multiplexer. In the present embodiment, DP0 (DN0) and DP4 (DN4) are input through the input ends of the 8:4 multiplexer, and the output ends of the 8:4 multiplexer are signals T AP (T AN ). Under the control of the above signals, the output result T AP of the 8:4 multiplexer is single pulse signals with a width of one unit pulse width and an interval of three unit pulse widths. Similarly to the present embodiment, DP1 (DN1) and DP5 (DN5), DP2 (DN2) and DP6 (DN6), and DP3 (DN3) and DP7 (DN7) are input through the input ends of the 8:4 multiplexer, and the output ends of the 8:4 multiplexer are signals T BP (T BN ), T CP (T CN ), and T DP (T DN ). That is, the first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, and the fourth 2:1 multiplexer respectively have output ends T AP , T BP, T CP , T DP , fifth 2:1 multiplexer, sixth 2:1 multiplexer, seventh 2:1 multiplexer, eighth 2:1 multiplexer have output terminals T AN , T BN , T CN , T DN It should be noted that the relative phase relationship between the signals described in the embodiment is only exemplary, and the actual use case must be based on the ability of a person skilled in the art to implement it.

[0056] 8 pieces of reconfigurable FFE tap generation module slices are connected with multiplexing-driver circuit slices, and the reference Figure 7 . Taking any slice as an example, the first output terminal T1 A(B、C、D)P , the second output terminal T1 A(B、C、D)N , the third output terminal T2 A(B、C、D)P , the fourth output terminal T2 A(B、C、D)N , the fifth output terminal T3 A(B、C、D)P , the sixth output terminal T3 A(B、C、D)N of the reconfigurable FFE tap generation module are connected with the first input terminal T1 A(B、C、D)P , the second input terminal T1 A(B、C、D)N , the third input terminal T2 A(B、C、D)P , the fourth input terminal T2 A(B、C、D)N , the fifth input terminal T3 A(B、C、D)P , the sixth input terminal T3 A(B、C、D)N of the multiplexing-driver module. The multiplexing-driver module serializes the input signal and transmits it to the channel.

[0057] Reference Figure 8 , the multiplexing-driver circuit (MUX-Driver) is composed of 8 slices with the same structure, and any slice contains three groups of driving circuits with the same structure to generate PAM-4 multi-level modulation signals. Taking any driving circuit as an example, the circuit is composed of a first MOS tube P1, a second MOS tube P2, a third MOS tube P3, a fourth MOS tube P4, a fifth MOS tube P5, a sixth MOS tube P6, a seventh MOS tube P7, an eighth MOS tube P8, and a tail current source to form a de-emphasis FFE unit. The source of the first MOS tube P1, the second MOS tube P2, the third MOS tube P3, the fourth MOS tube P4, the fifth MOS tube P5, the sixth MOS tube P6, the seventh MOS tube P7, and the eighth MOS tube P8 is connected to the current source, and the amplitude modulation of different slice taps is realized by adjusting the size of the tail current source. The drain of the first MOS tube P1, the third MOS tube P3, the fifth MOS tube P5, and the seventh MOS tube P7 is connected to the first output terminal OUT PThe drain of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 is connected to the first output end OUT N . The gate of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 is the input end of T AP , T BP , T CP , and T DP respectively. The gate of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 is the input end of T AN , T BN , T CN , and T DN respectively. The first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 are turned on or off according to the signals of the input ends T AP , T BP , T CP , and T DP in turn, and T AP , T BP , T CP , and T DP four-way data are serialized into one way. Similarly, the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 are turned on or off according to the signals of the input ends T AN , T BN , T CN , and T DN in turn, and T AN , T BN , T CN , and T DN four-way data are serialized into one way. This structure combines high-speed serialization and driving circuit, reduces the number of high-speed nodes inside the circuit, increases the internal bandwidth of the circuit while reducing the overall power consumption of the circuit. Take any chip as an example, the first output end of the first driving unit Drv1, the first output end of the second driving unit Drv2, and the first output end of the third driving unit Drv3 are connected to the first end of the first resistor R1. The second output end of the first driving unit Drv1, the second output end of the second driving unit Drv2, and the second output end of the third driving unit Drv3 are connected to the first end of the second resistor R2. The first end of the first resistor R1 is also connected to the first end of the load 2R L . The first end of the second resistor R2 is also connected to the second end of the load 2R L . The second end of the first resistor R1 and the second end of the second resistor R2 are both grounded.

[0058] Although the specific embodiments of the present application have been described above, it is understood by those skilled in the art that these are merely illustrative and various changes or modifications can be made to the present embodiments without departing from the principles and the spirit of the present application, and the scope of protection of the present application is defined only by the appended claims.

Claims

1. A reconfigurable FFE equalization circuit based on multi-phase clock serialization, characterized in that: include: A multi-phase clock generation circuit is used to receive a differential voltage signal from an external clock source and generate multiple voltage signals with different phases. The generated multiple voltage signals with different phases are input as clock signals to the reconfigurable FFE tap generation circuit; A reconfigurable FFE tap generation module is configured to receive multiple parallel data signals input from an external signal source, and serialize the multiple parallel data signals based on the clock signal to generate a reconfigurable multi-tap signal; The generated multi-tap signal serves as an input to a multiplexing-driving circuit; Multiplexing-driving circuit, used to serialize multiple parallel multi-tap signals and transmit them to the channel; The reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of 8 slices of the same structure, and the slices of the reconfigurable FFE tap generation module are signal-connected to the slices of the multiplexing-driving circuit in a one-to-one correspondence; Any slice of the reconfigurable FFE tap generation module includes a first reconfigurable serialization unit, a second reconfigurable serialization unit, and a third reconfigurable serialization unit; the eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input by the external signal source are respectively connected to the first input terminal MSB0, the second input terminal MSB1, the third input terminal MSB2, the fourth input terminal MSB3, the fifth input terminal MSB4, the sixth input terminal MSB5, the seventh input terminal MSB6, and the eighth input terminal MSB7 of the first reconfigurable serialization unit; at the same time, the eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input by the external signal source are respectively connected to the second reconfigurable serialization unit. The first input terminal MSB0, the second input terminal MSB1, the third input terminal MSB2, the fourth input terminal MSB3, the fifth input terminal MSB4, the sixth input terminal MSB5, the seventh input terminal MSB6, and the eighth input terminal MSB7 of the reconfigurable serialization unit are connected; the eight parallel data LSB0, LSB1, LSB2, LSB3, LSB4, LSB5, LSB6, and LSB7 input by the external signal source are respectively connected to the first input terminal LSB0, the second input terminal LSB1, the third input terminal LSB2, the fourth input terminal LSB3, the fifth input terminal LSB4, the sixth input terminal LSB5, the seventh input terminal LSB6, and the eighth input terminal LSB7 of the third reconfigurable serialization unit; the ninth input terminal CK0 and the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , sixteenth input terminal CK 315 The first output terminal CK0 and the second output terminal CK of the multi-phase clock generating circuit are connected to the 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 One-to-one connection; any reconfigurable serialization unit has an output terminal T AP 、T BP 、T CP 、T DP 、T AN 、T BN 、T CN 、T DN ; Any reconfigurable serialization unit includes: first to eighth 4:1 multiplexers, first to eighth single pulse generation modules, and first to eighth 2:1 multiplexers; The input ends of the first to eighth 4:1 multiplexers sequentially receive eight channels of parallel data input from an external signal source; the output of the first 4:1 multiplexer is connected to the input end of the first single pulse generation module, the output of the second 4:1 multiplexer is connected to the input end of the second single pulse generation module, the output of the third 4:1 multiplexer is connected to the input end of the third single pulse generation module, the output of the fourth 4:1 multiplexer is connected to the input end of the fourth single pulse generation module, the output of the fifth 4:1 multiplexer is connected to the input end of the fifth single pulse generation module, the output of the sixth 4:1 multiplexer is connected to the input end of the sixth single pulse generation module, the output of the seventh 4:1 multiplexer is connected to the input end of the seventh single pulse generation module, and the output of the eighth 4:1 multiplexer is connected to the input end of the eighth single pulse generation module; the output end DP of the first single pulse generation module <0> and DN <0> are respectively connected to the first input terminal of the first 2:1 multiplexer and the first input terminal of the fifth 2:1 multiplexer; the output terminal DP of the second single pulse generating module <1> and DN <1> are respectively connected to the first input terminal of the second 2:1 multiplexer and the first input terminal of the sixth 2:1 multiplexer; the output terminal DP of the third single pulse generating module <2> and DN <2> are respectively connected to the first input terminal of the third 2:1 multiplexer and the first input terminal of the seventh 2:1 multiplexer; the output terminal DP of the fourth single pulse generating module <3> and DN <3> are respectively connected to the first input terminal of the fourth 2:1 multiplexer and the first input terminal of the eighth 2:1 multiplexer; the output terminal DP of the fifth single pulse generating module <4> and DN <4> are respectively connected to the second input terminal of the first 2:1 multiplexer and the second input terminal of the fifth 2:1 multiplexer; the output terminal DP of the sixth single pulse generating module <5> and DN <5> are respectively connected to the second input terminal of the second 2:1 multiplexer and the second input terminal of the sixth 2:1 multiplexer; the output terminal DP of the seventh single pulse generating module <6> and DN <6> are respectively connected to the second input terminal of the third 2:1 multiplexer and the second input terminal of the seventh 2:1 multiplexer; the output terminal DP of the eighth single pulse generating module <7> and DN <7> are respectively connected to the second input terminal of the fourth 2:1 multiplexer and the second input terminal of the eighth 2:1 multiplexer; the first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, and the fourth 2:1 multiplexer each have an output terminal T AP 、T BP 、T CP 、T DP The fifth 2:1 multiplexer, the sixth 2:1 multiplexer, the seventh 2:1 multiplexer, and the eighth 2:1 multiplexer each have an output terminal T AN 、T BN 、T CN 、T DN .

2. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 1, characterized in that: The multi-phase clock generation circuit includes: a multi-phase delay generation module, a multi-phase injection-locked ring oscillator, a frequency and phase detector, and an operational amplifier Gm; The external clock source provides a differential voltage signal V INJ,P and V INJ,N The differential clock input terminals V INJP and V INJN The first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6, and the eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6, and the eighth input terminal CKDL7 of the multi-phase injection locked ring oscillator; the first output terminal CKR0, the second output terminal CKR 45 , the third output terminal CKR 90 , the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 The first output terminal CK0 and the second output terminal CK of the multi-phase clock generating circuit are connected to the 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 connected; The first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6 and the eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6 and the eighth input terminal CKDL7 of the phase frequency detector; the first differential output terminal V IP and the second differential output terminal V IN and the first differential input terminal V IP and the second differential input terminal V IN The output terminals of the operational amplifier Gm are connected to the bias voltage input terminals V ctrl and the bias voltage input terminal V of the multi-phase injection-locked ring oscillator ctrl connect.

3. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 1, characterized in that: Any slice of the multiplexing-driving circuit includes three groups of driving circuits with the same structure, and the three groups of driving circuits correspond one-to-one to the first reconfigurable serialization unit, the second reconfigurable serialization unit, and the third reconfigurable serialization unit; any driving circuit includes: a first MOS transistor P1, a second MOS transistor P2, a third MOS transistor P3, a fourth MOS transistor P4, a fifth MOS transistor P5, a sixth MOS transistor P6, a seventh MOS transistor P7, an eighth MOS transistor P8, and a tail current source; the sources of the first MOS transistor P1, the second MOS transistor P2, the third MOS transistor P3, the fourth MOS transistor P4, the fifth MOS transistor P5, the sixth MOS transistor P6, the seventh MOS transistor P7, and the eighth MOS transistor P8 are connected to the current source; the drains of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 are connected to the first output terminal OUT of the FFE equalization circuit. P The drains of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 are connected to the second output terminal OUT of the FFE equalization circuit. N The gates of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 are connected to the output terminals T of the corresponding reconfigurable serialization units. AP 、T BP 、T CP 、T DP The gates of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6 and the eighth MOS transistor P8 are connected one by one to the output terminal T of the corresponding reconfigurable serialization unit. AN 、T BN 、T CN 、T DN One-to-one connection.

4. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 3, characterized in that: The FFE equalization circuit further includes a first resistor R1, a second resistor R2, a load 2R L The drains of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 are all connected to the first end of the first resistor R1; the drains of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 are all connected to the first end of the second resistor R2; the first end of the first resistor R1 is also connected to the load 2R L The first end of the second resistor R2 is connected to the load 2R L the second end of the first resistor R1 and the second end of the second resistor R2 are both grounded.

5. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 4, characterized in that: The output resistance formed by the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, the seventh MOS transistor P7 and the first resistor R1 in parallel is recorded as R, and the output resistance formed by the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, the eighth MOS transistor P8 and the second resistor R2 in parallel is recorded as R′, and R is equal to R′.

6. A reconfigurable SerDes transmitter based on multi-phase clock serialization, characterized in that: The invention comprises a reconfigurable FFE equalization circuit based on multi-phase clock serialization as described in any one of claims 1-5.

7. A chip, characterized in that: The invention comprises a reconfigurable FFE equalization circuit based on multi-phase clock serialization as described in any one of claims 1-5.

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