Delay-locked loop circuit and system apparatus

Abstract

The application provides a kind of delay-locked loop circuit and system device, which optimizes the situation that the DLL locking time is lengthened by the minus 1C operation in the prior art, increases one step at the beginning of the first minus 1C operation (and can further be increased after the last minus 1C operation), so that there are two update opportunities in the original first minus 1C operation, avoids the situation that the actual minus 1C operation is "first plus 1C, then minus 2C", reduces the possibility of error in the phase detection result of the phase detector, thereby avoids the situation that the minus 1C operation which should be executed once is executed multiple times due to the error in the phase detection result of the phase detector, so that the DLL circuit can be normally locked, and the normal operation of the system device is ensured. In addition, the technical scheme of the application can further increase one step after completing the last minus 1C operation, so that there are two update opportunities in the original first fine adjustment operation (such as +4F operation), further reducing the possibility of error in the phase detection result of the phase detector.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop (PLL) technology, and in particular to a time-delay PLL circuit and system device. Background Technology

[0002] When an external clock signal applied from an external device is used in a corresponding system device, a delay or clock deviation caused by the internal circuitry of the system device may occur. Currently, this delay or clock deviation is usually compensated by a delay-locked loop (DLL) circuit, which locks the output frequency and phase of the system device to a fixed frequency and phase output clock signal. The output clock signal and the external clock signal are phase synchronized (either edge-aligned or differing by a fixed value). At this time, the DLL circuit is locked to ensure the normal operation of the system device.

[0003] Currently, during the actual DLL circuit locking process, the DLL circuit locking time may become longer, which may cause the system device to malfunction. Summary of the Invention

[0004] The purpose of this invention is to provide a time-delay phase-locked loop (DLL) circuit and system device that can optimize the situation where the DLL locking time is extended, thereby ensuring the normal operation of the system device.

[0005] To achieve the above objectives, the present invention provides a time-delay phase-locked loop circuit, comprising a controllable delay chain and a control circuit. The controllable delay chain includes a coarse-adjustment delay chain and a fine-adjustment delay chain. The coarse-adjustment delay chain outputs a first clock and a second clock with a phase difference of 1C to the fine-adjustment delay chain, where 1C is a unit coarse-adjustment step size. The control circuit outputs a coarse-adjustment code to control the delay of the coarse-adjustment delay chain and outputs a fine-adjustment code to control the delay of the fine-adjustment delay chain, and performs a 1C decrement operation on the output of the fine-adjustment delay chain. Specifically, during the first step of the 1C decrement operation on the output of the fine-adjustment delay chain, the control circuit is further configured to:

[0006] In the initial state, a second coarse tuning code is output to the coarse tuning delay chain, and a second fine tuning code is output to the fine tuning delay chain, so that the fine tuning delay chain selects the second clock output;

[0007] When the first update timing is reached, the output of the second fine-tuning code remains unchanged, so that the fine-tuning delay chain still selects the second clock output. At the same time, a first coarse-tuning code different from the second coarse-tuning code is output to the coarse-tuning delay chain to perform a 2C reduction operation on the first clock.

[0008] When the second update timing is reached, a first fine-tuning code, different from the second fine-tuning code, is output to the fine-tuning delay chain, causing the fine-tuning delay chain to select the first clock output to realize the first step of the output of the fine-tuning delay chain by decrementing by 1C.

[0009] Optionally, the first fine-tuning code is the minimum value among all fine-tuning codes that the control circuit can output, and the second fine-tuning code is the maximum value among all fine-tuning codes that the control circuit can output.

[0010] Optionally, the control circuit is further configured to: when the second update timing is reached, while outputting the first fine-tuning code, also output a zero coarse-tuning code different from the first coarse-tuning code to the coarse-tuning delay chain, so as to perform a 2C decrement operation on the second clock.

[0011] Optionally, the first coarse adjustment code is the second coarse adjustment code minus 1, and / or the zeroth coarse adjustment code is the first coarse adjustment code minus 1.

[0012] Optionally, the control circuit is further configured to start fine-tuning the output of the fine-tuning delay chain after completing the final step of the decrementing C operation on the output of the fine-tuning delay chain.

[0013] Optionally, during the first fine-tuning operation on the output of the fine-tuning delay chain, the control circuit is further configured to:

[0014] In the initial state, the zeroth coarse tuning code is output to the coarse tuning delay chain, and the first fine tuning code is output to the fine tuning delay chain, so that the fine tuning delay chain selects the first clock output;

[0015] When the first update timing is reached, the first fine-tuning code is kept unchanged, so that the fine-tuning delay chain still selects the first clock output, and the first coarse-tuning code is output to the coarse-tuning delay chain to perform a 2C increment operation on the second clock.

[0016] When the second update timing is reached, the first coarse tuning code is kept unchanged, and a third fine tuning code, which is different from the first fine tuning code, is output to the fine tuning delay chain, so that the fine tuning delay chain adjusts the phase of its output according to the third fine tuning code, thereby realizing the first step of fine tuning operation on the output of the fine tuning delay chain.

[0017] Optionally, after completing the first fine-tuning operation, the output of the fine-tuning delay chain is updated to the clock signal with the earlier phase between the first clock and the second clock.

[0018] Optionally, the control circuit includes:

[0019] A state broadening circuit is used to generate a fine-tuning gating signal and a broadening control signal based on an original control signal and an update timing signal. The first edge of the broadening control signal is aligned with the first edge of the original control signal, and the second edge of the broadening control signal is delayed relative to the second edge of the original control signal.

[0020] A fine-tuning code control circuit is used to generate a fine-tuning code control signal based on a fine-tuning control clock and the fine-tuning gate signal, wherein the fine-tuning code control signal is used to freeze the fine-tuning code.

[0021] Optionally, the state stretching circuit includes:

[0022] The first trigger has its clock terminal coupled to the update timing signal, its input terminal coupled to the original control signal, and its output terminal outputting a delayed control signal that is delayed relative to the original control signal.

[0023] An XOR NOT logic circuit, wherein its first input is coupled to the original control signal, its second input is coupled to the delay control signal, and its output outputs the fine-tuning gate signal; and...

[0024] The first AND logic circuit has a first input terminal coupled to the original control signal, a second input terminal coupled to the delay control signal, and an output terminal outputting the widening control signal.

[0025] And / or, the fine-tuning code control circuit includes a second AND logic circuit, whose first input is coupled to the fine-tuning gate signal, whose second input is coupled to the fine-tuning control clock, and whose output outputs the fine-tuning code control signal.

[0026] Optionally, the time-delay phase-locked loop circuit further includes:

[0027] A clock buffer circuit, whose input is coupled to the output of the fine-tuning delay chain, is used to convert the output of the fine-tuning delay chain into an internal clock required for the operation of the internal circuitry of the system device.

[0028] A clock buffer circuit is used to replicate clock signals. Its input is coupled to the output of the fine-tuning delay chain. The output of the fine-tuning delay chain is delayed and then output as a feedback clock signal.

[0029] The phase detector has one input terminal coupled to the input terminal of the controllable delay chain and the other input terminal coupled to the output terminal of the replicated clock buffer circuit. It is used to identify the phase difference between the external clock signal received by the controllable delay chain and the feedback clock signal, and outputs the phase detection result to the control circuit.

[0030] Based on the same inventive concept, the present invention also provides a system device comprising a time-delay phase-locked loop circuit as described in the present invention.

[0031] Optionally, the system device is a memory chip, the clock signal output by the delay phase-locked loop circuit is the data selection pulse signal of the memory chip, and the delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal input to the memory chip and the data selection pulse signal until the external clock signal and the data selection pulse signal are phase synchronized and locked.

[0032] Compared with the prior art, the time-delay phase-locked loop circuit and system device with the time-delay phase-locked loop circuit provided by the present invention optimize the situation where the DLL locking time is prolonged due to the subtraction of 1C operation in the prior art. It adds a step at the beginning of the first subtraction of 1C operation, so that there are two update opportunities in the original first subtraction of 1C operation, avoiding the situation of "adding 1C first and then subtracting 2C" in the actual subtraction of 1C operation, reducing the possibility of the phase detector's phase detection result being incorrect. This avoids the situation where the subtraction of 1C operation, which should be performed once, is performed multiple times due to the phase detector's phase detection result being incorrect, so that the DLL circuit can be locked normally and the normal operation of the system device can be guaranteed.

[0033] Furthermore, the technical solution of the present invention can add a step after completing the final step of subtracting 1C, so that there are two update opportunities in the original first step of fine adjustment operation (e.g., +4F operation), which further reduces the possibility of errors in the phase detector's phase detection result and is more conducive to realizing the fast locking of the DLL circuit. Attached Figure Description

[0034] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0035] Figure 1 This is a schematic diagram of an existing time-delay phase-locked loop circuit.

[0036] Figure 2 yes Figure 1 The diagram shows the control code and clock changes when the output of the delay chain is finely adjusted in the time-locked loop circuit to perform a +1C operation.

[0037] Figure 3 yes Figure 1 The diagram shows the control code and clock changes when fine-tuning the output of the delay chain in the time-locked loop circuit to perform a -1C operation.

[0038] Figure 4 yes Figure 1 The time-delay phase-locked loop circuit shown has DQS fb A schematic diagram showing the changes of VCLK during a -1C operation.

[0039] Figure 5This is a schematic diagram of a time-delay phase-locked loop circuit according to an embodiment of the present invention.

[0040] Figure 6 yes Figure 5 The diagram shows the control code and clock changes when fine-tuning the output of the delay chain in the time-locked loop circuit to perform a -1C operation.

[0041] Figure 7 yes Figure 5 The diagram shows the control code and clock changes when fine-tuning the output of the delay chain in the time-locked loop circuit to perform a -1C operation.

[0042] Figure 8 This is a schematic diagram illustrating a circuit example of the control circuit in a time-delay phase-locked loop circuit according to an embodiment of the present invention.

[0043] Figure 9 This is a timing diagram of some signals in a time-delay phase-locked loop circuit according to an embodiment of the present invention. Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0045] As described in the background section, DLL circuit technology has a wide range of applications, such as in DRAM (Dynamic Random Access Memory) chips. The DLL circuit is used to align the external clock signal VCLK, input from external buses to the DRAM chip, with the output clock signal DQS generated by the DRAM chip. When VCLK and DQS are phase-aligned, the DLL circuit locks. For DRAM chips, the fast locking of the DLL circuit ensures correct read and write operations.

[0046] Please refer to Figure 1 , Figure 1 This is a typical framework diagram of a DLL circuit, which includes a controllable delay line 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, and a phase detector (PD) 14. The replica clock buffer circuit 13 is a replica of the clock buffer circuit 11. The controllable delay line 10 receives an external clock signal VCLK, delays it, and outputs a delayed clock signal CLKout. The replica clock buffer circuit 13 provides a delay function to output the delayed clock signal CLKout as a feedback clock signal DQS. fb Phase detector 14 pairs VCLK and DQS fb The phase information is compared and controlled by the phase detector 14. The control circuit 12 generates a corresponding control code (i.e., coarse code and fine code) based on the phase detection result of the phase detector 14 to control the length of the controllable delay chain (DelayLine) 10 to increase or decrease, thereby increasing or decreasing the delay of CLKout relative to VCLK, and thus adjusting the phase difference between VCLK and DQS until the phase between VCLK and DQS is synchronized (or the phase difference between the two is 0). The DLL circuit completes the locking, and at this time VCLK and DQS are aligned (i.e. synchronized).

[0047] Please combine Figure 1The controllable delay chain 10 includes a coarse delay line 10a and a fine delay line 10b. During DLL locking, the coarse delay line 10a outputs two clock signals: a first clock (e.g., an odd clock) even clk and a second clock (e.g., an even clock) oddclk, based on the coarse code output by the control circuit 12. The time difference between these two clock signals is 1C (i.e., the minimum coarse adjustment step size, representing the minimum delay that the controllable delay chain 10 can increase or decrease during the coarse delay adjustment process). The fine delay line 10b receives the first clock even clk and the second clock odd clk output by the coarse delay line 10a, and outputs a phase-adjusted clock signal CLK_out based on the fine code output by the control circuit 12. For example, when the fine code is... <0000> When the first clock cycle clk is output as CLK_out, the fine-tuning code is... <1111> When the fine-tuning code reaches its maximum value, the second clock, odd clk, is output as CLK_out. When the fine-tuning code is at its intermediate value, the clock signal located between the phases of the first clock, even clk, and the second clock, odd clk, is output as CLK_out.

[0048] Here, it is assumed that when DLL locking begins, the fine code in the initial state is... <0000> To fine-tune delay chain 10b, select the first clock cycle (even clk) for output, i.e., CLK_out is set to even clk. When performing the +1C operation, please refer to... Figure 2 There are: ① Fine code from <0000> Switch directly to <1111> This indicates that the fine-tuning delay chain 10b switches its output CLK_out from even clk to odd clk; ② the coarse-tuning code is switched, code2 = code1 + 1, and the first clock even clk is adjusted. Thus, the fine-tuning delay chain 10b's output CLK_out ultimately achieves the +1C operation function. When performing the -1C operation, please refer to... Figure 3 There are: ① Fine code, starting from... <1111> Switch directly to <0000> ① This means that the fine-tuning delay chain 10b switches the output CLK_out from odd clk to even clk, which is equivalent to first performing "+1C" on CLK_out; ② The coarse code is switched, code1=code2-1, and the first clock even clk is adjusted, which is equivalent to performing "-2C" on CLK_out again. Thus, the output CLK_out of the fine-tuning delay chain 10b finally achieves the operation function of -1C.

[0049] Obviously, when performing a +1C or -1C operation, both the coarse code and the fine code will change, thus resulting in... Figure 2 , Figure 3 In the case of the first step ① followed by the second step ②, since the coarse adjustment delay chain 10a includes the initial delay, its delay is generally greater than that of the fine adjustment delay chain 10b. That is, the delay of the controllable delay chain 10 is finely adjusted first, then coarsely adjusted, under the control of the control circuit 12. Specifically, in the case of the -1C operation, since ① is followed by ②, the -1C operation is equivalent to "first +1C, then -2C". Ultimately, the input terminal of the phase detector 14 receives the feedback clock signal DQS. fb The process of "+1C first, then -2C" may lead to the following problems:

[0050] Please refer to Figure 4 As shown, assuming that DQS is at this time fb The rising edge occurs after the rising edge of VCLK. After the -1C operation, if the phase detection result of phase detector 14 flips, it indicates DQS. fb The rising edge is adjusted to before the rising edge of VCLK. However, since the actual -1C operation is "first +1C, then -2C", the phase detector 14 may detect the effect of +1C, and its phase detection result will not flip (i.e., the phase detection result of the phase detector 14 is incorrect). At this time, the control circuit 12 thinks that -1C is still needed. As a result, the -1C operation that should be performed in one step may be performed in multiple steps due to the incorrect phase detection result of the phase detector 14 (i.e., multiple steps of -1C operation are incorrectly performed), which will lead to DQS. fb As the rising edge moves further away from the rising edge of VCLK, the DLL locking time becomes significantly longer, affecting the normal operation of the system device.

[0051] Based on this, the present invention provides a time-delay phase-locked loop (DLL) circuit and a system device having the DLL circuit. By modifying the control circuit (also referred to as the "controller") in the DLL circuit, it optimizes the situation where the -1C operation in the prior art causes an increase in the DLL locking time. It adds a step at the beginning of the first subtraction-1C operation, giving the original first subtraction-1C operation two update opportunities, avoiding the situation where the actual subtraction-1C operation "adds 1C first, then subtracts 2C", thus ensuring that the phase detector in the DLL circuit receives the DQS... fbThe delay change matches the control code change output by the control circuit in the DLL circuit, reducing the possibility of the phase detector's detection result being incorrect. This avoids the situation where the decrement 1C operation, which should be performed once, is executed multiple times due to the phase detector's incorrect detection result, allowing the DLL circuit to lock normally and ensuring the normal operation of the system device. Furthermore, the technical solution of the present invention can add a step after completing the final decrement 1C operation, so that the original first step of fine adjustment operation (e.g., +4F operation) has two update opportunities, further reducing the possibility of the phase detector's detection result being incorrect.

[0052] Please refer to Figure 5 An embodiment of the present invention provides a time-locked loop (DLL) circuit, comprising a controllable delay chain 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, and a phase detector 14. The controllable delay chain 10 includes a coarse-adjustment delay chain 10a and a fine-adjustment delay chain 10b. The control circuit 12 is used to output a coarse-adjustment code to control the delay of the coarse-adjustment delay chain 10a. The control circuit 12 is also used to output a fine-adjustment code to control the delay of the fine-adjustment delay chain 10b and to implement the adjustment operation of the output CLK_out of the fine-adjustment delay chain 10b. The unit coarse adjustment step size of the coarse adjustment delay chain 10a is 1C (also called the "minimum coarse adjustment step size", representing the minimum delay that the coarse adjustment delay chain 10a can increase or decrease during the coarse adjustment process), and the unit coarse adjustment step size of the fine adjustment delay chain 10b is 1F (also called the "minimum fine adjustment step size", representing the minimum delay that the fine adjustment delay chain 10b can increase or decrease during the fine adjustment process). For example, 1C = 16F, and the adjustment operation implemented by the control circuit 12 on the output CLK_out of the fine adjustment delay chain 10b through the control code can include an operation of increasing 1C, decreasing 1C, increasing 4F, increasing 1F, decreasing 1F, etc.

[0053] The coarse adjustment delay chain 10a is coupled to the control circuit 12. During DLL locking, the coarse adjustment delay chain 10a outputs two clock signals, a first clock (e.g., an odd clock) "even clk" and a second clock (e.g., an even clock) "odd clk", to the fine adjustment delay chain 10b based on the coarse adjustment code output by the control circuit 12. The time difference between these two clock signals is a unit coarse adjustment step size 1C. The fine adjustment delay chain 10b receives the first clock "even clk" and the second clock "odd clk" output by the coarse adjustment delay chain 10a and outputs a phase-adjusted clock signal CLK_out based on the fine adjustment code output by the control circuit 12. In one example, when the fine adjustment code is... <0000> When the fine code reaches its minimum value, the first clock cycle (even clk) is output as CLK_out. <1111> When the fine code reaches its maximum value, the second clock, odd clk, is output as CLK_out. When the fine code is at its intermediate value, the clock signal located between the phases of the first clock, even clk, and the second clock, odd clk, is output as CLK_out.

[0054] The input of the clock buffer circuit 11 is coupled to the output of the fine-tuning delay chain 10b, and is used to convert the output CLK_out of the fine-tuning delay chain 10b into the internal clock DQS required for the operation of the internal circuitry of the system device.

[0055] The replica clock buffer circuit 13 is a replica circuit of the clock buffer circuit 11. The input of the replica clock buffer circuit 13 is coupled to the output of the fine-tuning delay chain 10b, and is used to delay the output CLK_out of the fine-tuning delay chain 10b and output it as the feedback clock signal DQS. fb .

[0056] One input of phase detector 14 is coupled to VCLK and the input of coarse adjustment delay chain 10a, and the other input of phase detector 14 is coupled to the output of replica clock buffer circuit 13, and is used to distinguish between external clock signal VCLK and feedback clock signal DQS. fb The phase difference between them is calculated, and the phase detection result is output to the control circuit 12.

[0057] The control circuit 12 generates a corresponding coarse code based on the phase detection result of the phase detector 14 to control the length of the coarse delay chain 10a to increase or decrease, thereby increasing or decreasing the delay of the first clock even clk or the second clock odd clk relative to VCLK. At the same time, it outputs a fine code to control the length of the fine delay chain 10b to increase or decrease, thereby increasing or decreasing the delay of CLK_out relative to VCLK. This adjusts the phase difference between VCLK and the internal clock signal DQS output by the clock buffer circuit until the phase between VCLK and DQS is synchronized. The DLL circuit completes locking, and at this time, VCLK and DQS are aligned (i.e. synchronized).

[0058] In the time-locked loop circuit of this embodiment, the process by which the control circuit 12 controls the controllable delay chain 10 to perform the fine-tuning operation of the output CLK_out of the delay chain 10b by adding 1C (i.e., "+1C") is the same as in the prior art. Please refer to [reference needed]. Figure 2 Assuming that when DLL locking begins, the initial fine-tuning code is... <0000> The fine-tuning delay chain 10b selects the first clock, even clk, as the output, i.e., CLK_out is even clk. During the increment operation ("+1C"), the following occurs: ① The fine-tuning code starts from... <0000> Switch directly to <1111> ① This indicates that the fine-tuning delay chain 10b switches its output CLK_out from even clk to oddclk; ② The coarse code is switched, code2=code1+1, and the first clock even clk is adjusted, thus the fine-tuning delay chain 10b's output CLK_out finally achieves the +1C operation function.

[0059] In this embodiment of the time-locked loop circuit, the process by which the control circuit 12 controls the controllable delay chain 10 to perform a decrement (i.e., "-1C") operation on the output CLK_out of the fine-tuning delay chain 10b differs from existing technologies. In one example, the control circuit 12 adds a step to the beginning of the CLK_out -1C operation (i.e., the first step -1C operation), making the DQS... fb The delay change matches the change of the control code output by the control circuit 12, reducing the possibility of errors in the phase detection result of the phase detector 14 and enabling the DLL circuit to lock normally.

[0060] In this example, the clock periods of the fine-tuning control clock Fine clk of the fine-tuning delay chain 10b and the coarse-tuning control clock Coarse clk of the coarse-tuning delay chain 10a are both Xn*Tck. This means that the control circuit 12 updates its output fine code and coarse code every Xn*Tck. Therefore, in this example, the control circuit 12 optimizes the -1C operation in the first step and completes it in two steps (i.e., the -1C operation in the first step contains 2 Xn*Tck). In the -1C operation in the first step, the control circuit 12 updates the control code once every Xn*Tck. Specifically, please refer to... Figure 5 and Figure 6 Assuming that in the initial state, the control circuit 12 outputs the second coarse tuning code 2 to the coarse tuning delay chain 10a, and simultaneously outputs the second fine tuning code. <1111> The fine-tuning delay chain 10b is configured to select the second clock, odd clk, as its output, i.e., CLK_out = oddclk. During the first step (-1C) operation of the output CLK_out of the fine-tuning delay chain 10b, the control circuit 12 is further configured as follows:

[0061] When the first update timing Xn1_1 (i.e., the first Xn*Tck) is reached, the control circuit 12 maintains the output of the second fine-tuning code unchanged, and simultaneously outputs a first coarse-tuning code code1, different from the second coarse-tuning code code2, to the coarse-tuning delay chain 10a, so as to first perform a subtraction operation of 2C ("-2C") on the first clock even clk (or, the first clock even clk is first subtracted by 2C). At this time, the fine-tuning delay chain 10b still selects the second clock odd clk for output, that is, the delay of CLK_out remains unchanged, and the phase detection result of the phase detector 14 remains unchanged (i.e., the output of the phase detector 14 remains unchanged). In one example, code1 = code2 - 1 (i.e., the first coarse-tuning code code1 is the second coarse-tuning code code2 minus 1), and this second fine-tuning code is the maximum value among all the fine-tuning codes that the control circuit 12 can output, for example, is <1111> .

[0062] When the second update timing Xn1_2 (i.e., the second Xn*Tck) is reached, the control circuit 12 outputs a first fine-tuning code different from the second fine-tuning code to the fine-tuning delay chain 10b. Simultaneously, it outputs a zeroth coarse-tuning code code0 different from both the second coarse-tuning code code2 and the first coarse-tuning code code1 to the coarse-tuning delay chain 10a. At this time, the fine-tuning delay chain 10b selects the first clock even clk for output, realizing the first step -1C operation of the fine-tuning delay chain 10b's output CLK_out, i.e., the delay of CLK_out is relative to... -1C. In one example, code0 = code1 - 1 (i.e., the zeroth coarse adjustment code 0 is the first coarse adjustment code 1 minus 1). Then, the second clock, odd clk, is subtracted by 2C ("-2C") (or, the second clock, odd clk, is then subtracted by 2C). This second fine adjustment code is the minimum value among all the fine adjustment codes that the control circuit 12 can output, for example, [missing value]. <0000> .

[0063] Afterwards, when performing the second and subsequent -1C operations on CLK_out, the normal timing sequence in the existing technology can be followed.

[0064] Therefore, please refer to Figure 6 When the +1C operation on CLK_out becomes a -1C operation, the -1C operation implemented by the control circuit 12 described above is executed. Compared with the prior art, this is achieved by executing the first update timing Xn1_1 operation an additional time (i.e., executing one more step such as...). Figure 6 In This allows CLK_out to be updated to the later phase signal among even clk and oddclk, preventing the "+1C first, then -2C" situation from occurring during normal -1C operations. In other words, this embodiment adds a step at the beginning of the first -1C operation, providing two update opportunities in the original first -1C operation. This reduces the error in the phase detector 14's phase detection result, preventing the -1C operation, which should be performed once, from being executed multiple times due to incorrect phase detector results. This ensures the DLL circuit can lock properly, guaranteeing the normal operation of the system device.

[0065] In another example, the clock periods of the fine-tuning control clock Fine clk of fine-tuning delay chain 10b and the coarse-tuning control clock Coarse clk of coarse-tuning delay chain 10a are both Xn*Tck. This means that the control circuit 12 updates its output fine code and coarse code every Xn*Tck. Thus, in this example, the control circuit 12 optimizes the first step -1C operation and completes it in two steps (i.e., the first step -1C operation contains 2 Xn*Tck). After the last step -1C operation, the first step fine-tuning operation Fine delay (its step size is, for example, +4F) is optimized to be completed in two steps (for example, the first step +4F operation is performed after the last step -1C operation, and the first step +4F operation contains 2 Xn*Tck). In the first step -1C operation and the first step fine-tuning operation (for example, the first step +4F operation), the control circuit 12 updates the control code once every Xn*Tck is reached. Therefore, the control circuit 12 first performs a decrement operation (C) on CLK_out (which can be executed in multiple work cycles, i.e., each work cycle can be called a one-step decrement operation or a single-cycle decrement operation), and then performs a fine-tuning operation (e.g., a +4F operation, which can also be executed in multiple work cycles, i.e., each work cycle can be called a one-step +4F operation or a single-cycle +4F operation). The control circuit 12 adds one step at the beginning (i.e., when the first step of the -C operation begins) and at the end (i.e., after the last step of the -C operation, or when the first step of the fine-tuning operation begins) of the -C operation on CLK_out, ultimately enabling DQS to achieve this. fb The delay change matches the change in the control code output by the control circuit 12, reducing the possibility of errors in the phase detection result of the phase detector 14 and enabling the DLL circuit to lock normally. Specifically, during the first step -1C operation on the output CLK_out of the fine-tuning delay chain 10b, the configuration function of the control circuit 12 is as follows: Figure 6 As mentioned in S11 and S12 above, they will not be repeated here.

[0066] Please combine further Figure 5 and Figure 7 As shown, in the initial state after completing the final step -1C operation, the control circuit 12 outputs the zeroth coarse adjustment code code0 to the coarse adjustment delay chain 10a, and simultaneously outputs the first fine adjustment code to the fine adjustment delay chain 10b, causing the fine adjustment delay chain 10b to select the first clock even clk for output. Furthermore, when performing the first fine adjustment operation (e.g., +4F operation) on the output CLK_out of the fine adjustment delay chain 10b, the control circuit 12 is further configured as follows:

[0067] When the first update timing Xn2_1 (i.e. the first Xn*Tck) is reached, the first fine-tuning code is kept unchanged, and the first coarse-tuning code code1 is output to the coarse-tuning delay chain 10a. At this time, the fine-tuning delay chain 10b still selects the first clock evenclk for output, that is, the delay of CLK_out remains unchanged, the phase detection result of phase detector 14 remains unchanged (i.e., the output of phase detector 14 remains unchanged), and at the same time, the second clock odd clk is incremented by 2C ("+2C").

[0068] When the second update timing Xn2_2 (i.e., the second Xn*Tck) is reached, the first coarse tuning code code1 is kept unchanged, and a third fine tuning code, different from the first fine tuning code, is output to the fine tuning delay chain 10b. The fine tuning delay chain 10b then performs phase adjustment on its output CLK_out according to this third fine tuning code, adding a normal delay to CLK_out, thus realizing the first step of the fine tuning operation (e.g., +4F) on the output CLK_out of the fine tuning delay chain 10b. In one example, the first fine tuning code is... <0000> The third fine-tuning code is <0100> .

[0069] Afterwards, when performing the second and subsequent fine-tuning operations on CLK_out, the normal timing sequence in the existing technology can be followed.

[0070] Therefore, when changing the CLK_out operation from -1C to +4F, one more step is performed compared to existing technologies. Figure 7 shown This allows CLK_out to be updated with the earlier phase signal from either even clk or odd clk, thus enabling the subsequent addition of a delay to CLK_out and enabling DQS. fb The delay change matches the change of the control code output by the control circuit 13, further reducing the possibility of errors in the phase detector's phase detection result, which is conducive to achieving phase alignment of VCLK and DQS more quickly and realizing fast locking of the DLL circuit.

[0071] It should be understood that the control circuit 12 in this embodiment can achieve the above-described functional configuration by adding any suitable hardware circuit design.

[0072] Alternatively, please refer to Figure 8 and Figure 9The hardware circuitry (i.e., the modified part) added to the control circuit 12 compared to the prior art includes a state widening circuit 121 and a fine-tuning code control circuit 122. The state widening circuit 121 is used to generate a fine-tuning gating signal Fine gating and a widening control signal -1Cctrl new based on the original control signal -1Cctrl and the update timing signal Xnclk. The first edge of the widening control signal -1Cctrl new is aligned with the first edge of the original control signal -1Cctrl, and the second edge of the widening control signal -1Cctrl new is delayed relative to the second edge of the original control signal -1Cctrl. The fine-tuning code control circuit 122 generates a fine-tuning code control signal, Fine clk new, based on the fine-tuning control clock Fine clk and the fine-tuning gating signal Fine gating. This Fine clk new signal is used to disable the fine-tuning control clock Fine clk at the beginning of the first step of the -1C operation on CLK_out and after the last step of the -1C operation (or at the beginning of the first step of the +4F operation), thus freezing the fine-tuning code. Specifically, in control circuit 122, during the -1C operation on CLK_out, -1C ctrl is active, and the clock periods of both the fine-tuning control clock Fine clk and the coarse-tuning control clock Coarseclk are Xn*Tck, representing an update of the fine-tuning code and coarse-tuning code every Xn*Tck. When -1C ctrl new becomes inactive, a valid signal for the +4F operation is triggered, and the CLK_out undergoes a normal +4F operation.

[0073] As an example, please refer to Figure 8The state-widening circuit includes a first flip-flop U1, an XOR logic circuit XNOR, a first AND logic circuit AND1, and a second AND logic circuit AND2. The clock terminal Clkb of the first flip-flop U1 is coupled to the update timing signal Xnclk, the input terminal D of the first flip-flop U1 is coupled to the original control signal -1Cctrl, and the output terminal Q of the first flip-flop U1 outputs a delay control signal -1Cctrldelay, which is delayed relative to the original control signal -1Cctrl. The XOR logic circuit XNOR can be an XOR gate or other circuits constituting XOR logic. The first input terminal of the XNOR logic circuit XNOR is coupled to the original control signal -1Cctrl, the second input terminal of the XNOR logic circuit XNOR is coupled to the delay control signal -1Cctrldelay, and the output terminal of the XNOR logic circuit XNOR outputs a fine-tuning gate signal Finegating. The first AND logic circuit AND1 can be an AND gate or other suitable circuits that constitute AND logic. The first input terminal of the first AND logic circuit AND1 is coupled to the original control signal -1C ctrl, the second input terminal of the first AND logic circuit AND1 is coupled to the delay control signal -1C ctrl delay, and the output terminal of the first AND logic circuit AND1 outputs the widened control signal -1C ctrl new.

[0074] In one example, the fine-tuning code control circuit 122 includes a second AND logic circuit AND2. The second AND logic circuit AND2 can be an AND gate or any other suitable circuit that constitutes AND logic. The first input of the second AND logic circuit AND2 is coupled to the fine-tuning gating signal Fine gating, the second input of the second AND logic circuit AND2 is coupled to the fine-tuning control clock Fine clk, and the output of the second AND logic circuit AND2 outputs the fine-tuning code control signal Fine clk new.

[0075] It should be understood that a state machine (not shown) may be provided in the control circuit 12. The aforementioned state widening circuit 121 and fine-tuning control circuit 122 may be integrated into the state machine. The state machine outputs corresponding coarse and fine tuning codes according to the outputs of the state widening circuit 121 and the fine-tuning control circuit 122 to control the controllable delay chain 10 to perform coarse tuning operations such as +1C and -1C and fine tuning operations such as +4F and +1F until VCLK is aligned with DQS. The state machine then enters a locked state, completing the locking of the DLL circuit.

[0076] Based on the same inventive concept, please refer to Figure 5 and Figure 8 This embodiment also provides a system device, which includes a time-delay phase-locked loop circuit as described in this invention.

[0077] In one example, the system device is a memory chip (e.g., a DRAM chip). The clock signal DQS output by the delay phase-locked loop circuit is the data select pulse signal of the memory chip. The delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal VCLK input to the memory chip and the data select pulse signal DQS until the external clock signal VCLK and the data select pulse signal DQS are synchronized and locked. For the memory chip, the fast locking of the DLL circuit can ensure the correct implementation of read, write and other operations.

[0078] In summary, the time-delay phase-locked loop (TLL) circuit and system device with the present invention optimize the situation where the DLL locking time is prolonged due to the subtraction of 1C operation in the prior art. By adding a step at the beginning of the first subtraction of 1C operation, the original first subtraction of 1C operation has two update opportunities, avoiding the situation of "adding 1C first and then subtracting 2C" in the actual subtraction of 1C operation, reducing the possibility of phase detector errors, and thus avoiding the situation where the subtraction of 1C operation, which should be performed once, is performed multiple times due to the phase detector's incorrect phase detection result. This ensures that the DLL circuit can lock normally and guarantees the normal operation of the system device.

[0079] Furthermore, the technical solution of the present invention can add a step after completing the final step of subtracting 1C, so that there are two update opportunities in the original first step of fine adjustment operation (e.g., +4F operation), which further reduces the possibility of errors in the phase detector's phase detection result and is more conducive to realizing the fast locking of the DLL circuit.

[0080] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A time-delay phase-locked loop circuit, comprising a controllable delay chain and a control circuit, wherein the controllable delay chain has a coarse-adjustment delay chain and a fine-adjustment delay chain, the coarse-adjustment delay chain being used to output a first clock and a second clock with a phase difference of 1C to the fine-adjustment delay chain, where 1C is a unit coarse-adjustment step size; characterized in that, The control circuit is used to output a coarse tuning code to control the delay of the coarse tuning delay chain and to output a fine tuning code to control the delay of the fine tuning delay chain, and to perform a decrement operation of 1C on the output of the fine tuning delay chain. Specifically, during the first decrement operation of the output of the fine tuning delay chain, the control circuit is further configured to: In the initial state, a second coarse tuning code is output to the coarse tuning delay chain, and a second fine tuning code is output to the fine tuning delay chain, so that the fine tuning delay chain selects the second clock output; When the first clock cycle of the fine-tuning control clock of the fine-tuning delay chain is reached, the first update opportunity is reached. At this time, the output of the second fine-tuning code remains unchanged, so that the fine-tuning delay chain still selects the second clock output. At the same time, a first coarse-tuning code different from the second coarse-tuning code is output to the coarse-tuning delay chain to perform a 2C reduction operation on the first clock. When the second clock cycle of the fine-tuning control clock is reached, the second update timing is reached. At this time, a first fine-tuning code, which is different from the second fine-tuning code, is output to the fine-tuning delay chain, so that the fine-tuning delay chain selects the first clock output to realize the first step of the output of the fine-tuning delay chain by decrementing by 1C.

2. The time-delay phase-locked loop circuit as described in claim 1, characterized in that, The first fine-tuning code is the minimum value among all fine-tuning codes that the control circuit can output, and the second fine-tuning code is the maximum value among all fine-tuning codes that the control circuit can output.

3. The time-delay phase-locked loop circuit as described in claim 1, characterized in that, The control circuit is further configured to: when the second update timing is reached, while outputting the first fine-tuning code, also output a zero coarse-tuning code different from the first coarse-tuning code to the coarse-tuning delay chain, so as to perform a 2C decrement operation on the second clock.

4. The time-delay phase-locked loop circuit as described in claim 3, characterized in that, The first coarse adjustment code is the second coarse adjustment code minus 1, and / or the zeroth coarse adjustment code is the first coarse adjustment code minus 1.

5. The time-delay phase-locked loop circuit as described in any one of claims 1-4, characterized in that, The control circuit is also used to start fine-tuning the output of the fine-tuning delay chain after completing the final step of the decrementing C operation on the output of the fine-tuning delay chain.

6. The time-delay phase-locked loop circuit as described in claim 5, characterized in that, During the first fine-tuning operation on the output of the fine-tuning delay chain, the control circuit is further configured to: In the initial state, the zeroth coarse tuning code is output to the coarse tuning delay chain, and the first fine tuning code is output to the fine tuning delay chain, so that the fine tuning delay chain selects the first clock output; When the first update timing is reached, the first fine-tuning code is kept unchanged, so that the fine-tuning delay chain still selects the first clock output, and the first coarse-tuning code is output to the coarse-tuning delay chain to perform a 2C increment operation on the second clock. When the second update timing is reached, the first coarse tuning code is kept unchanged, and a third fine tuning code, which is different from the first fine tuning code, is output to the fine tuning delay chain, so that the fine tuning delay chain adjusts the phase of its output according to the third fine tuning code, thereby realizing the first step of fine tuning operation on the output of the fine tuning delay chain.

7. The time-delay phase-locked loop circuit as described in claim 6, characterized in that, After completing the first fine-tuning operation, the output of the fine-tuning delay chain is updated to the clock signal with the earlier phase between the first clock and the second clock.

8. The time-delay phase-locked loop circuit as described in any one of claims 1-4 and 6-7, characterized in that, The control circuit includes: A state broadening circuit is used to generate a fine-tuning gating signal and a broadening control signal based on an original control signal and an update timing signal. The first edge of the broadening control signal is aligned with the first edge of the original control signal, and the second edge of the broadening control signal is delayed relative to the second edge of the original control signal. A fine-tuning code control circuit is used to generate a fine-tuning code control signal based on a fine-tuning control clock and the fine-tuning gate signal, wherein the fine-tuning code control signal is used to freeze the fine-tuning code.

9. The time-delay phase-locked loop circuit as described in claim 8, characterized in that, The state broadening circuit includes: The first trigger has its clock terminal coupled to the update timing signal, its input terminal coupled to the original control signal, and its output terminal outputting a delayed control signal that is delayed relative to the original control signal. An XOR NOT logic circuit, wherein its first input is coupled to the original control signal, its second input is coupled to the delay control signal, and its output outputs the fine-tuning gate signal; and The first AND logic circuit has a first input terminal coupled to the original control signal, a second input terminal coupled to the delay control signal, and an output terminal outputting the widening control signal. And / or, the fine-tuning code control circuit includes a second AND logic circuit, whose first input is coupled to the fine-tuning gate signal, whose second input is coupled to the fine-tuning control clock, and whose output outputs the fine-tuning code control signal.

10. The time-delay phase-locked loop circuit as described in any one of claims 1-4, 6-7, and 9, characterized in that, Also includes: A clock buffer circuit, whose input is coupled to the output of the fine-tuning delay chain, is used to convert the output of the fine-tuning delay chain into an internal clock required for the operation of the internal circuitry of the system device. A clock buffer circuit is used to replicate clock signals. Its input is coupled to the output of the fine-tuning delay chain. The output of the fine-tuning delay chain is delayed and then output as a feedback clock signal. The phase detector has one input terminal coupled to the input terminal of the controllable delay chain and the other input terminal coupled to the output terminal of the replicated clock buffer circuit. It is used to identify the phase difference between the external clock signal received by the controllable delay chain and the feedback clock signal, and outputs the phase detection result to the control circuit.

11. A system apparatus, characterized in that, Includes the time-delay phase-locked loop circuit as described in any one of claims 1-10.

12. The system apparatus as claimed in claim 11, characterized in that, The system device is a memory chip. The clock signal output by the delay phase-locked loop circuit is the data selection pulse signal of the memory chip. The delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal input to the memory chip and the data selection pulse signal until the external clock signal and the data selection pulse signal are phase synchronized and locked.

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