Fully-integrated digital-to-analog converter based on shift current mirror architecture and multi-segment data weighted average algorithm, and preparation method and equipment of fully-integrated digital-to-analog converter

Abstract

According to the fully-integrated digital-to-analog converter based on the shift current mirror architecture and the multi-segment data weighted average algorithm and the preparation method and equipment thereof, the shift current mirror architecture and the multi-segment data weighted average (MSeDWA) algorithm are adopted in the DAC, and the influence of process, voltage and temperature (PVT) changes on circuit performance is effectively compensated by integrating a programmable bias current generator, so that the circuit performance is improved, and the circuit performance is improved. And the stability and the adaptability of the DAC are obviously improved. In addition, the introduction of the power gating standard unit enables the selection of the type of the current mirror to be more flexible, thereby broadening the working voltage range of the DAC. In terms of circuit design, a multi-stage separation and gain configuration strategy is adopted and comprises a fixed gain stage and a variable gain stage, so that the conversion linearity is optimized and the requirements of different application scenes are met.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and electronic engineering, and in particular to a fully integrated digital-to-analog converter based on a shifted current mirror architecture and a multi-segment data weighted average algorithm. Background Art

[0002] In integrated circuit and electronic system design, digital-to-analog converters (DACs) are key players in converting digital signals into analog signals, and are the bridge for electronic systems to interact with the real-world analog environment. For example, fields such as audio output, sensor signal processing, and wireless communications all rely on high-performance DACs to ensure that digital data can be accurately converted into analog signals, thereby achieving effective transmission and processing of information.

[0003] In recent years, with the advancement of CMOS technology and the maturity of digital circuit design methods, fully integrated DAC technology has emerged and become a research hotspot. Fully integrated DAC abandons the complex design of traditional analog circuits and turns to a circuit design method based entirely on digital standard cells. With the help of electronic design automation (EDA) tools, circuit netlists and layouts are automatically generated, thereby reducing design difficulty and time. Fully integrated DAC not only has high portability and scalability, and is suitable for designs under rapid process evolution, but can also use the design characteristics of standard cells to be reused in different manufacturing processes.

[0004] Existing fully integrated DAC designs are mainly divided into two categories: DAC based on correction algorithms and DAC based on logic gate arrays. In the former, a digital pulse modulator (such as a Δ-Σ modulator) is used to calibrate the unit DAC output, and the resolution and linearity of the DAC are improved by eliminating high-frequency noise in a low-pass filter. Although this method can achieve high resolution at low speeds, there is a significant trade-off between power consumption and speed due to the need for a high sampling rate to maintain signal accuracy; the latter uses standard logic gates (such as NAND and NOR gates) to generate voltage or current outputs, which can support conversion speeds at Nyquist frequencies, but is limited in driving capability by the matching performance of P / N channel transistors, making it difficult to achieve high linearity, especially in high-speed application scenarios.

[0005] Although the existing fully integrated DACs meet certain application requirements to a certain extent, there are still many challenges in terms of PVT adaptability, operating voltage range, linearity, energy efficiency, etc. Therefore, it is particularly important to explore more efficient, stable, and low-power fully integrated DAC design technology. Summary of the invention

[0006] To solve the above problems, the present invention proposes a fully integrated DAC based on a shifted current mirror architecture and a multi-segment data weighted average (MSeDWA) algorithm. It is completely based on standard digital cells and uses electronic design automation (EDA) tools to achieve automated circuit netlist generation and layout, with high portability and scalability. The introduction of a programmable bias current generator can effectively suppress the impact of PVT changes on the circuit and improve the stability of the DAC. At the same time, the use of power-gated standard cells enables flexible selection of current mirrors, thereby expanding the operating voltage range. The multi-segment data weighted average algorithm further optimizes linearity, reduces THD, and meets the requirements of high-precision and high-efficiency conversion. By optimizing the gain configuration of the circuit, the present invention can also achieve high-efficiency output in different application scenarios, and is suitable for systems with strict requirements on linearity, power consumption and energy efficiency.

[0007] The technical solution of the present invention is as follows:

[0008] A fully integrated digital-to-analog converter with a shift current mirror architecture and a multi-segment data weighted average algorithm, the features of which include:

[0009] A programmable bias current generator, consisting of a digital-to-analog voltage converter (DAC) constructed from NAND logic gates, is used to generate and control the bias current of the current mirror and dynamically adjust the current output to achieve dynamic compensation for process, voltage, and temperature (PVT) variations in the circuit;

[0010] The shift current mirror architecture divides the current mirror into multiple controllable segments. Each segment contains several current units that can be turned on or off step by step as needed to reduce the mismatch error between the current segments and improve linearity.

[0011] The multi-segment data weighted average (MSeDWA) module is used to perform segment-wise weighted processing on the DAC input data and dynamically adjust the weight of each segment current to reduce signal distortion caused by mismatch;

[0012] A fixed gain stage and a variable gain stage, wherein the fixed gain stage is used for gain amplification of the basic current, and the variable gain stage is used for further current regulation, and the overall conversion accuracy is optimized through multi-stage gain configuration;

[0013] Fully digital standard cells are used to implement the functions of DAC, and the circuit netlist and layout are automatically generated through electronic design automation tools to improve portability and scalability.

[0014] Furthermore, the programmable bias current generator also includes a power-gated standard unit for converting a voltage signal into a required bias current and realizing flexible switching of different current mirror types to adapt to different working conditions and current requirements.

[0015] Furthermore, each current unit in the shifted current mirror architecture is independently controlled by a programmable gain factor to achieve precise adjustment of the current amplification factor.

[0016] Furthermore, the MSeDWA module divides the input data into several segments, and assigns different weighting coefficients to each segment to reduce signal distortion caused by mismatch and reduce total harmonic distortion (THD).

[0017] Furthermore, an automated gain configuration process is included, so that the fixed gain stage and the variable gain stage can flexibly adjust the gain value according to the input control signal to adapt to different frequency and current output requirements.

[0018] Furthermore, the EDA tool uses a dedicated layout algorithm to achieve optimal arrangement of current components to reduce the difference in current transmission paths and parasitic effects between components and improve the accuracy of current output.

[0019] Second, the present invention also provides a method for manufacturing the above-mentioned DAC, which is characterized in that it includes:

[0020] a) Design the circuit netlist and layout of the DAC using electronic design automation (EDA) tools;

[0021] b) Manufacture the DAC hardware circuit according to the designed circuit netlist and layout;

[0022] c) Calibrate and test the manufactured DAC to ensure it meets the predetermined performance requirements.

[0023] Third, the present invention also provides an electronic device, which is characterized in that it includes the above-mentioned DAC, is used to convert digital signals into analog signals, and is suitable for application scenarios such as wireless communications, precision sensors and Internet of Things devices.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1) It has the advantages of high integration, low power consumption and high energy efficiency, and can effectively solve the shortcomings of traditional DAC in terms of accuracy, linearity and PVT adaptability. By using standard digital units to realize circuit functions, the DAC of the present invention can be quickly transplanted to different process platforms and is suitable for a wide range of application fields, such as precision sensors, wireless communications, the Internet of Things and high-performance audio equipment.

[0026] 2) Experiments show that the DAC of the present invention can provide low power consumption and high energy efficiency output performance when operating in the frequency range of 14 MHz to 56 MHz, and its total harmonic distortion (THD) is kept below 39.9 dB.

[0027] 3) The addition of a programmable bias current generator enables the circuit to suppress current offset by more than 2.7 times under PVT variation conditions, further improving the applicability and stability of the circuit. It has broad application prospects in applications requiring high precision and high efficiency, such as wireless communications, precision sensors, the Internet of Things, and audio signal processing.

[0028] 4) It overcomes the shortcomings of traditional fully integrated DAC in terms of accuracy, linearity and PVT adaptability. This design not only has high energy efficiency, low power consumption and high integration, but is also suitable for various application scenarios with high requirements for DAC performance. Through a fully digital design method, the present invention achieves low-cost, short-cycle product development, and provides a novel and effective solution for high-performance DAC design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a fully integrated digital-to-analog converter architecture based on standard cells;

[0030] Figure 2 A schematic diagram of a flexibly configurable current mirror architecture based on a power gating unit;

[0031] Figure 3 This is a schematic diagram of the working principle of the weighted average algorithm for multi-segment data;

[0032] Figure 4 Automatically generate flow charts for fully integrated DAC circuits. DETAILED DESCRIPTION

[0033] In order to make the purpose, advantages, technical solutions and implementation methods of the present invention more clear, the present invention is further described in detail below in conjunction with examples and drawings, but this should not limit the protection scope of the present invention.

[0034] The present embodiment provides a fully integrated digital-to-analog converter (DAC) based on a shifted current mirror architecture and a multi-segment data weighted average (MSeDWA) algorithm. The DAC is completely composed of standard digital units and uses electronic design automation (EDA) tools to achieve automated circuit netlist generation and layout design, which not only improves the portability and scalability of the DAC, but also effectively reduces the design cost and shortens the development cycle.

[0035] The DAC is mainly composed of a programmable bias current generator, a fixed gain stage, a variable gain stage, and a multi-segment data weighted average (MSeDWA) module, each of which works together to achieve high-precision, low-distortion digital-to-analog conversion. The specific circuit implementation method is as follows:

[0036] First, the present invention designs a programmable bias current generator for generating and controlling the bias current of a current mirror, thereby realizing dynamic compensation for PVT (process, voltage and temperature) changes in a circuit. The bias current generator forms a 5-bit digital-to-analog voltage converter (DAC) through a NAND logic gate, and generates different bias voltage signals according to an input digital signal. The voltage signal is converted into a required bias current after passing through a power-gated standard unit. The current mirror architecture is used to amplify the bias current and drive the output stage of the DAC to achieve higher signal strength and voltage output range. Through the power-gated unit, the programmable bias current generator can realize flexible switching of different current mirror types without affecting the overall performance of the circuit, thereby adapting to different working conditions and current requirements, and improving the reliability and working range of the circuit.

[0037] In the design of the current mirror architecture, the present invention adopts a shift current mirror method to reduce the mismatch error between each current source. The shift current mirror structure divides the current mirror into multiple controllable segments, each segment contains a number of current units, which can be turned on or off step by step as needed to reduce current deviation and improve linearity. The current mirror architecture includes a "fixed gain" stage and a "variable gain" stage, wherein the "fixed gain" stage is used for gain amplification of the basic current, and the "variable gain" stage is used for further current regulation, and the overall conversion accuracy is optimized through multi-stage gain configuration. At the "fixed gain" stage, the present invention uses a power gating unit to form a key unit of the current mirror, and adjusts the current amplification factor through a programmable gain factor to ensure the current output requirements in different application scenarios. This design can effectively reduce the current drift caused by PVT changes, so that the circuit remains stable in high temperature, low voltage and other environments.

[0038] In order to further reduce the mismatch error, the present invention also introduces a multi-segment data weighted average (MSeDWA) algorithm. The MSeDWA algorithm performs segmented weighted processing on the DAC input data and dynamically adjusts the weight of each segment current to reduce the signal distortion caused by mismatch. Specifically, the algorithm divides the input data into several segments, and assigns different weighting coefficients to each segment of data, so that it plays a balancing role in the overall current output. This technology effectively reduces the total harmonic distortion (THD) of the signal and improves the linearity of the DAC output. The MSeDWA algorithm can compensate for the mismatch between current mirror units through multi-segment weight adjustment, and suppress unnecessary frequency components in the high-frequency region, thereby forming a cleaner analog signal at the output. This design not only ensures the high-precision output of the DAC, but also realizes the dynamic correction of the mismatch error.

[0039] In addition, in order to meet different frequency and precision requirements, the present invention designs an automated gain configuration process so that the "fixed gain" and "variable gain" stages of the current mirror can flexibly adjust the gain value according to the input control signal to adapt to different frequency and current output requirements. In implementation, through the gain configuration of the current mirror, an independent gain factor can be provided for each input current segment to ensure the output stability and linearity of the DAC under different working conditions. Especially in high-frequency output demand scenarios, by adjusting the gain setting of the "variable gain" stage, the DAC can quickly respond to frequency changes and maintain a stable output current amplitude, thereby meeting complex signal conversion requirements.

[0040] In terms of netlist generation and layout implementation, the DAC design of the present invention is completely based on standard digital cells, the circuit netlist is automatically generated by EDA tools, and a dedicated layout algorithm is used to achieve the optimal arrangement of current elements. With the help of EDA tools, the present invention can take into account the impact of random mismatch and process mismatch on circuit performance during the design process, thereby optimizing the layout of the current mirror unit to achieve optimal linearity and minimize circuit area. The layout algorithm will automatically distribute each current unit and adjust the position of the components according to the circuit simulation results to reduce the current transmission path differences and parasitic effects between components, thereby improving the accuracy of current output.

[0041] Through the design of the full synthesis method, the implementation process of the DAC of the present invention is greatly simplified, which can shorten the design cycle and reduce the development cost without sacrificing performance, while achieving higher reliability and process adaptability. The test results show that when the DAC of the present invention operates in the frequency range of 14MHz to 56MHz, it can provide low power consumption and high energy efficiency output performance, and its total harmonic distortion (THD) is maintained below 39.9dB, showing good linearity and energy efficiency. In addition, the addition of a programmable bias current generator enables the circuit to suppress the current offset by more than 2.7 times under PVT variation conditions, further improving the applicability and stability of the circuit. This design has broad application prospects in applications that require high precision and high efficiency, such as wireless communications, precision sensors, the Internet of Things, and audio signal processing.

[0042] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fully integrated digital-to-analog converter with a shift current mirror architecture and a multi-segment data weighted average algorithm, characterized in that: include: A programmable bias current generator, consisting of a digital-to-analog voltage converter (DAC) constructed from NAND logic gates, is used to generate and control the bias current of the current mirror and dynamically adjust the current output to achieve dynamic compensation for process, voltage, and temperature (PVT) variations in the circuit; The shift current mirror architecture divides the current mirror into multiple controllable segments. Each segment contains several current units that can be turned on or off step by step as needed to reduce the mismatch error between the current segments and improve linearity. The multi-segment data weighted average (MSeDWA) module is used to perform segment-wise weighted processing on the DAC input data and dynamically adjust the weight of each segment current to reduce signal distortion caused by mismatch; A fixed gain stage and a variable gain stage, wherein the fixed gain stage is used for gain amplification of the basic current, and the variable gain stage is used for further current regulation, and the overall conversion accuracy is optimized through multi-stage gain configuration; Fully digital standard cells are used to implement the functions of DAC, and the circuit netlist and layout are automatically generated through electronic design automation tools to improve portability and scalability.

2. The fully integrated digital-to-analog converter with a shifted current mirror architecture and a multi-segment data weighted average algorithm according to claim 1, characterized in that: The programmable bias current generator also includes a power-gated standard unit for converting a voltage signal into a required bias current and realizing flexible switching of different current mirror types to adapt to different working conditions and current requirements.

3. The fully integrated digital-to-analog converter with a shifted current mirror architecture and a multi-segment data weighted average algorithm according to claim 1, characterized in that: Each current unit in the shifted current mirror architecture is independently controlled through a programmable gain factor to achieve precise adjustment of the current amplification factor.

4. The fully integrated digital-to-analog converter with a shifted current mirror architecture and a multi-segment data weighted average algorithm according to claim 1, characterized in that: The MSeDWA module divides the input data into several segments, and assigns different weighting coefficients to each segment of data to reduce signal distortion caused by mismatch and lower total harmonic distortion (THD).

5. A fully integrated digital-to-analog converter with a shifted current mirror architecture and a multi-segment data weighted average algorithm according to any one of claims 1 to 4, characterized in that: It also includes an automated gain configuration process that enables the fixed gain stage and the variable gain stage to flexibly adjust the gain value according to the input control signal to adapt to different frequency and current output requirements.

6. The fully integrated digital-to-analog converter with a shifted current mirror architecture and a multi-segment data weighted average algorithm according to claim 1, characterized in that: The EDA tool uses a dedicated layout algorithm to achieve optimal arrangement of current components to reduce current transmission path differences and parasitic effects between components and improve the accuracy of current output.

7. A method for manufacturing the DAC according to any one of claims 1 to 6, characterized in that: include: a) Design the circuit netlist and layout of the DAC using electronic design automation (EDA) tools; b) Manufacture the DAC hardware circuit according to the designed circuit netlist and layout; c) Calibrate and test the manufactured DAC to ensure it meets the predetermined performance requirements.

8. An electronic device, characterized in that: A DAC comprising any one of claims 1 to 6, used for converting digital signals into analog signals, and suitable for application scenarios such as wireless communications, precision sensors and Internet of Things devices.

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