Clock synchronization method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a clock synchronization method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of clock synchronization. Comprising the steps that a clock synchronization signal is received, and the clock synchronization signal is generated by performing frequency division on a first clock signal currently corresponding to a first chip based on a target frequency division number; acquiring a second clock signal currently corresponding to a second chip; and adjusting the second clock signal according to the clock synchronization signal, a first clock period corresponding to the clock synchronization signal and a second clock period corresponding to the second chip so as to enable the first chip and the second chip to be in clock synchronization. Therefore, the clock synchronization signal is generated based on the first clock signal, and the second clock signal corresponding to the second chip and the first clock signal corresponding to the first chip are synchronized based on the clock synchronization signal, so that global clock synchronization between the first chip and the second chip is realized, and the precision of clock synchronization is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of clock synchronization technology, and in particular to a clock synchronization method, device, electronic device, chip and storage medium. Background Art

[0002] With the development of communication systems, Radio Frequency Integrated Circuit (RFIC) has more and more functions, such as adding central processing unit (CPU), digital front end (DFE), etc. These newly added functions require more precise timing control of RFIC to ensure that RFIC can control the RF link based on the same time reference with baseband integrated circuit (BBIC) to complete synchronization with the base station.

[0003] Although the clocks of BBIC and RFIC are from the same source, due to factors such as chip technology, phase-locked loop (PLL), temperature, etc., the global clocks of BBIC and RFIC will deviate, and long-term accumulation will cause large time deviations between BBIC and RFIC. Therefore, how to synchronize the clocks of BBIC and RFIC has become an urgent problem to be solved. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] The first embodiment of the present disclosure provides a clock synchronization method, including:

[0006] Receiving a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to the first chip based on a target frequency division number;

[0007] Obtaining a second clock signal currently corresponding to the second chip;

[0008] According to the clock synchronization signal, the first clock cycle and the second clock cycle, the second clock signal is adjusted to synchronize the clocks of the first chip and the second chip. The first clock cycle is the product of a first reference clock cycle corresponding to the first chip and the target division number, and the second clock cycle is a second reference clock cycle corresponding to the second chip.

[0009] A second aspect of the present disclosure provides a clock synchronization method, including:

[0010] Acquire a first clock signal currently corresponding to the first chip;

[0011] Based on the target frequency division number, the first clock signal is frequency-divided to obtain a clock synchronization signal;

[0012] The clock synchronization signal is sent.

[0013] The third aspect of the present disclosure provides a clock synchronization device, including:

[0014] A receiving module, configured to receive a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to the first chip based on a target frequency division number;

[0015] An acquisition module, used for acquiring a second clock signal currently corresponding to the second chip;

[0016] An adjustment module is used to adjust the second clock signal according to the clock synchronization signal, the first clock cycle and the second clock cycle to synchronize the clocks of the first chip and the second chip, wherein the first clock cycle is the product of a first reference clock cycle corresponding to the first chip and the target division number, and the second clock cycle is a second reference clock cycle corresponding to the second chip.

[0017] A fourth aspect of the present disclosure provides a clock synchronization device, including:

[0018] An acquisition module, used to acquire a first clock signal currently corresponding to the first chip;

[0019] A frequency division module, used to divide the first clock signal based on a target frequency division number to obtain a clock synchronization signal;

[0020] A sending module is used to send the clock synchronization signal.

[0021] A fifth aspect embodiment of the present disclosure proposes a second chip, comprising a processing circuit, wherein the processing circuit is configured to execute the clock synchronization method as described in the first aspect embodiment.

[0022] A sixth aspect embodiment of the present disclosure proposes a first chip, comprising a processing circuit, wherein the processing circuit is configured to execute the clock synchronization method as described in the second aspect embodiment.

[0023] The seventh aspect embodiment of the present disclosure proposes an electronic device, including: a first chip and a second chip, the second chip is used to execute the clock synchronization method as described in the first aspect embodiment, and the first chip is used to execute the clock synchronization method as described in the second aspect embodiment.

[0024] The eighth aspect embodiment of the present disclosure proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the clock synchronization method proposed in the first aspect embodiment of the present disclosure, or implements the clock synchronization method described in the second aspect embodiment.

[0025] The ninth aspect embodiment of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the clock synchronization method proposed in the first aspect embodiment of the present disclosure, or implements the clock synchronization method described in the second aspect embodiment.

[0026] The clock synchronization method, device, electronic device, chip and storage medium provided by the present disclosure have the following beneficial effects:

[0027] In the disclosed embodiment, a clock synchronization signal is received, wherein the clock synchronization signal is generated by dividing the first clock signal currently corresponding to the first chip based on the target frequency division number; a second clock signal currently corresponding to the second chip is obtained; and the second clock signal is adjusted according to the clock synchronization signal, the first clock cycle corresponding to the clock synchronization signal, and the second clock cycle corresponding to the second chip, so as to synchronize the clocks of the first chip and the second chip. Thus, based on the first clock signal, a clock synchronization signal is generated, and then based on the clock synchronization signal, the second clock signal corresponding to the second chip is synchronized with the first clock signal corresponding to the first chip, which not only realizes the synchronization of the global clock between the first chip and the second chip, but also improves the accuracy of clock synchronization.

[0028] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

[0031] Figure 2 A flowchart of a clock synchronization method provided by another embodiment of the present disclosure;

[0032] Figure 3 A flowchart of a clock synchronization method provided by another embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of an adjusted second clock signal provided by an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of an adjusted second clock signal provided by an embodiment of the present disclosure;

[0035] Figure 6 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

[0036] Figure 7 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

[0037] Figure 8 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of the structure of a clock synchronization device provided by an embodiment of the present disclosure;

[0039] Fig.10 A schematic diagram of the structure of a clock synchronization device provided by an embodiment of the present disclosure;

[0040] Fig.11 is a schematic diagram of the structure of a first chip proposed in an embodiment of the present disclosure;

[0041] Fig.12 is a schematic diagram of the structure of a second chip proposed in an embodiment of the present disclosure;

[0042] Fig.13 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0044] The clock synchronization method, device, electronic device, chip and storage medium of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0045] Figure 1 A flowchart of a clock synchronization method provided in an embodiment of the present application. It should be noted that the clock synchronization method of this embodiment can be applied to a clock synchronization device. In some possible embodiments, the device can be configured in an electronic device or a chip so that the electronic device or the chip can perform a clock synchronization function. In addition, in some possible embodiments, the clock synchronization device can also be software in an electronic device, etc. Among them, the software, for example, is communication software, etc.

[0046] like Figure 1 As shown, the clock synchronization method may include the following steps:

[0047] Step 101: Receive a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to a first chip based on a target frequency division number.

[0048] The first chip may be an RFIC chip in an electronic device, or a BBIC chip or other chip that requires clock synchronization.

[0049] The first clock signal may be a global clock signal corresponding to the first chip obtained after the first chip processes the clock signal generated by the crystal oscillator of the electronic device.

[0050] In some embodiments, the first chip may process the clock signal generated by the crystal oscillator through a phase locked loop (PLL) to change the frequency, phase, etc. of the clock signal. This disclosure is not limited to this.

[0051] It should be noted that due to factors such as the first chip process, phase locked loop (PLL), temperature, etc., there may be an error between the clock frequency corresponding to the first clock signal and the first reference clock frequency corresponding to the first chip. The first reference clock frequency may be a global clock frequency of the first chip set by the user.

[0052] In some embodiments, the first reference clock frequency corresponding to the first clock signal may be a multiple of the clock frequency of the crystal oscillator. For example, if the clock frequency of the crystal oscillator is 26 megahertz (MHz), the first reference clock frequency may be 312 MHz, 156 MHz, etc. This disclosure does not limit this.

[0053] In some embodiments, the first reference clock frequency corresponding to the first clock signal may also be a multiple of the data sampling rate. The data sampling rate is the sampling frequency when the first chip performs digital processing on the received analog signal. For example, if the data sampling rate is 38.4 MHz, the first reference clock frequency may be 245.76 MHz, 122.88 MHz, etc. This disclosure does not limit this.

[0054] In some embodiments, the target frequency division number may be 65536, that is, 2 to the 16th power; or 32768, that is, 2 to the 15th power, etc. This disclosure does not limit this.

[0055] Step 102: Obtain a second clock signal currently corresponding to the second chip.

[0056] The second chip and the first chip are different chips. If the first chip is an RFIC chip, the second chip is a BBIC chip; or if the first chip is a BBIC chip, the second chip is an RFIC chip.

[0057] The second clock signal may be a global clock signal corresponding to the second chip obtained after the second chip processes the clock signal generated by the crystal oscillator of the electronic device.

[0058] In some embodiments, the second chip may process the clock signal generated by the crystal oscillator through a phase locked loop (PLL) to change the frequency, phase, etc. of the clock signal. This disclosure is not limited to this.

[0059] It should be noted that due to factors such as the second chip process, a phase locked loop (PLL), and temperature, there may be an error between the clock frequency corresponding to the second clock signal and the second reference clock frequency corresponding to the second chip.

[0060] The second reference clock frequency may be a global clock frequency of the second chip set by a user.

[0061] In some embodiments, the second reference clock frequency corresponding to the second clock signal may be a multiple of the clock frequency of the crystal oscillator. For example, if the clock frequency of the crystal oscillator is 26 megahertz (MHz), the second reference clock frequency may be 312 MHz, 156 MHz, etc. This disclosure does not limit this.

[0062] In some embodiments, the second reference clock frequency corresponding to the second clock signal may also be a multiple of the data sampling rate. The data sampling rate is the sampling frequency when the first chip performs digital processing on the received analog signal. For example, if the data sampling rate is 38.4 MHz, the first reference clock frequency may be 245.76 MHz, 122.88 MHz, etc. This disclosure does not limit this.

[0063] In some embodiments, the global clock frequency of the first chip and the global clock frequency of the second chip may be the same or different. In some embodiments, the global clock frequency of the first chip and the global clock frequency of the second chip may be multiples of each other. This disclosure does not limit this.

[0064] Step 103, adjusting the second clock signal according to the clock synchronization signal, the first clock cycle and the second clock cycle, so as to synchronize the clocks of the first chip and the second chip.

[0065] The first clock cycle is the product of a first reference clock cycle corresponding to the first chip and a target frequency division number, and the second clock cycle is a second reference clock cycle corresponding to the second chip.

[0066] The first reference clock period is a clock period corresponding to the first reference clock frequency.

[0067] The second reference clock period is a clock period corresponding to the second reference clock frequency.

[0068] In some embodiments, the first clock cycle may also be understood as a clock cycle of a clock synchronization signal corresponding to the first clock signal when there is no error in the first clock signal.

[0069] In some embodiments, a ratio between a first clock period and a second clock period may be determined as a first number, and then the second clock signal may be adjusted based on the clock synchronization signal and the first number.

[0070] The first number may represent the relationship between a clock period corresponding to the clock synchronization signal and a clock period corresponding to the second clock signal when there is no error between the first clock signal and the second clock signal.

[0071] In some embodiments, the first quantity may be sent to the second chip after being determined by the first chip; or, it may be sent to the second chip after being determined by the second chip; or, it may be sent to the second chip after being determined by other chips or processors in the electronic device. This disclosure is not limited to this.

[0072] For example, the first reference clock frequency corresponding to the first chip and the second reference clock frequency corresponding to the second chip can both be 245.76 MHz, and the corresponding first reference clock period and second reference clock period can both be 4.07×10-8 seconds. If the target division number is 65536, the reference clock frequency corresponding to the clock synchronization signal can be 3.75 kHz (KHz), the first clock period can be 2.67×10-4 seconds, and the first number is 65536.

[0073] Figure 2 FIG. 1 is a schematic diagram of a clock synchronization signal and a second clock signal according to an embodiment of the present disclosure. Figure 2 As shown, when there is no error in the first clock signal and the second clock signal, each clock cycle of the clock synchronization signal corresponds to a first number of clock cycles in the second clock signal. In some embodiments, the clock cycle corresponding to the clock synchronization signal can also be defined as a synchronization cycle.

[0074] It should be noted that if there is an error between the first clock signal and the second clock signal, each synchronization cycle of the clock synchronization signal may correspond to a second number of cycles in the second clock signal, thereby causing the global clocks of the first chip and the second chip to be out of sync.

[0075] Therefore, within each synchronization cycle, the second clock signal can be adjusted based on the clock synchronization signal and the first number, so that the second clock signal has the first number of high levels in each synchronization cycle, thereby achieving synchronization between the second clock signal and the clock synchronization signal, thereby improving the synchronization accuracy and reliability between the first chip and the second chip.

[0076] In the disclosed embodiment, a clock synchronization signal is received, wherein the clock synchronization signal is generated by dividing the first clock signal currently corresponding to the first chip based on the target frequency division number; a second clock signal currently corresponding to the second chip is obtained; and the second clock signal is adjusted according to the clock synchronization signal, the first clock cycle corresponding to the clock synchronization signal, and the second clock cycle corresponding to the second chip, so as to synchronize the clocks of the first chip and the second chip. Thus, based on the first clock signal, a clock synchronization signal is generated, and then based on the clock synchronization signal, the second clock signal corresponding to the second chip is synchronized with the first clock signal corresponding to the first chip, which not only realizes the synchronization of the global clock between the first chip and the second chip, but also improves the accuracy of clock synchronization.

[0077] Figure 3 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the clock synchronization method may include the following steps:

[0078] Step 301: Receive a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to a first chip based on a target frequency division number.

[0079] Step 302: Acquire a second clock signal currently corresponding to the second chip.

[0080] The specific implementation forms of step 301 and step 302 can refer to the detailed descriptions in other embodiments of the present disclosure, and will not be described in detail here.

[0081] Step 303, when the i-th clock cycle of the clock synchronization signal has not ended and the first number of clock cycles of the second clock signal from the first moment have ended, extend the low level of the last clock cycle in the first number of clock cycles to the second moment.

[0082] The first moment is the start moment of the i-th clock cycle in the clock synchronization signal, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

[0083] Figure 4 A schematic diagram of an adjusted second clock signal provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, when the ith clock cycle of the clock synchronization signal has not ended, the first number of clock cycles have ended at the start time of the ith clock cycle in the second clock signal, so the low level of the last clock cycle in the first number of clock cycles is extended to the start time of the i+1th clock cycle in the second clock signal. This ensures that there are only the first number of high levels in the ith clock cycle, and further enables the global counter in the second chip to be synchronized with the global counter in the first chip in the ith clock cycle, ensuring the clock synchronization of the first chip and the second chip.

[0084] Step 304, when the i-th clock cycle of the clock synchronization signal has ended and the first number of clock cycles of the second clock signal from the first moment has not ended, shorten the low level of the last clock cycle in the first number of clock cycles to the second moment.

[0085] The first moment is the start moment of the i-th clock cycle in the clock synchronization signal, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

[0086] In some embodiments, before executing step 304, it is necessary to ensure that the difference between a first duration corresponding to a first number of clock cycles in the second clock signal and a clock cycle corresponding to the clock synchronization signal is less than a duration threshold, wherein the duration threshold is half of the clock cycle of the second clock signal, thereby avoiding that, within the i-th clock cycle of the synchronization clock signal, the high level of the second clock signal is less than the first number, thereby simplifying the complexity of clock synchronization and improving the accuracy of clock synchronization.

[0087] Figure 5 A schematic diagram of an adjusted second clock signal provided by an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, at the end of the i-th clock cycle of the clock synchronization signal, from the starting time of the i-th clock cycle in the second clock signal, the first number of clock cycles have not ended, and the low level of the last clock cycle in the first number of clock cycles is shortened to the starting time of the i-th clock cycle in the second clock signal, thereby ensuring that there are only the first number of high levels in the i-th clock cycle, and then the global counter in the second chip is synchronized with the global counter in the first chip in the i-th clock cycle, ensuring the clock synchronization of the first chip and the second chip.

[0088] In the disclosed embodiment, a clock synchronization signal is received, wherein the clock synchronization signal is generated by dividing the first clock signal currently corresponding to the first chip based on the target frequency division number, and the second clock signal currently corresponding to the second chip is obtained, and then when the i-th clock cycle of the clock synchronization signal has not ended and the first number of clock cycles of the second clock signal from the first moment have ended, the low level of the last clock cycle in the first number of clock cycles is extended to the second moment, or when the i-th clock cycle of the clock synchronization signal has ended and the first number of clock cycles of the second clock signal from the first moment have not ended, the low level of the last clock cycle in the first number of clock cycles is shortened to the second moment. Thus, it can be ensured that the second clock signal has a first number of high levels in the i-th clock cycle of the clock synchronization signal, and the low level of the last clock cycle in the i-th clock cycle is controlled to achieve clock synchronization between the first chip and the second chip, thereby not only improving the accuracy of clock synchronization, but also making clock synchronization simpler.

[0089] In some embodiments, the first reference clock cycle is greater than the second reference clock cycle. Thus, the duration of synchronizing the third number of clock cycles in the first clock signal each time is greater than the duration of synchronizing the third number of clock cycles in the second clock signal each time. In the disclosed embodiment, the second clock signal corresponding to the second chip is adjusted based on the clock synchronization signal corresponding to the first chip, which can further improve the synchronization accuracy.

[0090] In some embodiments, when the reference clock period corresponding to the baseband integrated circuit BBIC chip is greater than the reference clock period corresponding to the radio frequency integrated circuit RFIC chip, the BBIC chip is the first chip and the RFIC chip is the second chip; or,

[0091] In some embodiments, when a reference clock period corresponding to the BBIC chip is smaller than a reference clock period corresponding to the RFIC chip, the RFIC chip is the first chip and the BBIC chip is the second chip.

[0092] Figure 6 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the clock synchronization method may include the following steps:

[0093] Step 601, obtaining a first clock signal currently corresponding to a first chip.

[0094] The first chip may be an RFIC chip in an electronic device, or a BBIC chip or other chip that requires clock synchronization.

[0095] The first clock signal may be a global clock signal corresponding to the first chip obtained after the first chip processes the clock signal generated by the crystal oscillator of the electronic device.

[0096] In some embodiments, the first chip may process the clock signal generated by the crystal oscillator through a phase locked loop (PLL) to change the frequency, phase, etc. of the clock signal. This disclosure is not limited to this.

[0097] It should be noted that due to factors such as the first chip process, a phase locked loop (PLL), and temperature, there may be an error between the clock frequency corresponding to the first clock signal and the first reference clock frequency corresponding to the first chip.

[0098] The first reference clock frequency may be a global clock frequency of the first chip set by a user.

[0099] In some embodiments, the first reference clock frequency corresponding to the first clock signal may be a multiple of the clock frequency of the crystal oscillator.

[0100] In some embodiments, the target frequency division number may be 65536, that is, 2 to the 16th power; or 32768, that is, 2 to the 15th power, etc. This disclosure does not limit this.

[0101] Step 602: Divide the first clock signal based on the target frequency division number to obtain a clock synchronization signal.

[0102] In some embodiments, the target frequency division number may be 65536, that is, 2 to the 16th power; or 32768, that is, 2 to the 15th power, etc. This disclosure does not limit this.

[0103] In some embodiments, the first clock signal may be divided based on a frequency divider.

[0104] In some embodiments, a target bit position is determined based on a target frequency division number, and then a clock synchronization signal is generated according to a change in the target bit position of a counter in the first chip.

[0105] The change of the target bit of the counter (uni-counter) is caused by the first clock signal.

[0106] In some embodiments, 2 to the power of N is the target frequency division number, and N is the target bit number.

[0107] The counter is used to count and manage the pulses in the first clock signal. In the disclosed embodiment, the clock synchronization signal is directly generated based on the change of the target bit in the counter, which can realize the frequency division of the first clock signal more conveniently and quickly.

[0108] Step 603: Send a clock synchronization signal.

[0109] In some embodiments, the clock synchronization signal may be sent based on a synchronization pin (SYNC PAD) of the first chip.

[0110] In the disclosed embodiment, the first clock signal currently corresponding to the first chip is obtained, the first clock signal is divided based on the target frequency division number to obtain a clock synchronization signal, and the clock synchronization signal is sent. Thus, the first chip divides the first clock signal and sends the clock synchronization signal obtained after the frequency division to the second terminal, so that the second terminal can adjust the second clock signal based on the clock synchronization signal to achieve clock synchronization between the first chip and the second chip.

[0111] Figure 7 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the clock synchronization method may include the following steps:

[0112] Step 701, obtaining a first clock signal currently corresponding to a first chip.

[0113] Step 702, determining an initial frequency division number.

[0114] The initial frequency division number may be a power of 2.

[0115] Step 703: divide the first clock signal based on the initial frequency division number to obtain an initial clock synchronization signal.

[0116] The specific implementation method of step 703 is the same as that of step 602, and will not be described in detail here.

[0117] Step 704, when the clock period corresponding to the initial clock synchronization signal does not meet the preset condition, reduce the initial frequency division number, and return to execute the operation of obtaining the initial clock synchronization signal until the clock period corresponding to the initial clock synchronization signal meets the preset condition.

[0118] In some embodiments, the preset condition includes at least one of the following:

[0119] The difference between a second duration corresponding to a second number of clock cycles in the second clock signal and a clock cycle corresponding to the initial clock synchronization signal is less than a duration threshold;

[0120] The clock period corresponding to the initial clock synchronization signal is greater than the second time duration.

[0121] The second number is the ratio of the sixth clock cycle to the second clock cycle. The sixth clock cycle is the product of the first reference clock cycle corresponding to the first chip and the initial frequency division number corresponding to the initial clock synchronization signal. The second clock cycle is the second reference clock cycle corresponding to the second chip. The second clock signal is the clock signal currently corresponding to the second chip. The duration threshold is half of the clock cycle of the second clock signal.

[0122] Step 705: determine the initial frequency division number corresponding to the initial clock synchronization signal that meets the preset conditions as the target frequency division number.

[0123] In some embodiments, when the clock cycle corresponding to the initial clock synchronization signal is greater than the second time length corresponding to the second number of clock cycles in the second clock signal, the reduction of the initial frequency division number is stopped, and the current initial frequency division number is determined as the target frequency division number; or, when the difference between the second time length corresponding to the second number of clock cycles in the second clock signal and the clock cycle corresponding to the initial clock synchronization signal is less than a time length threshold, the difference between the second time length corresponding to the second number of clock cycles in the second clock signal and the clock cycle corresponding to the initial clock synchronization signal is less than the time length threshold, and the current initial frequency division number is determined as the target frequency division number.

[0124] Step 706: divide the first clock signal based on the target frequency division number to obtain a clock synchronization signal.

[0125] Step 707: Send a clock synchronization signal.

[0126] The specific implementation forms of step 706 and step 707 can refer to the detailed descriptions in other embodiments of the present disclosure, and will not be described in detail here.

[0127] In the disclosed embodiment, the initial frequency division number is first determined, and based on the initial frequency division number, the first clock signal is divided to obtain the initial clock synchronization signal. When the clock cycle corresponding to the initial clock synchronization signal does not meet the preset conditions, the initial frequency division number is reduced, and the operation of obtaining the initial clock synchronization signal is returned until the clock cycle corresponding to the initial clock synchronization signal meets the preset conditions. The initial frequency division number corresponding to the initial clock synchronization signal that meets the preset conditions is determined as the target frequency division number, and finally based on the target frequency division number, the first clock signal is divided to obtain the clock synchronization signal, and the clock synchronization signal is sent. Thus, the frequency division number can be continuously adjusted according to the relationship between the clock cycle corresponding to the initial clock synchronization signal and the clock cycle corresponding to the second clock signal, so that the clock cycle corresponding to the clock synchronization signal corresponding to the target frequency division number finally meets the preset conditions, and then the second chip only needs to adjust the duration of the low level in the second clock signal to achieve clock synchronization between the first chip and the second chip, thereby reducing the complexity of clock synchronization.

[0128] In some embodiments, after the global clocks of the first chip and the second chip are synchronized, the first chip only needs to send the value corresponding to the timing time in the counter to the second chip in advance through the communication interface between the first chip and the second chip, so that the first chip and the second chip can control the RF link at the timing time.

[0129] Figure 8 A flowchart of a clock synchronization method provided by an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the clock synchronization method may include: the clock chip sends the clock signal generated by the crystal oscillator to the first chip and the second chip respectively, the PLL in the first chip processes the input clock signal to obtain the first clock signal; the counter in the first chip counts the first signal and generates a clock synchronization signal according to the change of the target bit, and the first chip sends the generated clock synchronization signal to the second chip; the PLL in the second chip processes the input clock signal to obtain the second clock signal, the processing module of the second chip adjusts the second clock signal based on the first number and the first clock signal, and the counter in the second chip counts the adjusted second clock signal.

[0130] In order to implement the above embodiment, the present disclosure also proposes a clock synchronization device.

[0131] Fig. 9 A schematic diagram of the structure of a clock synchronization device provided in an embodiment of the present disclosure.

[0132] like Fig. 9 As shown, the clock synchronization device 900 may include:

[0133] A receiving module 901 is used to receive a clock synchronization signal, wherein the clock synchronization signal is generated by dividing the first clock signal currently corresponding to the first chip based on a target frequency division number;

[0134] An acquisition module 902 is used to acquire a second clock signal currently corresponding to the second chip;

[0135] The adjustment module 903 is used to adjust the second clock signal according to the clock synchronization signal, the first clock cycle and the second clock cycle to synchronize the clocks of the first chip and the second chip, wherein the first clock cycle is the product of the first reference clock cycle corresponding to the first chip and the target division number, and the second clock cycle is the second reference clock cycle corresponding to the second chip.

[0136] In some embodiments, the adjustment module 903 is used to:

[0137] determining a ratio between the first clock cycle and the second clock cycle as a first quantity;

[0138] The second clock signal is adjusted according to the clock synchronization signal and the first quantity.

[0139] In some embodiments, the adjustment module 903 is used to:

[0140] When the i-th clock cycle of the clock synchronization signal has not ended and the first number of clock cycles of the second clock signal from the first moment have ended, extending the low level of the last clock cycle of the first number of clock cycles to the second moment;

[0141] The first moment is the start moment of the i-th clock cycle, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

[0142] In some embodiments, a difference between a first duration corresponding to a first number of clock cycles in the second clock signal and a clock cycle corresponding to the clock synchronization signal is less than a duration threshold, wherein the duration threshold is half of the clock cycle of the second clock signal.

[0143] In some embodiments, the adjustment module 903 is used to:

[0144] When the i-th clock cycle of the clock synchronization signal has ended and the first number of clock cycles of the second clock signal from the first moment has not ended, shortening the low level of the last clock cycle of the first number of clock cycles to the second moment;

[0145] The first moment is the start moment of the i-th clock cycle, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

[0146] In some embodiments, the first reference clock period is greater than the second reference clock period.

[0147] The functions and specific implementation principles of the above modules in the embodiments of the present disclosure can be referred to the above method embodiments, and will not be repeated here.

[0148] The clock synchronization device of the disclosed embodiment receives a clock synchronization signal, wherein the clock synchronization signal is generated by dividing the first clock signal currently corresponding to the first chip based on the target frequency division number; obtains the second clock signal currently corresponding to the second chip; and adjusts the second clock signal according to the clock synchronization signal, the first clock cycle corresponding to the clock synchronization signal, and the second clock cycle corresponding to the second chip, so as to synchronize the clocks of the first chip and the second chip. Thus, based on the first clock signal, a clock synchronization signal is generated, and then based on the clock synchronization signal, the second clock signal corresponding to the second chip is synchronized with the first clock signal corresponding to the first chip, which not only realizes the synchronization of the global clock between the first chip and the second chip, but also improves the accuracy of clock synchronization.

[0149] Fig.10 Schematic diagram of the structure of the clock synchronization device provided by the embodiment of the present disclosure. Fig.10 As shown, the clock synchronization device 1000 may include:

[0150] An acquisition module 1001 is used to acquire a first clock signal currently corresponding to a first chip;

[0151] A frequency division module 1002, configured to divide the first clock signal based on a target frequency division number to obtain a clock synchronization signal;

[0152] The sending module 1003 is used to send a clock synchronization signal.

[0153] In some embodiments, the system further includes a determining module for:

[0154] Determine the initial frequency division number;

[0155] Based on the initial frequency division number, the first clock signal is divided to obtain an initial clock synchronization signal;

[0156] When the clock cycle corresponding to the initial clock synchronization signal does not meet the preset condition, the initial frequency division number is reduced, and the operation of obtaining the initial clock synchronization signal is returned to be executed until the clock cycle corresponding to the initial clock synchronization signal meets the preset condition;

[0157] An initial frequency division number corresponding to an initial clock synchronization signal that meets a preset condition is determined as a target frequency division number.

[0158] In some embodiments, the preset condition includes at least one of the following:

[0159] The difference between a second duration corresponding to a second number of clock cycles in the second clock signal and a clock cycle corresponding to the initial clock synchronization signal is less than a duration threshold;

[0160] The clock period corresponding to the initial clock synchronization signal is greater than the second time length;

[0161] Among them, the second number is the ratio of the sixth clock cycle to the second clock cycle, the sixth clock cycle is the product of the first reference clock cycle corresponding to the first chip and the initial division number corresponding to the initial clock synchronization signal, the second clock cycle is the second reference clock cycle corresponding to the second chip, the second clock signal is the clock signal currently corresponding to the second chip, and the duration threshold is half of the clock cycle of the second clock signal.

[0162] In some embodiments, the frequency division module 1002 is used to:

[0163] Based on the target frequency division number, determine the target bit position;

[0164] A clock synchronization signal is generated according to a change in a target bit position of a counter in the first chip, wherein the change in the target bit position of the counter is caused by a first clock signal.

[0165] The functions and specific implementation principles of the above modules in the embodiments of the present disclosure can be referred to the above method embodiments, and will not be repeated here.

[0166] The clock synchronization device of the embodiment of the present disclosure obtains the first clock signal currently corresponding to the first chip, divides the first clock signal based on the target frequency division number, obtains the clock synchronization signal, and sends the clock synchronization signal. Thus, the first chip divides the first clock signal and sends the clock synchronization signal obtained after the frequency division to the second terminal, so that the second terminal can adjust the second clock signal based on the clock synchronization signal, thereby realizing clock synchronization between the first chip and the second chip.

[0167] In order to implement the above embodiments, the present disclosure further proposes a first chip, the chip comprising a processing circuit, and the processing circuit is configured to execute the clock synchronization method provided in the above embodiments.

[0168] Fig.11 is a schematic diagram of the structure of the first chip proposed in the embodiment of the present disclosure. Fig.11 The structure of the first chip 1100 is shown, but is not limited thereto.

[0169] In some embodiments, the first chip 1100 includes a processing circuit 1101 , and the processing circuit 1101 is configured to execute any of the above methods.

[0170] In some embodiments, the first chip 1100 further includes one or more interface circuits 1102. Optionally, the interface circuit 1102 may perform at least one of the communication steps of sending and / or receiving in the above method, such as performing step 603.

[0171] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0172] In order to implement the above embodiments, the present disclosure further proposes a second chip, which includes a processing circuit, and the processing circuit is configured to execute the clock synchronization method provided in the above embodiments.

[0173] Fig.12 is a schematic diagram of the structure of the second chip proposed in the embodiment of the present disclosure. Fig.12 The structure of the second chip 1200 is shown, but is not limited thereto.

[0174] In some embodiments, the second chip 1200 includes a processing circuit 1201 , and the processing circuit 1201 is configured to execute any of the above methods.

[0175] In some embodiments, the second chip 1200 further includes one or more interface circuits 1202. Optionally, the interface circuit 1202 may perform at least one of the communication steps of sending and / or receiving in the above method, such as performing step 101.

[0176] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0177] In order to implement the above embodiment, the present disclosure further provides an electronic device, including: a first chip and a second chip.

[0178] The first chip is used to execute the above Figure 6 or Figure 7 The clock synchronization method shown in the figure, the second chip is used to execute the aforementioned Figure 1 or Figure 3 The clock synchronization method shown.

[0179] Fig.13 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Fig.13 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0180] like Fig.13 As shown, the electronic device 1300 includes: a first chip 1301 and a second chip 1302 .

[0181] The first chip is used to execute the above Figure 6 or Figure 7 The clock synchronization method shown in the figure, the second chip is used to execute the aforementioned Figure 1 or Figure 3 The clock synchronization method shown.

[0182] In order to implement the above embodiments, the present disclosure further proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the clock synchronization method proposed in the above embodiments of the present disclosure is implemented.

[0183] In order to implement the above embodiments, the present disclosure further proposes a computer program product, including a computer program, which implements the clock synchronization method proposed in the above embodiments of the present disclosure when the computer program is executed by a processor.

[0184] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this disclosure shall comply with the relevant laws and regulations and shall not violate public order and good morals.

[0185] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0186] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0187] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0188] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0189] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0190] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0191] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0192] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0193] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A clock synchronization method, characterized in that: The method comprises: Receiving a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to the first chip based on a target frequency division number; Obtaining a second clock signal currently corresponding to the second chip; According to the clock synchronization signal, the first clock cycle and the second clock cycle, the second clock signal is adjusted to synchronize the clocks of the first chip and the second chip, wherein the first clock cycle is the product of a first reference clock cycle corresponding to the first chip and the target division number, and the second clock cycle is a second reference clock cycle corresponding to the second chip.

2. The method according to claim 1, characterized in that The adjusting the second clock signal according to the clock synchronization signal, the first clock cycle and the second clock cycle includes: determining a ratio between the first clock period and the second clock period as a first quantity; The second clock signal is adjusted according to the clock synchronization signal and the first number.

3. The method according to claim 2, characterized in that The adjusting the second clock signal according to the clock synchronization signal and the first quantity includes: When the i-th clock cycle of the clock synchronization signal has not ended and a first number of clock cycles of the second clock signal from the first moment have ended, extending the low level of the last clock cycle of the first number of clock cycles to the second moment; The first moment is the start moment of the i-th clock cycle, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

4. The method according to claim 2, characterized in that: A difference between a first duration corresponding to a first number of clock cycles in the second clock signal and a clock cycle corresponding to the clock synchronization signal is less than a duration threshold, wherein the duration threshold is half of the clock cycle of the second clock signal.

5. The method according to claim 4, characterized in that The adjusting the second clock signal according to the clock synchronization signal and the first quantity includes: When the i-th clock cycle of the clock synchronization signal has ended and the first number of clock cycles of the second clock signal from the first moment has not ended, shortening the low level of the last clock cycle of the first number of clock cycles to the second moment; The first moment is the start moment of the i-th clock cycle, and the second moment is the start moment of the i+1-th clock cycle in the clock synchronization signal.

6. The method according to claim 1, characterized in that The first reference clock period is greater than the second reference clock period.

7. A clock synchronization method, characterized in that: The method comprises: Acquire a first clock signal currently corresponding to the first chip; Based on the target frequency division number, the first clock signal is frequency-divided to obtain a clock synchronization signal; The clock synchronization signal is sent.

8. The method according to claim 7, characterized in that Before dividing the first clock signal based on the target frequency division number to obtain the clock synchronization signal, the method further includes: Determine the initial frequency division number; Based on the initial frequency division number, the first clock signal is frequency-divided to obtain an initial clock synchronization signal; When the clock cycle corresponding to the initial clock synchronization signal does not meet the preset condition, the initial frequency division number is reduced, and the operation of obtaining the initial clock synchronization signal is returned to be executed until the clock cycle corresponding to the initial clock synchronization signal meets the preset condition; An initial frequency division number corresponding to an initial clock synchronization signal that meets a preset condition is determined as the target frequency division number.

9. The method according to claim 8, characterized in that The preset condition includes at least one of the following: A difference between a second duration corresponding to a second number of clock cycles in the second clock signal and a clock cycle corresponding to the initial clock synchronization signal is less than a duration threshold; The clock period corresponding to the initial clock synchronization signal is greater than the second duration; Among them, the second number is the ratio of the sixth clock cycle to the second clock cycle, the sixth clock cycle is the product of the first reference clock cycle corresponding to the first chip and the initial division number corresponding to the initial clock synchronization signal, the second clock cycle is the second reference clock cycle corresponding to the second chip, the second clock signal is the clock signal currently corresponding to the second chip, and the duration threshold is half of the clock cycle of the second clock signal.

10. The method according to claim 7, characterized in that The step of dividing the first clock signal based on the target frequency division number to obtain a clock synchronization signal includes: Based on the target frequency division number, determining a target bit position; The clock synchronization signal is generated according to a change in a target bit position of a counter in the first chip, wherein the change in the target bit position of the counter is caused by the first clock signal.

11. A clock synchronization device, characterized in that: The device comprises: A receiving module, configured to receive a clock synchronization signal, wherein the clock synchronization signal is generated by dividing a first clock signal currently corresponding to the first chip based on a target frequency division number; An acquisition module, used for acquiring a second clock signal currently corresponding to the second chip; An adjustment module is used to adjust the second clock signal according to the clock synchronization signal, the first clock cycle and the second clock cycle to synchronize the clocks of the first chip and the second chip, wherein the first clock cycle is the product of a first reference clock cycle corresponding to the first chip and the target division number, and the second clock cycle is a second reference clock cycle corresponding to the second chip.

12. A clock synchronization device, characterized in that: The device comprises: An acquisition module, used to acquire a first clock signal currently corresponding to the first chip; A frequency division module, used to divide the first clock signal based on a target frequency division number to obtain a clock synchronization signal; A sending module is used to send the clock synchronization signal.

13. A second chip, characterized in that: The method comprises a processing circuit configured to execute the clock synchronization method according to any one of claims 1 to 6.

14. A first chip, characterized in that: The method comprises a processing circuit configured to execute the clock synchronization method as claimed in any one of claims 7 to 10.

15. An electronic device, characterized in that: It comprises a first chip and a second chip, wherein the second chip is used to execute the clock synchronization method as described in any one of claims 1-6, and the first chip is used to execute the clock synchronization method as described in any one of claims 7-10.

16. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the clock synchronization method as described in any one of claims 1 to 6 is implemented, or the clock synchronization method as described in any one of claims 7 to 10 is implemented.

17. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the clock synchronization method as described in any one of claims 1 to 6, or implements the clock synchronization method as described in any one of claims 7 to 10.

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