Three-dimensional stacked access memory structure and integration method thereof

Abstract

The invention provides a three-dimensional stacked access memory structure and an integration method thereof, and belongs to the technical field of semiconductors. The memory is formed by stacking a plurality of unit structures from bottom to top, each unit structure comprises a ring gate low-power-consumption bidirectional conduction device serving as a write-in tube of the memory and a storage capacitor, the source end of the write-in tube serves as a bottom electrode of the storage capacitor at the same time, and connection of the write-in tube and the storage capacitor in the horizontal direction is achieved; the grid ends of the write-in tubes of the unit structures in the same row are connected together through a grid conducting layer to form a word line, the drain ends of the write-in tubes of the unit structures in the same column are connected together through contact metal to form a bit line, and the top electrodes of the storage capacitors in the same row are connected together through interconnection metal to form a plate line; the memory is long in retention time, high in reading speed, low in power consumption, and high in stacking and storage density of multiple layers of memory units; in the integration method, the repetitive unit structures share the process steps of photoetching, etching, ion implantation, annealing and the like, so that the process cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional stacked access memory structure and an integration method thereof. Background Art

[0002] With the development of artificial intelligence and Internet of Things technologies, the demand for high-speed, high-density, and low-power memory has increased dramatically. Existing memories need to compromise between operating speed, storage density, and operating power consumption, and cannot have the advantages of all three at the same time. Therefore, it is necessary to invent a new type of high-speed, high-density, and low-power memory. Summary of the invention

[0003] The purpose of the present invention is to design a three-dimensional stacked access memory structure and its integration method, wherein the memory structure includes a ring-gate low-power bidirectional conductive device as a write tube of the memory and a storage capacitor, thereby achieving high-speed reading and writing while extending the memory retention time and reducing the power consumption of the memory.

[0004] The technical solution of the present invention is as follows:

[0005] A three-dimensional stacked access memory structure is composed of multiple unit structures stacked from bottom to top. Each unit structure includes a write tube and a storage capacitor. The source end of the write tube also serves as the bottom electrode of the storage capacitor to realize the connection between the write tube and the storage capacitor in the horizontal direction. The gate ends of the write tubes of the unit structure in the same row are connected together through a gate conductive layer to form a word line WL, the drain ends of the write tubes of the unit structure in the same column are connected together through a contact metal to form a bit line BL, and the top electrodes of the storage capacitors in the same row are connected together through an interconnection metal to form a plate line PL. The write tube is a low-power bidirectional conductive device with a ring gate structure. The specific characteristics are that the two sides of the channel of the write tube are its source end and drain end respectively, the gate end is in a direction perpendicular to the channel and surrounds the four sides of the channel, the source end is close to the gate end in the horizontal direction, and the drain end is separated from the gate end in the horizontal direction. The write tube channel is composed of a write channel layer, and the gate end is composed of a gate dielectric layer and a gate conductive layer. The drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the semiconductor parts of the source end and the drain end are opposite. The storage capacitor is composed of a bottom electrode, a storage medium and a top electrode. The bottom electrode is composed of a contact metal at the source end of the write tube. The storage medium layer surrounds and wraps the bottom electrode. The top electrode surrounds and wraps the storage medium layer.

[0006] The present invention also provides a method for integrating the above three-dimensional stacked access memory structure, the specific steps comprising:

[0007] Step 1: depositing multiple layers of sacrificial layer material and write channel layer material on a substrate, wherein the specific method is to deposit a layer of sacrificial layer material, then deposit a layer of write channel layer material, and then repeatedly deposit sacrificial layer material and write channel layer material, and the last deposited material is the sacrificial layer material, and the number of layers of the write channel layer is the number of repetitions of the unit structure in the above memory structure;

[0008] Step 2: define the active area, the specific method is to pattern the active area by photolithography, and then etch the sacrificial layer material outside the active area and the write channel layer material to form the active area;

[0009] Step 3: forming active area isolation, the specific method is to deposit isolation layer material, then pattern the memory array area by photolithography, then etch the excess isolation layer material outside the memory array, and then planarize it by chemical mechanical polishing (CMP);

[0010] Step 4: forming a sidewall isolation, the specific method is to pattern the sidewall area by photolithography, then etch the sacrificial layer material and the isolation layer material in the sidewall area, then deposit the sidewall layer material, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess sidewall layer material outside the storage array;

[0011] Step 5: forming a write-in tube gate terminal, specifically, patterning the area between the write-in tube gate and the gate by photolithography, then etching the isolation layer between the write-in tube gates, then depositing the sidewall layer material, then planarizing by CMP, then patterning the area between the write-in tube gates by photolithography, then etching the redundant sidewall layer material between the write-in tube gates, then preparing the gate stack by a standard polySi-SiO2 process or HKMG process, and then removing the photoresist and redundant materials;

[0012] Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by photolithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by photolithography, then etching the sacrificial layer material in the source region of the write tube, and then forming an N-type semiconductor layer by ion implantation;

[0013] Step 7: forming source-drain contacts, specifically, patterning the source and drain of the write tube by photolithography, then etching the isolation layer material in the region between the write tube sources and the region between the write tube drains, then depositing the sidewall layer material, then flattening by CMP, then patterning the source and drain of the write tube by photolithography, then etching the redundant sidewall layer material in the region between the write tube sources and the region between the drains, then depositing the pre-contact metal, then using annealing to allow the pre-contact metal to react with the semiconductor to generate metal silicide as the contact metal, then removing the unreacted pre-contact metal, and then using annealing to activate the impurities;

[0014] Step 8: forming a storage capacitor region, the specific method is to pattern the region outside the storage capacitor by photolithography, and then deposit a storage dielectric layer and a top metal electrode layer;

[0015] Step 9: cutting off the storage capacitor interconnection area, the specific method is to pattern the storage capacitor area by photolithography, and then etch the storage dielectric layer and the top metal electrode layer;

[0016] Step 10: forming a board line interconnection line, the specific method is to deposit a sidewall layer material, define the area outside the board line interconnection line by photolithography, then etch the sidewall layer material at the board line interconnection line, then deposit an interconnection metal layer, and then remove excess photoresist and metal;

[0017] Step 11: forming a bit line contact, the specific method is to photolithography the area outside the bit line, then etch the sacrificial layer material at the bit line, then deposit the pre-contact metal, then use annealing to allow the pre-contact metal to react with the semiconductor, then remove the unreacted pre-contact metal, and then anneal, the metal silicide formed in the bit line area can serve as the bit line contact.

[0018] Specifically, the substrate in step 1 can be a bare silicon wafer or a silicon wafer on which front-end devices and circuits have been prepared. The sacrificial layer material can be a dielectric material such as fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, etc., whose dielectric constant is not greater than that of silicon dioxide, or a semiconductor material such as germanium silicon. The thickness of the deposited single-layer sacrificial layer material is between 10nm and 500nm, and the method of depositing the sacrificial layer material can be PVD, CVD, epitaxy, etc. The write channel layer material can be a semiconductor material such as amorphous silicon or single crystal silicon, and the thickness of the deposited single-layer write channel layer material is between 10nm and 500nm, and the method of depositing the write channel layer material can be PVD, CVD, epitaxy, etc.

[0019] The isolation material in step 3 may be a dielectric material such as silicon dioxide, and the method of depositing the isolation material may be PVD, CVD, ALD, etc. The thickness of the isolation layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material;

[0020] The sidewall material in step 4 may be a dielectric material such as silicon nitride, and the sidewall material may be deposited by PVD, CVD, ALD, etc. The thickness of the sidewall layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material;

[0021] The P-type impurities implanted in step 6 may be boron or boron fluoride, and the N-type impurities may be phosphorus or arsenic. The energy of the ion implantation is between 1keV and 100keV, and the dose of the ion implantation is between 1E13cm -2 To 1E17cm -2 The angle of ion implantation is between 0° and 90°;

[0022] In step 7 and step 11, the pre-contact metal material may be a metal such as titanium, nickel or cobalt, and the contact metal material may be a metal silicide material such as titanium silicon, nickel silicon or cobalt silicon. The pre-contact metal material may be deposited by PVD or the like, and the thickness of the pre-contact metal material is between 10 nm and 1000 nm;

[0023] The storage dielectric layer material in step 8 may be a high dielectric constant layer such as hafnium oxide, zirconium oxide, aluminum oxide and a stack thereof, or a resistive dielectric layer such as tantalum oxide, or a phase change material such as GeSbTe, or a ferroelectric dielectric layer such as hafnium oxide, hafnium lanthanum oxide, or hafnium silicon oxide, and the top metal electrode layer material may be a metal material such as titanium nitride, tantalum nitride, or tungsten;

[0024] The interconnection metal material in step 10 can be a metal material such as tungsten, copper, titanium nitride, tantalum nitride, etc., or a stacked material of several metals.

[0025] The specific technical effects of the three-dimensional stacked access memory structure and its integration method of the present invention are as follows:

[0026] 1. The write tube of the proposed memory structure is a low-power, gate-all-around bidirectional conduction device, which can simultaneously achieve the advantages of long retention time and low power consumption;

[0027] 2. The proposed memory structure is a three-dimensional structure, which can realize the stacking of multiple layers of memory cells in a limited area and increase the storage density;

[0028] 3. The proposed integration method enables multiple repetitive unit structures in the storage structure to share the process steps of lithography, etching, ion implantation, annealing, etc., which significantly reduces the process cost of storing information per bit in the storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Yes Description Figures 2 to 13 Schematic diagram of viewing angles;

[0030] Figure 2is a schematic diagram of the display effect obtained by using the memory structure and the integration method proposed by the present invention, showing a cross-sectional view along the channel direction, wherein Figure 2 (b) is a schematic diagram of a single storage unit structure. Figure 2 (a) is a memory structure diagram after multiple unit structures are stacked up and down;

[0031] Figure 3-Figure 13 This is a schematic diagram of the steps for preparing the memory structure proposed by the present invention by using the integration method proposed by the present invention, wherein:

[0032] Figure 3 is a front view of depositing multiple layers of sacrificial layer materials and writing channel layers;

[0033] Figure 4 It is the top view after defining the active area;

[0034] Figure 5 is a top view after forming an active area isolation layer;

[0035] Figure 6 It is a front view after forming the side wall isolation layer;

[0036] Figure 7 (a) is a cross-sectional view along the channel direction after the write gate end is formed. Figure 7 (b) is a top view after the write-in tube gate end is formed;

[0037] Figure 8 It is a cross-sectional view along the channel direction after the source and drain semiconductor layers are formed;

[0038] Fig. 9 It is a cross-sectional view along the channel direction after the source-drain contact is formed;

[0039] Fig.10 is a cross-sectional view along the channel direction after the storage capacitor region is formed;

[0040] Fig.11 is a cross-sectional view along the channel direction after the storage capacitor interconnection region is removed;

[0041] Fig.12 It is a cross-sectional view along the channel direction after the board line interconnection line is formed;

[0042] Fig.13 It is a cross-sectional view along the channel direction after the bit line contact is formed;

[0043] In the figure:

[0044] 1——Write channel layer 2——Sacrificial layer

[0045] 3——Isolation layer 4——Side wall layer

[0046] 5——Gate dielectric layer 6——Gate conductive layer

[0047] 7——P-type semiconductor layer 8——N-type semiconductor layer

[0048] 9——Contact metal 10——Storage medium layer

[0049] 11——Top metal electrode 12——Interconnect metal

[0050] 13——WL 14——BL

[0051] 15——PL DETAILED DESCRIPTION

[0052] The present invention is further described below by examples. It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0053] Figure 2 is a schematic diagram of one of the presentation effects obtained by using the memory structure and integration method proposed by the present invention, wherein Figure 2 (b) is a schematic diagram of a single storage unit structure. Figure 2 (a) is a diagram of the memory structure after multiple unit structures are stacked up and down. Figure 1 Yes Description Figures 2 to 13 Schematic diagram of viewing angles, with the directions of the three viewing angles along the channel direction, top view and front view marked. Figure 2 The memory structure shown in (a) consists of multiple Figure 2 The unit structure shown in (b) is stacked from bottom to top. Figure 2 (b), the write tube is located on the left and the storage capacitor is located on the right. Each unit structure consists of a write tube and a storage capacitor. The source end of the write tube also serves as the bottom electrode of the storage capacitor to achieve the connection between the write tube and the storage capacitor in the horizontal direction. In each unit structure, the write tube is a low-power bidirectional conductive device with a ring-gate structure. The specific features are as follows: the channel of the write tube is composed of a write tube channel layer 1 composed of lightly doped single crystal silicon, and the right and left sides of the write tube channel are its source and drain ends respectively. The gate end is composed of a stacked gate dielectric layer 5 composed of silicon dioxide and hafnium oxide and a gate conductive layer 6 composed of titanium nitride, with a length of 60nm. The gate end is in a direction perpendicular to the channel and surrounds the channel on all sides. Figure 2The cross-sectional view along the channel direction shows that the gate end is located on the upper and lower sides of the channel. The source end is composed of a contact metal 9 composed of metal silicide and an N-type semiconductor layer 8 composed of arsenic-doped single crystal silicon. The source end is located on the right side of the channel, and the source end is close to the gate end in the horizontal direction. The drain end is composed of a contact metal 9 composed of metal silicide and a P-type semiconductor layer 7 composed of boron fluoride-doped single crystal silicon. The drain end is located on the left side of the channel, and the drain end is 40nm away from the gate end in the horizontal direction. The storage capacitor is composed of a bottom electrode, a storage dielectric layer and a top electrode, and the specific features are as follows: the bottom electrode of the storage capacitor is composed of a contact metal 9 composed of a metal silicide at the source end of the write tube, the storage dielectric layer 10 wraps the contact metal 9 at the source end of the write tube, and the top metal electrode layer 11 wraps the storage dielectric layer 10.

[0054] Figure 2 The memory structure shown in (a) can be achieved by placing multiple Figure 2 (b) is obtained by stacking the unit structure shown in FIG. 1 up and down. The specific features are as follows: the gate ends of the write tubes of the unit structure in the same row are connected together through the gate conductive layer 6 to form a word line WL13, the drain ends of the write tubes of the unit structure in the same column are connected together through the contact metal 9 to form a bit line BL14, and the top electrodes 11 of the storage capacitors of the unit structure in the same row are connected together through the interconnection metal 12 to form a plate line PL15. In each unit structure, the source end of the write tube serves as the top electrode of the storage capacitor.

[0055] Figure 2 The memory shown can be prepared by the integration method proposed in this patent. The specific method is shown in FIG. Figures 3 to 13 , the steps are as follows:

[0056] First, a plurality of sacrificial layer materials composed of fluorine-doped silicon dioxide and a write channel layer material composed of amorphous silicon are deposited on the substrate, such as Figure 3 As shown, the specific method is to deposit a 200nm layer of fluorine-doped silicon dioxide by PVD, then deposit a 100nm layer of amorphous silicon, and then repeatedly deposit fluorine-doped silicon dioxide and amorphous silicon layers, a total of four layers of fluorine-doped silicon dioxide and three layers of amorphous silicon;

[0057] Next, define the active region, such as Figure 4 As shown, the specific method is to pattern the active area by photolithography, and then etch the fluorine-doped silicon dioxide and amorphous silicon outside the active area to form the active area;

[0058] Next, an active region isolation layer is formed, such as Figure 5 As shown, the specific method is to deposit an isolation layer material composed of 1300nm silicon dioxide, then pattern the storage array area by photolithography, then etch the excess silicon dioxide outside the storage array, and then planarize it by chemical mechanical polishing (CMP);

[0059] Next, a sidewall isolation layer is formed, such as Figure 6 As shown, the specific method is to pattern the sidewall area by photolithography, then etch the fluorine-doped silicon dioxide and silicon dioxide in the sidewall area, then deposit a sidewall layer material composed of 1300nm silicon nitride, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess silicon nitride outside the storage array;

[0060] Next, the gate end of the write tube is formed, such as Figure 7 As shown, the specific method is to pattern the area between the gate and the pipe by photolithography, then etch the silicon dioxide isolation layer between the gate and the pipe, then deposit the silicon nitride sidewall, then planarize it by CMP, then pattern the area between the gate and the pipe by photolithography, then etch the excess silicon nitride between the gate and the pipe, then use the standard HKMG process to prepare the gate dielectric layer and the gate conductive layer, then remove the photoresist and excess materials, and the gate conductive layer formed in this step connects the gate ends of multiple unit structures together to form WL.

[0061] Next, source and drain semiconductor layers are formed, such as Figure 8 As shown, the specific method is to pattern the drain area of ​​the write tube by photolithography, then etch the fluorine-doped silicon dioxide in the drain area, and then ion-implant boron fluoride at a condition of 5keV5E15cm -2 The injection angle is 10°, and then the source region of the write tube is patterned by photolithography, and then the fluorine-doped silicon dioxide in the source region of the write tube is etched, and then arsenic is ion-implanted. The injection conditions are 12keV5E15cm -2 , the injection angle is 10°;

[0062] Next, source and drain contacts are formed, such as Fig. 9 As shown, the specific method is to pattern the source and drain of the write tube by photolithography, then etch the silicon dioxide isolation layer in the area between the write tube sources and the silicon dioxide isolation layer in the area between the write tube drains, then deposit silicon nitride sidewalls, then flatten by CMP, then pattern the source and drain of the write tube by photolithography, then etch the excess silicon nitride material in the area between the write tube sources and the area between the drains, then deposit 90nm nickel, then anneal at 500℃ for 15min to generate nickel-silicon alloy, then remove unreacted nickel, then anneal at 600℃ for 30min to activate impurities and convert the amorphous silicon in the write tube area into single crystal silicon;

[0063] Next, the storage capacitor region is formed, such as Fig.10 As shown, the specific method is to pattern the area outside the storage capacitor by photolithography, then deposit 10nm of hafnium oxide as a storage dielectric layer, and then deposit 20nm of titanium nitride as a top metal electrode layer;

[0064] Next, the storage capacitor interconnection area is cut out, such as Fig.11 As shown, the specific method is to pattern the storage capacitor area by photolithography, and then etch the hafnium oxide and titanium nitride;

[0065] Next, board interconnects are formed, such as Fig.12 As shown, the specific method is to deposit 1300nm silicon nitride, use photolithography to define the area outside the board line interconnection line, then etch the silicon nitride at the board line interconnection line, then deposit 100nm tungsten as the interconnection metal layer, and then remove the excess photoresist and metal;

[0066] Next, the bit line contacts are formed, such as Fig.13 As shown, the specific method is to photolithography the area outside the bit line, then etch the fluorine-doped silicon dioxide at the bit line, then deposit 50nm nickel, then anneal at 550℃ for 12min, then remove the unreacted nickel, and then anneal at 550℃ for 30min again to form a contact metal composed of nickel-silicon alloy in the BL area, which can be used as a bit line contact.

[0067] Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A three-dimensional stacked access memory structure, characterized in that: It is composed of multiple unit structures stacked from bottom to top, each unit structure includes a write tube and a storage capacitor, the source end of the write tube is also used as the bottom electrode of the storage capacitor, so as to realize the connection between the write tube and the storage capacitor in the horizontal direction; the gate ends of the write tubes of the unit structures in the same row are connected together through the gate conductive layer to form a word line WL, the drain ends of the write tubes of the unit structures in the same column are connected together through the contact metal to form a bit line BL, and the top electrodes of the storage capacitors in the same row are connected together through the interconnection metal to form a plate line PL; The write tube is a low-power bidirectional conductive device with a ring-gate structure. The two sides of the channel of the write tube are its source end and drain end respectively. The gate end surrounds the channel in a direction perpendicular to the channel, the source end is close to the gate end in the horizontal direction, and the drain end is separated from the gate end by a distance in the horizontal direction. The write tube channel is composed of a write channel layer, the gate end is composed of a gate dielectric layer and a gate conductive layer, the drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the semiconductor parts of the source end and the drain end are opposite. The storage capacitor is composed of a bottom electrode, a storage medium and a top electrode. The bottom electrode is composed of a contact metal at the source end of the write tube. The storage medium layer surrounds and wraps the bottom electrode. The top electrode surrounds and wraps the storage medium layer.

2. A method for integrating a three-dimensional stacked access memory structure, characterized in that: The specific steps include: Step 1: depositing multiple layers of sacrificial layer material and write channel layer material on a substrate, wherein the specific method is to deposit a layer of sacrificial layer material, then deposit a layer of write channel layer material, and then repeatedly deposit sacrificial layer material and write channel layer material, and the last deposited material is the sacrificial layer material, and the number of layers of the write channel layer is the number of repetitions of the unit structure in the above memory structure; Step 2: define the active area, the specific method is to pattern the active area by photolithography, and then etch the sacrificial layer material outside the active area and the write channel layer material to form the active area; Step 3: forming active area isolation, the specific method is to deposit isolation layer material, then pattern the memory array area by photolithography, then etch the excess isolation layer material outside the memory array, and then planarize it by chemical mechanical polishing (CMP); Step 4: forming a sidewall isolation, the specific method is to pattern the sidewall area by photolithography, then etch the sacrificial layer material and the isolation layer material in the sidewall area, then deposit the sidewall layer material, then planarize it by CMP, then pattern the storage array area by photolithography, and then etch the excess sidewall layer material outside the storage array; Step 5: forming a write-in tube gate terminal, specifically, patterning the area between the write-in tube gate and the gate by photolithography, then etching the isolation layer between the write-in tube gates, then depositing the sidewall layer material, then planarizing by CMP, then patterning the area between the write-in tube gates by photolithography, then etching the redundant sidewall layer material between the write-in tube gates, then preparing the gate stack by a standard polySi-SiO2 process or HKMG process, and then removing the photoresist and redundant materials; Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by photolithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by photolithography, then etching the sacrificial layer material in the source region of the write tube, and then forming an N-type semiconductor layer by ion implantation; Step 7: forming source-drain contacts, specifically, patterning the source and drain of the write tube by photolithography, then etching the isolation layer material in the region between the write tube sources and the region between the write tube drains, then depositing the sidewall layer material, then flattening by CMP, then patterning the source and drain of the write tube by photolithography, then etching the redundant sidewall layer material in the region between the write tube sources and the region between the drains, then depositing the pre-contact metal, then using annealing to allow the pre-contact metal to react with the semiconductor to generate metal silicide as the contact metal, then removing the unreacted pre-contact metal, and then using annealing to activate the impurities; Step 8: forming a storage capacitor region, specifically by patterning the region outside the storage capacitor by photolithography, and then depositing a storage dielectric layer and a top metal electrode layer; Step 9: cutting off the storage capacitor interconnection area, the specific method is to pattern the storage capacitor area by photolithography, and then etch the storage dielectric layer and the top metal electrode layer; Step 10: forming a board line interconnection line, the specific method is to deposit a sidewall layer material, define the area outside the board line interconnection line by photolithography, then etch the sidewall layer material at the board line interconnection line, then deposit an interconnection metal layer, and then remove excess photoresist and metal; Step 11: forming a bit line contact, the specific method is to photolithography the area outside the bit line, then etch the sacrificial layer material at the bit line, then deposit the pre-contact metal, then use annealing to allow the pre-contact metal to react with the semiconductor, then remove the unreacted pre-contact metal, and then anneal, the metal silicide formed in the bit line area can serve as the bit line contact.

3. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: The substrate in step 1 is a bare silicon wafer, or a silicon wafer on which front-end devices and circuits have been prepared; the sacrificial layer material is a dielectric material with a dielectric constant not greater than that of silicon dioxide: fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a semiconductor material: germanium silicon; the thickness of the deposited single-layer sacrificial layer material is between 10nm and 500nm, and the method of depositing the sacrificial layer material is: PVD, CVD or epitaxy; the write channel layer material is amorphous silicon or single crystal silicon, the thickness of the deposited single-layer write channel layer material is between 10nm and 500nm, and the method of depositing the write channel layer material is PVD, CVD or epitaxy.

4. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: The isolation material in step 3 is a dielectric material silicon dioxide, and the isolation material is deposited by PVD, CVD or ALD. The thickness of the isolation layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material.

5. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: The sidewall material in step 4 is a dielectric material silicon nitride, and the sidewall material is deposited by PVD, CVD or ALD. The thickness of the sidewall layer material is greater than the total thickness of the multi-layer stacked sacrificial layer material and the write channel layer material.

6. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: In step 6, the P-type impurity ion implanted is boron or boron fluoride, the N-type impurity is phosphorus or arsenic, the energy of the ion implantation is between 1keV and 100keV, and the dose of the ion implantation is 1E13cm -2 To 1E17cm -2 The angle of ion implantation is between 0° and 90°.

7. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: In step 7 and step 11, the pre-contact metal material is a metal: titanium, nickel or cobalt, and the contact metal material is a metal silicide material: titanium silicon, nickel silicon or cobalt silicon; the method of depositing the pre-contact metal material is PVD, and the thickness of the pre-contact metal material is between 10nm and 1000nm.

8. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: The storage medium layer material in step 8 is a high dielectric constant layer and its stack: hafnium oxide, zirconium oxide or aluminum oxide, or a resistive dielectric layer: tantalum oxide, or a phase change material: GeSbTe, or a ferroelectric dielectric layer: hafnium nitride, hafnium lanthanum oxide or hafnium silicon oxide, and the top metal electrode layer material is a metal material: titanium nitride, tantalum nitride or tungsten.

9. The method for integrating a three-dimensional stacked access memory structure according to claim 2, wherein: The interconnection metal material in step 10 is a metal material: tungsten, copper, titanium nitride, tantalum nitride, or a stacked material of several metals.

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