Three-dimensional memory structure and integration method thereof

Abstract

The application provides a three-dimensional memory structure and an integrated method thereof, and belongs to the technical field of semiconductors. The memory structure is composed of multiple unit structures stacked from bottom to top, each unit structure comprises a ring gate low-power bidirectional conducting device as a write-in tube of the memory and a ring channel high-performance device as a read-out tube of the memory, the source end of the write-in tube simultaneously serves as the gate end of the read-out tube, and the write-in tube and the read-out tube are connected in the horizontal direction; the memory structure simultaneously realizes the advantages of long holding time, fast read-out speed and low power consumption, realizes the stacking of multiple storage units in a limited area, and increases the storage density; the method makes multiple repetitive unit structures in the storage structure share the process steps of photolithography, etching, ion implantation, annealing and the like, and significantly reduces the process cost of each bit of storage information in the storage structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a three-dimensional memory structure and an integration method thereof. BACKGROUND

[0002] With the development of artificial intelligence and Internet of Things technology, the demand for high-speed, high-density, low-power storage is increasing. The existing memory needs to be balanced between operation speed, storage density and operation power consumption, and cannot have all three advantages at the same time. Therefore, a new type of high-speed, high-density, low-power storage is needed. SUMMARY

[0003] The purpose of the present application is to design a three-dimensional memory structure and an integration method thereof, which comprises a ring gate low-power bidirectional conduction device as a write-in tube of the memory and a ring channel high-performance device as a read-out tube of the memory, so as to realize high-speed reading and writing, prolong the retention time of the memory and reduce the power consumption of the memory.

[0004] The technical scheme of the present application is as follows:

[0005] A three-dimensional memory structure is composed of a plurality of unit structures stacked from bottom to top, each unit structure comprising a write-in tube and a read-out tube, the source end of the write-in tube simultaneously serving as the gate end of the read-out tube, thereby realizing the connection of the write-in tube and the read-out tube in the horizontal direction. The gate ends of the write-in tubes of the unit structures in the same row are connected together through a gate conductive layer to form a write-in word line WWL, the drain ends of the write-in tubes of the unit structures in the same column are connected together through a contact metal to form a write-in bit line WBL, the source end of the write-in tube simultaneously serves as the gate end of the read-out tube and the storage node SN of the unit structure, the source ends of the read-out tubes of the unit structures in the same row are connected together through a source-drain metal to form a read-out word line RWL, and the drain ends of the read-out tubes of the unit structures in the same column are connected together through a contact metal to form a read-out bit line RBL. The write-in tube is a low-power bidirectional conduction device with a ring gate structure, and the specific features are that the channel of the write-in tube is flanked by its source end and drain end, the gate end wraps around the channel in the direction perpendicular to the channel, the source end is next to the gate end in the horizontal direction, and the drain end is separated from the gate end by a distance in the horizontal direction. The channel of the write-in tube is composed of a write-in channel layer, and the gate end is composed of a gate dielectric layer and a gate conductive layer. The drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, that is, the doping types of the semiconductor parts of the source end and the drain end are opposite. The read-out tube is a high-performance device with a ring channel structure, and the specific features are that the gate end of the read-out tube is composed of the contact metal of the source end of the write-in tube and the read-out tube gate dielectric, and the read-out tube gate dielectric wraps around the contact metal of the source end of the write-in tube. The channel of the read-out tube is composed of a read-out channel layer, and the read-out channel layer wraps around the read-out tube gate dielectric layer. The source end and the drain end of the read-out tube are each composed of a contact metal and a read-out channel layer close to the contact metal, and both the source end and the drain end are in contact with the read-out tube channel.

[0006] The application also provides an integration method of the three-dimensional memory structure, and the specific steps include:

[0007] Step 1: depositing a plurality of layers of a sacrificial layer material and a write channel layer material on a substrate, specifically, depositing a layer of the sacrificial layer material, then depositing a layer of the write channel layer material, then repeating the deposition of the sacrificial layer material and the write channel layer material, and finally depositing the material as the sacrificial layer material, the number of layers of the write channel layer is the number of repetitions of the unit structure in the memory structure;

[0008] Step 2: defining an active region, specifically, patterning the active region by means of photolithography, then etching the sacrificial layer material and the write channel layer material outside the active region to form the active region;

[0009] Step 3: forming an active region isolation, specifically, depositing an isolation layer material, then patterning the memory array region by means of photolithography, then etching the excess isolation layer material outside the memory array, and then planarizing by means of chemical mechanical polishing (CMP);

[0010] Step 4: forming a side wall isolation, specifically, patterning the side wall region by means of photolithography, then etching the sacrificial layer material and the isolation layer material in the side wall region, then depositing a side wall layer material, then planarizing by means of CMP, then patterning the memory array region by means of photolithography, then etching the excess side wall layer material outside the memory array;

[0011] Step 5: forming a write tube gate end, specifically, patterning the region between the write tube gates and the gate by means of photolithography, then etching the isolation layer between the write tube gates, then depositing a side wall layer material, then planarizing by means of CMP, then patterning the region between the write tube gates by means of photolithography, then etching the excess side wall layer material between the write tube gates, then preparing a gate stack by means of a standard polySi-SiO2 process or an HKMG process, and then removing the photoresist and the excess material;

[0012] Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by means of photolithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by means of ion implantation, then patterning the source region of the write tube by means of photolithography, then etching the sacrificial layer material in the source region of the write tube, and then forming an N-type semiconductor layer by means of ion implantation;

[0013] Step 7: Form source-drain contact, by patterning the source and drain of the write tube using photolithography, etching the isolation layer material in the region between the source and drain of the write tube and the isolation layer material in the region between the drain of the write tube, depositing a sidewall layer material, planarizing using CMP, patterning the source and drain of the write tube using photolithography, etching the excess sidewall layer material in the region between the source and drain of the write tube and the region between the drain of the write tube, depositing a contact pre-metal, reacting the contact pre-metal with the semiconductor to form a metal silicide as the contact metal using annealing, removing the unreacted contact pre-metal, and activating the impurities using annealing;

[0014] Step 8: Form the read tube region, by patterning the read tube region using photolithography, etching the excess contact metal on the source of the write tube outside the read tube region to form the read tube region;

[0015] Step 9: Form the read tube gate dielectric, by patterning the read tube region using photolithography, depositing a gate dielectric layer material, and removing the photoresist and excess material;

[0016] Step 10: Form the read tube channel layer, by patterning the read tube region using photolithography, forming a read tube channel layer material, and removing the photoresist and excess material;

[0017] Step 11: Form the read tube independent channel regions, by patterning the read tube channel region using photolithography, etching the read tube channel layer material outside the read tube channel region to remove the interconnect region of multiple read tubes;

[0018] Step 12: Form the read tube sidewall, by depositing a sidewall layer material, patterning the read tube sidewall region using photolithography, and etching the sidewall layer material outside the sidewall region to form the read tube sidewall;

[0019] Step 13: Form the read tube source-drain metal contact, by patterning the read tube channel region using photolithography, forming a contact metal, removing the photoresist and excess material, and annealing;

[0020] Step 14: Form the RWL, by patterning the RWL region using photolithography, depositing a source-drain metal, removing the photoresist and excess metal;

[0021] Step 15: Form the WBL and RBL regions, by depositing a sidewall layer material, planarizing using CMP, patterning the WBL and RBL regions using photolithography, and etching the sacrificial layer material in the WBL and RBL regions;

[0022] Step 16: Forming RBL and WBL metal contacts, by depositing a contact pre-metal, then annealing the contact pre-metal to react with the semiconductor, then removing the unreacted contact pre-metal, and then annealing to form metal silicide in the RBL and WBL regions as RBL and WBL metal contacts.

[0023] Specifically, the substrate in step 1 can be a bare silicon wafer or a silicon wafer on which front-end devices and circuits have been fabricated. The sacrificial layer material can be fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or other dielectric materials with a dielectric constant no greater than that of silicon dioxide, or a semiconductor material such as germanium-silicon. The thickness of the deposited single layer of sacrificial layer material is between 10 nm and 500 nm, and the sacrificial layer material can be deposited by PVD, CVD, epitaxy, or the like. The write channel layer material can be a semiconductor material such as amorphous silicon or single-crystal silicon, and the thickness of the deposited single layer of write channel layer material is between 10 nm and 500 nm. The write channel layer material can be deposited by PVD, CVD, epitaxy, or the like.

[0024] The isolation material in step 3 can be a dielectric material such as silicon dioxide, and the isolation material can be deposited by PVD, CVD, ALD, or the like. The thickness of the isolation layer material is greater than the total thickness of the multiple layers of stacked sacrificial layer material and write channel layer material.

[0025] The sidewall material in step 4 can be a dielectric material such as silicon nitride, and the sidewall material can be deposited by PVD, CVD, ALD, or the like. The thickness of the sidewall layer material is greater than the total thickness of the multiple layers of stacked sacrificial layer material and write channel layer material.

[0026] The P-type impurities for ion implantation in step 6 can be boron or boron fluoride, and the N-type impurities can be phosphorus or arsenic. The ion implantation energy is between 1 keV and 100 keV, the ion implantation dose is between 1E13 cm -2 and 1E17 cm -2 , and the ion implantation angle is between 0° and 90°.

[0027] The contact pre-metal material in step 7 can be a metal such as titanium, nickel, or cobalt, and the contact metal material can be a metal silicide material such as titanium silicide, nickel silicide, or cobalt silicide. The contact pre-metal material can be deposited by PVD or the like, and the thickness of the contact pre-metal material is between 10 nm and 1000 nm.

[0028] The width of the etched contact metal in step 8 is no greater than twice the thickness of the readout tube channel layer material in step 10.

[0029] The gate dielectric layer material in step 9 can be silicon dioxide, hafnium oxide, zirconium oxide or other dielectric layer or a stack of two of the dielectric layers, and the deposition method of the gate dielectric layer material can be ALD, CVD or the like, and the thickness of the gate dielectric layer material is between 1 nm and 10 nm;

[0030] The readout tube channel layer material in step 10 can be N-type impurity-doped amorphous silicon, N-type impurity-doped monocrystalline silicon or oxide semiconductor, and the formation method of the readout tube channel layer material can be PVD, CVD, ALD, epitaxy or the like, and ion implantation or the like. The thickness of the readout tube channel layer material is between 1 nm and 100 nm;

[0031] The contact metal in step 13 can be titanium, tantalum, titanium nitride, tantalum nitride, platinum or the like, or titanium silicon, nickel silicon, cobalt silicon or the like;

[0032] The source-drain metal in step 14 can be tungsten, copper, titanium nitride, tantalum nitride or the like, or a stack of several metals. The specific technical effects of the three-dimensional memory structure and the integrated method thereof are as follows:

[0033] 1. The write tube of the proposed memory structure is a ring gate low-power bidirectional conduction device, and the readout tube is a ring channel high-performance device, which can simultaneously realize long hold time, fast readout speed and low power consumption;

[0034] 2. The proposed memory structure is a three-dimensional structure, which can realize the stacking of multiple layers of storage units in a limited area, thereby increasing the storage density;

[0035] 3. The proposed integrated method enables multiple repetitive unit structures in the storage structure to share photolithography, etching, ion implantation, annealing and other process steps, thereby significantly reducing the process cost of each bit of storage information in the storage structure. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic view of the perspective view; Figures 2 to 18

[0037] Figure 2 is a schematic view of the perspective view; Figure 2 (a) is a schematic view of a single storage unit structure, Figure 2 (b) is a schematic view of a memory structure after stacking multiple unit structures one above another;

[0038] Figures 3-18 is a schematic view of the perspective view; ​

[0039] Figure 3 is a front view of depositing a plurality of sacrificial layer materials and writing a channel layer;

[0040] Figure 4 is a top view after defining active regions;

[0041] Figure 5 is a top view after forming active region isolation;

[0042] Figure 6 is a front view after forming sidewall isolation;

[0043] Figure 7 (a) is a cross-sectional view along the channel direction after forming write tube gate ends, Figure 7 (b) is a top view after forming write tube gate ends;

[0044] Figure 8 is a cross-sectional view along the channel direction after forming source / drain semiconductor layers;

[0045] Figure 9 is a cross-sectional view along the channel direction after forming source / drain contacts;

[0046] Figure 10 is a cross-sectional view along the channel direction after forming readout tube regions;

[0047] Figure 11 is a cross-sectional view along the channel direction after forming readout tube gate dielectric;

[0048] Figure 12 is a cross-sectional view along the channel direction after forming readout tube channel layers;

[0049] Figure 13 is a cross-sectional view along the channel direction after forming readout tube independent channel regions;

[0050] Figure 14 is a cross-sectional view along the channel direction after forming readout tube sidewalls;

[0051] Figure 15 is a cross-sectional view along the channel direction after forming readout tube source / drain metal contacts;

[0052] Figure 16 is a cross-sectional view along the channel direction after forming RWL;

[0053] Figure 17 is a cross-sectional view along the channel direction after forming WBL and RBL regions;

[0054] Figure 18 is a cross-sectional view along the channel direction after forming RBL and WBL metal contacts;

[0055] In the figures:

[0056] 1 - write channel layer 2 - sacrificial layer

[0057] 3 - isolation layer 4 - sidewall layer

[0058] 5 - gate dielectric layer 6 - gate conductive layer

[0059] 7 - P-type semiconductor layer 8 - N-type semiconductor layer

[0060] 9 - contact metal 10 - read channel layer

[0061] 11 - source / drain metal 12 - WWL

[0062] 13 - WBL 14 - RWL

[0063] 15 - RBL DETAILED DESCRIPTION

[0064] The application will be further described by examples. It should be noted that the purpose of the disclosed examples is to help further understand the application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the application and the appended claims. Therefore, the application should not be limited to the disclosed examples, and the scope of the application claimed is defined by the scope of the claims.

[0065] Figure 2 is one of the presentation effect schematic diagrams obtained by using the memory structure and the integrated method proposed by the application, wherein Figure 2 (b) is a schematic diagram of a single memory cell structure, Figure 2 (a) is a memory structure diagram after stacking a plurality of cell structures up and down. Figure 1 is to illustrate Figures 2 to 18 a schematic diagram of a perspective view, wherein the directions of three perspective views of a cross-sectional view along a channel direction, a top view and an elevation view are marked. Figure 2 (a) shows a memory structure composed of a plurality of Figure 2 (b) shows a cell structure stacked from bottom to top, wherein Figure 2 In (b), the write tube is located on the left side and the read tube is located on the right side. Each cell structure is composed of a write tube and a read tube, and the source end of the write tube simultaneously serves as the gate end of the read tube, realizing the connection of the write tube and the read tube in the horizontal direction. In each cell structure, the write tube is a low-power bidirectional conduction device with a ring gate structure, and the specific features are as follows: the channel of the write tube is composed of a write tube channel layer 1 composed of lightly doped single crystal silicon, and the right side and the left side of the write tube channel are the source end and the drain end thereof, respectively. The gate end is composed of a stacked gate dielectric layer 5 composed of silicon dioxide and hafnium oxide and a gate conductive layer 6 composed of titanium nitride, with a length of 60 nm. The gate end surrounds the channel in the direction perpendicular to the channel and wraps around the channel in four directions.Figure 2 The cross-sectional view along the channel direction shows that the gate is located on both sides of the channel. The source is composed of the contact metal 9 composed of metal silicide and the N-type semiconductor layer 8 composed of arsenic-doped single crystal silicon. The source is located on the right side of the channel and is adjacent to the gate in the horizontal direction. The drain is composed of the contact metal 9 composed of metal silicide and the P-type semiconductor layer 7 composed of boron fluoride-doped single crystal silicon. The drain is located on the left side of the channel and is separated from the gate by 40 nm in the horizontal direction. The read tube is a high-performance device with a ring channel structure, and the specific features are as follows: the gate of the read tube is composed of the contact metal 9 composed of metal silicide of the source of the write tube and the gate dielectric layer 5 composed of a silicon dioxide-hafnium oxide stack. The read tube gate dielectric layer 5 wraps the contact metal 9 of the source of the write tube. The read tube channel is the read tube channel layer 10 composed of arsenic-doped single crystal silicon, and the read tube channel 10 wraps the read tube gate dielectric layer 5. The source and drain of the read tube are composed of the contact metal 9 composed of metal silicide and the adjacent read tube channel layer 10, respectively. The contact metal of the source is separated from the contact metal of the drain by 60 nm, and the contact metal of the source is connected between multiple unit structures through the source-drain metal 11.

[0066] Figure 2 (a) The memory structure shown can be obtained by stacking multiple Figure 2 (b) The unit structure shown is stacked up and down. The specific features are as follows: the gates of the write tubes in the same row of unit structures are connected together through the gate conductive layer 6 to form the write word line WWL 12. The drains of the write tubes in the same column of unit structures are connected together through the contact metal 9 to form the write bit line WBL 13. The sources of the read tubes in the same row of unit structures are connected together through the source-drain metal to form the read word line RWL 14. The drains of the read tubes in the same column of unit structures are connected together through the contact metal to form the read bit line RBL 15. In each unit structure, the source of the write tube serves as the gate of the read tube, and the source of the write tube and the gate of the read tube are the storage node SN of the unit structure.

[0067] Figure 2 The memory shown can be prepared by the integrated method proposed in this patent, and the specific method is shown in Figures 3 to 18 , and the steps are as follows:

[0068] First, deposit a sacrificial layer material composed of multiple layers of fluorine-doped silicon dioxide and a write channel layer material composed of amorphous silicon on the substrate, as shown in Figure 3 The specific method is to deposit a layer of 200 nm fluorine-doped silicon dioxide by PVD, then deposit a layer of 100 nm amorphous silicon, then repeat the deposition of fluorine-doped silicon dioxide and amorphous silicon layers, a total of four layers of fluorine-doped silicon dioxide and three layers of amorphous silicon;

[0069] Second, define the active area, as shown in Figure 4As shown, the specific method is to pattern the active region by lithography, then etch the fluorine-doped silicon dioxide and amorphous silicon outside the active region to form the active region;

[0070] Next, the active region isolation layer is formed, as shown: Figure 5 As shown, the specific method is to deposit an isolation layer material composed of 1300 nm of silicon dioxide, then pattern the memory array area by lithography, then etch the excess silicon dioxide outside the memory array, then planarize by chemical mechanical polishing (CMP);

[0071] Next, the sidewall isolation layer is formed, as shown: Figure 6 As shown, the specific method is to pattern the sidewall area by lithography, then etch the fluorine-doped silicon dioxide and silicon dioxide in the sidewall area, then deposit a sidewall layer material composed of 1300 nm of silicon nitride, then planarize by CMP, then pattern the memory array area by lithography, then etch the excess silicon nitride outside the memory array;

[0072] Next, the write tube gate end is formed, as shown: Figure 7 As shown, the specific method is to pattern the area between the write tube gates and the gate by lithography, then etch the silicon dioxide isolation layer between the write tube gates, then deposit a silicon nitride sidewall, then planarize by CMP, then pattern the area between the write tube gates by lithography, then etch the excess silicon nitride between the write tube gates, then prepare the gate dielectric layer and gate conductive layer using a standard HKMG process, then remove the photoresist and excess material. The gate conductive layer formed in this step connects the gate ends of multiple unit structures together to form the WWL.

[0073] Next, the source-drain semiconductor layer is formed, as shown: Figure 8 As shown, the specific method is to pattern the drain area of the write tube by lithography, then etch the fluorine-doped silicon dioxide in the drain area, then ion implant boron fluoride with an implantation condition of 5 keV 5E15 cm -2 and an implantation angle of 10°, then pattern the source area of the write tube by lithography, then etch the fluorine-doped silicon dioxide in the source area of the write tube, then ion implant arsenic with an implantation condition of 12 keV 5E15 cm -2 and an implantation angle of 10°;

[0074] Next, the source-drain contact is formed, as shown: Figure 9As shown, the specific method is to pattern the source and drain of the write tube by means of photolithography, then etch the silicon dioxide isolation layer in the region between the source and drain of the write tube and the silicon dioxide isolation layer in the region between the drain and the source of the write tube, then deposit silicon nitride side walls, then planarize by means of CMP, then pattern the source and drain of the write tube by means of photolithography, then etch the excess silicon nitride material in the region between the source and drain of the write tube and in the region between the drain and the source of the write tube, then deposit 90nm nickel, then anneal at 500℃ for 15min to form a nickel-silicon alloy, then remove the unreacted nickel, then anneal at 600℃ for 30min to activate the impurities and change the amorphous silicon in the region of the write tube into single crystal silicon;

[0075] Next, the read tube region is formed, as shown in Figure 10 The specific method is to pattern the read tube region by means of photolithography, then etch the excess nickel-silicon alloy on the source of the write tube and outside the read tube region to form the read tube region.

[0076] Next, the read tube gate dielectric is formed, as shown in Figure 11 The specific method is to pattern the read tube region by means of photolithography, then deposit a 3nm hafnium oxide dielectric layer, then deposit a 1nm silicon dioxide dielectric layer, then remove the photoresist and excess material.

[0077] Next, the read tube channel layer is formed, as shown in Figure 12 The specific method is to pattern the read tube region by means of photolithography, then deposit 60nm amorphous silicon material, then ion implant arsenic with an implantation condition of 12keV 5E15cm -2 , an implantation angle of 10°, and then remove the photoresist and excess material.

[0078] Next, the read tube independent channel region is formed, as shown in Figure 13 The specific method is to pattern the read tube channel region by means of photolithography, then etch the amorphous silicon outside the read tube channel region to remove the interconnection region of multiple read tubes.

[0079] Next, the read tube side wall is formed, as shown in Figure 14 The specific method is to deposit 1300nm silicon nitride, then pattern the read tube side wall region by means of photolithography, then etch the silicon nitride outside the side wall region to form the read tube side wall.

[0080] Next, the contact metal of the read tube source and drain region is formed, as shown in Figure 15As shown, the specific method is to pattern the readout tube channel region by photolithography, then deposit 30nm of nickel, then anneal at 650℃ for 12 minutes, then remove the unreacted nickel, and then anneal again at 650℃ for 30 minutes to form a nickel-silicon alloy in the source and drain regions of the readout tube, while converting the amorphous silicon in the readout tube region into single crystal silicon, and then remove the photoresist and excess materials;

[0081] Next, form the RWL, such as Figure 16 As shown, the specific method is to pattern the RWL area by photolithography, and then deposit source and drain metal composed of metal tungsten. The metal tungsten connects the readout source regions of multiple unit structures together to form the RWL, and then remove the photoresist and excess metal;

[0082] Next, the WBL and RBL regions are formed as Figure 17 As shown, the specific method is to deposit 1300nm of silicon nitride, then planarize it by CMP, then pattern the WBL and RBL regions by photolithography, and then etch the fluorine-doped silicon dioxide in the WBL and RBL regions;

[0083] Next, the contact metals of RBL and WBL regions are formed, such as Figure 18 As shown, the specific method is to deposit 50nm nickel, then anneal at 550℃ for 12min, then remove the unreacted nickel, and then anneal again at 550℃ for 30min to form a contact metal composed of nickel-silicon alloy in the RBL and WBL regions. The contact metal connects the write tube drain regions of multiple unit structures together to form WBL, and connects the read tube drain regions of multiple unit structures together to form RBL.

[0084] Although the present invention has been disclosed above with reference to preferred embodiments, this is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the present invention, utilize the methods and technical content disclosed above to make many possible changes and modifications to the present invention, or modify the present invention into equivalent embodiments with equivalent variations. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. An integration method of a three-dimensional memory structure, characterized by, The specific steps include: Step 1: depositing a plurality of layers of sacrificial layer material and write channel layer material on a substrate, specifically, depositing a layer of sacrificial layer material, then depositing a layer of write channel layer material, then repeating the deposition of the sacrificial layer material and the write channel layer material, and finally depositing the material as the sacrificial layer material, the number of layers of the write channel layer being the number of repetitions of the unit structure in the above-mentioned memory structure; Step 2: defining an active region, specifically, patterning the active region by lithography, then etching the sacrificial layer material and the write channel layer material outside the active region to form the active region; Step 3: forming an active region isolation, specifically, depositing an isolation layer material, then patterning the memory array region by lithography, then etching the excess isolation layer material outside the memory array, then planarizing by chemical mechanical polishing (CMP); Step 4: forming a sidewall isolation, specifically, patterning the sidewall region by lithography, then etching the sacrificial layer material and the isolation layer material in the sidewall region, then depositing a sidewall layer material, then planarizing by CMP, then patterning the memory array region by lithography, then etching the excess sidewall layer material outside the memory array; Step 5: forming a write tube gate end, specifically, patterning the region between the write tube gates and the gate by lithography, then etching the isolation layer between the write tube gates, then depositing a sidewall layer material, then planarizing by CMP, then patterning the region between the write tube gates by lithography, then etching the excess sidewall layer material between the write tube gates, then preparing a gate stack by a standard polySi-SiO2 process or an HKMG process, then removing the photoresist and excess material; Step 6: forming a source-drain semiconductor layer, specifically, patterning the drain region of the write tube by lithography, then etching the sacrificial layer material in the drain region, then forming a P-type semiconductor layer by ion implantation, then patterning the source region of the write tube by lithography, then etching the sacrificial layer material in the source region of the write tube, then forming an N-type semiconductor layer by ion implantation; Step 7: forming a source-drain contact, specifically, patterning the source and drain of the write tube by lithography, then etching the isolation layer material in the region between the source and the drain of the write tube and the isolation layer material in the region between the source and the drain of the write tube, then depositing a sidewall layer material, then planarizing by CMP, then patterning the source and drain of the write tube by lithography, then etching the excess sidewall layer material in the region between the source and the drain of the write tube and in the region between the source and the drain of the write tube, then depositing a pre-contact metal, then reacting the pre-contact metal with the semiconductor by annealing to form a metal silicide as a contact metal, then removing the unreacted pre-contact metal, then activating the impurities by annealing; Step 8: forming a read tube region, specifically, patterning the read tube region by lithography, then etching the excess contact metal on the source of the write tube and outside the read tube region to form the read tube region; Step 9: forming a read tube gate dielectric, specifically, patterning the read tube region by lithography, then depositing a gate dielectric layer material, then removing the photoresist and excess material; Step 10: Forming the readout trench layer, the method is to pattern the readout region by lithography, then form the readout trench layer material, and then remove the photoresist and excess material; Step 11: Forming the readout independent trench region, the method is to pattern the readout trench region by lithography, then etch the readout trench layer material outside the readout trench region, and remove the interconnection region of multiple readouts; Step 12: Forming the readout sidewall, the method is to deposit the sidewall layer material, then pattern the readout sidewall region by lithography, then etch the sidewall layer material outside the sidewall region, and form the readout sidewall; Step 13: Forming the readout source-drain metal contact, the method is to pattern the readout trench region by lithography, then form the contact metal, then remove the photoresist and excess material, and then anneal; Step 14: Forming the RWL, the method is to pattern the RWL region by lithography, then deposit the source-drain metal, then remove the photoresist and excess metal; Step 15: Forming the WBL and RBL regions, the method is to deposit the sidewall layer material, then planarize by CMP, then pattern the WBL and RBL regions by lithography, and then etch the sacrificial layer material in the WBL and RBL regions; Step 16: Forming the RBL and WBL metal contact, the method is to deposit the pre-contact metal, then react the pre-contact metal with the semiconductor by annealing, then remove the unreacted pre-contact metal, and then anneal, and the metal silicide formed in the RBL and WBL regions can be used as the RBL and WBL metal contact.

2. The method of integrating three-dimensional memory structures of claim 1, wherein, The substrate in step 1 The substrate is a bare silicon wafer or a silicon wafer on which front-end devices and circuits have been prepared; the sacrificial layer material is a dielectric material with a dielectric constant not greater than that of silicon dioxide, such as fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a semiconductor material such as germanium-silicon; the thickness of the deposited single-layer sacrificial layer material is between 10 nm and 500 nm; the method of depositing the sacrificial layer material is PVD, CVD, or epitaxy; and the write-in channel layer material is amorphous silicon or single-crystal silicon, and the thickness of the deposited single-layer write-in channel layer material is between 10 nm and 500 nm.

3. The method of integrating three-dimensional memory structures of claim 1, wherein, The isolation material in step 3 is a dielectric material, such as silicon dioxide, and the method of depositing the isolation material is PVD, CVD, or ALD; the thickness of the isolation layer material is greater than the total thickness of the multilayer-stacked sacrificial layer material and write-in channel layer material.

4. The method of integrating three-dimensional memory structures of claim 1, wherein, The sidewall material in step 4 is a dielectric material, such as silicon nitride, and the method of depositing the sidewall material is PVD, CVD, or ALD; the thickness of the sidewall layer material is greater than the total thickness of the multilayer-stacked sacrificial layer material and write-in channel layer material.

5. The method of integrating three-dimensional memory structures of claim 1, wherein, The P-type impurity ion implanted in step 6 is boron or boron fluoride, the N-type impurity is phosphorus or arsenic, the ion implantation energy is between 1 keV and 100 keV, the ion implantation dose is between 1E13 cm -2 and 1E17 cm -2 , and the ion implantation angle is between 0° and 90°.

6. The method of integrating three-dimensional memory structures of claim 1, wherein, The pre-contact metal material in step 7 is a metal, such as titanium, nickel, or cobalt, and the contact metal material is a metal silicide material, such as titanium silicide, nickel silicide, or cobalt silicide; the method of depositing the pre-contact metal material is PVD; and the thickness of the pre-contact metal material is between 10 nm and 1000 nm.

7. The method of integrating three-dimensional memory structures of claim 1, wherein, The width of the contact metal etched in step 8 is not more than twice the thickness of the readout tube channel layer material in step 10; The gate dielectric layer material in step 9 is silicon dioxide, hafnium oxide, zirconium oxide, or a stack of two of the above materials, and the deposition method of the gate dielectric layer material is ALD or CVD, and the thickness of the gate dielectric layer material is between 1 nm and 10 nm; The readout tube channel layer material in step 10 is N-type impurity-doped amorphous silicon, N-type impurity-doped single crystal silicon, or an oxide semiconductor, and the formation method of the readout tube channel layer material is a material deposition process: PVD, CVD, ALD, epitaxy, and an auxiliary doping means: ion implantation; The thickness of the readout tube channel layer material is between 1 nm and 100 nm; The contact metal in step 13 is titanium, tantalum, titanium nitride, tantalum nitride, platinum, titanium silicon, nickel silicon, or cobalt silicon; The source-drain metal in step 14 is tungsten, copper, titanium nitride, tantalum nitride, or a stack of several metals.

8. A three-dimensional memory structure integrated using the integrated method of claim 1, wherein, The plurality of unit structures are stacked from bottom to top, each unit structure comprising a write tube and a readout tube, the source end of the write tube simultaneously serving as the gate end of the readout tube, thereby realizing the connection of the write tube and the readout tube in the horizontal direction; the gate ends of the write tubes of the same row of unit structures are connected together through a gate conductive layer to form a write word line WWL, the drain ends of the write tubes of the same column of unit structures are connected together through a contact metal to form a write bit line WBL, the source end of the write tube simultaneously serving as the gate end of the readout tube and a storage node SN of the unit structure, the source ends of the readout tubes of the same row of unit structures are connected together through a source-drain metal to form a readout word line RWL, and the drain ends of the readout tubes of the same column of unit structures are connected together through a contact metal to form a readout bit line RBL; the write tube is a low-power bidirectional conduction device with a ring gate structure, and the readout tube is a high-performance device with a ring channel structure.

9. The three-dimensional memory structure of claim 8, wherein, The write tube has a channel, and the channel is surrounded by a source end and a drain end, and a gate end in a direction perpendicular to the channel; the source end is adjacent to the gate end in the horizontal direction, and the drain end is separated from the gate end by a distance in the horizontal direction; the channel of the write tube is composed of a write channel layer, the gate end is composed of a gate dielectric layer and a gate conductive layer, the drain end is composed of a contact metal and a P-type semiconductor, and the source end is composed of a contact metal and an N-type semiconductor, i.e., the doping types of the semiconductor parts of the source end and the drain end are opposite.

10. The three-dimensional memory structure of claim 8, wherein, The gate end of the readout tube is composed of the contact metal of the source end of the write tube and a readout tube gate dielectric, the readout tube gate dielectric surrounds the contact metal of the source end of the write tube, the channel of the readout tube is composed of a readout channel layer, the readout channel layer surrounds the readout tube gate dielectric layer, the source end and the drain end of the readout tube are each composed of a contact metal and a readout channel layer close to the contact metal, and the source end and the drain end are each in contact with the channel of the readout tube. ​

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