Devices and systems related to package architectures and methods of forming package architectures

Abstract

The disclosure relates to devices and systems related to a package architecture and methods of forming a package architecture. A method, system, and device for providing a first layer including a first device region and a second device region and a second layer including an interconnect die including interface logic are disclosed. The first device region and the second device region are mounted on a first side of the interconnect die, and the first device region and the second device region are communicatively coupled to the interface logic.

Description

Technical Field

[0001] The subject matter disclosed herein relates to microelectronic packaging and integrated circuit (IC) packaging. More specifically, the subject matter disclosed herein relates to packaging architecture using a multi-stack architecture. Background Art

[0002] Semiconductor devices can be connected to additional devices and circuits on different substrates. Forming connections between substrates can provide increased computing by allowing different computing components to operate in coordination. However, forming connections between substrates can lead to complications. Packaging describes a general method for connecting and integrating multiple computing components together in an integrated unit, and can involve multiple different types of integrated circuits on multiple substrates that can be combined into a single unit. Packaging can also describe a method for protecting multiple computing components within a single unit by using various techniques that provide thermal, physical, and electrical protection. Such protection can only provide a limited number of external connections for the protected computing components. The background technology concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. The background technology or fields described herein should also not be intended to limit the disclosure of this article to a specific use or concept. Summary of the invention

[0003] Example embodiments provide a device associated with a packaging architecture, the device including a first layer, the first layer including a first device region and a second device region. The device includes a second layer, the second layer including an interconnect die, the interconnect die including an interface logic. The first device region and the second device region are mounted on a first side of the interconnect die, and the first device region and the second device region are communicatively coupled to the interface logic.

[0004] In some embodiments, the first device area includes at least one component device, the at least one component device includes at least one of a memory device and a processing device, and the second device area includes at least one component device, the at least one component device includes at least one of a memory device and a processing device. The first device area may include a first device and a second device, the first device includes at least one of a memory device and a processing device, and the second device includes at least one of a memory device and a processing device. In some embodiments, the first device area and the second device area may have the same device composition. In some embodiments, the first device area and the second device area may have different device compositions. In some embodiments, the interface logic may include serial interface logic or parallel interface logic. In some embodiments, the interface logic may be between the first device area and the second device area. In some embodiments, the interconnection die has an interconnection region on a second side of the interconnection die, the second side of the interconnection die being opposite to the first side of the interconnection die. The interconnection region may be formed by at least one of a column, a bump, and a pad. The interconnection region may be communicatively coupled to the first device area and the second device area. In some embodiments, the interface logic may include serial interface logic or parallel interface logic, the interface logic may be mounted on a first side of the first device area, and the second device area may be mounted on a second side of the first device area opposite to the first side.

[0005] Example embodiments provide a system associated with a packaging architecture, the system comprising a first layer and a second layer, wherein the second layer is on top of the first layer. The first layer may include a first device stack and a second device stack. The first device stack is formed in a first device region, and the second device stack is formed in a second device region. The second layer may include an interconnect die and an interface logic. The first device stack may be connected by a first through-path, the second device stack may be connected by a second through-path, and both the first through-path and the second through-path are communicatively connected to the interface logic. In some embodiments, the first device stack and the second device stack have the same device composition. In some embodiments, the first device stack and the second device stack have different device compositions. In some embodiments, the interface logic is parallel logic and is arranged on a first side of the first device stack, wherein the second device stack is arranged on a second side of the first device stack opposite to the first side.

[0006] Example embodiments provide a method for forming a package architecture, the method comprising: forming an interconnect die, the interconnect die including embedded interface logic; and forming a wiring layer communicatively coupled to the embedded interface logic. A first device and a second device may be mounted on the interconnect die, wherein the first device and the second device are communicatively coupled to the wiring layer. An additional first device may be mounted on the first device to form a first device area, wherein the additional first device is communicatively coupled to the first device. An additional second device may be mounted on the second device to form a second device area, wherein the additional second device is communicatively coupled to the second device. A molding layer may be formed over the interconnect die, the first device area, and the second device area. In some embodiments, the first device area and the second device area may have the same device composition. In some embodiments, the first device area and the second device area may have different device compositions. In some embodiments, mounting the first device and the second device on the interconnect die includes mounting the first device on a first side of the embedded interface logic and mounting the second device on a second side of the embedded interface logic, the second side being opposite to the first side. In some implementations, mounting the first device and the second device on the interconnect die includes mounting the second device on a first side of the first device and mounting the embedded interface logic on a second side of the first device, the second side being opposite the first side. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following sections, various aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0008] Figure 1 depicts a perspective view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0009] Figure 2 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0010] Figure 3 depicts a top view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0011] Figure 4 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0012] Figure 5 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0013] Fig. 6A depicts a cross-sectional view of an example implementation of a package structure assembly at a first time in accordance with various implementations of the subject matter disclosed herein;

[0014] Figure 6B depicts a cross-sectional view of an example embodiment of a package structure assembly at a second time in accordance with various embodiments of the subject matter disclosed herein;

[0015] Figure 6C depicts a cross-sectional view of an example embodiment of a package structure assembly at a third time in accordance with various embodiments of the subject matter disclosed herein;

[0016] Fig.6D depicts a cross-sectional view of an example embodiment of a package structure assembly at a fourth time in accordance with various embodiments of the subject matter disclosed herein;

[0017] Fig. 6E depicts a cross-sectional view of an example embodiment of a package structure assembly at a fifth time in accordance with various embodiments of the subject matter disclosed herein;

[0018] Figure 7 Depicted are example implementations of methods of forming package structures according to various implementations of the subject matter disclosed herein;

[0019] Figure 8 depicts a cross-sectional view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0020] Fig. 9 depicts a top view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein;

[0021] Fig.10 A top view depicting an example implementation of a package structure according to various implementations of the subject matter disclosed herein; and

[0022] Fig.11 Depicted is a top view of an example implementation of a package structure according to various implementations of the subject matter disclosed herein. DETAILED DESCRIPTION

[0023] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other examples, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0024] References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing throughout this specification may not necessarily all refer to the same embodiment. In addition, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional," "pre-determined," etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two dimensional," "predetermined," etc.), and capitalized terms (e.g., "Counter Clockwise," "Three-Dimensional," etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clockwise," "three-dimensional," etc.). Such occasional interchangeable usages should not be considered inconsistent with each other.

[0025] In addition, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the size of some elements may be enlarged relative to other elements. In addition, if deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements.

[0026] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprising" and / or "comprising ..." indicate the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0027] It will be understood that when an element or layer is referred to as being on, "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0028] As used herein, the terms "first", "second", etc. are used as labels for the nouns preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. In addition, the same figure mark may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0030] As used herein, a substrate may refer to various materials and structures, including wafers using silicon, wafers using silicon on insulator (SOI) (such as glass), wafers of other semiconductor materials (such as germanium), and other semiconductor materials on insulators. In some embodiments, the substrate may include organic materials. In some embodiments, the substrate may be referred to as a wafer, a die, and a chip individually or in combination. Therefore, in some embodiments, the bonding substrate may be referred to as a die-to-die (D2D) bonding, a wafer-to-wafer bonding (W2W), or a die-to-wafer bonding (D2W). In some embodiments, the substrate may include circuits (such as integrated circuits, including a central processing unit (CPU)), logic chips, memories (such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate DRAM or DDR DRAM), application processors (AP), graphics processing units (GPU), other forms of auxiliary processing units (xPU), artificial intelligence (AI) chips, high bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASICs). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, the substrate may include a packaged chip.

[0031] As used herein, high bandwidth memory or HBM may refer to a chip structure that includes one or more HBM modules. In some embodiments, HBM may be manufactured by advanced silicon node processes.

[0032] As used herein, packaging refers to the process of forming interconnections between substrates. In some embodiments, the interconnection can be between direct surfaces (direct surface) and involve W2W, D2D and D2W bonding. In other embodiments, the technology including wire bonding and other forms of indirect bonding can be performed alone or in combination with W2W, D2D and D2W bonding. In some embodiments, the circuit can be directly facing each other, and in other embodiments, flip chip bonding can be used. In some embodiments, the substrates can be interconnected on the front side or circuit side of the substrate. In other embodiments, the substrate can be interconnected on the back side or back side opposite to the circuit structure. In some embodiments, the interconnection can include a through silicon via (TSV) or other forms of through chip vias, in which one or more substrates can be connected using a path that travels through an interposer (such as another substrate or chip). In some embodiments, the connection on the surface of the substrate (such as a pad) can be used to form an interconnection, and the additional material (such as solder) between the pads can be used to form an interconnection.

[0033] As used herein, a conductor may refer to a variety of conductive materials, including materials that may be used alone or in combination with other materials, such as in alloy form. In some embodiments, the conductor is copper (Cu). In some embodiments, the copper (Cu) may be in the form of Cu (II), Cu (III), or other forms of copper alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru). Such a list of elements is not intended to be exhaustive, and in other embodiments, any other known type of conductive material may be used.

[0034] Various embodiments of devices, systems, and methods related to packaging architectures are disclosed herein to modularly create stacked logic and memory building block architectures using various forms of bonding, including hybrid bonding. As used herein, hybrid bonding can be defined as bonding a conductive portion to a conductive portion and a dielectric portion to a dielectric portion.

[0035] Various embodiments of devices, systems, and methods related to packaging architectures are disclosed herein to modularly create stacked logic and memory building block architectures using a shared die stacked thereon with multiple devices. The stacked logic and memory building block architecture may include a base die that provides logic, routing, and power delivery to one or more stacks of memory and computing elements. As used herein, a device stack or stack of devices may refer to a combination of memory, computing, and supporting circuit architectures, for example, chiplets and dies containing separate memory elements, processing units, input-output (I / O) circuits, and other forms of integrated chips.

[0036] The stacked logic and memory building block architecture using a shared die can provide an integrated unit that allows multiple different computing devices to be placed together to achieve high-density computing and memory. Multiple devices such as chiplets and dies can be stacked together to create an HBM module that provides high-bandwidth memory for fields such as HPC and AI. The stack of devices can then be integrated into a larger system (such as a system on a chip (SOC)) and provide additional computing resources to improve performance. Such a larger system may face complexity when adding additional device stacks because the central computing device for such a larger system has space limitations in adding interconnections. Various embodiments of the stacked logic and memory building block architecture disclosed herein can allow multiple device stacks to be integrated on a shared interconnect die. The shared interconnect die can provide connections for multiple device stacks to communicate with the central computing device. In some embodiments, the shared interconnect die may include logic for providing D2D connections between multiple device stacks and additional computing resources on another die.

[0037] Figure 1An exemplary embodiment of a device package 100 is depicted from a perspective view. An interconnect die 102 supports a first device region 104 and a second device region 106 (also generally referred to herein as a "device" and collectively referred to as "device"). In some embodiments, the device may include a processor die or a processor chiplet. In some embodiments, the device may be various forms of memory, including DRAM, SRAM, and other forms of memory. In some embodiments, the device may include a core device (e.g., a processor or other form of microcontroller) to serve as a controller. In some embodiments, the first device region 104 and the second device region 106 may each include a stack of one or more component devices.

[0038] In some embodiments, the interconnect die 102 can be a silicon die, while in other embodiments, various semiconductor materials can be used alone or in combination. For example, in some embodiments, the interconnect die 102 can include an SOI substrate (such as glass) and germanium, sapphire, or other forms of semiconductors (either alone, in combination with another semiconductor, or in combination with an insulator such as glass).

[0039] The interconnect die 102 may also be referred to as a base die, a buffer die, an interconnect die, and a support interconnect. In some embodiments, the interconnect die 102 may be used as a buffer for HBM die stacking. The interconnect die 102 may have high-speed interconnects (such as physical layer (PHY) interconnects, D2D interconnects, and fine pitch microbumps) and any other suitable form of interconnects. In some embodiments, the interconnect die 102 may include one or more test logics for testing various devices in the device package 100. For example, in some embodiments, the interconnect die 102 may include one or more of a unit-level test circuit, an I / O test circuit, and a loopback test circuit of a DRAM core die. In some embodiments, one or more test logics may be used with a first device area 104, a second device area 106, or a combination thereof. In some embodiments, one or more test logics may be used with a device outside the device package 100, and in some embodiments, one or more test logics may be used within the device package 100.

[0040] Figure 2 Another view of the device package 100 is depicted, showing in cross-section the Figure 1 The device package 100 shown in FIG. Figure 2As shown in , the first device region 104 has a plurality of component devices, including a vertically stacked first layer device 112, a second layer device 114, a third layer device 116, and a fourth layer device 118, wherein the first layer device 112 is on top of the second layer device 114, the second layer device 114 is on top of the third layer device 116, the third layer device 116 is on top of the fourth layer device 118, and the fourth layer device 118 is on top of the interconnection tube die 102. In some embodiments, the stack of component devices may include memory devices, core devices, processing devices, and combinations thereof. In some embodiments, the first device region 104 and the second device region 106 may include the same component devices (that is, device composition), while in other embodiments, the component devices (that is, device composition) in the first device region 104 and the second device region 106 may be different. In some embodiments, the through-via 120 may electrically connect the various devices in the device region to each other and to the interconnection tube die 102.

[0041] The number of component devices within the first device area 104 or the second device area 106 can vary, and the number of component devices provided and the type of component devices can vary based on the relative amount of computing expected for each device. For example, a desired ratio between core die and memory die may be desired, such as 1 core for every 4 memory dies may be desired in some embodiments. However, in other embodiments, for example, the ratio may vary, and in some embodiments, the ratio may be greater and include 1 core for every 5, 6, 10, or even 16 memory dies. The number and nature of the devices may be referred to as the device composition.

[0042] Figure 3 Additional views of the device package 100 are depicted, wherein Figure 2 The cross-sectional view and Figure 1 Compared with the perspective view, Figure 3 1 depicts a top view of the device package 100. Figure 2 and Figure 3 As shown in the exemplary embodiment of FIG. 1 , a molding layer 108 (such as a dielectric material or an adhesive layer (such as a resin or epoxy)) can be provided between the first device region 104, the second device region 106, and the interconnect die 102. In some embodiments, a dielectric material such as silicon nitride (Si 3 N 4 ) or silicon dioxide (SiO 2) to form a mold layer 108. In some embodiments, the first device region 104 and the second device region 106 can be encapsulated by the mold layer 108, and an additional encapsulation layer can be included on the side or top of the first device region 104 and the second device region 106. The encapsulation layer can be a dielectric material or an adhesive layer (such as a resin or epoxy). In some embodiments, the mold layer 108 can provide mechanical support (such as holding the device in place), as well as provide electrical isolation, and can provide a thermal path for heat from the device to transfer therethrough. In some embodiments, the mold layer 108 can cover the first layer device 112, while in other embodiments, the mold layer 108 may not cover the first layer device 112, so that the first layer device 112 has an exposed top surface.

[0043] In the device package 100, the first device region 104 and the second device region 106 can be electrically connected to one or more wiring layers 122 within the interconnect die 102 via the through-via 120. The one or more wiring layers 122 within the interconnect die 102 can, in turn, electrically connect the first device region 104 and the second device region 106 to an additional interposer or substrate using an interconnect 130 on the bottom side of the interconnect die 102, which is opposite to the top side of the interconnect die 102 that holds the first device region 104 and the second device region 106. The interconnect 130 on the bottom side of the interconnect die 102 can include one or more pillars 132 and one or more bumps 134. In some embodiments, the one or more pillars 132 can be formed of copper or any other suitable conductive material. In some embodiments, the one or more bumps 134 can include microbumps, balls, and other forms (such as controlled collapse chip connection (C4) bumps) alone or in combination. In some embodiments, one or more bumps 134 may be formed on one or more pillars 132, and in some embodiments, one or more bumps 134 may be used alone or in combination with one or more pillars 132 in the same plane. In some embodiments, the interposer may include one or more redistribution layers, allowing the first device region 104 and the second device region 106 to be electrically coupled to one or more computing devices via one or more bumps 134 and one or more pillars 132. In addition, the interconnect 130 may provide mechanical support for the device package 100 to be mounted on an interposer or substrate.

[0044] Although referred to as wiring layers 122, one or more of the wiring layers 122 may take the form of a series of pads, bumps, vias, through vias, traces, redistribution layers, and other forms of connections for redistributing signals in various combinations. Similarly, the redistribution layers may also take the form of a series of pads, bumps, vias, through vias, traces, and other forms of connections for redistributing signals in various combinations.

[0045] In some embodiments, the interconnect die 102 can include one or more components embedded in the interconnect die 102. In some embodiments, the interconnect can be embedded within the interconnect die 102. Figure 4 An example implementation having interface logic 150 embedded within the interconnect die 102 is depicted.

[0046] In some embodiments, the interface logic 150 may be a D2D Internet Protocol or D2D IP logic. In some embodiments, the interface logic 150 may be an interface logic within the interconnect die 102. In some embodiments, the interface logic 150 may be on the surface of the interconnect die 102. In some embodiments, the interface logic 150 may be distributed across the logic of the interconnect die 102 and may exist on one or more layers across the interconnect die 102 or within the interconnect die 102. In other embodiments, the interface logic 150 may exist in a single location on the interconnect die 102, in one or more layers. In some embodiments, the interface logic 150 may take the form of a chiplet, which may be embedded within the interconnect die 102.

[0047] exist Figure 4 In an exemplary embodiment of the present invention, the interface logic 150 can be placed within the interconnect die 102 between the first device region 104 and the second device region 106. The interface logic 150 can be electrically connected to one or more wiring layers 122 to electrically connect the first device region 104 and the second device region 106 to an external device (such as an interposer or substrate). In other embodiments (such as Figure 5 In some exemplary embodiments, the interface logic 150 may be placed at the edge of the interconnect die 102, and in some embodiments may not be directly below the first device region 104 or the second device region 106, while in other embodiments, the interface logic 150 may be below a single device in the first device region 104 or the second device region 106. In some embodiments, the interface logic 150 may be distributed across the logic of the interconnect die 102 and may exist on one or more layers. In other embodiments, the interface logic 150 may exist in a single location on the interconnect die 102, in one or more layers.

[0048] In some embodiments, the placement of the device may be related to the protocol used by the interface logic 150 and whether the interface logic 150 uses a serial protocol or a parallel protocol. Figure 4 In an exemplary embodiment of the present invention, a serializer / deserializer (SerDes) protocol can be used to provide a SerDes connection 152 using the SerDes D2D IP. In some embodiments, other serial protocols can be used alone or in combination with the SerDes protocol. Figure 5 In an exemplary embodiment of the present invention, the Universal Chiplet Interconnect Express (UCIe) protocol can be used to provide the parallel connection 154. In some embodiments, other parallel protocols can be used alone or in combination with the UCIe protocol. In some embodiments, the serial protocol can be used with the interface logic 150 directly below the first device area 104 and the second device area 106. In some embodiments, the parallel protocol can be used with the interface logic 150 placed at the edge of the interconnect die 102. Of course, in other embodiments, the parallel protocol can be used with the interface logic 150 directly below the first device area 104 and the second device area 106; and the serial protocol can be used with the interface logic 150 placed at the edge of the interconnect die 102. In some embodiments, the interface logic 150 can be oriented along the edge of the device package 100. In some embodiments, the placement of the interface logic 150 oriented along the side of the device package 100 can allow for a more direct connection to the additional die, and can provide a reduction in routing distance, as well as a reduction in delay and an increase in the performance of the device package 100 as a whole.

[0049] FIG. 6A to FIG. 6E An illustrative embodiment of a process of forming a device package structure, such as device package 100 or any other device package structure shown herein, is depicted. Figure 7 Depicted are the components used to form FIG. 6A to FIG. 6E An example implementation of process 700 of an illustrative embodiment of a device packaging structure.

[0050] Fig. 6A Shows Figure 7 At S710 in, wherein a first device layer 601 on the interconnect die 102 is formed on a carrier substrate 602. The carrier substrate 602 may be any suitable substrate, such as a glass substrate. In some embodiments, a release layer may be formed on the carrier substrate 602 before the interconnect die 102 is formed on the carrier substrate 602. The release layer may include a material such as a polymer, wax, epoxy, or resin (which serves as a sacrificial layer) and may be cleanly removed from the carrier substrate 602 and the interconnect die 102. In some embodiments, the interconnect die 102 may be formed using a complementary metal oxide semiconductor (CMOS) process (such as deposition, lithography, etching, passivation directly on the carrier substrate 602). In some embodiments, the interconnect die 102 may be formed on a separate substrate and transferred to the carrier substrate 602. The interface logic 150 may be formed as part of the interconnect die 102, or may be formed separately and transferred to the interconnect die 102.

[0051] On top of the interconnect die 102, a first device layer 601 is formed by mounting a first base device 604 and a second base device 606 on the interconnect die 102. The first base device 604 and the second base device 606 may be core devices or memory devices. The devices in the first device layer 601 may be mounted directly on the interconnect die 102 and connected to one or more wiring layers 122. In some embodiments, the first device layer 601 may be directly bonded to one or more wiring layers 122. In some embodiments, the first device layer 601 may be indirectly bonded to one or more wiring layers 122, for example, by using one or more intermediate layers. In some embodiments, the first device layer 601 and the interconnect die 102 may include a metal material and a dielectric material (including the surface of the dielectric material and the metal material). For example, the first base device 604 and the second base device 606 may include a conductive interconnect for forming a through-via 120. The conductive interconnect may take the form of a metal interconnect surrounded by a dielectric material, wherein both the dielectric material and the metal material are present on the surface of the first device layer 601. In some embodiments, a metal bond may be used between the first device layer 601 and the interconnect die 102, a dielectric bond may be used between the first device layer 601 and the interconnect die 102, or in some embodiments, a hybrid bond may be used between the first device layer 601 and the interconnect die 102. In some embodiments, a heat treatment or other thermal processing may be provided to form or strengthen the bond between the first device layer 601 and the interconnect die 102.

[0052] Figure 6B Shows Figure 7 At S720 in the embodiment, the first device region 104 and the second device region 106 are formed by stacking additional device layers on the first device layer 601. Similar to the first device layer 601 on the interconnect die 102, the additional device layers can be stacked on the first device layer 601. The additional device layers can be aligned so that the through vias 120 are formed within each stack. Additional thermal treatment or thermal processing can be provided to form or strengthen the bonding between each layer.

[0053] Figure 6C Shows Figure 7At S730 in the step, a mold layer 108 is deposited over the first device region 104, the second device region 106, and the interconnect die 102. The mold layer 108 may be deposited to provide electrical separation between the first device region 104, the second device region 106, and the interconnect die 102, and to provide mechanical support for the stacked devices. After the mold layer 108 is formed, the surface of the mold layer 108, the first device region 104, and the second device region 106 may be subjected to a process for smoothing and / or planarizing the surface, the process including one or more grinding, polishing, and smoothing processes, including chemical mechanical planarization (CMP). In some embodiments, the process may expose the top surface of the first device region 104 and the second device region 106. In other embodiments, the top surface of one or more of the first device region 104 and the second device region 106 may remain covered by the mold layer 108.

[0054] Fig.6D Shows Figure 7 At S740 in the process, the first device region 104 and the second device region 106 mounted on the interconnect die 102 are released from the carrier substrate 602. For example, the carrier substrate 602 may be released by using one or more of a layer release technique, a chemical release technique, a thermal release technique, and a photo release technique to release an adhesive layer coupling the carrier substrate 602 to the interconnect die 102. For example, in some embodiments, the chemical release technique may use a solvent to directly dissolve the adhesive, while the thermal release technique may apply heat to the carrier wafer to melt the adhesive, and the photo release technique may use a laser to directly apply energy to the adhesive layer to reduce the adhesive strength.

[0055] Fig. 6E Shows Figure 7 At S750 in the embodiment, interconnect 130 may be formed on the bottom of interconnect die 102. Interconnect 130 may include pads, bumps, microbumps, pillars, balls, and other forms (such as C4 bumps) alone or in combination. In some embodiments, dielectric material or adhesive material (including bottom fill) may also be included. Fig. 6E In an example embodiment, the interconnect 130 includes one or more pillars 132 formed on the bottom of the interconnect die 102 and one or more bumps 134 formed on the one or more pillars 132 .

[0056] Figure 8 An example implementation of a device package structure 800 is depicted. Figure 8 The device package structure 800 and Figures 1 to 3The device package 100 of the present invention is different in that a pillar interconnect 802 is used instead of the interconnect 130. The pillar interconnect 802 includes a pillar 804 connected to the bottom of the interconnect die 102. In some embodiments, the pillar interconnect 802 may include one or more pads. The pillar 804 and the one or more pads may be formed of copper or any other suitable conductive material. In some embodiments, the pillar interconnect 802 may be assembled to the package using metal bonding, diffusion bonding, or hybrid bonding.

[0057] Fig. 9 An exemplary embodiment of a first packaging structure 900 including a device package disclosed herein is depicted. For example, in some embodiments, one or more of the device packages 100 can be mounted within a larger package that includes one or more computing devices, one or more I / O devices (such as a connection chiplet 914), a support substrate 902, and one or more embedded bridges. The first packaging structure 900 can allow one or more of the device packages 100 to be communicatively coupled with one or more computing devices to provide computing resources such as memory and processing.

[0058] The one or more computing devices may include a first computing device 910, a second computing device 912, and a third computing device 916. In some embodiments, the computing device may include a processor die or a processor chiplet. In some embodiments, a single computing device may be used, while in other embodiments, additional computing devices may be added, for example, 4, 6, 8, 16, or 32 computing devices may be added. In some embodiments, the first computing device 910 and the second computing device 912 may share a support die, while in other embodiments, each computing device may have a separate support die. In some embodiments, the support die may be a silicon die, while in other embodiments, various semiconductor materials may be used. In some embodiments, the computing device may include a processor die or a processor chiplet.

[0059] A plurality of device packages may exist in the first package structure 900. The plurality of device packages may include the device package 100. Fig. 9 In an exemplary embodiment, first device package 920, third device package 922, and fifth device package 924 may be on one side of a computing device, while second device package 921, fourth device package 923, and sixth device package 925 may be on the opposite side.

[0060] The connectivity chiplet 914 may include I / O circuitry to allow the first package structure 900 to be connected to additional devices. For example, in some embodiments, the connectivity chiplet 914 may provide wireless connectivity using one or more forms of radio frequency protocols for one or more frequency spectrums. In some embodiments, the connectivity chiplet 914 may provide optical or wired communications alone or in some combination with wireless communications.

[0061] Fig. 9 An exemplary embodiment of a first package structure 900 using a support substrate 902 is depicted. In some embodiments, the support substrate 902 can be an organic substrate such as a polymer, while in other embodiments, an inorganic substrate such as a semiconductor including silicon, or alternatively a SOI substrate such as glass can be used. In some embodiments, the support substrate 902 can be a plurality of substrates, and in some embodiments can be a plurality of substrates stacked one on top of another. Fig. 9 In the embodiment, multiple device packages can be connected to one or more computing devices and connecting chiplets 914 via a supporting substrate 902.

[0062] Fig.10 An exemplary embodiment of a second package structure 1000 using an interposer 1002 on a support substrate 902 is depicted. Fig.10 In, with Fig. 9 Differently, device package 100 and other components may be mounted on interposer 1002 , which itself is mounted on support substrate 902 . Fig.10 The second package structure 1000 may include Fig. 9 elements of the first package structure 900, as discussed further above. In some embodiments, the interposer 1002 can be made of silicon, while in other embodiments, another form of semiconductor (such as germanium) can be used. In some embodiments, multiple interposer substrates can be shared on a single support substrate. In some embodiments, the support substrate 902 can have the interposer 1002 mounted thereon in various manners, and can include pads, bumps, micro-bumps, pillars, balls, and other forms (such as C4 bumps), either individually or in combination. Fig.10 In the example, multiple device packages can be connected to one or more computing devices and connected chiplets 914 via an interposer 1002 .

[0063] In addition to or in place of computing devices and multi-device packages, the interposer 1002 may include additional devices. In addition, a stiffener 1004 is shown as surrounding the perimeter on the support substrate 902. The stiffener 1004 may be a rigid material to provide additional mechanical support to the support substrate 902. The stiffener 1004 may be made of a material having a higher elastic modulus than the elastic modulus of the support substrate 902, and may therefore include materials such as metals (e.g., aluminum, copper, or steel), ceramics, composite materials, or other suitable materials. The stiffener 1004 may be used in conjunction with a cover design to provide additional protection for the second package structure 1000, including protection against mechanical deformation, deformation, and warping. In some embodiments, the cover may be used to provide additional mechanical, thermal, and electrical protection for the second package structure 1000. In some embodiments, a coverless design may be used instead.

[0064] Additionally, the stiffener 1004 may be formed directly on the support substrate 902, such as by additive manufacturing of a suitable material, to provide additional rigidity to the support substrate 902, or may be formed separately and mounted on the support substrate 902 using a bonding process or adhesive, such as an epoxy or resin. In some embodiments, an additional layer of molding material or packaging material may be deposited between the interposer 1002 and the stiffener 1004. In some embodiments, a lid may be further mounted to the second package structure 1000 and attached to the stiffener 1004.

[0065] Fig.11 An exemplary embodiment of a third package structure 1100 using an embedded bridge structure is depicted. Fig. 9 and Fig.10 In contrast, the third package structure 1100 uses one or more embedded bridges within an overmolding layer 1102 . Fig.11 The third package structure 1100 may further include Fig.10 The components of the second package structure 1000 and Fig. 9 The components of the first package structure 900 are as shown above. Fig.11As discussed further in , multiple device packages can be connected to one or more computing devices via separate embedded bridges via a supporting substrate. A first embedded bridge 1110 can connect a first device package 920 to a first computing device 910 on a first side, while a second embedded bridge 1111 connects a second device package 921 to the first computing device 910 on a second side opposite the first side. A third embedded bridge 1112 can connect a third device package 922 to a second computing device 912 on a first side, while a fourth embedded bridge 1113 can connect a fourth device package 923 to the second computing device 912 on a second side. A fifth embedded bridge 1114 can connect a fifth device package 924 to a third computing device 916 on a first side, while a sixth embedded bridge 1115 can connect a sixth device package 925 to the third computing device 916 on a second side.

[0066] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0067] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring the operations to be performed in the particular order shown or in a continuous order, or performing all of the operations shown, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0068] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0069] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

[0070] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 543,507, filed on October 10, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

Claims

1. A device related to a packaging architecture, comprising: A first layer, including a first device region and a second device region; as well as a second layer including an interconnect die including interface logic; wherein the first device region and the second device region are mounted on a first side of the interconnect die; as well as Wherein the first device region and the second device region are communicatively coupled to the interface logic.

2. The device of claim 1, wherein the first device region includes at least one component device selected from the group consisting of a memory device and a processing device; and The second device area includes at least one component device selected from the group consisting of a memory device and a processing device. 3 . The device of claim 1 , wherein the first device area includes a first device and a second device, the first device being selected from the group consisting of a memory device and a processing device, and the second device being selected from the group consisting of a memory device and a processing device. 4 . The device of claim 1 , wherein the first device region and the second device region are identical in device composition. 5 . The device of claim 1 , wherein the first device region and the second device region are different in device composition.

6. The device of claim 1, wherein the interface logic comprises serial interface logic or parallel interface logic; and The interface logic is arranged between the first device area and the second device area.

7. The device of claim 1, wherein the interconnect die has an interconnect region on a second side of the interconnect die, the second side of the interconnect die being opposite to the first side of the interconnect die; and Wherein the interconnection region is selected from the group consisting of a pillar, a bump and a pad. 8 . The device of claim 7 , wherein the interconnect region is communicatively coupled to the first device region and the second device region.

9. The device of claim 1, wherein the interface logic comprises serial interface logic or parallel interface logic; and Wherein the interface logic is mounted on a first side of the first device region, and the second device region is mounted on a second side of the first device region, and wherein the second side is opposite to the first side.

10. A system related to a packaging architecture, comprising: A first layer including a first device stack and a second device stack, wherein the first device stack is formed in a first device region and the second device stack is formed in a second device region; as well as The second layer, including the interconnect die and interface logic, Wherein the first layer is mounted on top of the second layer.

11. The system according to claim 10, wherein The first device stacks are connected by a first through via, wherein the second device stacks are connected by a second through via, and Wherein the first pass-through pathway and the second pass-through pathway are communicatively coupled to the interface logic. 12 . The system of claim 10 , wherein the first device stack has the same device composition as the second device stack.

13. The system of claim 10, wherein the first device stack differs from the second device stack in device composition.

14. The system of claim 10, wherein The interface logic is arranged between the first device stack and the second device stack, and The interface logic is serial logic.

15. The system of claim 10, wherein The interface logic is arranged on a first side of the first device stack, and the second device stack is arranged on a second side of the first device stack, the second side being opposite to the first side, and The interface logic is parallel logic.

16. A method of forming a package architecture, comprising: forming an interconnect die including embedded interface logic, and forming a wiring layer communicatively coupled to the embedded interface logic; mounting a first device and a second device on the interconnect die, the first device and the second device being communicatively coupled to the wiring layer; installing an additional first device on the first device to form a first device region; mounting an additional second device on the second device to form a second device region; wherein the additional first device is communicatively coupled to the first device; wherein the additional second device is communicatively coupled to the second device; and A molding layer is formed over the interconnect die, the first device region, and the second device region. The method according to claim 16 , wherein the first device region and the second device region have the same device composition.

18. The method of claim 16, wherein a device composition of the first device region is different from a device composition of the second device region.

19. The method of claim 16, wherein mounting the first device and the second device on the interconnect die comprises mounting the first device on a first side of the embedded interface logic and mounting the second device on a second side of the embedded interface logic, wherein the second side is opposite to the first side.

20. The method of claim 16, wherein mounting the first device and the second device on the interconnect die comprises mounting the second device on a first side of the first device and mounting the embedded interface logic on a second side of the first device, wherein the second side is opposite the first side.

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