Preparation method of self-aligned trench device and self-aligned trench device

Abstract

The invention provides a preparation method of a self-aligned trench device and the self-aligned trench device, and relates to the technical field of semiconductors, and the method comprises the steps: carrying out the partition etching of a first region and a second region of a first insulating layer, enabling the first region to form a positioning window, enabling the second region to form a positioning groove, and etching a substrate to form a trench. And preparing a second insulating layer, a first conductive layer and a third insulating layer in the groove, and then etching the first insulating layer and the substrate to form a metal contact hole. Compared with the prior art, the method has the advantages that the positioning grooves are formed by performing partition etching on the first insulating layer, the metal contact holes can be prepared by utilizing a self-alignment process by utilizing the positioning grooves, the alignment precision is high, the grooves and the metal contact holes can be designed on the same layout, additional alignment steps are not needed, the manufacturing process is simplified, and the manufacturing cost is reduced. The use of photoetching and etching steps is reduced, the manufacturing cost is reduced, and the consistency and the yield of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a method for preparing a self-aligned groove device and the self-aligned groove device. Background Art

[0002] With the rapid development of electric vehicles, smart grids, renewable energy conversion systems and other fields, the performance requirements for power semiconductor devices are increasing, including lower energy loss, higher switching speed, stronger thermal stability and longer service life. As an advanced power device structure born in response to these requirements, micro-trench gate devices effectively optimize the electric field distribution and current path inside the device by adopting a fine micro-trench gate design. This design not only significantly reduces the on-resistance of the device and improves its power density, but also enhances the breakdown voltage capability of the device, ensuring stable operation under high voltage and high current conditions. In power semiconductor devices, especially in complex structures such as IGBT (insulated gate bipolar transistor), the electric field distribution and current control at the bottom of the trench are key factors in determining device performance. Traditional device designs often have difficulty in effectively suppressing problems such as electric field concentration and parasitic capacitance, thereby limiting the switching speed, energy efficiency and long-term reliability of the device. In order to solve these problems, a P-type shielding layer technology at the bottom of the trench has been developed. This technology forms an effective electric field shielding layer by introducing a layer of P-type semiconductor material with a specific doping concentration at the bottom of the trench. This P-type shielding layer can guide the electric field distribution to make it more uniform, thereby significantly reducing the electric field concentration effect and reducing the loss of the device under high-voltage working conditions. At the same time, the P-type shielding layer can also effectively suppress the formation of parasitic capacitance and improve the switching speed and dynamic performance of the device.

[0003] The inventors have found through research that in the manufacturing process of micro-trench gate devices, due to the small size of micro-trench unit cells, traditional alignment processes often rely on complex lithography and etching steps, which are not only time-consuming and labor-intensive, but also easily introduce alignment errors, thereby affecting the electrical performance and reliability of the device. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method for preparing a self-aligned groove device and a self-aligned groove device, which utilizes a self-aligned process to prepare metal contact holes with high alignment accuracy, and the grooves and metal contact holes can be designed on the same layout without the need for additional alignment steps, thereby simplifying the manufacturing process, reducing the use of photolithography and etching steps, reducing manufacturing costs, and improving device consistency and yield.

[0005] In a first aspect, the present invention provides a method for preparing a self-aligned trench device, comprising:

[0006] Forming a first doping region of a first conductivity type and a second doping region of a second conductivity type on a substrate, wherein the second doping region and the first doping region are sequentially stacked and distributed on the substrate;

[0007] depositing a first insulating layer on the substrate;

[0008] Etching the first region and the second region of the first insulating layer so that a positioning window without film layer residue is formed in the first region, and a positioning groove with film layer residue is formed in the second region;

[0009] Etching the substrate in the positioning window to form a groove;

[0010] forming a second insulating layer on the sidewalls and bottom wall of the trench;

[0011] depositing a first conductive layer in the trench;

[0012] forming a third insulating layer on the first conductive layer;

[0013] Etching the first insulating layer and the substrate to form metal contact holes at positions corresponding to the positioning grooves;

[0014] Depositing a second conductive layer on the third insulating layer, wherein the second conductive layer covers the first insulating layer and fills the metal contact hole;

[0015] A first buffer layer and a second buffer layer are sequentially deposited on the second conductive layer.

[0016] In an optional implementation, the step of etching the first region and the second region of the first insulating layer includes:

[0017] forming a photoresist layer on a surface of the first insulating layer;

[0018] Expose and develop the photoresist layer using a half-tone mask to remove the photoresist layer corresponding to the first region of the first insulating layer and thin the photoresist layer corresponding to the second region of the first insulating layer;

[0019] The photoresist layer and the first insulating layer are etched so that a positioning window without film layer residue is formed in the first region, and a positioning groove with film layer residue is formed in the second region.

[0020] In an optional embodiment, the depth of the trench is greater than the sum of the thicknesses of the first doping region and the second doping region, so that the trench passes through the first doping region and the second doping region.

[0021] In an optional embodiment, the step of forming a second insulating layer on the sidewalls and bottom wall of the trench includes:

[0022] The sidewalls and bottom wall of the trench are thermally oxidized to generate gate oxide, so that the sidewalls and bottom wall of the trench form the second insulating layer.

[0023] In an optional embodiment, before the step of forming a second insulating layer on the sidewalls and bottom wall of the trench, the preparation method further includes:

[0024] Thermally oxidizing the sidewalls and bottom wall of the trench to form a sacrificial oxide layer;

[0025] Implanting a third doping region of the second conductivity type into the bottom wall of the trench;

[0026] The sacrificial oxide layer is removed by etching.

[0027] In an optional embodiment, the step of forming a third insulating layer on the first conductive layer includes:

[0028] Silicon oxide is generated by thermal oxidation on the top of the first conductive layer to form the third insulating layer.

[0029] In an optional embodiment, the step of etching the first insulating layer and the substrate includes:

[0030] Etching the first insulating layer to expose the substrate corresponding to the positioning groove;

[0031] The substrate corresponding to the positioning groove is etched to form the metal contact hole.

[0032] In an optional implementation, the metal contact hole passes through the first doping layer.

[0033] In an optional embodiment, after the step of etching the substrate corresponding to the positioning groove, the preparation method further includes:

[0034] A fourth doping region of the second conductivity type is formed by implanting at the bottom wall of the metal contact hole.

[0035] In a second aspect, the present invention provides a self-aligned trench device, which is prepared by the method for preparing a self-aligned trench device as described in any one of the aforementioned embodiments, and the self-aligned trench device comprises:

[0036] A substrate, on which a first doping region of a first conductivity type and a second doping region of a second conductivity type are disposed, and the second doping region and the first doping region are sequentially stacked and distributed on the substrate;

[0037] A first insulating layer, which is disposed on the substrate and is provided with a positioning window and a metal contact hole, and the substrate at the positioning window is provided with a groove;

[0038] a second insulating layer, the second insulating layer being disposed on the sidewalls and the bottom wall of the trench;

[0039] a first conductive layer, wherein the first conductive layer is disposed in the groove;

[0040] a third insulating layer, the third insulating layer being disposed on the first conductive layer and extending to the positioning window;

[0041] a second conductive layer, wherein the second conductive layer is disposed on the third insulating layer and covers the first insulating layer, and the second conductive layer fills the metal contact hole; and a first buffer layer, wherein the first buffer layer is disposed on the second conductive layer;

[0042] A second buffer layer is disposed on the first buffer layer.

[0043] The method for preparing a self-aligned groove device and the self-aligned groove device provided in the embodiment of the present invention adopt a special process to perform partition etching on the first area and the second area of ​​the first insulating layer, so that a positioning window is formed in the first area and a positioning groove is formed in the second area. The positioning window can be used to prepare the subsequent groove, and the positioning groove can be used to prepare the subsequent metal contact hole, so that the groove and the metal contact hole can be designed on the same layout. Specifically, the substrate is etched through the positioning window to form a groove, and the second insulating layer, the first conductive layer and the third insulating layer are prepared in the groove, and then the first insulating layer is etched to expose the substrate at the positioning groove. At this time, the remaining first insulating layer can form a mask and then the substrate is etched to form a metal contact hole, so that the metal contact hole is self-aligned. Since the positioning groove has accurately positioned the position of the metal contact hole, no additional alignment steps are required, and the metal contact hole can be prepared using the self-alignment process. Compared with the prior art which requires an additional alignment step (additional mask design), the embodiment of the present invention forms positioning grooves by partitioned etching of the first insulating layer. The positioning grooves can be used to achieve self-alignment of the metal contact holes. The metal contact holes are prepared using a self-alignment process with high alignment accuracy. The grooves and metal contact holes can be designed on the same layout without the need for additional alignment steps, thereby simplifying the manufacturing process, reducing the use of photolithography and etching steps, reducing manufacturing costs, and improving device consistency and yield.

[0044] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A flowchart showing a method for preparing a self-aligned trench device provided by an embodiment of the present invention is shown;

[0047] Figures 2 to 12 A process flow chart of a method for preparing a self-aligned trench device provided by an embodiment of the present invention is shown;

[0048] Fig.13 A schematic structural diagram of a self-aligned trench device provided by an embodiment of the present invention is shown.

[0049] Description of main component symbols:

[0050] 100-self-aligned groove device; 110-substrate; 111-first doping region; 112-second doping region; 113-groove; 114-third doping region; 115-fourth doping region; 120-first insulating layer; 121-positioning window; 122-positioning groove; 123-metal contact hole; 130-second insulating layer; 140-third insulating layer; 150-first conductive layer; 160-second conductive layer; 170-first buffer layer; 180-second buffer layer; 190-photoresist layer; 200-half-tone mask. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0052] As disclosed in the background technology, in the prior art, during the manufacturing process of the micro-groove 113 gate device, due to the small size of the micro-groove 113 unit cell, the traditional alignment process often relies on complex photolithography and etching steps, which are not only time-consuming and labor-intensive, but also easily introduce alignment errors, thereby affecting the electrical performance and reliability of the device.

[0053] In view of this, the present application introduces a self-alignment process, which can cleverly utilize the natural growth or etching characteristics of semiconductor materials under specific conditions, so that key structures such as the gate and the source (or drain) can be automatically and accurately positioned without the need for additional alignment steps. Through the self-alignment process, the alignment accuracy between the gate and the source of the micro-groove 113 gate device has been significantly improved, thereby reducing the on-resistance of the device, improving the switching speed, and enhancing the breakdown voltage capability of the device. In addition, the self-alignment process also simplifies the manufacturing process, reduces the use of photolithography and etching steps, reduces manufacturing costs, and improves the consistency and yield rate of the device. Therefore, the application of the self-alignment process in the micro-groove 113 gate technology not only promotes the improvement of device performance, but also promotes the optimization of manufacturing efficiency, and lays a solid foundation for the wide application of micro-groove 113 gate devices in high-performance, high-reliability application fields such as electric vehicles and smart grids.

[0054] The following is a detailed description of a method for preparing a self-aligned trench device 100 and the self-aligned trench device 100 provided in an embodiment of the present invention. It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0055] See also Figure 1 An embodiment of the present invention provides a method for preparing a self-aligned groove device 100, which is used to prepare the self-aligned groove device 100. The preparation method can use a self-alignment process to prepare a metal contact hole 123 with high alignment accuracy. The groove 113 and the metal contact hole 123 can be designed on the same layout without the need for additional alignment steps, thereby simplifying the manufacturing process, reducing the use of photolithography and etching steps, reducing manufacturing costs, and improving device consistency and yield.

[0056] The method for preparing the self-aligned trench device 100 provided in the embodiment of the present invention comprises the following process steps:

[0057] S1: forming a first doping region 111 of a first conductivity type and a second doping region 112 of a second conductivity type on a substrate 110 .

[0058] See also Figure 2, wherein the second doping region 112 and the first doping region 111 are sequentially stacked and distributed on the substrate 110. Specifically, a substrate 110 may be provided first, and a first doping region 111 of a first conductivity type and a second doping region 112 of a second conductivity type may be formed on the substrate 110 by ion implantation and diffusion processes, wherein the first doping region 111 is located above the second doping region 112 and is located on one side surface of the substrate 110. The material of the substrate 110 includes but is not limited to silicon, silicon carbide, gallium nitride, gallium arsenide, diamond, etc., and the conductivity type is N-type or P-type, and the conductivity type of the substrate 110 may be referred to as the first conductivity type. At the same time, the first doping region 111 is a first conductivity type with a higher doping concentration than the substrate 110, and the doping impurities include phosphorus, arsenic, selenium, sulfur, etc. The second doping region 112 is a P-type or N-type semiconductor, referred to as the second conductivity type, and the doping impurities include boron, aluminum, gallium, etc.

[0059] It should be noted that, in this embodiment, the injection energy of the first doping region 111 may be 20-200 keV, with a dose of 1E13-1E16, and the injection energy of the second doping region 112 may be 50-300 keV, with a dose of 1E13-1E14.

[0060] S2 : depositing a first insulating layer 120 on the substrate 110 .

[0061] See also Figure 3 Specifically, a layer of dielectric material can be deposited by CVD to form the first insulating layer 120. The material of the first insulating layer 120 includes but is not limited to silicon oxide, silicon nitride, etc. The first insulating layer 120 can be used as a hard mask when the trench 113 is subsequently etched and formed, and the thickness thereof is 5000A-20000A.

[0062] S3: etching the first region and the second region of the first insulating layer 120 .

[0063] See also Figure 4 and Figure 5 In this embodiment, a half tone mask 200 (HTM) can be used to etch different regions of the first insulating layer 120, so that a positioning window 121 without film layer residue is formed in the first region A1, and a positioning groove 122 with film layer residue is formed in the second region A2.

[0064] Specifically, a photoresist layer 190 may be first formed on the surface of the first insulating layer 120, and then the photoresist layer 190 may be exposed and developed using a half-tone mask 200 to remove the photoresist layer 190 corresponding to the first area A1 of the first insulating layer 120, and to thin the photoresist layer 190 corresponding to the second area A2 of the first insulating layer 120. Figure 4; Then the photoresist layer 190 and the first insulating layer 120 are etched to form a positioning window 121 without film layer residue in the first region A1, and a positioning groove 122 with film layer residue is formed in the second region A2, such as Figure 5 The positioning window 121 can be used as an etching window for the subsequent groove 113, and the positioning groove 122 can be used as an etching window for the subsequent metal contact hole 123. Therefore, the patterns of the groove 113 and the metal contact hole 123 can be designed on the same layout, and the patterns are transferred to the first insulating layer 120 through exposure, development and etching through a half tone mask to form a positioning window 121 (a region where the groove 113 is to be formed) without film layer residue and a positioning groove 122 (a region where the metal contact hole 123 is to be formed) with a certain film layer thickness.

[0065] The photoresist layer 190 can be formed by spin coating, baking, exposure and development, with a thickness of 2000A-20000A. When etching the first insulating layer 120, a dry etching process or a wet etching process can be used.

[0066] S4 : etching the substrate 110 in the positioning window 121 to form a groove 113 .

[0067] See also Figure 6 Specifically, the substrate 110 is etched with the first insulating layer 120 as a hard mask to form a deep trench 113, the depth of which is greater than the sum of the thicknesses of the first doping region 111 and the second doping region 112, so that the trench 113 passes through the first doping region 111 and the second doping region 112. The etching of the substrate 110 may be dry etching or wet etching, the trench 113 has an etching depth of 2 μm-6 μm, a width of the trench 113 of 100 nm-1500 nm, and a distance between adjacent trenches 113 of 100 nm-2000 nm.

[0068] S5 : forming a second insulating layer 130 on the sidewalls and bottom wall of the trench 113 .

[0069] See also Figure 7 Here, the sidewalls and bottom walls of the trench 113 can be thermally oxidized to generate gate oxide, so that the sidewalls and bottom walls of the trench 113 form a second insulating layer 130. Before forming the second insulating layer 130, it is also necessary to form a third doping region 114 on the bottom wall of the trench 113. Specifically, the sidewalls of the trench 113 are first thermally oxidized to form a sacrificial oxide layer, and then the third doping region 114 of the second conductivity type is implanted into the bottom wall of the trench 113, and then the sacrificial oxide layer is etched away. By forming a sacrificial oxide layer and then etching away, the sidewall morphology of the trench 113 can be made smoother and the sidewall defects can be reduced.

[0070] In actual preparation, silicon oxide can be first generated on the side wall of the groove 113 by thermal oxidation to form a sacrificial oxide layer, and then injected to form the third doping region 114, thereby forming a P-type shielding layer, and then the sacrificial oxide layer is etched away and then thermally oxidized to generate gate oxide, thereby forming a second insulating layer 130 on the side wall and bottom wall of the groove 113.

[0071] The material of the second insulating layer 130 includes but is not limited to silicon oxide, silicon nitride, etc. The third doping region 114 is a P-type or N-type semiconductor with a lower doping concentration than the first doping region 111, called the second conductivity type, and the doping impurities include boron, aluminum, gallium, etc. The injection energy of the third doping region 114 is 20-100keV, and the dose is 1E11-1E13. At the same time, the second insulating layer 130 is formed by thermal growth to form a gate oxide layer, and its thickness is 500-3000A.

[0072] S6 : depositing a first conductive layer 150 in the trench 113 .

[0073] See also Figure 8 and Fig. 9 Specifically, the first conductive layer 150 can be formed by deposition through a CVD process. After deposition, the first conductive layer 150 outside the trench 113 needs to be etched, and the etching process is dry etching or wet etching, so that the first conductive layer 150 is confined within the trench 113, and the top side of the first conductive layer 150 is preferably flush with the opening position of the trench 113. The first conductive layer 150 is a gate, and the material includes but is not limited to polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon, etc., and preferably can be polysilicon.

[0074] S7 : forming a third insulating layer 140 on the first conductive layer 150 .

[0075] See also Fig.10 Specifically, silicon oxide can be generated by thermal oxidation on the top of the first conductive layer 150 to form the third insulating layer 140. The first conductive layer 150 at the top of the trench 113 is exposed to the positioning window 121, and the first conductive layer 150 at the top of the trench 113 is thermally oxidized to generate silicon oxide, thereby forming the third insulating layer 140. Here, the third insulating layer 140 can be used as a hard mask layer for subsequent etching.

[0076] S8: etching the first insulating layer 120 and the substrate 110 to form metal contact holes 123 at positions corresponding to the positioning grooves 122 .

[0077] See also Fig.11 and Fig.12Specifically, the first etching may be performed first, with the substrate 110 as an etching stop layer, the first insulating layer 120 is etched, and the substrate 110 corresponding to the positioning groove 122 is exposed, and then the second etching is performed, with the remaining first insulating layer 120 and the third insulating layer 140 as hard masks, the substrate 110 corresponding to the positioning groove 122 is etched to form a metal contact hole 123, and then the fourth doping region 115 of the second conductivity type is implanted at the bottom wall of the metal contact hole 123. The metal contact hole 123 may be formed on the first insulating layer 120 and extend downward into the substrate 110, that is, the metal contact hole 123 extends from the first insulating layer 120 to the second doping region 112 in the substrate 110.

[0078] It should be noted that, when etching the first insulating layer 120, due to the presence of the positioning groove 122, the entire first insulating layer 120 will not be completely etched away when the substrate 110 is exposed, but a certain thickness of the first insulating layer 120 will remain on both sides of the positioning groove 122. The third insulating layer 140 formed by thermal growth of the remaining first insulating layer 120 and the top of the trench 113 can form a complete hard mask layer for etching the metal contact hole 123, thereby forming the metal contact hole 123 in a self-aligned manner.

[0079] The metal contact hole 123 passes through the first insulating layer 120 and the first doping layer, and extends to the second doping region 112. The fourth doping region 115 can be formed at the bottom of the metal contact hole 123 by ion implantation and diffusion process, and the fourth doping region 115 is a P-type or N-type semiconductor with a higher concentration, called the second conductivity type, and the doping impurities include boron, aluminum, gallium, etc., and the implantation energy is 20-100 keV, and the dose is 1E13-1E16.

[0080] It should be noted that, in this embodiment, the thickness of the third insulating layer 140 and the depth of the positioning groove 122 can be set so that the first insulating layer 120 remaining after the metal contact hole 123 is formed is flush with the third insulating layer 140, thereby improving its flatness and facilitating the subsequent deposition to form the second conductive layer 160.

[0081] S9 : depositing a second conductive layer 160 on the third insulating layer 140 .

[0082] See also Fig.13 , wherein the second conductive layer 160 covers the first insulating layer 120 and fills the metal contact hole 123. Specifically, in actual preparation, the second conductive layer 160 can be deposited on the third insulating layer 140 and the first insulating layer 120, and a corresponding pattern can be etched, wherein the second conductive layer 160 fills the metal contact hole 123. The thickness of the second conductive layer 160 is 1 μm-6 μm, and the deposition process is evaporation or sputtering.

[0083] It should be noted that the second conductive layer 160 here is an electrode, and its material includes but is not limited to polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon.

[0084] S10 : depositing a first buffer layer 170 and a second buffer layer 180 sequentially on the second conductive layer 160 .

[0085] Please continue to see Fig.13 Specifically, after forming the second conductive layer 160, the first buffer layer 170 and the second buffer layer 180 can be sequentially prepared and patterned. The material of the first buffer layer 170 includes but is not limited to silicon oxide, silicon nitride, etc. The material of the second buffer layer 180 includes but is not limited to polyimide, etc. The thickness of the first buffer layer 170 is 1000A-20000A, and it is prepared by CVD, and the etching process is dry etching or wet etching. At the same time, the thickness of the second buffer layer 180 is 50000A-150000A, and it is prepared by photolithography.

[0086] The preparation method provided by the embodiment of the present invention mainly designs the groove 113 and the metal contact hole 123 on a layout, and transfers the pattern to the first insulating layer 120 through exposure, development and etching through a half tone mask, forming a positioning window 121 (the area to be formed of the groove 113) without film layer residue and a positioning groove 122 (the area to be formed of the metal contact hole 123) with a certain film layer thickness. Then, the first insulating layer 120 is used as the first hard mask, the substrate 110 is etched to form the groove 113, and then thermally oxidized to form a sacrificial oxide layer and ion implanted to form a P-type shielding layer directly below the groove 113. Then, the sacrificial oxide layer is etched away and thermally grown to form a gate oxide. Then, the gate is filled and etched. Then, the top of the gate of the groove 113 is thermally grown to oxidize into silicon oxide to form the third insulating layer 140. The first insulating layer 120 is etched again to expose the area to be formed of the metal contact hole 123. At this time, the first insulating layer 120 of a certain thickness still exists in other areas except the positions of the groove 113 and the metal contact hole 123. The remaining film layer of the first insulating layer 120 and the third insulating layer 140 formed by thermal growth on the top of the trench 113 together form a complete second hard mask for etching the metal contact hole 123, thereby forming the metal contact hole 123 in a self-aligned manner.

[0087] The preparation method provided by the embodiment of the present invention is an improvement on the preparation process of the electrode metal contact hole 123 of the groove 113 type power semiconductor chip. Specifically, after the first insulating layer 120 is deposited, the half tone mask of the custom groove 113 and the electrode metal contact hole 123 during the layout design is used for exposure, development and etching. During exposure, the mask groove 113 area is fully transparent, and the metal contact hole 123 area is partially transparent. Through the different light intensities through the mask, after development, the groove 113 area is ensured to be free of photoresist, and the metal contact hole 123 area has a certain thickness of photoresist due to partial exposure. Then, etching is performed to form a completely etched positioning window 121 (groove 113 to be formed area) and an incompletely etched positioning groove 122 (metal contact hole 123 to be formed area) on the first insulating layer 120. By controlling the remaining film thickness of the positioning groove 122 of the first insulating layer 120, after further etching to form the groove 113, the positioning groove 122 still has a certain thickness of the first insulating layer 120. Then, thermal growth is performed to form a sacrificial oxide layer and ion implantation is performed to form a P-type electric field shielding region directly below the trench 113. The sacrificial oxide layer is then etched away and thermal growth is performed to form a gate oxide, i.e., a second insulating layer 130. Then, polysilicon is deposited and a polysilicon gate is etched. Thermal growth is performed again to oxidize the polysilicon at the top of the trench 113 to form silicon oxide for insulation protection, and a third insulating layer 140 is formed. The first insulating layer 120 is then etched to expose the area where the metal contact hole 123 is to be formed. At this time, a certain thickness of the first insulating layer 120 still exists in other areas except for the trench 113 and the metal contact hole 123 area. At this time, the remaining first insulating layer 120 and the third insulating layer 140 at the top of the trench 113 are used as a complete second hard mask to self-align and etch the metal contact hole 123, thereby realizing the preparation of a high-precision electrode contact hole through a self-alignment process and a hard mask process, and a complete second hard mask is used as an insulation protection between the gate and the emitter. The self-aligned metal contact hole 123 formed by this scheme is completely determined by the layout design and has a high degree of design freedom. And designing the groove 113 and the metal contact hole 123 on one layout can save a photomask and simplify the process flow. Moreover, the first conductive type source region is less affected by the process, which is mainly determined during the design, and can ensure the area and dose of the source region, so that the current density and on-resistance of the device are controllable. This scheme is compatible with the traditional groove 113 gate structure manufacturing method in terms of process, especially in the development of micro-groove 113 gate structure towards narrower and smaller spacing. This method can avoid the problems of threshold drift, GE short circuit caused by the offset of the metal electrode hole due to overlay deviation in the lithography process. In addition, it can also achieve a smaller cell size, a narrower hole current path, improve the electron injection efficiency, and better coordinate the compromise relationship between the on-state voltage drop and the switching loss.This structure can effectively reduce the cell size of the micro-groove 113-gate power semiconductor chip and reduce the photolithography accuracy requirements on the process platform.

[0088] See also Fig.13 The embodiment of the present invention further provides a self-aligned groove device 100, which is prepared by the preparation method of the self-aligned groove device 100 as described above. The self-aligned groove device 100 includes a substrate 110, a first insulating layer 120, a second insulating layer 130, a third insulating layer 140, a first conductive layer 150, a second conductive layer 160, a first buffer layer 170, and a second buffer layer 180. A first doping region 111 of a first conductive type and a second doping region 112 of a second conductive type are provided on the substrate 110. The second doping region 112 and the first doping region 111 are sequentially stacked and distributed on the substrate 110. The first insulating layer 120 is provided on the substrate 110, and a fixed A positioning window 121 and a metal contact hole 123 are formed, and a groove 113 is provided on the substrate 110 at the positioning window 121; a second insulating layer 130 is provided on the side walls and the bottom wall of the groove 113; a first conductive layer 150 is provided in the groove 113; a third insulating layer 140 is provided on the first conductive layer 150 and extends to the positioning window 121; a second conductive layer 160 is provided on the third insulating layer 140 and covers the first insulating layer 120, and the second conductive layer 160 is filled to the metal contact hole 123; a first buffer layer 170, and the first buffer layer 170 is provided on the second conductive layer 160; a second buffer layer 180, and the second buffer layer 180 is provided on the first buffer layer 170.

[0089] To summarize, the preparation method of the self-aligned groove device 100 and the self-aligned groove device 100 provided in the embodiment of the present invention use a halftone mask process to perform partitioned etching on the first area and the second area of ​​the first insulating layer 120, so that a positioning window 121 is formed in the first area and a positioning groove 122 is formed in the second area. The subsequent preparation of the groove 113 can be achieved through the positioning window 121, and the subsequent preparation of the metal contact hole 123 can be achieved through the positioning groove 122, so that the groove 113 and the metal contact hole 123 can be designed on the same layout. Specifically, the substrate 110 is etched through the positioning window 121 to form the groove 113, and the second insulating layer 130, the first conductive layer 150 and the third insulating layer 140 are prepared in the groove 113, and then the first insulating layer 120 is etched to expose the substrate 110 at the positioning groove 122. At this time, the remaining first insulating layer 120 can form a mask and then the substrate 110 is etched to form the metal contact hole 123, so as to self-align and form the metal contact hole 123. Since the positioning groove 122 has accurately positioned the position of the metal contact hole 123, no additional alignment step is required, and the metal contact hole 123 can be prepared by using the self-alignment process. Compared with the prior art which requires an additional alignment step (additional mask design), the embodiment of the present invention forms a positioning groove 122 by etching a partition of the first insulating layer 120. The positioning groove 122 can be used to achieve self-alignment of the metal contact hole 123. The metal contact hole 123 is prepared using a self-alignment process with high alignment accuracy. The groove 113 and the metal contact hole 123 can be designed on the same layout without the need for an additional alignment step, thereby simplifying the manufacturing process, reducing the use of photolithography and etching steps, reducing manufacturing costs, and improving device consistency and yield.

[0090] In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the invented product is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0091] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly stipulated and limited, the terms "setting", "deposition", "extension", "generation" and "formation" should be understood in a broad sense. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0092] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or perform equivalent replacements on some of the technical features thereof; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. They should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a self-aligned trench device, characterized in that: include: Forming a first doping region of a first conductivity type and a second doping region of a second conductivity type on a substrate, wherein the second doping region and the first doping region are sequentially stacked and distributed on the substrate; depositing a first insulating layer on the substrate; Etching the first region and the second region of the first insulating layer so that a positioning window without film layer residue is formed in the first region, and a positioning groove with film layer residue is formed in the second region; Etching the substrate in the positioning window to form a groove; forming a second insulating layer on the sidewalls and bottom wall of the trench; depositing a first conductive layer in the trench; forming a third insulating layer on the first conductive layer; Etching the first insulating layer and the substrate to form metal contact holes at positions corresponding to the positioning grooves; Depositing a second conductive layer on the third insulating layer, wherein the second conductive layer covers the first insulating layer and fills the metal contact hole; A first buffer layer and a second buffer layer are sequentially deposited on the second conductive layer.

2. The method for preparing a self-aligned trench device according to claim 1, characterized in that: The step of etching the first region and the second region of the first insulating layer comprises: forming a photoresist layer on a surface of the first insulating layer; Expose and develop the photoresist layer using a half-tone mask to remove the photoresist layer corresponding to the first region of the first insulating layer and thin the photoresist layer corresponding to the second region of the first insulating layer; The photoresist layer and the first insulating layer are etched so that a positioning window without film layer residue is formed in the first region, and a positioning groove with film layer residue is formed in the second region.

3. The method for preparing a self-aligned trench device according to claim 1, characterized in that: The depth of the trench is greater than the sum of the thicknesses of the first doping region and the second doping region, so that the trench passes through the first doping region and the second doping region.

4. The method for preparing a self-aligned trench device according to claim 1, characterized in that: The step of forming a second insulating layer on the sidewalls and bottom wall of the trench comprises: The sidewalls and bottom wall of the trench are thermally oxidized to generate gate oxide, so that the sidewalls and bottom wall of the trench form the second insulating layer.

5. The method for preparing a self-aligned trench device according to claim 1 or 4, characterized in that: Before the step of forming a second insulating layer on the sidewalls and bottom wall of the trench, the preparation method further comprises: Thermally oxidizing the sidewalls and bottom wall of the trench to form a sacrificial oxide layer; Implanting a third doping region of the second conductivity type into the bottom wall of the trench; The sacrificial oxide layer is removed by etching.

6. The method for preparing a self-aligned trench device according to claim 1, characterized in that: The step of forming a third insulating layer on the first conductive layer comprises: Silicon oxide is generated by thermal oxidation on the top of the first conductive layer to form the third insulating layer.

7. The method for preparing a self-aligned trench device according to claim 1, characterized in that: The step of etching the first insulating layer and the substrate comprises: Etching the first insulating layer to expose the substrate corresponding to the positioning groove; The substrate corresponding to the positioning groove is etched to form the metal contact hole.

8. The method for preparing a self-aligned trench device according to claim 7, characterized in that: The metal contact hole passes through the first insulating layer and the first doping layer in sequence.

9. The method for preparing a self-aligned trench device according to claim 7, characterized in that: After the step of etching the substrate corresponding to the positioning groove, the preparation method further includes: A fourth doping region of the second conductivity type is formed by implanting at the bottom wall of the metal contact hole.

10. A self-aligned trench device, manufactured by the method for manufacturing a self-aligned trench device according to any one of claims 1 to 9, characterized in that: The self-aligned trench device comprises: A substrate, on which a first doping region of a first conductivity type and a second doping region of a second conductivity type are disposed, and the second doping region and the first doping region are sequentially stacked and distributed on the substrate; A first insulating layer, which is disposed on the substrate and is provided with a positioning window and a metal contact hole, and the substrate at the positioning window is provided with a groove; a second insulating layer, the second insulating layer being disposed on the sidewalls and the bottom wall of the trench; a first conductive layer, wherein the first conductive layer is disposed in the groove; a third insulating layer, the third insulating layer being disposed on the first conductive layer and extending to the positioning window; a second conductive layer, wherein the second conductive layer is disposed on the third insulating layer and covers the first insulating layer, and the second conductive layer fills the metal contact hole; a first buffer layer, wherein the first buffer layer is disposed on the second conductive layer; A second buffer layer is disposed on the first buffer layer.

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