C: GaN gate enhanced HEMT device and preparation method thereof

Abstract

The invention discloses a C: GaN gate enhanced HEMT (High Electron Mobility Transistor) device and a preparation method thereof, the device comprises a substrate layer, a nucleating layer, a high-resistance buffer layer, a back barrier layer, a GaN channel layer, an insertion layer and a barrier layer which are sequentially arranged from bottom to top, and a C-doped C: GaN cap layer and a TiN metal layer are sequentially arranged in the middle of the upper surface of the barrier layer; two sides of the upper surface of the barrier layer respectively comprise a first ion implantation region and a second ion implantation region; a source electrode and a drain electrode are arranged on the inner sides of the first ion implantation region and the second ion implantation region respectively, and the lower surfaces of the source electrode and the drain electrode are both in contact with the GaN channel layer; passivation layers are arranged on the upper surfaces of the TiN metal layer and the barrier layer and on the two sides of the C: GaN cap layer, and a gate electrode is arranged on the upper surface of the C: GaN cap layer. By arranging the C: GaN cap layer and the back barrier layer, the grid electric leakage is effectively reduced, the positive withstand voltage of the grid is improved, and an enhanced device with stable threshold voltage is obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a C:GaN gate-enhanced HEMT device and a preparation method thereof. Background Art

[0002] In the field of semiconductor devices, High Electron Mobility Transistor (HEMT) plays an indispensable role in high-power and high-bandwidth circuits due to its high breakdown electric field, polarization-induced high mobility, high switching speed, and high-density two-dimensional electron gas (2DEG) formed at the heterojunction interface.

[0003] Gallium nitride (GaN) is a wide bandgap semiconductor material with excellent properties and good application prospects. In order to give full play to the superior performance of GaN devices and carry out research based on GaN monolithic integrated circuits, enhanced HEMT devices are needed in practical application scenarios. At present, the methods for preparing enhanced HEMT devices include gate grooves, thin barrier layers, p-GaN gates, and fluorine plasma injection.

[0004] However, in practical applications, the enhanced HEMT prepared by the above method has problems such as low forward withstand voltage, large gate leakage current, small saturation current, complex process and poor repeatability. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a C:GaN gate-enhanced HEMT device and a method for preparing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] One aspect of the present invention provides a C:GaN gate-enhanced HEMT device, comprising a substrate layer, a nucleation layer, a high-resistance buffer layer, a back barrier layer, a GaN channel layer, an insertion layer and a barrier layer arranged in sequence from bottom to top, wherein:

[0007] A C-doped C:GaN cap layer and a TiN metal layer are sequentially arranged in the middle of the upper surface of the barrier layer from bottom to top;

[0008] Both sides of the upper surface of the barrier layer include a first ion implantation region and a second ion implantation region, respectively, wherein the first ion implantation region and the second ion implantation region both extend downward from the upper surface of the barrier layer to the upper surface of the back barrier layer;

[0009] A source electrode and a drain electrode are respectively disposed inside the first ion implantation region and the second ion implantation region, and the lower surfaces of the source electrode and the drain electrode are in contact with the GaN channel layer;

[0010] A passivation layer is disposed on the upper surfaces of the TiN metal layer and the barrier layer and on both sides of the C:GaN cap layer. A gate electrode is disposed on the upper surface of the C:GaN cap layer.

[0011] In one embodiment of the present invention, the material used for the barrier layer is Al x Ga 1-x N, wherein x=0.1-0.5, and the thickness of the barrier layer is 10-30 nm.

[0012] In one embodiment of the present invention, the material used for the back barrier layer is Al a Ga 1-a N, wherein a=0.05-0.2, and the thickness of the back barrier layer is 100-500 nm.

[0013] In one embodiment of the present invention, the doping concentration of the C element in the C:GaN cap layer is 10 18 ~10 20 cm -3 , the thickness of the C:GaN cap layer is 50 to 200 nm.

[0014] In one embodiment of the present invention, the implanted ions in the first ion implantation region and the second ion implantation region are N ions with an implantation concentration of 10 18 ~10 20 cm -3 .

[0015] In one embodiment of the present invention, a gate window is opened on the passivation layer on the upper surface of the TiN metal layer, and the gate electrode is arranged in the gate window.

[0016] In one embodiment of the present invention, the material of the passivation layer includes one or more of SiO2, SiN, AlON or Al2O3.

[0017] In one embodiment of the present invention, the material of the gate electrode is Ti, Al, Ti / Al or TiN / Ti / Al / TiN; the material of the source electrode and the drain electrode is Ti, Al or a metal composite layer or alloy containing Ti / Al.

[0018] Another aspect of the present invention provides a method for preparing a C:GaN gate enhancement mode HEMT device, comprising:

[0019] Step 1: epitaxially growing a nucleation layer, a high-resistance buffer layer, a back barrier layer, a GaN channel layer, an insertion layer, a barrier layer and a C-doped C:GaN cap layer on the substrate layer in sequence;

[0020] Step 2: depositing TiN metal on the upper surface of the C:GaN cap layer to form a TiN metal layer;

[0021] Step 3: performing ion implantation on the left and right sides of the upper surface of the TiN metal layer to form a first ion implantation region and a second ion implantation region extending to the lower surface of the GaN channel layer;

[0022] Step 4: Determine the gate region, and etch the TiN metal layer and the C:GaN cap layer outside the gate region;

[0023] Step 5: depositing a dielectric material on the upper surfaces of the TiN metal layer and the barrier layer and on both sides of the C:GaN cap layer to form a passivation layer;

[0024] Step 6: etching the passivation layer in the gate region to form a gate window extending to the upper surface of the TiN metal layer, and depositing a gate metal inside the gate window to form a gate electrode;

[0025] Step 7: forming a source electrode and a drain electrode inside the first ion implantation region and the second ion implantation region, wherein lower surfaces of the source electrode and the drain electrode are in contact with the GaN channel layer.

[0026] In one embodiment of the present invention, the S6 includes:

[0027] The passivation layer in the gate area is etched by photolithography and development technology until the upper surface of the TiN metal layer forms a gate window, and the gate metal is deposited in the gate window by physical vapor deposition to form a gate electrode. The material of the gate layer is Ti, Al, Ti / Al or TiN / Ti / Al / TiN.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The present invention obtains a usable enhanced HEMT device structure by providing a C:GaN cap layer and a back barrier layer, effectively reduces gate leakage, improves the gate forward withstand voltage, and obtains an enhanced device with a stable threshold voltage.

[0030] 2. The C:GaN gate-enhanced HEMT device of the present invention uses AlGaN as a back barrier layer, raises the conduction band of the GaN channel layer, thereby reducing the leakage path to the high-resistance buffer layer, enhancing the confinement of channel carriers, and limiting the 2EDG in a narrow channel, thereby increasing the density of the device 2EDG and reducing the current collapse phenomenon; a C-doped GaN cap layer is used, and the C element is doped to make the C:GaN show shallow acceptor characteristics, deplete part of the charge in the two-dimensional electron gas, and increase the threshold voltage and gate forward withstand voltage of the device; negatively polarized charges exist at the interface between the thick AlGaN back barrier layer and the GaN channel layer of the present invention, acting as virtual p-type doping, which increases the energy band of the GaN layer and further increases the threshold voltage of the HEMT device.

[0031] 3. The preparation method of the present invention is compatible with the current process of p-GaN HEMT, the preparation process is simple, and no complicated groove etching is required.

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic structural diagram of a C:GaN gate enhancement type HEMT device provided by an embodiment of the present invention;

[0034] Figure 2 It is a flow chart of a method for preparing a C:GaN gate enhancement type HEMT device provided by an embodiment of the present invention;

[0035] Figure 3a to Figure 3g It is a schematic diagram of a preparation process of a C:GaN gate enhancement type HEMT device provided in an embodiment of the present invention.

[0036] Description of reference numerals:

[0037] 1. Substrate layer; 2. Nucleation layer; 3. High-resistance buffer layer; 4. Back barrier layer; 5. GaN channel layer; 6. AlN insertion layer; 7. Barrier layer; 8. C:GaN cap layer; 9. TiN metal layer; 10. Passivation layer; 11. Gate electrode; 12. Source electrode; 13. Drain electrode; 14. First ion implantation region; 15-Second ion implantation region. DETAILED DESCRIPTION

[0038] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a C:GaN gate enhancement type HEMT device and a preparation method thereof proposed in accordance with the present invention are described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0039] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0040] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0041] Embodiment 1

[0042] See also Figure 1 , Figure 1 The schematic diagram of the structure of a C:GaN gate-enhanced HEMT device provided by an embodiment of the present invention is a schematic diagram of the structure of a C:GaN gate-enhanced HEMT device. The C:GaN gate-enhanced HEMT device improves the current density and gate forward withstand voltage of the device and reduces the leakage of the device while ensuring the device is enhanced. The C:GaN gate-enhanced HEMT device comprises a substrate layer 1, a nucleation layer 2, a high-resistance buffer layer 3, a back barrier layer 4, a GaN channel layer 5, an insertion layer 6 and a barrier layer 7 which are sequentially arranged from bottom to top, wherein a C-doped C:GaN cap layer 8 and a TiN metal layer 9 are sequentially arranged from bottom to top in the middle of the upper surface of the barrier layer 7; both sides of the upper surface of the barrier layer 7 respectively comprise a first ion implantation region 14 and a second ion implantation region 15, and both the first ion implantation region 14 and the second ion implantation region 15 extend downward from the upper surface of the barrier layer 7 to the upper surface of the back barrier layer 4; a source electrode 12 and a drain electrode 13 are respectively arranged inside the first ion implantation region 14 and the second ion implantation region 15, and the lower surfaces of the source electrode 12 and the drain electrode 13 are in contact with the GaN channel layer 5; a passivation layer 10 is arranged on the upper surfaces of the TiN metal layer 9 and the barrier layer 7 and both sides of the C:GaN cap layer 8, and a gate electrode 11 is arranged on the upper surface of the C:GaN cap layer.

[0043] In this embodiment, the substrate layer 1 can be made of sapphire, Si or SiC. The material of the nucleation layer 2 is AlN with a thickness of 50-500 nm; the material of the high-resistance buffer layer 3 is GaN doped with C, where the doping concentration of C is 10 17 ~1020 cm -3 , thickness is 800~6000nm; the material of back barrier layer 4 is Al a Ga 1-a N, wherein a=0.05-0.2, the thickness of the back barrier layer 4 is 100-500 nm; the thickness of the GaN channel layer 5 is 50-500 nm, and the thickness of the AlN insertion layer 6 is 0.5-2 nm; providing the back barrier layer 4 can improve the conduction band of the GaN channel layer 5, thereby reducing the leakage path to the bottom of the high-resistance buffer layer 3, and the back barrier layer 4 can confine the 2DEG in a narrow channel, thereby improving the density of the 2EDG.

[0044] The material used for the barrier layer 7 is Al x Ga 1-x N, wherein x=0.1-0.5, and the thickness of the barrier layer 7 is 10-30 nm. It should be noted that different thicknesses of the barrier layer 7 and different x values ​​are related to the threshold voltage and the saturation current density, so selecting a suitable x value can prevent strain relaxation of the barrier layer 7 while satisfying the electron concentration.

[0045] The doping concentration of C element in C:GaN cap layer 8 is 10 18 ~10 20 cm -3 The thickness of the C:GaN cap layer 8 is 50-200 nm. The doping of the C element makes the C:GaN cap layer 8 present a shallow acceptor characteristic, depletes part of the charge in the two-dimensional electron gas, and improves the threshold voltage and gate forward withstand voltage of the device. The thickness of the TiN metal layer 9 is 5 nm-300 nm.

[0046] Furthermore, the implanted ions in the first ion implantation region 14 and the second ion implantation region 15 are N ions, and the implantation concentration is 10 18 ~10 20 cm -3 The thickness of the passivation layer 10 is greater than the sum of the thicknesses of the C:GaN cap layer 8 and the TiN metal layer 9. A gate window is provided on the passivation layer 10 on the upper surface of the TiN metal layer 9, and a gate electrode 11 is provided in the gate window. The material of the passivation layer 10 includes one or more of SiO2, SiN, AlON or Al2O3.

[0047] The material of the gate electrode 11 of this embodiment is Ti, Al, Ti / Al or TiN / Ti / Al / TiN, that is, the material of the gate electrode 11 can be a single metal layer of Ti or Al, or a Ti / Al stacked metal, or a TiN / Ti / Al / TiN stacked metal. The material of the source electrode 12 and the drain electrode 13 is Ti, Al or a metal composite layer or alloy containing Ti / Al.

[0048] The C:GaN gate enhanced HEMT device of the present invention obtains a usable enhanced HEMT device structure by setting a C:GaN cap layer and a back barrier layer, effectively reducing gate leakage, improving the gate forward withstand voltage, and obtaining an enhanced device with a stable threshold voltage. The present invention uses AlGaN as a back barrier layer to raise the conduction band of the GaN channel layer, thereby reducing the leakage path to the bottom of the high-resistance buffer layer, enhancing the confinement of the channel carriers, and limiting the 2EDG in a narrow channel, thereby increasing the density of the device 2EDG and weakening the current collapse phenomenon; a C-doped GaN cap layer is used, and the C element is doped to make C:GaN show shallow acceptor characteristics, deplete part of the charge in the two-dimensional electron gas, and increase the threshold voltage and gate forward withstand voltage of the device; negatively polarized charges exist at the interface between the thick AlGaN back barrier layer and the GaN channel layer of the present invention, acting as virtual p-type doping, which increases the energy band of the GaN layer and further increases the threshold voltage of the HEMT device.

[0049] Embodiment 2

[0050] Based on Example 1, this example proposes a method for preparing a C:GaN gate enhancement mode HEMT device, see Figure 2 , Figure 3a to Figure 3g , the preparation method comprises the following steps:

[0051] Step 1: epitaxially grow a nucleation layer 2, a high-resistance buffer layer 3, a back barrier layer 4, a GaN channel layer 5, an insertion layer 6, a barrier layer 7 and a C-doped C:GaN cap layer 8 in sequence on a substrate layer 1.

[0052] See also Figure 3a First, the selected substrate layer 1 is subjected to surface pretreatment, specifically, organic cleaning, acid washing and deionized water washing are performed to remove surface impurities and oxides of the substrate layer 1. The substrate layer 1 of this embodiment can be made of sapphire, Si or SiC material. Subsequently, a nucleation layer 2 with a thickness of 50 to 500 nm, a high-resistance buffer layer 3 with a thickness of 800 to 6000 nm, a back barrier layer 4 with a thickness of 100 to 500 nm, a GaN channel layer 5 with a thickness of 50 to 500 nm, an AlN insertion layer 6 with a thickness of 0.5 to 2 nm, and an AlN layer with a thickness of 10 to 30 nm are sequentially grown on the substrate layer 1 using the metal-organic chemical vapor deposition (MOCVD) technology. x Ga 1-x A barrier layer 7 composed of N (x=0.1-0.5) and a C-doped C:GaN cap layer 8 with a thickness of 50-200 nm.

[0053] The material of the nucleation layer 2 is AlN, and the material of the high-resistance buffer layer 3 is GaN doped with C, wherein the doping concentration of C is 1017 ~10 20 cm -3 The doping concentration of C in the C:GaN cap layer is 10 18 ~10 20 cm -3 ; The material used for the back barrier layer 4 is Al a Ga 1-a N, a=0.05-0.2, providing the back barrier layer 4 can improve the conduction band of the GaN channel layer 5, thereby reducing the leakage path to the bottom of the high-resistance buffer layer 3, and the back barrier layer 4 can confine the 2DEG in a narrow channel, thereby increasing the density of the 2EDG.

[0054] Step 2: Deposit TiN metal on the upper surface of the C:GaN cap layer 8 to form a TiN metal layer 9.

[0055] Specifically, see Figure 3b In this embodiment, a physical vapor deposition (PVD) process is used to sputter and deposit TiN metal on the upper surface of the C-doped C:GaN cap layer 8 to form a TiN metal layer 9 with a thickness of 5 nm to 300 nm.

[0056] Step 3: ion implantation is performed on the left and right sides of the upper surface of the TiN metal layer 9 to form a first ion implantation region 14 and a second ion implantation region 15 extending to the lower surface of the GaN channel layer 5 .

[0057] Specifically, see Figure 3c N ions are implanted on both sides of the upper surface of the TiN metal layer 9 to form a first ion implantation region 14 and a second ion implantation region 15 extending to the lower surface of the GaN channel layer. The ion implantation concentration of the first ion implantation region 14 and the second ion implantation region 15 is 10 18 ~10 20 cm -3 .

[0058] Step 4: Determine the gate region, and etch the TiN metal layer 9 and the C:GaN cap layer 8 outside the gate region.

[0059] Specifically, a gate region is determined on the upper surface of the TiN metal layer 9. The gate region of the present embodiment is located in the middle of the upper surface of the TiN metal layer 9. Then, the TiN metal layer and the C:GaN cap layer outside the gate region are etched using a selective self-stop etching technique, and the first ion implantation region 14 and the second ion implantation region 15 are etched to be flush with the upper surface of the barrier layer 4. Figure 3d shown.

[0060] Step 5: a dielectric material is deposited on the upper surfaces of the TiN metal layer 9 and the barrier layer 7 and on both sides of the C:GaN cap layer 8 to form a passivation layer 10 .

[0061] Specifically, see Figure 3e , using a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process, one or more layers of dielectric material are deposited on the upper surface of the TiN metal layer 9 and the barrier layer 7 and on both sides of the C-doped C:GaN cap layer 8 to form a passivation layer 10, and the dielectric material includes one or more of SiO2, SiN, AlON or Al2O3.

[0062] Step 6: Etch the passivation layer 10 in the gate region to form a gate window extending to the upper surface of the TiN metal layer 9 , and deposit gate metal inside the gate window to form a gate electrode 11 .

[0063] See also Figure 3f , using photolithography and development technology, the passivation layer 10 in the gate area is etched until the upper surface of the TiN metal layer 9 forms a gate window, and then the gate metal is deposited in the gate window by physical vapor deposition to form a gate electrode 11. The material of the gate layer includes Ti, Al, Ti / Al or TiN / Ti / Al / TiN.

[0064] Step 7: forming a source electrode 12 and a drain electrode 13 inside the first ion implantation region 14 and the second ion implantation region 15 , wherein the lower surfaces of the source electrode 12 and the drain electrode 13 are in contact with the upper surface of the GaN channel layer 5 .

[0065] Specifically, Figure 3g As shown, the source region and the drain region are respectively determined above the passivation layer 10 inside the first ion implantation region 14 and the second ion implantation region 15, the passivation layer 10, the barrier layer 7 and the GaN channel layer 6 of the source region and the drain region are etched away, and the source metal and the drain metal are respectively deposited above the GaN channel layer, and rapid thermal annealing is performed to form the source electrode 12 and the drain electrode 13, and the source electrode 12 and the drain electrode 13 are respectively in ohmic contact with the GaN channel layer, the annealing temperature is 565°C, and the time is 90s.

[0066] In summary, the preparation method of the C:GaN gate-enhanced HEMT device proposed in the embodiment of the present invention epitaxially grows a C:GaN cap layer on the upper surface of the barrier layer, showing shallow acceptor characteristics, depleting part of the charge in the two-dimensional electron gas, thereby increasing the threshold voltage and the forward withstand voltage of the gate, and reducing the leakage of the gate region; a back barrier layer is set below the GaN channel layer to raise the conduction band of the channel layer, enhance the confinement of the channel carriers, and confine the 2DEG in a narrow channel to increase the density of the two-dimensional electron gas while reducing the downward leakage path. Negatively polarized charges exist at the interface between the AlGaN back barrier layer and the GaN channel layer, acting as virtual p-type doping, further increasing the threshold voltage of the device. The preparation method of the present invention is compatible with the current p-GaN HEMT process, has a simple preparation process, and does not require complex groove etching.

[0067] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0068] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0069] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A C:GaN gate enhancement mode HEMT device, characterized in that: The invention comprises a substrate layer (1), a nucleation layer (2), a high-resistance buffer layer (3), a back barrier layer (4), a GaN channel layer (5), an insertion layer (6) and a barrier layer (7) which are arranged in sequence from bottom to top, wherein: A C-doped C:GaN cap layer (8) and a TiN metal layer (9) are sequentially arranged in the middle of the upper surface of the barrier layer (7) from bottom to top; Both sides of the upper surface of the barrier layer (7) respectively include a first ion implantation region (14) and a second ion implantation region (15), and both the first ion implantation region (14) and the second ion implantation region (15) extend downward from the upper surface of the barrier layer (7) to the upper surface of the back barrier layer (4); A source electrode (12) and a drain electrode (13) are respectively arranged inside the first ion implantation region (14) and the second ion implantation region (15), and the lower surfaces of the source electrode (12) and the drain electrode (13) are in contact with the GaN channel layer (5); A passivation layer (10) is provided on the upper surfaces of the TiN metal layer (9) and the barrier layer (7) and on both sides of the C:GaN cap layer (8), and a gate electrode (11) is provided on the upper surface of the C:GaN cap layer.

2. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The material used for the barrier layer (7) is Al x Ga 1-x N, wherein x=0.1-0.5, and the thickness of the barrier layer (7) is 10-30 nm.

3. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The material used for the back barrier layer (4) is Al a Ga 1-a N, wherein a=0.05-0.2, and the thickness of the back barrier layer (4) is 100-500 nm.

4. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The doping concentration of the C element in the C:GaN cap layer (8) is 10 18 ~10 20 cm -3 The thickness of the C:GaN cap layer (8) is 50 to 200 nm.

5. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The implanted ions in the first ion implantation area (14) and the second ion implantation area (15) are N ions, and the implantation concentration is 10 18 ~10 20 cm -3 .

6. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: A gate window is provided on the passivation layer (10) on the upper surface of the TiN metal layer (9), and the gate electrode (11) is arranged in the gate window.

7. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The material of the passivation layer (10) includes one or more of SiO2, SiN, AlON or Al2O3.

8. The C:GaN gate-enhanced HEMT device according to claim 1, characterized in that: The material of the gate electrode (11) is Ti, Al, Ti / Al or TiN / Ti / Al / TiN; the material of the source electrode (12) and the drain electrode (13) is Ti, Al or a metal composite layer or alloy containing Ti / Al.

9. A method for preparing a C:GaN gate-enhanced HEMT device, characterized in that: include: Step 1: epitaxially growing a nucleation layer, a high-resistance buffer layer, a back barrier layer, a GaN channel layer, an insertion layer, a barrier layer and a C-doped C:GaN cap layer on the substrate layer in sequence; Step 2: depositing TiN metal on the upper surface of the C:GaN cap layer to form a TiN metal layer; Step 3: performing ion implantation on the left and right sides of the upper surface of the TiN metal layer to form a first ion implantation region and a second ion implantation region extending to the lower surface of the GaN channel layer; Step 4: Determine the gate region, and etch the TiN metal layer and the C:GaN cap layer outside the gate region; Step 5: depositing a dielectric material on the upper surfaces of the TiN metal layer and the barrier layer and on both sides of the C:GaN cap layer to form a passivation layer; Step 6: etching the passivation layer in the gate region to form a gate window extending to the upper surface of the TiN metal layer, and depositing a gate metal inside the gate window to form a gate electrode; Step 7: forming a source electrode and a drain electrode inside the first ion implantation region and the second ion implantation region, wherein lower surfaces of the source electrode and the drain electrode are in contact with the GaN channel layer.

10. The method for preparing a C:GaN gate-enhanced HEMT device according to claim 9, characterized in that: The S6 includes: The passivation layer in the gate area is etched by photolithography and development technology until the upper surface of the TiN metal layer forms a gate window, and the gate metal is deposited in the gate window by physical vapor deposition to form a gate electrode. The material of the gate layer is Ti, Al, Ti / Al or TiN / Ti / Al / TiN.

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