P-type gate structure normally-closed GaN HEMT device and preparation method thereof

Abstract

The invention discloses a p-type gate structure normally-closed GaN HEMT device and a preparation method thereof. The p-type gate structure normally-closed GaN HEMT device comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a spacer layer and a barrier layer which grow in sequence. A source electrode and a drain electrode are arranged above the barrier layer, and a first groove is formed between the source electrode and the drain electrode; an AlN layer is arranged above the barrier layer, the source electrode, the drain electrode and the first groove; a first CuCrO2 layer is arranged above the AlN layer, a first passivation layer is arranged above the AlN layer, the source electrode, the first CuCrO2 layer and the drain electrode, and grid electrode grooves are formed in the upper sides of the first passivation layer and the first CuCrO2 layer; a second CuCrO2 layer is arranged on the first CuCrO2 layer, and a grid electrode is arranged on the second CuCrO2 layer; a second passivation layer is arranged above the grid electrode; a floating field plate is arranged above the second passivation layer; a third passivation layer is arranged above the floating field plate; a source electrode field plate is arranged above the source electrode; and a drain interconnection layer is arranged above the drain. The invention solves the problems of low threshold voltage and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a p-type gate structure normally-off GaN HEMT device and a preparation method thereof. Background Art

[0002] Compared with traditional silicon-based materials and second-generation semiconductors (represented by gallium arsenide), gallium nitride materials have become one of the preferred materials for third-generation semiconductors due to their larger bandgap, higher withstand voltage, charge density and electron mobility. In particular, heterojunction devices (high electron mobility transistors) composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) have excellent performance. Due to the material properties of gallium nitride, its positive and negative charges are not in the center and have spontaneous polarization, and when forming a heterojunction with aluminum gallium nitride, the piezoelectric polarization effect caused by stress leads to the formation of a triangular potential well at the AlGaN / GaN interface, which binds electrons in it and generates a natural conductive channel. Therefore, GaN HEMT (High Electron Mobility Transistor) devices are usually normally-on devices.

[0003] Power devices are divided into two types according to the value of the bias applied to the gate when the device is turned on: normally-on (depletion mode) and normally-off (enhancement mode). Normally-on devices are generally in the on state when no gate bias is applied, and often require a negative bias to turn the device off, which will increase the static power consumption in the circuit and also increase the design cost and difficulty of the circuit. Normally-off devices only work when a positive bias is applied, and are turned off when no bias is applied. Compared with normally-on devices, normally-off AlGaN / GaN HEMTs exhibit significant performance such as good failure protection, fast switching speed, and low reverse conduction loss. In practical applications, they are safer and more energy-efficient, and can effectively reduce the complexity of circuit design. Therefore, they have more outstanding research value, use value, and a broader market.

[0004] At present, the common means of realizing normally-off GaN HEMT devices include P-GaN gate structure, groove gate structure, fluorine ion implantation and cascode structure. The most representative method of realizing normally-off GaN HEMT devices is p-type gate technology. This technology was first proposed by Toyota in 2007 and has gradually developed into one of the mainstream commercial technologies. This type of normally-off device deposits a layer of Mg ion-doped p-GaN cap layer on the AlGaN barrier layer, and then deposits metal on the cap layer to form a gate. There are still some problems with the P-GaN gate structure: on the one hand, due to the similar material properties of AlGaN and GaN, the etching selectivity between them is difficult to optimize. Therefore, when etching the non-gate area, the etching depth, the roughness and uniformity of the surface after etching are difficult to control. At the same time, the etching damage caused by dry etching will also reduce the electrical performance and reliability of AlGaN / GaN HEMT. Secondly, the threshold voltage (V th ) is relatively low (about 1 V) because the Mg doping in GaN is difficult to activate, so the low hole concentration may limit V th further increase.

[0005] In recent years, many intrinsic p-type metal oxides (tin oxide, nickel oxide, cuprous oxide) have been used to replace the p-type GaN cap layer to realize the normally-off GaN HEMT. These p-type metal oxides can be grown using magnetron sputtering technology, and then form a P-type gate by lift-off technology. On the one hand, the magnetron sputtering process is simple and low in cost. Secondly, the etching damage can be avoided to a large extent without etching or compatibility with wet etching process. However, most binary p-type metal oxides easily capture holes due to the deep energy levels formed by the O-2p orbital of the material itself, and the strong electronegativity of oxygen atoms also constrains the movement of holes, so the hole concentration is low and the hole mobility is low, which leads to a low threshold voltage of the prepared GaN HEMT device. Summary of the invention

[0006] In view of this, the purpose of the present invention is to propose a p-type gate structure normally-off GaN HEMT device to solve the problems of low threshold voltage, etching damage, low conductivity of ordinary binary p-type oxide, and small positive shift of threshold voltage caused by low hole carrier concentration in traditional P-GaN gate technology.

[0007] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0008] The present invention provides a p-type gate structure normally-off GaN HEMT device, comprising: a substrate, a nucleation layer, a buffer layer, a channel layer, a spacer layer, a barrier layer, a source, a drain, an AlN layer, a first CuCrO2 layer, a first passivation layer, a second CuCrO2 layer, a gate, a second passivation layer, a floating field plate, a third passivation layer, a source field plate and a drain interconnection layer;

[0009] The substrate, the nucleation layer, the buffer layer, the channel layer, the spacer layer and the barrier layer are stacked in sequence from bottom to top;

[0010] A source groove is provided on the left side of the barrier layer, a drain groove is provided on the right side of the barrier layer, and a first groove is provided between the source groove and the drain groove and at a position close to the drain groove;

[0011] The source electrode is located on the source electrode groove, and the drain electrode is located on the drain electrode groove;

[0012] A left isolation groove is provided on the left side of the barrier layer, the left side of the spacer layer, the left side of the channel layer and the upper left side of the buffer layer, and a right isolation groove is provided on the right side of the barrier layer, the right side of the spacer layer, the right side of the channel layer and the upper right side of the buffer layer;

[0013] The AlN layer is located on the barrier layer, the source electrode and the drain electrode, and a second groove is formed at the first groove;

[0014] The first CuCrO2 layer is disposed above a portion of the AlN layer and is located between the source electrode and the drain electrode and close to the second groove;

[0015] The first passivation layer covers the AlN layer, the source electrode, the first CuCrO2 layer, the drain electrode and the second groove;

[0016] A gate groove is provided from the middle of the first passivation layer to the upper surface of the first CuCrO2 layer;

[0017] The second CuCrO2 layer is arranged directly below the gate groove and located in the middle of the upper side of the first CuCrO2 layer; the lower side of the gate is arranged in the gate groove and located above the second CuCrO2 layer, and the upper side of the gate is located above a portion of the first passivation layer;

[0018] The second passivation layer covers the first passivation layer and the gate;

[0019] The lower side of the floating field plate is arranged in the second passivation layer and is located to the right of the gate and directly above the second groove, and the upper side of the floating field plate is located above a portion of the second passivation layer and directly above the gate;

[0020] The third passivation layer covers the second passivation layer and the floating field plate;

[0021] A source window is provided in the region above the source electrode among the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer, and the lower side of the source field plate is arranged in the source window and the upper side thereof is located above a portion of the third passivation layer;

[0022] A drain window is provided in the region above the drain in the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer. The lower side of the drain interconnect layer is arranged in the drain window and the upper side thereof is located above a portion of the third passivation layer.

[0023] Further, the material of the substrate includes one of sapphire, silicon, gallium nitride, silicon carbide, ceramic polyaluminum nitride composite material, insulating silicon substrate and diamond;

[0024] The material of the nucleation layer is aluminum nitride;

[0025] The material of the buffer layer is iron- or carbon-doped gallium nitride, a superlattice of alternately grown AlN and GaN multilayers, and Al x1 Ga 1-x1 One of N;

[0026] The material of the channel layer is gallium nitride;

[0027] The material of the barrier layer is Al x2 Ga 1-x2 N, x2 is 0.1-0.25;

[0028] The source and drain electrodes are one of a Ti / Al / Ni / Au multilayer metal stacked structure, a Ti / Al / TiN multilayer metal stacked structure, a Ti / Al / Ti / Au multilayer metal stacked structure, and a Ti / Al / Ti / TiN multilayer metal stacked structure.

[0029] The gate adopts one of a Ti / Al multi-layer metal stacking structure, a Ti / Au multi-layer metal stacking structure, and a TiN / Al / TiN multi-layer metal stacking structure;

[0030] The materials of the first passivation layer, the second passivation layer and the third passivation layer include one or more of silicon dioxide, silicon nitride and aluminum oxide;

[0031] The material of the floating field plate is TiN;

[0032] The material of the drain interconnection layer is a TiN / Al / TiN multi-layer metal stacked in sequence structure.

[0033] Furthermore, the thickness of the nucleation layer is 1-3 nm;

[0034] The thickness of the buffer layer is 1-6 μm;

[0035] The thickness of the channel layer is 50-500nm;

[0036] The thickness of the barrier layer is 10-20 nm;

[0037] The thickness of the first passivation layer and the second passivation layer is 50-300nm;

[0038] The thickness of the third passivation layer is 300nm-600nm;

[0039] The thickness of the AlN layer is 2-5 nm;

[0040] The thickness of the first CuCrO2 layer is 80-150nm;

[0041] The thickness of the floating field plate is 80-150 nm.

[0042] Furthermore, the width of the nucleation layer is the same as the width of the substrate;

[0043] The width of the buffer layer is the same as the width of the nucleation layer;

[0044] A table is formed in the middle of the upper side of the buffer layer;

[0045] The width of the channel layer is the same as the width of the mesa;

[0046] The width of the spacer layer is the same as the width of the channel layer;

[0047] The width of the barrier layer is the same as that of the spacer layer.

[0048] Furthermore, the distance between the source and the left side wall of the first CuCrO2 layer is smaller than the distance between the source and the left side wall of the gate, and the distance between the drain and the right side wall of the first CuCrO2 layer is smaller than the distance between the drain and the right side wall of the gate; the distance between the first CuCrO2 layer and the source is smaller than the distance between the first CuCrO2 layer and the drain, and the distance between the gate and the source is smaller than the distance between the gate and the drain.

[0049] Furthermore, the floating field plate is an inverted L-shaped structure, and the source field plate and the drain interconnect layer are T-shaped structures.

[0050] Furthermore, the upper surface of the second CuCrO2 layer is flush with the upper surface of the first CuCrO2 layer, and the hole concentration of the first CuCrO2 layer is 10 18 -10 20 cm -3 The hole concentration of the second CuCrO2 layer is 10 16 -10 18 cm -3 .

[0051] The present invention also provides a method for preparing a p-type gate structure normally-off GaN HEMT device, the method needs to provide the above-mentioned p-type gate structure normally-off GaN HEMT device, comprising the following steps:

[0052] Step 1, epitaxially growing a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer in sequence from bottom to top on the substrate;

[0053] Step 2, etching a source groove and a drain groove on the left and right sides of the barrier layer respectively, etching a first groove on the barrier layer between the source groove and the drain groove and close to the drain groove; preparing a source electrode above the source groove, and preparing a drain electrode above the drain groove;

[0054] Step 3, isolating the upper left side of the buffer layer, the left side of the channel layer, the left side of the spacer layer and the left side of the barrier layer, as well as the upper right side of the buffer layer, the right side of the channel layer, the right side of the spacer layer and the right side of the barrier layer by ion implantation or etching, and performing high temperature annealing;

[0055] Step 4, depositing an AlN layer on the barrier layer, the source electrode and the drain electrode, and forming a second groove at the first groove;

[0056] Step 5, preparing a first CuCrO2 layer above a portion of the AlN layer, between the source and the drain and close to the second groove, and performing high temperature annealing on the first CuCrO2 layer;

[0057] Step 6, preparing a first passivation layer on the surfaces of the AlN layer, the source electrode, the first CuCrO2 layer, the drain electrode and the second groove;

[0058] Step 7, a gate groove is opened from the middle of the first passivation layer to the upper surface of the first CuCrO2 layer, a second CuCrO2 layer is formed by oxygen plasma treatment directly below the gate groove and located in the middle of the upper side of the first CuCrO2 layer, and a gate is prepared on the second CuCrO2 layer in the gate groove to form a Schottky contact;

[0059] Step 8, preparing a second passivation layer above the first passivation layer and the gate;

[0060] Step 9, preparing a floating field plate on the second passivation layer and the gate;

[0061] Step 10, preparing a third passivation layer above the second passivation layer and the floating field plate;

[0062] Step 11, a source window is formed in the region above the source electrode in the AlN layer, the first passivation layer, the second passivation layer, and the third passivation layer, and a drain window is formed in the region above the drain electrode in the AlN layer, the first passivation layer, the second passivation layer, and the third passivation layer;

[0063] Step 12: depositing a source field plate in the source window, and depositing a drain interconnect layer in the drain window.

[0064] Furthermore, in the step 1, the epitaxial growth method adopts one of MOCVD, HVPE and MBE; in the step 3, the ion implantation uses F ion or N ion implantation; in the step 4, the AlN layer is deposited by a low-temperature deposition process; in the step 5, the first CuCrO2 layer is prepared by a radio frequency magnetron sputtering process; in the step 6, the first passivation layer is prepared by a low-temperature deposition process or a high-temperature and low-pressure process; in the step 8, the second passivation layer is prepared by a low-temperature deposition process; in the step 10, the third passivation layer is prepared by a low-temperature deposition process; in the steps 7 and 11, the gate groove, the source window and the drain window are opened by ICP etching technology.

[0065] Furthermore, in the step 2, before preparing the source and drain, the source groove, the drain groove and the first groove are treated with an inorganic solution or an organic solution, the inorganic solution is HF solution, HCL / H2O2 solution, KOH solution or TMAH solution, and the organic solution is NMP solution.

[0066] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0067] 1. The present invention uses a CuCrO2 gate structure to replace the traditional p-GaN gate structure, providing a feasible way to realize a normally-off device. This method effectively avoids the problems of surface state, roughness, and depth caused by p-GaN doping and etching.

[0068] 2. Compared with binary p-type oxides such as Cu2O and NiO, CuCrO2 has a higher hole concentration, about 10 20 cm -3 , which can further deplete the two-dimensional electron gas formed by the AlGaN / GaN heterojunction structure, and realize a normally-off device without an external bias.

[0069] 3. The present invention provides a feasible exploration idea for the research of normally-off (enhancement mode) devices, and opens up new application prospects of ternary p-type TCO material gate structure in normally-off AlGaN / GaN HEMT devices.

[0070] 4. The introduction of the floating field plate and the source field plate, as well as the etching of the first groove, effectively optimizes the electric field concentration effect at the gate-drain edge. At the same time, the inverted "L"-shaped field plate can redistribute the electric field and improve the overall device breakdown.

[0071] 5. Use AlN layer to passivate the device, which greatly improves the channel two-dimensional electron gas. At the same time, its high thermal conductivity combined with the groove enhances the heat dissipation effect of the device and greatly improves the device performance.

[0072] 6. The intrinsic p-type metal oxide CuCrO2 can form hybrid energy levels due to the high degree of hybridization of electron orbitals, which weakens the binding effect of the O-2p orbitals on holes, and can obtain higher hole concentrations and higher hole mobility, which is beneficial to the realization of normally-off AlGaN / GaN HEMT devices in principle. Secondly, the bandgap width of CuCrO2 can reach about 3.4eV, which can form a good heterostructure with gallium nitride. CuCrO2 film can also be prepared by magnetron sputtering, and then a P-CuCrO2 gate can be obtained by stripping technology. By adjusting the relevant parameters of magnetron sputtering, the prepared CuCrO2 film can achieve a hole concentration from 10 15 -10 20 cm -3 At the same time, oxygen plasma treatment will reduce the concentration of the film, effectively expand the gate depletion region, and increase the gate breakdown voltage. For gold semi-contact, it can effectively avoid FP emission, reduce leakage current, and improve gate reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0074] Figure 1 It is a schematic diagram of the structure of a substrate, a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer provided in an embodiment of the present invention.

[0075] Figure 2 is Figure 1 Schematic diagram of the structure of etching a source groove, a drain groove and a first groove on the barrier layer in FIG.

[0076] Figure 3 is Figure 2 Schematic diagram of preparing source and drain electrodes on the source groove and drain groove in FIG.

[0077] Figure 4 is Figure 3Schematic diagram of the structure of etching the left isolation layer and the right isolation layer.

[0078] Figure 5 is Figure 4 Schematic diagram of the structure for preparing AlN layer on the potential barrier.

[0079] Figure 6 is Figure 5 Schematic diagram of the structure for preparing the first CuCrO2 layer on the AlN layer.

[0080] Figure 7 is Figure 6 Schematic diagram of the structure for preparing the first passivation layer on the AlN layer and the first CuCrO2 layer.

[0081] Figure 8 is Figure 7 Schematic diagram of the structure of etching a gate groove on the first passivation layer and the first CuCrO2 layer.

[0082] Fig. 9 is Figure 8 Schematic diagram of the structure for preparing a second CuCrO2 layer on the gate groove.

[0083] Fig.10 is Fig. 9 Schematic diagram of the structure of preparing the gate on the second CuCrO2 layer.

[0084] Fig.11 is Fig.10 Schematic diagram of the structure of preparing a second passivation layer on the first passivation layer and the gate.

[0085] Fig.12 is Fig.11 Schematic diagram of the structure of preparing a floating field plate on the second passivation layer.

[0086] Fig.13 is Fig.12 Schematic diagram of the structure of preparing the third passivation layer on the second passivation layer and the floating field plate.

[0087] Fig.14 is Fig.13 Schematic diagram of the structure of preparing source window and drain window above the source and drain.

[0088] Fig.15 It is a schematic structural diagram of a p-type gate normally-off GaN HEMT device provided by an embodiment of the present invention.

[0089] Fig.16 (a) is the energy band diagram of the normally-on GaN HEMT device; Fig.16 (b) is the energy band diagram of a normally-off GaN HEMT device with a p-CuCrO2 gate structure.

[0090] Description of the numbers in the figure:

[0091] 1-substrate, 2-nucleation layer, 3-buffer layer, 4-channel layer, 5-spacer layer, 6-barrier layer, 7-source, 8-drain, 9-AlN layer, 10-first CuCrO2 layer, 11-first passivation layer, 12-second CuCrO2 layer, 13-gate, 14-second passivation layer, 15-floating field plate, 16-third passivation layer, 17-source field plate, 18-drain interconnect layer, 19-source groove, 20-drain groove, 21-first groove, 22-left isolation groove, 23-right isolation groove, 24-second groove, 25-gate groove, 26-source window, 27-drain window. DETAILED DESCRIPTION

[0092] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present invention, but are not intended to limit the scope of the present invention. Similarly, the following examples are only partial embodiments of the present invention rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0093] See also Fig.15 A p-type gate structure normally-off GaN HEMT device of the present invention comprises: a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a spacer layer 5, a barrier layer 6, a source 7, a drain 8, an AlN layer 9, a first CuCrO2 layer 10, a first passivation layer 11, a second CuCrO2 layer 12, a gate 13, a second passivation layer 14, a floating field plate 15, a third passivation layer 16, a source field plate 17 and a drain interconnect layer 18 (equivalent to a drain field plate);

[0094] The substrate 1, the nucleation layer 2, the buffer layer 3, the channel layer 4, the spacer layer 5 and the barrier layer 6 are stacked in sequence from bottom to top;

[0095] A source groove 19 is provided on the left side of the barrier layer 6, a drain groove 20 is provided on the right side of the barrier layer 6, and a first groove 21 is provided between the source groove 19 and the drain groove 20 and at a position close to the drain groove 20;

[0096] The source electrode 7 is located on the source electrode groove 19, and the drain electrode 8 is located on the drain electrode groove 20;

[0097] A left isolation groove 22 is provided on the left side of the barrier layer 6, the left side of the spacer layer 5, the left side of the channel layer 4 and the upper left side of the buffer layer 3, and a right isolation groove 23 is provided on the right side of the barrier layer 6, the right side of the spacer layer 5, the right side of the channel layer 4 and the upper right side of the buffer layer 3;

[0098] The AlN layer 9 is located on the barrier layer 6, the source electrode 7 and the drain electrode 8, and forms a second groove 24 at the first groove 21;

[0099] The first CuCrO2 layer 10 is disposed above a portion of the AlN layer 9 and is located between the source electrode 7 and the drain electrode 8 and close to the second groove 24;

[0100] The first passivation layer 11 covers the AlN layer 9, the source electrode 7, the first CuCrO2 layer 10, the drain electrode 8 and the second groove 24;

[0101] A gate groove 25 is provided from the middle of the first passivation layer 11 to the upper surface of the first CuCrO2 layer 10;

[0102] The second CuCrO2 layer 12 is disposed directly below the gate groove 25 and located in the middle of the upper side of the first CuCrO2 layer 10;

[0103] The lower side of the gate 13 is disposed in the gate groove 25 and is located above the second CuCrO2 layer 12, and the upper side of the gate 13 is located above a portion of the first passivation layer 11;

[0104] The second passivation layer 14 covers the first passivation layer 11 and the gate 13;

[0105] The lower side of the floating field plate 15 is disposed in the second passivation layer 14 and is located to the right of the gate 13 and directly above the second groove 24 . The upper side of the floating field plate 15 is located above a portion of the second passivation layer 14 and directly above the gate 13 .

[0106] The third passivation layer 16 covers the second passivation layer 14 and the floating field plate 15;

[0107] A source window 26 is provided in the region above the source electrode 7 among the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16, and the lower side of the source field plate 17 is arranged in the source window 26 and the upper side thereof is located above a portion of the third passivation layer 16;

[0108] A drain window 27 is formed in the AlN layer 9 , the first passivation layer 11 , the second passivation layer 14 and the third passivation layer 16 in the region above the drain 8 . The lower side of the drain interconnection layer 18 is arranged in the drain window 27 and the upper side thereof is located above a portion of the third passivation layer 16 .

[0109] In this embodiment, the material of the substrate 1 includes one of sapphire, silicon, gallium nitride, silicon carbide, ceramic polyaluminum nitride composite material, insulating silicon-based and diamond;

[0110] The material of the nucleation layer 2 is aluminum nitride;

[0111] The material of the buffer layer 3 is iron- or carbon-doped gallium nitride, a superlattice of multiple layers of AlN and GaN grown alternately, and Al x1 Ga 1-x1 One of N, the range of x1 is 0<x1<1;

[0112] The material of the channel layer 4 is gallium nitride;

[0113] The material of the barrier layer 6 is Al x2 Ga 1-x2 N, x2 is 0.1-0.25;

[0114] The source electrode 7 and the drain electrode 8 adopt one of a Ti / Al / Ni / Au multilayer metal stacking structure (i.e., Ti, Al, Ni and Au are stacked in sequence from bottom to top), a Ti / Al / TiN multilayer metal stacking structure (i.e., Ti, Al and TiN are stacked in sequence from bottom to top), a Ti / Al / Ti / Au multilayer metal stacking structure (i.e., Ti, Al, Ti and Au are stacked in sequence from bottom to top), and a Ti / Al / Ti / TiN multilayer metal stacking structure (i.e., Ti, Al, Ti and TiN are stacked in sequence from bottom to top);

[0115] The gate 13 adopts one of a Ti / Al multilayer metal stacking structure (i.e., Ti and Al are stacked in sequence from bottom to top), a Ti / Au multilayer metal stacking structure (i.e., Ti and Au are stacked in sequence from bottom to top), and a TiN / Al / TiN multilayer metal stacking structure (i.e., TiN, Al and TiN are stacked in sequence from bottom to top);

[0116] The materials of the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 include one or more of silicon dioxide, silicon nitride and aluminum oxide;

[0117] The material of the floating field plate 15 is TiN;

[0118] The material of the drain interconnection layer 18 is a TiN / Al / TiN multi-layer metal stacked structure (ie, TiN, Al and TiN are stacked from bottom to top).

[0119] In this embodiment, the thickness of the nucleation layer 2 is 1-3 nm;

[0120] The thickness of the buffer layer 3 is 1-6 μm;

[0121] The thickness of the channel layer 4 is 50-500nm;

[0122] The thickness of the barrier layer 6 is 10-20 nm;

[0123] The thickness of the first passivation layer 11 and the second passivation layer 14 is 50-300 nm;

[0124] The thickness of the third passivation layer 16 is 300nm-600nm;

[0125] The thickness of the AlN layer 9 is 2-5 nm;

[0126] The thickness of the first CuCrO2 layer 10 is 80-150nm;

[0127] The thickness of the floating field plate 15 is 80-150 nm.

[0128] In this embodiment, the width of the nucleation layer 2 is the same as the width of the substrate 1;

[0129] The width of the buffer layer 3 is the same as that of the nucleation layer 2;

[0130] A table is formed in the middle of the upper side of the buffer layer 3;

[0131] The width of the channel layer 4 is the same as the width of the mesa;

[0132] The width of the spacer layer 5 is the same as the width of the channel layer 4;

[0133] The width of the barrier layer 6 is the same as the width of the spacer layer 5 .

[0134] In this embodiment, the distance between the source 7 and the left side wall of the first CuCrO2 layer 10 is smaller than the distance between the source 7 and the left side wall of the gate 13, and the distance between the drain 8 and the right side wall of the first CuCrO2 layer 10 is smaller than the distance between the drain 8 and the right side wall of the gate 13; the distance between the first CuCrO2 layer 10 and the source 7 is smaller than the distance between the first CuCrO2 layer 10 and the drain 8, indicating that the first CuCrO2 layer 10 is located between the source 7 and the drain 8, close to the source 7, and the left and right sides of the first CuCrO2 layer 10 usually represent the left and right sides of the device gate, and a larger Lgd (the distance between the first CuCrO2 layer 10 and the drain 8) can bring about a higher device breakdown, and a smaller Lgs (the distance between the first CuCrO layer 10 and the source 7) will result in a small resistance, and the current regulation ability will also be enhanced, so it is closer to the source 7. Due to the distance relationship between the first CuCrO 2 layer 10 and the source electrode 7 and the drain electrode 8 , the distance between the gate electrode 13 and the source electrode 7 is smaller than the distance between the gate electrode 13 and the drain electrode 8 .

[0135] In this embodiment, the floating field plate 15 is an inverted L-shaped structure, and the source field plate 17 and the drain interconnect layer 18 are T-shaped structures. The function of this structure is to optimize the electric field distribution and reduce the probability of electrons tunneling from the barrier layer 6 between the gate 13 and the drain 8 to the surface trap, thereby hindering the formation of the virtual gate effect, weakening the virtual gate effect, and effectively suppressing the current collapse effect of the device.

[0136] In this embodiment, the upper surface of the second CuCrO2 layer 12 is flush with the upper surface of the first CuCrO2 layer 10, and the hole concentration of the first CuCrO2 layer 10 is 10 18 -10 20 cm -3 The hole concentration of the second CuCrO2 layer 12 is 10 16 -10 18 cm -3 .

[0137] like Figures 1 to 15 As shown, the present invention also provides a method for preparing a p-type gate structure normally-off GaN HEMT device, the method needs to provide the above-mentioned p-type gate structure normally-off GaN HEMT device, comprising the following steps:

[0138] Step 1, epitaxially growing a nucleation layer 2, a buffer layer 3, a channel layer 4, a spacer layer 5 and a barrier layer 6 on the substrate 1 from bottom to top; the epitaxial growth method adopts one of MOCVD, HVPE and MBE;

[0139] Step 2, a source groove 19 and a drain groove 20 are respectively etched on the left and right sides of the barrier layer 6, and a first groove 21 is etched on the barrier layer 6 between the source groove 19 and the drain groove 20 and close to the drain groove 20; after etching, the source groove 19, the drain groove 20 and the first groove 21 are treated with an inorganic solution or an organic solution to repair the etching damage; the inorganic solution is HF solution, HCL / H2O2 solution, KOH solution or TMAH solution, and the organic solution is NMP solution. Through solution treatment, the interface roughness can be effectively improved, the etching damage can be optimized, the ohmic contact can be effectively optimized, and the contact resistance can be reduced. Then, a source electrode 7 is prepared above the source electrode groove 19, and a drain electrode 8 is prepared above the drain electrode groove 20; the source electrode 7 and the drain electrode 8 preferably adopt one of a Ti / Al / Ni / Au multi-layer metal stacking structure, a Ti / Al / TiN multi-layer metal stacking structure, a Ti / Al / Ti / Au multi-layer metal stacking structure, and a Ti / Al / Ti / TiN multi-layer metal stacking structure;

[0140] Step 3, isolating the upper left side of the buffer layer 3, the left side of the channel layer 4, the left side of the spacer layer 5 and the left side of the barrier layer 6, as well as the upper right side of the buffer layer 3, the right side of the channel layer 4, the right side of the spacer layer 5 and the right side of the barrier layer 6 by ion implantation or etching, preferably using F ion or N ion implantation; performing high temperature annealing after ion implantation to repair lattice damage;

[0141] Step 4, depositing an AlN layer 9 on the barrier layer 6, the source electrode 7 and the drain electrode 8 by a low temperature deposition process, and forming a second groove 24 at the first groove 21;

[0142] Step 5: Prepare the first CuCrO2 layer 10 by radio frequency magnetron sputtering process above part of the AlN layer 9, between the source electrode 7 and the drain electrode 8 and near the second groove 24, and perform high temperature annealing on it; the growth parameters of the first CuCrO2 layer 10 grown by radio frequency magnetron sputtering process are: Ar atmosphere 70sccm, target material is CuCrO2 target, sputtering pressure is 2.0Pa, and p-type CuCrO2 film is grown at room temperature. After the magnetron sputtering operation, the first CuCrO2 layer 10 is peeled off and then subjected to rapid thermal annealing treatment at a temperature of 700-900°C for 5 minutes.

[0143] Step 6, preparing a first passivation layer 11 on the surface of the AlN layer 9, the source electrode 7, the first CuCrO2 layer 10, the drain electrode 8 and the second groove 24 by a low-temperature deposition process or a high-temperature and low-pressure process; the low-temperature deposition process is an inductively coupled plasma chemical vapor deposition process or an atomic layer deposition device (ALD), the reaction chamber temperature in the inductively coupled plasma chemical vapor deposition (PECVD) is 100-350°C, and the reaction chamber temperature in the atomic layer deposition device (ALD) is 50-450°C; the high-temperature and low-pressure deposition process is a low-pressure chemical vapor deposition (LPCVD), and the temperature of the reaction chamber is 650-800°C.

[0144] Step 7, using ICP etching technology to open a gate groove 25 from the middle of the first passivation layer 11 to the upper surface of the first CuCrO2 layer 10, and forming a second CuCrO2 layer 12 directly below the gate groove 25 and located in the middle of the upper side of the first CuCrO2 layer 10 after oxygen plasma treatment; then preparing a gate 13 above the second CuCrO2 layer 12 in the gate groove 25 to form a Schottky contact; the gate 13 adopts one of a Ti / Al multi-layer metal stacking structure, a Ti / Au multi-layer metal stacking structure, and a TiN / Al / TiN multi-layer metal stacking structure;

[0145] Step 8: preparing a second passivation layer 14 on the first passivation layer 11 and the gate 13 by using a low temperature deposition process;

[0146] Step 9, preparing a floating field plate 15 on the second passivation layer 14 and the gate 13;

[0147] Step 10: preparing a third passivation layer 16 on the second passivation layer 14 and the floating field plate 15 by using a low temperature deposition process;

[0148] Step 11, etching the region above the source electrode 7 in the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 using the ICP etching technology to open a source window 26; etching the region above the drain electrode 8 in the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 using the ICP etching technology to open a drain window 27;

[0149] Step 12: depositing a source field plate 17 in the source window 26 , and depositing a drain interconnect layer 18 in the drain window 27 .

[0150] The principle of a p-type gate normally-off GaN HEMT device structure of the present invention is:

[0151] like Fig.16 (a) shows the energy band structure of a normally-on AlGaN / GaN HEMT device. Due to the polarization reaction of the GaN material, the GaN conduction band bends, forming an electronic potential well at the interface with the AlGaN, and the potential well is below the Fermi level. Fig.16 As shown in (b), with the introduction of CuCrO2, the holes in the material itself will deplete the 2DEG in the channel below, causing its energy band to shift upward and the potential well to be higher than the Fermi level, thus causing its threshold voltage to be positive. The use of the ternary compound CuCrO2 gate structure to replace the traditional p-GaN, p-Cu2O or p-NiO gate structure effectively reduces the restriction of the O-2p orbital on holes due to the formation of a new hybrid orbit, greatly increasing the hole carrier concentration. Its hole concentration can reach up to 10 20 cm -3 , which is greater than the hole concentration of Cu2O, can more effectively deplete the two-dimensional electron gas under its channel, making the device a normally-off device without an external bias. At the same time, its band structure is similar to that of NiO, and its band gap is larger than that of Cu2O. After oxygen plasma treatment, the hole concentration will decrease. For the gate 13, the work functions of the two are consistent, the barrier height is constant, and the reduction of hole concentration can effectively avoid tunneling, reduce the leakage of the gate 13, and effectively improve the breakdown of the gate 13.

[0152] Example 1

[0153] See also Fig.15The p-type gate structure normally-off GaN HEMT device of this embodiment includes a substrate 1, in this example, silicon is used as the substrate 1; and a nucleation layer 2 (in this example, AlN is used), a buffer layer 3 (in this example, carbon-doped GaN is used), a channel layer 4 (in this example, GaN is used), a spacer layer 5 (in this example, AlN is used) and a barrier layer 6 (in this example, Al is used) are grown on the substrate 1 from bottom to top. 0.18 Ga 0.82 N); a source electrode 7 and a drain electrode 8 are provided at both ends above the barrier layer 6, the source electrode 7 is on the left side and the drain electrode 8 is on the right side, and a first groove 21 is provided between the source electrode 7 and the drain electrode 8 near the drain electrode 8; an AlN layer 9 is provided above the barrier layer 6, the source electrode 7, the drain electrode 8 and the first groove 21 to form a second groove 24; a first CuCrO2 layer 10 is provided above the AlN layer 9, and a first passivation layer 11 (SiN is used in this example) is provided above the AlN layer 9, the source electrode 7, the first CuCrO2 layer 10, the drain electrode 8 and the second groove 24 x ), a gate groove 25 is provided in the middle of the first passivation layer 11 and in the middle of the upper side of the first CuCrO2 layer 10; a second CuCrO2 layer 12 is provided in the gate groove 25 and above the first CuCrO2 layer 10, and a gate 13 is provided in the gate groove 25 and above the second CuCrO2 layer 12; a second passivation layer 14 (in this example, SiN x ); a floating field plate 15 is provided above the second passivation layer 14; a third passivation layer 16 (SiO2 is used in this example) is provided above the floating field plate 15; a source field plate 17 is provided above the source 7 and above a portion of the third passivation layer 16; a drain interconnection layer 18 is provided above the drain 8 and above a portion of the third passivation layer 16.

[0154] A method for preparing a p-type gate structure normally-off GaN HEMT device of the present invention, as follows Figures 1 to 15 As shown, specifically including:

[0155] (1) Provide silicon as substrate 1, the thickness of substrate 1 is 1000 μm, and perform single-side polishing standard RCA cleaning, wherein organic cleaning is first performed, using acetone and ethanol solution for ultrasonic cleaning; secondly, use standard RCA cleaning. First, use sulfuric acid: hydrogen peroxide = 3:1 solution for cleaning; then use hydrofluoric acid and water solution of 1:20 for cleaning at room temperature, and finally use ammonia water, hydrogen peroxide and water solution of 1:1:5 for cleaning. The cleaning effect can remove organic matter and oxides on the surface; the substrate 1 is 6 inches, and silicon is used as substrate 1 because of its low cost, good electrical and thermal conductivity, and mature application in the industry, which is conducive to heterogeneous integration with silicon-based devices.

[0156] (2) Metal organic chemical vapor epitaxy (MOCVD) is used on a silicon substrate 1. In a reaction chamber, trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH3) are used as Al source, Ga source, and N source, respectively. Hydrogen (H2) and nitrogen (N2) are used as carrier gases. From top to bottom, a 1 nm thick nucleation layer 2 (AlN is used in this example), a 5.2 μm thick buffer layer 3 (carbon-doped GaN is used in this example), a 200 nm thick channel layer 4 (GaN is used in this example), a 0.5 nm thick spacer layer 5 (AlN is used in this example), and a 15 nm thick barrier layer 6 (AlN is used in this example) are grown in sequence. 0.18 Ga 0.82 N). Among them, the role of the nucleation layer 2 is to guide the newly formed crystal nuclei, promote the growth of grains, and improve the crystallinity of the material; the role of the buffer layer 3 is to reduce the defect density of the epitaxial layer and increase the device's breakdown voltage; the role of the channel layer 4 is to form a natural conductive channel at the interface between the upper spacer layer 5 and the barrier layer 6, that is, to form 2DEG.

[0157] (3) Perform organic and inorganic cleaning on silicon-based AlGaN epitaxial wafers.

[0158] (4) After photolithography and development, the barrier layer 6 is etched by a Cl-based dry method using an inductively coupled plasma (ICP) technique to etch out ohmic grooves of the source 7 and drain 8 (i.e., source groove 19 and drain groove 20), and a first groove 21 with an etching depth of about 5-10 nm is formed between the source groove 19 and the drain groove 20 and on the side close to the drain groove 20. After etching, a TMAH solution or a KOH solution is used to repair the etching damage. In this example, the function of the first groove 21 is to optimize the electric field distribution of the gate and drain and to increase the breakdown voltage of the overall device. The first groove 21 can be etched multiple times at a time or multiple times to form a stepped groove, which effectively optimizes the electric field distribution of the gate and drain.

[0159] (5) After the source groove 19 and the drain groove 20 are developed by double-layer photolithography, a Ti / Al / Ni / Au multilayer metal is deposited on the source groove 19 and the drain groove 20 on the surface of the barrier layer 6 by electron beam evaporation equipment, and the structure is stacked from bottom to top. After the lift-off process, the structure is annealed at 850°C for 45s to form the ohmic contact source 7 and drain 8. The first layer of Ti reacts with the Al, GaN or AlGaN diffused to the surface to form TiN, and AlTi3 is produced at the same time, forming N vacancies in the barrier layer 6. The N vacancies will increase the electron concentration at the contact surface between the metal and AlGaN, similar to N-type doping, and promote the formation of its ohmic contact. The role of Ni is to block the downward diffusion of Au and reduce the reaction between Au and Al. The role of Al is to form an alloy with Ti, which has a low resistivity and improves the good conductivity. The role of Au is to prevent the oxidation of Ti and Al and improve the thermal stability of the ohmic contact.

[0160] (6) After photolithography and development, an ion implantation device is used to implant N ions on the upper left side of the buffer layer 3, the left side of the channel layer 4, the left side of the spacer layer 5, and the left side of the barrier layer 6, as well as on the upper right side of the buffer layer 3, the right side of the channel layer 4, the right side of the spacer layer 5, and the right side of the barrier layer 6, followed by rapid thermal annealing to repair lattice damage at a temperature of 700-850°C.

[0161] (7) Using an atomic layer deposition device, a 3 nm thick AlN layer 9 is deposited. The AlN layer 9 increases the polarization of the III-V compound and the concentration of the two-dimensional electron gas in the channel, thereby increasing the current and reducing the overall resistance. At the same time, AlN has high thermal conductivity, and the combination with the first groove 21 effectively improves the heat dissipation of the device.

[0162] (8) After the double-layer photoresist is developed, the CuCrO2 window is defined, and a radio frequency magnetron sputtering station is used. The radio frequency power is 100W, a pure CuCrO2 target is used in the reaction chamber, high-purity Ar is used as the reaction gas, the gas flow rate is 70sccm, and the sputtering pressure is 2.0Pa. The CuCrO2 film is grown at room temperature. Then, the first CuCrO2 layer 10 in the gate 13 region is left by a lift-off process, with a thickness of 80nm-100nm, and is rapidly thermally annealed in an oxygen atmosphere at a temperature of 700-850°C.

[0163] (9) Using low-pressure chemical vapor deposition equipment, under the conditions of power of 450 W, temperature of 700-850° C., and pressure of 12.5 Pa, a first passivation layer 11 (in this example, SiN is used) with a thickness of 100 nm to 300 nm is grown using SiH4 and NH3 gases. x ).

[0164] (10) After photolithography and development, the gate groove 25 is defined, and the first passivation layer 11 above the first CuCrO2 layer 10 and the middle portion of the upper side of the first CuCrO2 layer 10 are opened using inductively coupled plasma (ICP) technology to separate the first passivation layer 11 into left and right regions.

[0165] (11) The first CuCrO2 layer 10 is treated with oxygen plasma at a power of 500 W and an O2 flow rate of 20 sccm; the upper layer is oxidized and the hole concentration is reduced to form the second CuCrO2 layer 12, while the lower layer maintains the original high hole concentration.

[0166] (12) After the double-layer photoresist is developed, the gate 13 region is defined, and Ti / Au metal is deposited using an electron beam evaporation device. After a stripping process, the Schottky gate 13 is obtained. Ti is selected as the metal for preparing the Schottky gate because its work function is significantly different from that of the CuCrO2 material. Au is introduced to prevent metal oxidation and reduce the resistance of the gate 13.

[0167] (13) Using a plasma chemical vapor deposition device, under the conditions of power of 450 W, temperature of 350° C., and pressure of 12.5 Pa, a second passivation layer 14 (in this example, SiN x ).SiN x Multilayer passivation with AlN and single layer SiN x In contrast, it can reduce leakage current and effectively improve breakdown.

[0168] (14) TiN is evaporated using MOCVD equipment, and after a stripping process, a floating field plate 15 with a thickness of 80-150 nm is obtained. With the support of the inverted "L"-shaped floating field plate 15, the electric field distribution of the gate and drain is optimized based on the etched first groove 21, which greatly improves the breakdown voltage of the device, can reduce the probability of electrons tunneling from the barrier layer 6 between the gate 13 and the drain 8 to the surface trap, hinder the formation of the virtual gate effect, weaken the virtual gate effect, and effectively suppress the current collapse effect of the device.

[0169] (15) Using a plasma chemical vapor deposition device, under the conditions of power of 450 W, temperature of 350° C., and pressure of 12.5 Pa, a third passivation layer 16 (in this example, SiN x ).

[0170] (16) After photolithography and development, the source window 26 and the drain window 27 are defined. Using inductively coupled plasma (ICP) technology, the first passivation layer 11, the second passivation layer 14, and the third passivation layer 16 are etched by a F-based dry method, and the AlN layer 9 is etched by a Cl-based dry method to open holes above the source 7 and the drain 8.

[0171] (17) After the double-layer photoresist is developed, the source field plate 17 region is defined; TiN / Al / TiN metal is plated using MOCVD equipment, and after the stripping process, the source field plate 17 and drain interconnect layer 18 are obtained. The thickness of the first layer of TiN is 80-100nm, the thickness of Al is 200-500nm, and the thickness of the top TiN is 120-180nm. The source field plate 17 greatly improves the breakdown voltage of the device.

[0172] In this example, the width of the gate 13 is Wg=100μm, the length of the gate 13 is Lg=5μm, the distance between the gate 13 and the source 7 is Lgs=3μm, the distance between the gate 13 and the drain 8 is Lgd=16μm, and the metal length between the source 7 and the drain 8 is Ls=Lg=3μm.

[0173] The above descriptions are only some embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A p-type gate structure normally-off GaN HEMT device, characterized in that: include: Substrate, nucleation layer, buffer layer, channel layer, spacer layer, barrier layer, source, drain, AlN layer, first CuCrO2 layer, first passivation layer, second CuCrO2 layer, gate, second passivation layer, floating field plate, third passivation layer, source field plate and drain interconnection layer; The substrate, the nucleation layer, the buffer layer, the channel layer, the spacer layer and the barrier layer are stacked in sequence from bottom to top; A source groove is provided on the left side of the barrier layer, a drain groove is provided on the right side of the barrier layer, and a first groove is provided between the source groove and the drain groove and at a position close to the drain groove; The source electrode is located on the source electrode groove, and the drain electrode is located on the drain electrode groove; A left isolation groove is provided on the left side of the barrier layer, the left side of the spacer layer, the left side of the channel layer and the upper left side of the buffer layer, and a right isolation groove is provided on the right side of the barrier layer, the right side of the spacer layer, the right side of the channel layer and the upper right side of the buffer layer; The AlN layer is located on the barrier layer, the source electrode and the drain electrode, and a second groove is formed at the first groove; The first CuCrO2 layer is disposed above a portion of the AlN layer and is located between the source electrode and the drain electrode and close to the second groove; The first passivation layer covers the AlN layer, the source electrode, the first CuCrO2 layer, the drain electrode and the second groove; A gate groove is provided from the middle of the first passivation layer to the upper surface of the first CuCrO2 layer; The second CuCrO2 layer is disposed directly below the gate groove and located in the middle of the upper side of the first CuCrO2 layer; The lower side of the gate is arranged in the gate groove and is located above the second CuCrO2 layer, and the upper side of the gate is located above a portion of the first passivation layer; The second passivation layer covers the first passivation layer and the gate; The lower side of the floating field plate is arranged in the second passivation layer and is located to the right of the gate and directly above the second groove, and the upper side of the floating field plate is located above a portion of the second passivation layer and directly above the gate; The third passivation layer covers the second passivation layer and the floating field plate; A source window is provided in the region above the source electrode among the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer, and the lower side of the source field plate is arranged in the source window and the upper side thereof is located above a portion of the third passivation layer; A drain window is provided in the region above the drain in the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer. The lower side of the drain interconnect layer is arranged in the drain window and the upper side thereof is located above a portion of the third passivation layer.

2. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The material of the substrate includes one of sapphire, silicon, gallium nitride, silicon carbide, ceramic polyaluminum nitride composite material, insulating silicon base and diamond; The material of the nucleation layer is aluminum nitride; The material of the buffer layer is iron- or carbon-doped gallium nitride, a superlattice of alternately grown AlN and GaN multilayers, and Al x1 Ga 1-x1 One of N; The material of the channel layer is gallium nitride; The material of the barrier layer is Al x2 Ga 1-x2 N, x2 is 0.1-0.25; The source and drain electrodes are one of a Ti / Al / Ni / Au multilayer metal stacked structure, a Ti / Al / TiN multilayer metal stacked structure, a Ti / Al / Ti / Au multilayer metal stacked structure, and a Ti / Al / Ti / TiN multilayer metal stacked structure. The gate adopts one of a Ti / Al multi-layer metal stacking structure, a Ti / Au multi-layer metal stacking structure, and a TiN / Al / TiN multi-layer metal stacking structure; The materials of the first passivation layer, the second passivation layer and the third passivation layer include one or more of silicon dioxide, silicon nitride and aluminum oxide; The material of the floating field plate is TiN; The material of the drain interconnection layer is a TiN / Al / TiN multi-layer metal stacked in sequence structure.

3. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The thickness of the nucleation layer is 1-3 nm; The thickness of the buffer layer is 1-6 μm; The thickness of the channel layer is 50-500nm; The thickness of the barrier layer is 10-20 nm; The thickness of the first passivation layer and the second passivation layer is 50-300nm; The thickness of the third passivation layer is 300nm-600nm; The thickness of the AlN layer is 2-5 nm; The thickness of the first CuCrO2 layer is 80-150nm; The thickness of the floating field plate is 80-150 nm.

4. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The width of the nucleation layer is the same as the width of the substrate; The width of the buffer layer is the same as the width of the nucleation layer; A table is formed in the middle of the upper side of the buffer layer; The width of the channel layer is the same as the width of the mesa; The width of the spacer layer is the same as the width of the channel layer; The width of the barrier layer is the same as that of the spacer layer.

5. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The distance between the source electrode and the left side wall of the first CuCrO2 layer is smaller than the distance between the source electrode and the left side wall of the gate electrode, and the distance between the drain electrode and the right side wall of the first CuCrO2 layer is smaller than the distance between the drain electrode and the right side wall of the gate electrode; the distance between the first CuCrO2 layer and the source electrode is smaller than the distance between the first CuCrO2 layer and the drain electrode, and the distance between the gate electrode and the source electrode is smaller than the distance between the gate electrode and the drain electrode.

6. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The floating field plate is an inverted L-shaped structure, and the source field plate and the drain interconnect layer are T-shaped structures.

7. A p-type gate structure normally-off GaN HEMT device according to claim 1, characterized in that: The upper surface of the second CuCrO2 layer is flush with the upper surface of the first CuCrO2 layer, and the hole concentration of the first CuCrO2 layer is 10 18 -10 20 cm -3 The hole concentration of the second CuCrO2 layer is 10 16 -10 18 cm -3 .

8. A method for preparing a p-type gate structure normally-off GaN HEMT device, characterized in that: The method needs to provide a p-type gate structure normally-off GaN HEMT device as described in any one of claims 1 to 7, comprising the following steps: Step 1, epitaxially growing a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer in sequence from bottom to top on the substrate; Step 2, etching a source groove and a drain groove on the left and right sides of the barrier layer respectively, etching a first groove on the barrier layer between the source groove and the drain groove and close to the drain groove; preparing a source electrode above the source groove, and preparing a drain electrode above the drain groove; Step 3, isolating the upper left side of the buffer layer, the left side of the channel layer, the left side of the spacer layer and the left side of the barrier layer, as well as the upper right side of the buffer layer, the right side of the channel layer, the right side of the spacer layer and the right side of the barrier layer by ion implantation or etching, and performing high temperature annealing; Step 4, depositing an AlN layer on the barrier layer, the source electrode and the drain electrode, and forming a second groove at the first groove; Step 5, preparing a first CuCrO2 layer above a portion of the AlN layer, between the source and the drain and close to the second groove, and performing high temperature annealing on the first CuCrO2 layer; Step 6, preparing a first passivation layer on the surfaces of the AlN layer, the source electrode, the first CuCrO2 layer, the drain electrode and the second groove; Step 7, a gate groove is opened from the middle of the first passivation layer to the upper surface of the first CuCrO2 layer, a second CuCrO2 layer is formed by oxygen plasma treatment directly below the gate groove and located in the middle of the upper side of the first CuCrO2 layer, and a gate is prepared on the second CuCrO2 layer in the gate groove to form a Schottky contact; Step 8, preparing a second passivation layer above the first passivation layer and the gate; Step 9, preparing a floating field plate on the second passivation layer and the gate; Step 10, preparing a third passivation layer above the second passivation layer and the floating field plate; Step 11, a source window is formed in the region above the source electrode in the AlN layer, the first passivation layer, the second passivation layer, and the third passivation layer, and a drain window is formed in the region above the drain electrode in the AlN layer, the first passivation layer, the second passivation layer, and the third passivation layer; Step 12: depositing a source field plate in the source window, and depositing a drain interconnect layer in the drain window.

9. The method for preparing a p-type gate normally-off GaN HEMT device according to claim 8, characterized in that: In the step 1, the epitaxial growth method adopts one of MOCVD, HVPE and MBE; in the step 3, the ion implantation adopts F ion or N ion implantation; in the step 4, the AlN layer is deposited by a low-temperature deposition process; in the step 5, the first CuCrO2 layer is prepared by a radio frequency magnetron sputtering process; in the step 6, the first passivation layer is prepared by a low-temperature deposition process or a high-temperature and low-pressure process; in the step 8, the second passivation layer is prepared by a low-temperature deposition process; in the step 10, the third passivation layer is prepared by a low-temperature deposition process; in the steps 7 and 11, the gate groove, the source window and the drain window are opened by ICP etching technology.

10. The method for preparing a p-type gate normally-off GaN HEMT device according to claim 8, characterized in that: In the step 2, before preparing the source and drain, the source groove, the drain groove and the first groove are treated with an inorganic solution or an organic solution, the inorganic solution is HF solution, HCL / H2O2 solution, KOH solution or TMAH solution, and the organic solution is NMP solution.

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