Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate which comprises a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface of the back of the gate structure, wherein the mask corresponds to the conductive channel region; a first concave part is arranged on the mask; removing the mask and the gate structures on the two sides of the conductive channel region, wherein a second concave part is formed in the gate structure corresponding to the conductive channel region; doping the substrate at two sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, wherein the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second concave part; and forming a first metal contact body in the first contact hole, and forming a second metal contact body in the second contact hole. According to the invention, the process window for etching the contact hole can be enlarged, and the abnormal rate of etching through the metal silicide layer is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Metal Oxide Semiconductor Field-Effect-Transistor (MOSFET) is characterized by an oxide layer between the metal gate and the channel, so it has a very high input resistance. MOS tubes play an important role in many electronic devices due to their high input impedance, low power consumption, fast switching speed and easy integration.

[0003] Figure 1 FIG. 1 shows a schematic diagram of the structure of a MOS tube in the prior art. Figure 1 As shown, the MOS transistor includes: a semiconductor substrate 10'; a gate structure 20' located on the semiconductor substrate 10', the gate structure 20' is located in a conductive channel region 11', the gate structure 20' of the conductive channel region 11' is a gate of the MOS transistor to be formed, the gate structure 20' includes a gate oxide layer 21' and a gate electrode layer 22' located on the gate oxide layer 21'; doped regions 12' located on both sides of the gate structure 20', the doped regions 12' are source regions or drain regions of the MOS transistor to be formed; a covering layer 12' and the gate structure 20' A metal silicide layer 30' on the top surface; a dielectric layer 40' located on the metal silicide layer 30' and on the sidewall of the gate structure 20', wherein the dielectric layer 40' is provided with through contact holes, part of which corresponds to the metal silicide layer 30' in the doped region 12', and part of which corresponds to the gate structure 20'; a metal contact body 50' located in the contact hole, part of which is electrically connected to the metal silicide layer 30' in the doped region 12', and part of which is electrically connected to the metal silicide layer 30' on the gate structure 20'. The metal silicide layer 30' is used to reduce the resistance of the gate, source and drain. The metal contact body 50' is used to connect the source or drain region and the gate of the MOS transistor to the upper metal wiring to realize the logic function.

[0004] There is a large height difference between the gate structure 20' and the doped region 12' in the existing MOS transistor, so the metal silicide layer 30' formed on the top of the gate structure 20' and the metal silicide layer 30' formed on the doped region 12' have a certain height difference, so the depth of the contact hole formed on the dielectric layer 40' and corresponding to the doped region 12' is higher than the depth of the contact hole formed on the dielectric layer 40' and corresponding to the gate structure 20'. Therefore, when manufacturing the contact hole in the existing method, it is easy to over-etch the contact hole corresponding to the gate structure 20, and the metal silicide layer 30' is etched through, resulting in the risk of increased resistance at the gate structure 20'.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a semiconductor device and a method for preparing the same, so as to reduce the abnormality rate when etching contact holes, increase the process window for etching contact holes, and improve the reliability of the semiconductor device.

[0007] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] Providing a semiconductor substrate including a conductive channel region;

[0009] forming a gate structure on a surface of the semiconductor substrate;

[0010] A mask is formed on a side of the gate structure away from the semiconductor substrate, and the mask corresponds to the conductive channel region; a first recessed portion is provided on the mask;

[0011] The mask and the gate structures on both sides of the conductive channel region are removed, and a second recessed portion is formed in the gate structure corresponding to the conductive channel region;

[0012] Doping the semiconductor substrate on both sides of the conductive channel region to form a doped region;

[0013] forming a metal silicide layer on a side of the gate structure facing away from the semiconductor substrate and on the doped region;

[0014] forming a dielectric layer on a side of the metal silicide layer away from the semiconductor substrate, wherein the dielectric layer is provided with a first contact hole and a second contact hole, wherein the first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recessed portion;

[0015] A first metal contact body is formed in the first contact hole, and a second metal contact body is formed in the second contact hole.

[0016] In some embodiments, the material of the metal silicide layer includes at least one of cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide, and tantalum silicide.

[0017] In some embodiments, on a vertical projection plane of the semiconductor substrate, an area of ​​the second recessed portion is larger than an area of ​​the second contact hole.

[0018] In some embodiments, at least a portion of the second metal contact is located in the second recess.

[0019] In some embodiments, the step of doping the semiconductor substrate on both sides of the conductive channel region comprises the following steps:

[0020] Lightly doping the semiconductor substrate to form a well region;

[0021] The well region is heavily doped to form a heavily doped contact region.

[0022] In some embodiments, the dielectric layer is silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, or silicon nitride oxide.

[0023] In some embodiments, the gate structure includes a gate dielectric layer located on a surface of the semiconductor substrate and a gate electrode layer located on a surface of the gate dielectric layer.

[0024] In some embodiments, before forming the dielectric layer on the side of the metal silicide facing away from the semiconductor substrate, the method further includes the following steps:

[0025] A spacer structure is formed on the sidewall of the gate structure in the conductive channel region.

[0026] In some embodiments, the forming of the first metal contact body in the first contact hole and the forming of the second metal contact body in the second contact hole comprises the steps of:

[0027] forming a metal contact layer on a side of the dielectric layer away from the semiconductor substrate;

[0028] The metal contact layer is planarized until the first metal contact body and the second metal contact body expose the surface of the dielectric layer.

[0029] In some embodiments, the metal contact layer includes one or more of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0030] An embodiment of the present invention further provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method as described above, and the device comprises:

[0031] A substrate including a conductive channel region and a doped region;

[0032] A gate structure, located on the surface of the substrate and corresponding to the conductive channel region; the gate structure is provided with a second recessed portion;

[0033] a metal silicide layer, located on a side of the gate structure away from the semiconductor substrate and on a surface of the doped region, and the second recess is filled with the metal silicide layer;

[0034] a dielectric layer, located on a side of the metal silicide layer away from the semiconductor substrate; the dielectric layer is provided with a first contact hole and a second contact hole, the first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recessed portion;

[0035] A first metal contact body is disposed in the first contact hole, and a second metal contact body is disposed in the second contact hole.

[0036] The semiconductor device and the method for manufacturing the same provided by the present invention have the following advantages:

[0037] The technical solution utilizes a mask provided with a first recessed portion, so that a second recessed portion is provided on the top of the gate structure after the mask is removed, thereby thickening the metal silicide layer provided on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, the abnormal rate of penetrating the metal silicide layer when etching the first contact hole can be reduced, the process window for etching the contact hole can be increased, the yield rate of preparing MOSFET devices can be improved, and the reliability of semiconductor devices can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0039] Figure 1 It is a cross-sectional schematic diagram of a MOS transistor in the prior art;

[0040] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0041] Figures 3 to 8 It is a schematic cross-sectional structure diagram of a MOS transistor forming process in one embodiment of the present invention.

[0042] Reference numerals:

[0043] 10' Substrate 20 Gate structure in prior art

[0044] 11' Conductive channel region in the prior art 21 Gate oxide layer

[0045] 12' Doping region 22 Gate electrode layer in the prior art

[0046] 20' The second recessed portion of the gate structure 221 in the prior art

[0047] 21' Gate oxide layer 30 Metal silicide layer in the prior art

[0048] 22' Gate electrode layer 40 dielectric layer in the prior art

[0049] 30' Metal silicide layer 41 first contact hole in the prior art

[0050] 40' The dielectric layer 42 in the prior art The second contact hole

[0051] 50' Metal contact body in the prior art 50 Metal contact layer

[0052] 10 substrate 51 first contact body

[0053] 11 Conductive channel region 52 Second contact body

[0054] 12 Doping region 60 Mask layer

[0055] 601 first recessed portion DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0057] In the representations of the present application, the representations with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the represented specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples represented in the present application and the features of the different embodiments or examples, unless they contradict each other.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0059] It should be further understood that the terms "comprises" and "includes" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0060] In order to solve the problems in the prior art, an embodiment of the present invention provides a method for preparing a semiconductor device. Figure 2 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, a method for preparing a semiconductor includes: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the side of the gate structure away from the semiconductor substrate, and the mask corresponds to the conductive channel region; a first recess is provided on the mask; removing the mask and the gate structures on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recess; doping the semiconductor substrate on both sides of the conductive channel region to form a doped region; forming a metal silicide layer on the side of the gate structure away from the semiconductor substrate and on the doped region; forming a dielectric layer on the side of the metal silicide layer away from the semiconductor substrate, the dielectric layer is provided with a first contact hole and a second contact hole, the first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recess; forming a first metal contact body in the first contact hole, and forming a second metal contact body in the second contact hole.

[0061] The technical solution utilizes a mask provided with a first recessed portion, so that a second recessed portion is provided on the top of the gate structure after the mask is removed, thereby thickening the metal silicide layer provided on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, the abnormal rate of penetrating the metal silicide layer when etching the first contact hole can be reduced, the process window for etching the contact hole can be increased, the yield rate of preparing MOSFET devices can be improved, and the reliability of semiconductor devices can be improved.

[0062] In order to make the purpose, features and advantages of the present invention more clearly understood, reference is made to the accompanying drawings. Figures 2 to 8 The method for preparing the MOS transistor of the present invention is described in detail.

[0063] Figures 3 to 8 It is a schematic cross-sectional structure diagram of a semiconductor device forming process in one embodiment of the present invention.

[0064] like Figure 3 As shown, step S100: provide a semiconductor substrate 10. Specifically, the semiconductor substrate 10 can be at least one of the following materials: Si (silicon), Ge (germanium), SiC (silicon carbide), InP (indium phosphide) or other III and IV compound semiconductors, wherein the silicon material includes single crystal silicon, polycrystalline silicon or amorphous silicon. The semiconductor substrate 10 can also be a semiconductor-on-insulator structure, which includes an insulator and a semiconductor material layer located on the insulator, and the material of the semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, etc.

[0065] Please continue reading Figure 3 , step S200: forming a gate structure 20 on the surface of the semiconductor substrate 10. In this embodiment, the gate structure 20 may include a gate dielectric layer 21 located on the surface of the semiconductor substrate 10 and a gate electrode layer 22 located on the surface of the gate dielectric layer 21. The material of the gate dielectric layer 21 may be a composite material layer composed of one or more materials selected from silicon oxide, chromium oxide or silicon oxynitride. The material of the gate electrode layer 22 may be, for example, a polysilicon layer or a metal material.

[0066] like Figure 4 As shown, step S300 : forming a mask 60 on a side of the gate structure 20 away from the semiconductor substrate 10 , and the mask 60 corresponds to the conductive channel region 11 ; a first recess 601 is provided on the mask 60 .

[0067] Furthermore, if Figure 5As shown, step 400: remove the mask 60 and the gate structure 20 on both sides of the conductive channel region 11, and the gate structure 20 corresponding to the conductive channel region 11 is formed with a second recessed portion 221. When the mask 60 is removed by an etching process, the thickness of the mask 60 at the first recessed portion 601 is small, so a groove, i.e., the second recessed portion 221, is etched on the gate structure 20 corresponding to the first recessed portion 601. The gate structure 20 controls the generation and elimination of charges in the conductive channel region. The shape of the first recessed portion 601 is not limited to Figure 5 The shape shown is a schematic diagram. Those skilled in the art can set the shape of the first recessed portion 601 according to actual needs.

[0068] Furthermore, if Figure 5 As shown, step 500: doping the semiconductor substrate 10 on both sides of the conductive channel region 11 to form a doped region 12, where the doped region 12 is a source region or a drain region.

[0069] Furthermore, if Figure 6 As shown, step 600: forming a metal silicide layer 30 on the side of the gate structure 20 facing away from the semiconductor substrate 10 and on the doped region 12. The metal silicide layer 30 can be used to reduce the contact resistance between the gate structure 20 and the doped region 12. The material of the metal silicide layer 30 includes at least one of cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide and metal tantalum silicide.

[0070] Furthermore, if Figure 7 As shown, step S700: forming a dielectric layer 40 on the side of the metal silicide layer 30 away from the semiconductor substrate 10, the dielectric layer 40 is provided with a first contact hole 41 and a second contact hole 42, the first contact hole 41 corresponds to the doped region 12, and the second contact hole 42 corresponds to the second recessed portion 221.

[0071] In the embodiment of the present invention, on the vertical projection plane of the semiconductor substrate 10, the area of ​​the second recessed portion 221 is larger than the area of ​​the second contact hole 42. This arrangement makes it difficult for the thickness of the metal silicide layer 30 thereunder to be etched through when the second contact hole 42 is etched, thereby reducing the abnormality rate of etching through the metal silicide layer 30.

[0072] Further, such as Figure 8 As shown, step S800 : forming a first metal contact body 51 in the first contact hole 41 , and forming a second metal contact body 52 in the second contact hole 42 .

[0073] The present technical solution utilizes a mask 60 having a first recessed portion 601, so that after the mask 60 is removed, a second recessed portion 221 is provided on the top of the gate structure 20, thereby thickening the metal silicide layer 30 provided on the surface of the gate structure 20. When etching the first contact hole corresponding to the gate structure 20, the process window for etching the first contact hole can be increased, the abnormal rate of penetrating the metal silicide layer 30 when etching the first contact hole can be reduced, the process window for etching the contact hole can be increased, the yield rate of preparing MOSFET devices can be improved, and the reliability of semiconductor devices can be improved.

[0074] Furthermore, in some embodiments of the present invention, the method for forming the metal silicide layer 30 is, for example, to form a metal layer on the surface where the doped region 12 and the gate structure 20 are exposed; and to further anneal the metal layer so that the metal layer and the silicon element in the semiconductor substrate 10 and the gate structure 20 in contact with the metal layer react chemically, thereby generating the metal silicide layer 30. The metal silicide layer 30 can reduce the resistance between the contact body formed subsequently and the doped region 12 and the gate structure 20. The metal layer material is a single metal or alloy of Ni, W, Ti, Ta, Pt, and Co.

[0075] Furthermore, in some embodiments, step S500 of doping the semiconductor substrate 10 on both sides of the conductive channel region 11 includes the following steps:

[0076] Doping is performed on the semiconductor substrate 10 to form a well region;

[0077] Doping is performed in the well region to form a heavily doped contact region.

[0078] The doping region is formed by, for example, a high-density plasma doping process, and N-type or P-type doping ion implantation is performed according to the doping concentration designed by the process. In the embodiment of the present invention, in the process steps of performing N-type or P-type doping ion implantation to form the lightly doped region and the heavily doped region, the ion implantation process adopts a certain tilt angle, and an annealing process can be used after the ion implantation, so that a part of the lightly doped region and the heavily doped region are located directly below the gate structure 20. The annealing treatment activates the doping ions so that the doping ions are redistributed in the substrate, and at the same time, repairs the lattice damage to the substrate caused by the ion process.

[0079] In the embodiment of the present invention, the semiconductor device formed is an NMOS transistor for exemplary explanation, and the implanted ions of the ion implantation are N-type ions, and the N-type ions are P, As or Sb. In other embodiments, when the semiconductor device formed is a PMOS transistor, the implanted ions of the ion implantation are P-type ions, and the P-type ions are B, Ga or In.

[0080] In some embodiments, before the step of forming the dielectric layer 40 on the side of the metal silicide layer 30 facing away from the semiconductor substrate 10, the following steps are further included:

[0081] A spacer structure is formed on the sidewall of the gate structure 20 in the conductive channel region 11 .

[0082] The sidewall structure is used to limit the lateral current between the gate structure 20 and the source or drain, prevent the current from directly leaking from the source or drain, and improve the reliability of the semiconductor device. The material of the sidewall structure is, for example, a composite material layer composed of one or more materials of silicon oxide, silicon nitride or silicon oxynitride.

[0083] Furthermore, the material of the dielectric layer 40 may be silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. The dielectric layer may be formed by, for example, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0084] Furthermore, step S800 forms a first metal contact body 51 in the first contact hole 41 and a second metal contact body 52 in the second contact hole 42, including the steps of:

[0085] A metal contact layer 50 is formed on a side of the dielectric layer 40 facing away from the semiconductor substrate 10;

[0086] The metal contact layer 50 is planarized until the first metal contact body 51 and the second metal contact body 52 expose the surface of the dielectric layer 40 .

[0087] The material of the metal contact layer 50 may include one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum. The process of forming the metal contact body in the contact hole includes using chemical vapor deposition or physical vapor deposition process, and using chemical mechanical polishing process to flatten the metal contact layer 50.

[0088] The embodiment of the present invention further provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method as described above. The semiconductor device can achieve the technical effect of the semiconductor device manufacturing method as described above, which will not be described in detail here. Figure 8 As shown, the semiconductor device includes:

[0089] A substrate 10, comprising a conductive channel region 11 and a doped region 12;

[0090] The gate structure 20 is located on the surface of the semiconductor substrate 10 and corresponds to the conductive channel region 11 . The gate structure 20 is provided with a second recessed portion 221 .

[0091] The metal silicide layer 30 is located on a side of the gate structure 20 away from the semiconductor substrate 10 and on a surface of the doped region 12 , and the metal silicide layer 30 fills the second recess 221 ;

[0092] The dielectric layer 40 is located on the side of the metal silicide layer 30 away from the semiconductor substrate 10; the dielectric layer 40 is provided with a first contact hole 41 and a second contact hole 42, the first contact hole 41 corresponds to the doped region 12, and the second contact hole 42 corresponds to the second recessed portion 221;

[0093] A first metal contact body 51 is disposed in the first contact hole 41 , and a second metal contact body 52 is disposed in the second contact hole 42 .

[0094] In summary, the semiconductor device and the method for manufacturing the same provided by the present invention have the following advantages:

[0095] The technical solution utilizes a mask provided with a first recessed portion, so that a second recessed portion is provided on the top of the gate structure after the mask is removed, thereby thickening the metal silicide layer provided on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, the abnormal rate of penetrating the metal silicide layer when etching the first contact hole can be reduced, the process window for etching the contact hole can be increased, the yield rate of preparing MOSFET devices can be improved, and the reliability of semiconductor devices can be improved.

[0096] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate including a conductive channel region; forming a gate structure on a surface of the semiconductor substrate; A mask is formed on a side of the gate structure away from the semiconductor substrate, and the mask corresponds to the conductive channel region; a first recessed portion is provided on the mask; The mask and the gate structures on both sides of the conductive channel region are removed, and a second recessed portion is formed in the gate structure corresponding to the conductive channel region; Doping the semiconductor substrate on both sides of the conductive channel region to form a doped region; forming a metal silicide layer on a side of the gate structure facing away from the semiconductor substrate and on the doped region; forming a dielectric layer on a side of the metal silicide layer away from the semiconductor substrate, wherein the dielectric layer is provided with a first contact hole and a second contact hole, wherein the first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recessed portion; A first metal contact body is formed in the first contact hole, and a second metal contact body is formed in the second contact hole.

2. The method for preparing a semiconductor device according to claim 1, wherein: The material of the metal silicide layer includes at least one of cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide and tantalum silicide.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: On a vertical projection plane of the semiconductor substrate, an area of ​​the second recessed portion is larger than an area of ​​the second contact hole.

4. The method for preparing a semiconductor device according to claim 1, wherein: The step of doping the semiconductor substrate on both sides of the conductive channel region comprises the following steps: Lightly doping the semiconductor substrate to form a well region; The well region is heavily doped to form a heavily doped contact region.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The dielectric layer is made of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

6. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: Before forming the dielectric layer on the side of the metal silicide facing away from the semiconductor substrate, the method further comprises the following steps: A spacer structure is formed on the sidewall of the gate structure in the conductive channel region.

8. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of forming a first metal contact body in the first contact hole and forming a second metal contact body in the second contact hole comprises the following steps: forming a metal contact layer on a side of the dielectric layer away from the semiconductor substrate; The metal contact layer is planarized until the first metal contact body and the second metal contact body expose the surface of the dielectric layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The metal contact layer includes one or a combination of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

10. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for preparing the semiconductor device according to any one of claims 1 to 9, wherein the device comprises: A substrate including a conductive channel region and a doped region; A gate structure, located on the surface of the substrate and corresponding to the conductive channel region; the gate structure is provided with a second recessed portion; A metal silicide layer, located on a side of the gate structure away from the semiconductor substrate and on a surface of the doped region; a dielectric layer, located on a side of the metal silicide layer away from the semiconductor substrate; the dielectric layer is provided with a first contact hole and a second contact hole, the first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recessed portion; A first metal contact body is disposed in the first contact hole, and a second metal contact body is disposed in the second contact hole.

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