Power switch transistor

Abstract

The invention relates to a power switch transistor, and belongs to the field of semiconductor power devices. The transistor comprises a drift region, a semiconductor body region, a terminal voltage-withstanding region, a floating electrode semiconductor region, a gate insulating medium region, a third electrode polycrystalline semiconductor region, a first insulating passivation layer, a second insulating passivation layer, a second electrode metal region, a floating electrode metal region, a third electrode metal region, a first electrode semiconductor region and a first electrode metal region, and the second insulating passivation layer and the second electrode surface metal layer form a terminal metal shielding structure, so that the influence of a packaging lead or a copper strip on a terminal voltage-resistant region of the power switch transistor chip can be effectively eliminated, the breakdown voltage of the chip is ensured not to be interfered, the length of the packaging lead or the copper strip can be further shortened, and the power switch transistor chip can be manufactured. And even lead bonding is not needed, so that the area occupied by the chip packaging lead and the parasitic inductance introduced by the lead are reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor power devices and relates to a power switching transistor. Background Art

[0002] Power switching transistors are essential basic electronic components in power electronic systems and are one of the most widely used power semiconductor devices. Their main function is to control the switching of high voltage and high current. Common power switching transistors include power MOSFET and IGBT. In practical applications, power switching transistors can appear in single tube form or in module form. There is generally only one power switching transistor chip in a single tube; while modules often include multiple chips, such as a single-phase full-bridge inverter module containing 4 power switching transistor chips; in some switching power modules, power switching transistor chips are used in combination with power diode chips. Whether in a single tube or in a module, the electrodes on the surface of the power switching transistor chip need to be connected to the electrodes of the remaining chips or the pins of the tube shell, generally using wires or copper tape bonding. Due to factors such as electrical isolation and process limitations, longer wires or copper tapes will occupy a certain amount of space and will also introduce parasitic inductance, thereby affecting the switching speed and increasing switching losses. Therefore, advanced packaging technology reduces the device area and parasitic inductance by continuously shortening the length of the wires or copper tapes. However, shortening the length of the wires or copper tapes may affect the breakdown voltage of the chip.

[0003] Power switching transistors often need to withstand high voltages. Therefore, in addition to the active area for conduction in the power switching transistor chip, a terminal withstand voltage area is generally set around the active area. Common terminal withstand voltage structures include field limiting rings, field plates, and junction terminal extension injection. When the power switching transistor chip is subjected to a high blocking voltage, the terminal withstand voltage area shares the high voltage distributed along the surface. This high voltage not only appears inside and on the surface of the chip, but also forms an electric field above the terminal withstand voltage area. Conductive materials such as metals (such as leads and copper strips) above the terminal withstand voltage area will affect the distribution of the electric field and ultimately affect the breakdown voltage of the chip. Therefore, when packaging and wiring, the leads or copper strips will be arc-shaped to keep a certain distance from the terminal withstand voltage area of ​​the chip to avoid affecting the breakdown voltage of the chip. However, the increase in the length of the arc-shaped leads or copper strips will take up more space. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a power switching transistor, which eliminates the influence of the package lead or copper tape on the terminal voltage-resistant area of ​​the power switching transistor chip by setting a shielding structure on the transistor terminal voltage-resistant area, thereby ensuring that the breakdown voltage of the chip is not disturbed, and the length of the package lead or copper tape can be further shortened, and even wire bonding is not required, thereby reducing the volume occupied by the chip package lead and the parasitic inductance introduced by the lead.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A power switch transistor, the transistor device comprising:

[0007] Drift zone;

[0008] A semiconductor body region is formed in the drift region and is flush with an upper surface of the drift region;

[0009] A terminal voltage-withstanding region is formed in the drift region and distributed on both sides of the semiconductor body region, and the upper surface of the terminal voltage-withstanding region is flush with the upper surface of the drift region;

[0010] A floating electrode semiconductor region is formed in the drift region and distributed on both sides of the semiconductor body region, and the upper surface of the floating electrode semiconductor region is flush with the upper surface of the drift region; wherein the floating electrode semiconductor region is located outside the terminal withstand voltage region;

[0011] A gate insulating dielectric region, wherein the gate insulating dielectric region has a plurality of parts, each of which is formed at intervals on the upper surface of the semiconductor body region;

[0012] A third electrode polycrystalline semiconductor region is formed in each portion of the gate insulating dielectric region;

[0013] A first insulating passivation layer is formed on the upper surface of the drift region and the terminal withstand voltage region and is distributed on both sides of the outer gate insulating dielectric region;

[0014] A second insulating passivation layer is formed on the upper surface of the first insulating passivation layer at both sides;

[0015] A second electrode metal region is formed on the upper surface of the drift region and between the first insulating passivation layer and the second insulating passivation layer on both sides, filling the gaps between each portion of the gate insulating dielectric region, and the second electrode metal region extends to the top surface of the transistor device, thereby covering a portion of the second insulating passivation layer;

[0016] A floating electrode metal region is formed on the upper surface of the floating electrode semiconductor region and is surrounded by a first insulating passivation layer;

[0017] a third electrode metal region, a portion of the third electrode metal region is formed on the upper surface of the second insulating passivation layer not covered by the second electrode metal region, and another portion of the third electrode metal region penetrates the second insulating passivation layer and the first insulating passivation layer and extends to the surface of the third electrode polycrystalline semiconductor region;

[0018] A first electrode semiconductor region is formed on the lower surface of the drift region;

[0019] The first electrode metal region is formed on the lower surface of the first electrode semiconductor region.

[0020] The second electrode metal region and the third electrode metal region cover the top surface of the transistor device and form two equipotential surfaces.

[0021] The semiconductor body region may have multiple parts, each of which is separated by a drift region, and a semiconductor source region is formed in each part of the semiconductor body region, and the upper surface of the semiconductor source region is flush with the upper surface of the semiconductor body region. Based on the multiple parts of the semiconductor body region, a gate insulating dielectric region is formed above each two adjacent semiconductor body regions, and the lower surface of each gate insulating dielectric region is in contact with the upper surface of the semiconductor body region, the semiconductor source region and the drift region respectively.

[0022] Optionally, the second electrode metal region is formed on the upper surface of the drift region and between the first insulating passivation layer and the second insulating passivation layer on both sides, filling the gaps between each gate insulating dielectric region, wherein the second electrode metal region has a groove, and the second electrode metal regions on both sides of the groove extend to the top surface of the transistor device and cover the second insulating passivation layer on both sides; in the groove, a first insulating passivation layer and a second insulating passivation layer are stacked sequentially from bottom to top, based on this structure, a part of the third electrode metal region is formed on the upper surface of the second insulating passivation layer in the groove, and another part penetrates the second insulating passivation layer and the first insulating passivation layer in the groove, and extends to the surface of the third electrode polycrystalline semiconductor region. Thus, the second electrode metal region and the third electrode metal region form two equipotential surfaces on the top surface of the transistor device.

[0023] Optionally, a plurality of gate insulating dielectric regions may extend into the drift region, wherein two sides of a portion of the gate insulating dielectric region located in the drift region are in contact with the semiconductor body region respectively.

[0024] The beneficial effects of the present invention are as follows: the present invention forms a terminal metal shielding structure by introducing an insulating passivation layer, which can effectively eliminate the influence of the package lead or copper tape on the terminal withstand voltage area of ​​the power switch transistor chip, and ensure that the breakdown voltage of the chip is not disturbed. Compared with the conventional power switch transistor structure, the present invention can further shorten the length of the package lead or copper tape, and even eliminate the need for wire bonding, thereby reducing the area occupied by the chip package lead and the parasitic inductance introduced by the lead.

[0025] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 A schematic diagram of the structure of a power switch transistor provided in Embodiment 1 of the present invention;

[0028] Figure 2 A schematic diagram of the structure of a power switch transistor provided in Embodiment 2 of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a power switch transistor provided in Embodiment 3 of the present invention;

[0030] Figure 4 This is a schematic diagram of the power switch transistor structure provided in Example 4 of the present invention.

[0031] Figure markings: 1-first electrode metal region; 2-second electrode metal region; 3-third electrode metal region; 4-floating electrode metal region; 5-first electrode semiconductor region; 6-drift region; 7-semiconductor source region; 8-floating electrode semiconductor region; 9-semiconductor body region; 10-terminal voltage-withstand region; 11-gate insulating dielectric region; 12-first insulating passivation layer; 13-second insulating passivation layer; 14-third electrode polycrystalline semiconductor region. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0033] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0034] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0035] In order to avoid the influence on the terminal withstand voltage area of ​​the power switch transistor chip under the premise of shortening the length of the package lead or copper tape, the present invention proposes a terminal metal shielding structure, thereby effectively eliminating the influence of the package lead or copper tape on the terminal withstand voltage area of ​​the power switch transistor chip, ensuring that the breakdown voltage of the chip is not disturbed, so that the length of the package lead or copper tape can be further shortened, and even wire bonding is not required, thereby reducing the volume occupied by the chip package lead and the parasitic inductance introduced by the lead. The power switch transistor proposed by the present invention will be described in detail with multiple embodiments below.

[0036] Example 1

[0037] like Figure 1 As shown, the power switch transistor provided in this embodiment includes:

[0038] A semiconductor lightly doped drift region 6 of the first conductivity type;

[0039] A first electrode semiconductor region 5 located below the drift region 6, the first electrode semiconductor region 5 is in contact with the drift region 6, and the first electrode semiconductor region 5 is heavily doped compared to the drift region 6, and may be of the first conductivity type or the second conductivity type;

[0040] A first electrode metal region 1 is located below the first electrode semiconductor region 5, and the first electrode semiconductor region 5 is in contact with the first electrode metal region 1;

[0041] A plurality of semiconductor body regions 9 of the second conductivity type, a terminal withstand voltage region 10 of the second conductivity type, and a floating electrode semiconductor region 8 are arranged inside the drift region 6; wherein the semiconductor body region 9 and the terminal withstand voltage region 10 are surrounded by the drift region 6; among the plurality of semiconductor body regions 9, the semiconductor body regions at the edges of both sides are in contact with the terminal withstand voltage region 10 respectively; a plurality of semiconductor source regions 7 of the first conductivity type are arranged inside the semiconductor body region 9, the semiconductor source region 7 is surrounded by the semiconductor body region, and the semiconductor source region 7 is heavily doped;

[0042] A gate insulating dielectric region 11 is disposed on the adjacent semiconductor body region 9, wherein the gate insulating dielectric region 11 covers a portion of the semiconductor source region 7, a portion of the semiconductor body region 9 and a portion of the drift region 6;

[0043] A third electrode polycrystalline semiconductor region 14 embedded in each gate insulating dielectric region 11, wherein the third electrode polycrystalline semiconductor region 14, a portion of the gate insulating dielectric region 11, a portion of the semiconductor source region 7, a portion of the semiconductor body region 9 and a portion of the drift region 6 constitute a MOS cell structure;

[0044] A second electrode metal region 2 is provided on the MOS cell structure and the terminal withstand voltage region 10, and the second electrode metal region 2 covers a portion of the semiconductor source region 7, a portion of the semiconductor body region 9, a portion of the terminal withstand voltage region 10, and the top surface and both sides of the gate insulating dielectric region 11; wherein the second electrode metal region 2 is formed with a groove;

[0045] A floating electrode semiconductor region 8 located in the drift region 6 and distributed on both sides of the terminal voltage-withstanding region 10;

[0046] The floating electrode metal region 4 is arranged above the floating electrode semiconductor regions 8 on both sides, and the floating electrode metal region is in contact with the top surface of part of the floating electrode semiconductor region 8;

[0047] A first insulating passivation layer 12 is located above the terminal withstand voltage regions 10 on both sides and in the groove of the second electrode metal region 2. The first insulating passivation layer 12 covers part of the floating electrode semiconductor region 8, part of the drift region 6 and part of the terminal withstand voltage region 10. The floating electrode metal region 4 is surrounded by the first insulating passivation layer 12;

[0048] A second insulating passivation layer 13 is located above the three-part first insulating passivation layer 10, and the bottom surface of the second insulating passivation layer 13 is in contact with the top surface of the first insulating passivation layer 12;

[0049] The third electrode metal region 3 is disposed on the upper surface of the second insulating passivation layer 13 in the groove of the second electrode metal region 2 .

[0050] The second electrode metal region is divided into three parts: upper, middle and lower parts; the lower part of the second electrode metal region is embedded in the first insulating passivation layer; the middle surface part of the second electrode metal region passes through the second insulating passivation layer and is embedded in the first insulating passivation layer; the upper part of the second electrode metal region is located on the second insulating passivation layer, and its bottom surface is connected to the top surface of the second insulating passivation layer;

[0051] The third electrode metal region is divided into an upper part and a lower part, the lower part of the third electrode metal region passes through the second insulating passivation layer, the first insulating passivation layer and the gate insulating dielectric region until the bottom surface of the lower part of the third electrode metal region contacts the top surface of the third electrode polycrystalline semiconductor region; the upper part of the third electrode metal region is located on the second insulating passivation layer, and the bottom surface thereof is connected to the top surface of the second insulating passivation layer;

[0052] This embodiment introduces a thicker second insulating passivation layer into the power switch transistor chip, thickens the second electrode metal area and the third electrode metal area, and extends the second electrode metal area and the third electrode metal area to the chip surface, so that the chip surface becomes two equipotential surfaces. When the power switch transistor is subjected to a high blocking voltage, the electric field above the terminal withstand voltage area of ​​the chip is confined in the insulating passivation layer and is determined by the thickness and dielectric constant of the insulating passivation layer, thereby shielding the effect of the connecting metal wires (such as leads, copper strips, etc.) passing through the chip surface on the electric field in the terminal withstand voltage area, ensuring that the breakdown voltage of the chip is not affected. Among them, the thickness of the second insulating passivation layer needs to be reasonably set to ensure that it is not broken down by the high blocking voltage and works safely and reliably.

[0053] When the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

[0054] When the first electrode semiconductor region 5 is of the first conductivity type, the power switching transistor is a MOSFET structure, the first electrode is the drain, the second electrode is the source, and the third electrode is the gate; when the first electrode semiconductor region 5 is of the second conductivity type, the power switching transistor is an IGBT structure, the first electrode is the collector, the second electrode is the emitter, and the third electrode is the gate.

[0055] The semiconductor region may be made of silicon, or may be made of germanium, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, diamond, or aluminum nitride.

[0056] The terminal voltage-withstanding region 10 may be a floating field limiting ring, a junction terminal extension, a field plate, etc., or a combination structure of a floating field limiting ring, a junction terminal extension, and a field plate.

[0057] Example 2

[0058] like Figure 2As shown, compared with the device proposed in Example 1, this embodiment does not have a groove in the second electrode metal region 2, and reduces the width of the second electrode metal region 2 in the lateral direction, thereby increasing the width of the second insulating passivation layer 13 on one side of the second electrode metal region 2 in the lateral direction; at the same time, the third electrode metal region 3 is arranged on the upper surface of the second insulating passivation layer 13 on one side of the second electrode metal region 2, and the second electrode metal region 2 and the third electrode metal region 3 are still extended to the surface of the transistor chip, so that the chip surface becomes two equipotential surfaces.

[0059] Example 3

[0060] like Figure 3 As shown, compared with the device proposed in Example 1, the present embodiment extends the gate insulating dielectric region 11 into the drift region 6 to form a trench MOS cell structure, and the left and right sides of the portion of the gate insulating dielectric region 11 located in the drift region 6 are in contact with the semiconductor source region 7 and the semiconductor body region 9. In addition, the polycrystalline semiconductor region 14 located in the gate insulating dielectric region 11 is also correspondingly extended in the vertical direction, but does not protrude outside the gate insulating dielectric region 11.

[0061] Example 4

[0062] like Figure 4 As shown, compared with the device proposed in Example 2, the present embodiment extends the gate insulating dielectric region 11 into the drift region 6 to form a trench MOS cell structure, and the left and right sides of the portion of the gate insulating dielectric region 11 located in the drift region 6 are in contact with the semiconductor source region 7 and the semiconductor body region 9. In addition, the polycrystalline semiconductor region 14 located in the gate insulating dielectric region 11 is also correspondingly extended in the vertical direction, but does not protrude outside the gate insulating dielectric region 11.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A power switching transistor, characterized in that: It includes: Drift zone; A semiconductor body region, wherein the semiconductor body region is formed in the drift region and is flush with an upper surface of the drift region; A terminal voltage-withstanding region, wherein the terminal voltage-withstanding region is formed in the drift region and distributed on both sides of the semiconductor body region, and an upper surface of the terminal voltage-withstanding region is flush with an upper surface of the drift region; A floating electrode semiconductor region, wherein the floating electrode semiconductor region is formed in the drift region and distributed on both sides of the semiconductor body region, and an upper surface of the floating electrode semiconductor region is flush with an upper surface of the drift region; A gate insulating dielectric region, wherein a plurality of the gate insulating dielectric regions are formed at intervals on the upper surface of the semiconductor body region; a third electrode polycrystalline semiconductor region, wherein the third electrode polycrystalline semiconductor region is formed in the plurality of gate insulating dielectric regions; A first insulating passivation layer, wherein the first insulating passivation layer is formed on the upper surfaces of the drift region and the terminal withstand voltage region and is distributed on both sides of the outer gate insulating dielectric region; A second insulating passivation layer, wherein the second insulating passivation layer is formed on upper surfaces of the first insulating passivation layer at both sides; A second electrode metal region, wherein the second electrode metal region is formed on the upper surface of the drift region and between the first insulating passivation layer and the second insulating passivation layer on both sides thereof, filling the gaps between the plurality of gate insulating dielectric regions, and the second electrode metal region extends to the top surface of the transistor device to cover a portion of the second insulating passivation layer; a floating electrode metal region, wherein the floating electrode metal region is formed on an upper surface of the floating electrode semiconductor region and is surrounded by the first insulating passivation layer; a third electrode metal region, a portion of the third electrode metal region is formed on the upper surface of the second insulating passivation layer not covered by the second electrode metal region, and another portion of the third electrode metal region penetrates the second insulating passivation layer and the first insulating passivation layer and extends to the surface of the third electrode polycrystalline semiconductor region; A first electrode semiconductor region, wherein the first electrode semiconductor region is formed on a lower surface of the drift region; A first electrode metal region is formed on a lower surface of the first electrode semiconductor region.

2. The power switch transistor according to claim 1, characterized in that: The semiconductor body region has a plurality of parts, and each part is separated by the drift region.

3. The power switch transistor according to claim 2, characterized in that: A semiconductor source region is formed in each of the semiconductor body regions, and an upper surface of the semiconductor source region is flush with an upper surface of the semiconductor body region.

4. The power switching transistor according to claim 2 or 3, characterized in that: A plurality of gate insulating dielectric regions are formed on the upper surface of the semiconductor body region, wherein one gate insulating dielectric region is formed above every two adjacent semiconductor body regions; the lower surface of each gate insulating dielectric region is in contact with the upper surfaces of the semiconductor body region, the semiconductor source region and the drift region respectively.

5. The power switch transistor according to claim 1, characterized in that: The second electrode metal region is formed on the upper surface of the drift region and between the first insulating passivation layer and the second insulating passivation layer on both sides, filling the gaps between the multiple gate insulating dielectric regions, the second electrode metal region has a groove, the second electrode metal regions on both sides of the groove extend to the top surface of the transistor device and cover the second insulating passivation layer on both sides; the first insulating passivation layer and the second insulating passivation layer stacked in sequence from bottom to top are formed in the groove, a part of the third electrode metal region is formed on the upper surface of the second insulating passivation layer in the groove, and the other part penetrates the second insulating passivation layer and the first insulating passivation layer in the groove and extends to the surface of the third electrode polycrystalline semiconductor region.

6. The power switch transistor according to claim 1, characterized in that: A plurality of gate insulating dielectric regions extend into the drift region, and two sides of a portion of the gate insulating dielectric region located in the drift region are in contact with the semiconductor body region respectively.

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