High-integration-level double-layer integrated circuit structure and preparation method thereof

Abstract

The invention provides a high-integration-level double-layer integrated circuit structure and a preparation method, and the method comprises the steps: a first wafer comprises an upper substrate and a first isolation layer, a second wafer comprises a lower substrate and a second isolation layer, and the first isolation layer and the second isolation layer are bonded together to form an isolation layer; forming a first through hole penetrating through the upper substrate and the lower substrate, and forming isolation regions in the first through hole and on the surfaces of the upper substrate and the lower substrate; forming devices on the upper substrate and the lower substrate; and forming a second through hole in the isolation region in the first through hole, and forming a conductive layer in the second through hole for connecting devices on the upper substrate and the lower substrate in series. According to the invention, the upper and lower symmetrical devices are formed on the two bonded wafers, and the upper and lower layers of devices are connected in series through the through conductive layer, so that a part of preparation process can be saved, the process flow is shortened, and the integration level of the chip is improved.

Description

Technical Field

[0001] The invention belongs to the field of double-layer integrated circuits, and in particular relates to a highly integrated double-layer integrated circuit structure and a preparation method thereof. Background Art

[0002] Since the birth of Moore's Law, the number of transistors has doubled every year. As time goes by, the process node has reached 2nm or even 0.3nm, all for the purpose of increasing the number of transistors and improving the operating speed of chips. When it grows to a certain extent, the number of transistors can only be increased by changing the structure, but the change of structure will make the process very complicated, such as Fin FET and GAA. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a highly integrated double-layer integrated circuit structure and a preparation method thereof, which can increase the number of transistors while saving process flow.

[0004] The technical solution adopted by the present invention to solve the above technical problems is: As a first aspect of the present invention, the present invention provides a method for preparing a highly integrated double-layer integrated circuit structure, comprising the steps of: The first wafer includes an upper substrate and a first isolation layer, the second wafer includes a lower substrate and a second isolation layer, and the first isolation layer and the second isolation layer are bonded together to form an isolation layer; Forming a first through hole penetrating the upper substrate and the lower substrate, and forming an isolation region in the first through hole, on the surface of the upper substrate, and on the surface of the lower substrate; forming devices on the upper substrate and the lower substrate; A second through hole is formed in the isolation region within the first through hole, and a conductive layer is formed in the second through hole for connecting devices located on the upper substrate and the lower substrate in series.

[0005] According to the above method, the formation of the isolation zone specifically includes: forming an oxide layer and an etching stop layer of a certain thickness on the surfaces of the upper substrate and the lower substrate respectively; Forming a layer required for exposure, development and etching on the etching stop layer on one side, etching a first through hole, the first through hole penetrating the upper substrate and the lower substrate and extending all the way to the etching stop layer on one side; Filling an insulating layer in the first through hole, wherein the insulating layer and the oxide layers on both sides together constitute the isolation region; Annealing makes the insulating layer more densely filled.

[0006] According to the above method, when the device is a MOS tube, its formation includes: Performing ion implantation on the regions on the upper substrate and the lower substrate for forming the device, respectively, to form well regions; The first annealing activates ions in the well regions of the upper substrate and the lower substrate; Removing the isolation regions on the surfaces of the upper substrate and the lower substrate to expose the isolation regions and the well region in the first through hole, and then forming a gate oxide layer of a certain thickness on the surfaces of the upper substrate and the lower substrate; Forming a polysilicon layer used as a gate on the surfaces of the gate oxide layers of the upper substrate and the lower substrate respectively, and performing gate ion doping; The second annealing makes the gate ions in the upper and lower polysilicon layers implanted uniformly; A gate, a source and a drain are formed on the upper substrate, the lower substrate and the corresponding polysilicon layer respectively.

[0007] According to the above method, when gate ion doping is performed on the upper and lower polysilicon layers respectively, carbon group element ions are also injected; the carbon group element ions in the upper and lower polysilicon layers are injected uniformly during the second annealing process.

[0008] According to the above method, the formation of the conductive layer specifically includes: forming an etch stop layer and an ILD oxide layer on the outer surfaces of the gate, source and drain of the upper substrate and the lower substrate respectively; forming a first metal from the ILD oxide layer on one side through the isolation region to the etch stop layer on the opposite side; Forming a second metal connected to the first metal on the ILD oxide layer on the other side; The first metal and the second metal form a conductive layer.

[0009] According to the above method, the device is a MOS tube, a diode, a triode, an IGBT or a thyristor.

[0010] As a second aspect of the present invention, the present invention provides a highly integrated double-layer integrated circuit structure, comprising an upper substrate, an isolation layer and a lower substrate obtained by a bonding process; devices are formed on the upper substrate and the lower substrate respectively, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer; The double-layer integrated circuit structure also includes a conductive layer that penetrates the upper substrate, the lower substrate and the isolation layer, and is used to connect devices formed in series on the upper substrate and the lower substrate.

[0011] According to the above scheme, it also includes an isolation region that penetrates the upper substrate and the lower substrate, and the conductive layer is formed in the isolation region and connected in series with the device; The device is provided with contacts, and the conductive layer is isolated from each contact by an ILD oxide layer.

[0012] According to the above scheme, the device is a MOS tube, including a well region formed in the upper substrate or the lower substrate, a source and a drain are respectively formed in the well region, a gate is formed on the outer surface of the well region, and the gate is located between the source and the drain, the source and the drain are connected by a channel, and the channel is isolated from the gate.

[0013] According to the above solution, a dielectric barrier layer is provided on the outer surface of the device.

[0014] The unexpected beneficial effects of the present invention are: 1. In terms of process, the wafers are first bonded to form an isolation area that runs through the upper substrate and the lower substrate, and then devices are formed on the upper substrate and the lower substrate. Finally, a conductive layer is formed in the isolation area. An unexpected effect is that in the process of forming the device, part of the process of device formation can be integrated, which saves the process flow and improves the efficiency of the process. At the same time, in terms of structure, by forming upper and lower symmetrical devices on the two bonded wafers, the upper and lower devices are connected in series using the conductive layer that runs through. An unexpected effect is that double the devices can be integrated on a chip of the same area, greatly improving the integration of the chip.

[0015] 2. The isolation area can be formed by etching only once, without having to be formed separately on the upper substrate and the lower substrate. Annealing after filling the insulating layer also only needs to be done once, so that the process is integrated, the process flow is saved, and the process efficiency is improved.

[0016] 3. When forming devices on the upper substrate and the lower substrate, although some processes still need to be completed separately, the annealing process has been integrated, which further saves the process flow and improves the efficiency of the process.

[0017] 4. After gate ion implantation and before the second annealing, additional carbon group element ions are implanted to slow down the growth and expansion of grains. The grain boundary length is smaller than the reserved length after the second annealing, causing the current flow path to become longer, thereby preventing subsequent ion implantation from passing through the gate to the current channel, thereby avoiding leakage problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a method flow chart of an embodiment of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure before two wafers are bonded.

[0020] Figure 3 It is a schematic diagram of the structure after two wafers are bonded.

[0021] Figure 4 It is a schematic diagram of the structure before etching the first through hole.

[0022] Figure 5It is a schematic diagram of the structure after etching the first through hole and filling the insulating layer.

[0023] Figure 6 It is a schematic diagram of the structure after removing the STI etch stop layer.

[0024] Figure 7 It is a schematic diagram of the structure for forming a well region by ion implantation.

[0025] Figure 8 It is a schematic diagram of the structure after annealing after forming the well region.

[0026] Fig. 9 It is a schematic diagram of the structure after the isolation areas on the surfaces of the upper substrate and the lower substrate are removed.

[0027] Fig.10 It is a schematic diagram of the structure after the gate oxide layer is formed.

[0028] Fig.11 It is a schematic diagram of the structure after the polysilicon layer and the sacrificial oxide layer are formed.

[0029] Fig.12 It is a schematic diagram of the structure after gate ion doping of the upper and lower polysilicon layers.

[0030] Fig.13 It is a schematic diagram of the structure after the gate and the surrounding gate oxide layer are formed.

[0031] Fig.14 It is a schematic diagram of the structure after the first sidewall process and LDD process.

[0032] Fig.15 It is a schematic diagram of the structure after the second sidewall process and source / drain ion implantation process.

[0033] Fig.16 It is a schematic diagram of the structure after the self-aligned silicide barrier layer process is performed.

[0034] Fig.17 It is a schematic diagram of the structure after the ILD oxide layer is formed.

[0035] Fig.18 This is a schematic diagram of the structure after the device is formed on the other side of the wafer.

[0036] Fig.19 It is a schematic diagram of the structure after metal contacts are formed on the device.

[0037] Fig. 20 It is a schematic diagram of the structure for preparing to etch the second through hole.

[0038] Fig.21 Schematic diagram of the structure after the second through hole is formed.

[0039] Fig. 22 It is a schematic diagram of the structure after the first metal is formed.

[0040] Fig.23 It is a schematic diagram of the structure after etching a through hole connected to the second through hole on the other side.

[0041] Fig.24 It is a schematic diagram of a partial cross-sectional structure of a device according to an embodiment of the present invention.

[0042] In the figure: 100-upper substrate; 200 - isolation layer, 201 - first oxide layer, 202 - second oxide layer, 203 - third oxide layer, 204 - fourth oxide layer, 2041 - second through hole, 205 - gate oxide layer, 206 - sacrificial oxide layer, 207 - ILD oxide layer; 300-lower substrate; 401-well region, 402-source, 403-gate, 404-drain; 501-source contact, 502-gate contact, 503-drain contact; 600-conductive layer, 601-first metal; 701- STI etch stop layer, 702- etch stop layer; 801-α-C layer, 802-oxide layer, 803-BARC, 804-photoresist, 805-TiN layer, 806-SiON layer, 807-SiCN film; 900-polysilicon layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0044] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0045] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0046] The present invention provides a method for preparing a high-integration double-layer integrated circuit structure. Figure 1 As shown, specifically including: S1. Bonding two wafers, that is, the first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer, and bonding the first isolation layer and the second isolation layer together to form an isolation layer.

[0047] S2. Form a first through hole penetrating the upper substrate and the lower substrate, and form an isolation region in the first through hole and on the surface of the upper substrate and the surface of the lower substrate.

[0048] S3, forming devices on the upper substrate and the lower substrate; S4. Form a second through hole in the isolation region within the first through hole, and form a conductive layer in the second through hole for connecting devices located on the upper substrate and the lower substrate in series.

[0049] At the same time, the present invention also provides a highly integrated double-layer integrated circuit structure, including an upper substrate, an isolation layer and a lower substrate obtained by a bonding process; devices are formed on the upper substrate and the lower substrate respectively, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer; and also includes a conductive layer that runs through the upper substrate, the lower substrate and the isolation layer, and is used to connect the devices formed in series on the upper substrate and the lower substrate.

[0050] The device may be a MOS tube, a diode, a triode, an IGBT or a thyristor, etc. As long as the concept of the present invention is adopted, a vertically symmetrical device is formed by two bonded wafers, and the vertically symmetrical devices are connected in series through a penetrating conductive layer, they are all within the scope of protection of the present invention. The structural improvement of the device itself is not within the scope of protection of the device structure of the present invention.

[0051] The present invention is further described below by taking a MOS tube as an example.

[0052] Continue as Figure 1 As shown, the present invention provides a method for preparing a highly integrated double-layer integrated circuit structure, which specifically includes the following steps: S1. Bonding two wafers, that is, the first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer, and bonding the first isolation layer and the second isolation layer together to form an isolation layer.

[0053] like Figure 2 As shown, two single crystal silicon wafers are taken as the upper substrate 100 and the lower substrate 300, and oxide layers of a certain thickness are grown on the surfaces of the wafers as the first isolation layer and the second isolation layer, namely the first oxide layer 201 and the second oxide layer 202, and then the two are bonded together by a bonding process as shown in FIG. Figure 3 The stacked structure of the upper substrate 100 , the isolation layer 200 and the lower substrate 300 is shown; the isolation layer 200 is formed by bonding the first oxide layer 201 and the second oxide layer 202 .

[0054] In this embodiment, the bonding process specifically includes: using plasma to activate the dangling bonds on the surface of the wafer (N2 plasma can be used), and then using deionized water to rinse the hydrophilic substance on the surface of the wafer, and then flipping the two wafers, annealing the surfaces with the grown oxide layers face to face at 350 degrees for 120 minutes to form the above-mentioned stacking structure.

[0055] S2, forming a first through hole penetrating the upper substrate and the lower substrate on the stacked structure, and forming an isolation region in the first through hole, on the surface of the upper substrate, and on the surface of the lower substrate. Specifically comprising: like Figure 4 As shown, on one side of the stacked structure, a third oxide layer 203 and an STI etch stop layer 701 of a certain thickness are grown; on the other side of the stacked structure, a third oxide layer 203 and an STI etch stop layer 701 of a certain thickness are produced, as well as other layers required for exposure, development and etching, wherein the other layers sequentially include an α-C (amorphous carbon) layer 801, an oxide layer 802, a BARC (Bottom Anti-Reflective Coating) 803 and a photoresist 804; wherein the photoresists 804 are arranged at intervals, and the distance is determined according to the first through hole to be set, that is, the position where the first through hole is required to be opened is not coated with photoresist.

[0056] The STI etch stop layer 701 on one side is etched from the other side of the stack structure (i.e., the side coated with photoresist). In this embodiment, the STI etch stop layer 701 is SiN, and then the insulating layer, i.e., the fourth oxide layer 204, is filled to repair the damage to the substrate caused by etching. Then, CMP (chemical mechanical polishing process, a process of precisely grinding and polishing the surface of the silicon wafer by combining chemical and mechanical methods) is used to smooth the surface, forming a Figure 5 Annealing makes the TEOS (tetraethoxysilane) filled with the insulating layer more dense.

[0057] The STI etch stop layer 701 on both sides is removed by using a WET process (wet process), and phosphoric acid can be used for etching. The third oxide layer 203 and the fourth oxide layer 204 on both sides of the stacked structure together constitute the isolation region, such as Figure 6 The third oxide layer 203 and the fourth oxide layer 204 are both SiO2.

[0058] It should be noted that the above growth and WET processes are completed on both sides respectively, etching only needs to be completed on one side, and annealing only needs to be done once. Therefore, the annealing process has been integrated.

[0059] S3, forming devices on the upper substrate and the lower substrate. Figure 6 The MOS transistor is formed in the area between adjacent fourth oxide layers 204. It should be noted that this embodiment only takes a part of the upper substrate and the lower substrate as an example, and it is not necessary to have a fourth oxide layer 204 between every two devices on the actual wafer, as long as the fourth oxide layer 204 is set at the place where communication is required.

[0060] S3 specifically includes: S301, ion implantation is performed on the upper substrate 100 and the lower substrate 300 in the region where the device is formed, to form a well region 401, such as Figure 7 shown.

[0061] Among them, it is necessary to use photoresist 804 to block the part that does not need ion implantation, and then expose and develop the PW area. The ion implantation process is used to implant ions on both sides of the wafer to form PW (P-type well). The injected ions are mainly B and BF. A total of four implantations are required, of which B is implanted three times and BF is implanted once. The junction depth of BF implantation is shallow, forming a channel area, adjusting the threshold voltage, and forming a Figure 7 structure.

[0062] S302, remove the photoresist 804, and then perform the first annealing to activate the ions in the well region 401 in the upper substrate and the lower substrate, and push them to a fixed position to meet the depth required by the device. The annealing temperature can be 1050 degrees Celsius and the time can be 5 seconds. Figure 8 The structure shown.

[0063] S303, such as Fig. 9 and Fig.10 As shown, the isolation regions on the surfaces of the upper substrate 100 and the lower substrate 300 are removed to expose the isolation region in the first through hole, namely the fourth oxide layer 204 and the well region 401, and then a gate oxide layer 205 of a certain thickness is re-formed on the surfaces of the upper substrate 100 and the lower substrate 100.

[0064] In this embodiment, the WET process is used to remove the originally grown third oxide layer 203. Here, the photomask of the low-voltage device is used to open the area where the gate oxide layer needs to be regrown, and the area that does not need to be removed is covered with PR. Here, the WET process can use DHF (a mixture of HF, H2O2, and H2O) + SPM (a mixture of H2SO4, H2O2, and H2O). Then, the RTP process (Rapid Thermal Processing) and the ISSG process (In Situ Steam Generation) are used to grow a gate oxide layer 205 of a certain thickness. The thickness of the gate oxide layer of a general low-voltage device is 22A.

[0065] S304, such as Fig.11 As shown, polysilicon layers 900 for serving as gate electrodes are formed on the surfaces of the upper substrate 100 and the lower substrate 300 , respectively, and a sacrificial oxide layer 206 is formed on the outer surface of the polysilicon layer 900 .

[0066] In this embodiment, a polysilicon layer of a certain thickness is grown on both sides of the wafer by using a furnace tube process, which is used as a gate of MOS, and then a sacrificial oxide layer 206 is grown on the polysilicon layer by using the furnace tube process.

[0067] S305, gate ion doping is performed on the upper and lower polysilicon layers respectively, such as Fig.12 Then annealing is performed for the second time.

[0068] It should be noted that in order to reduce the on-resistance of the gate, the general process technology will perform ion doping in the polysilicon layer. Generally, N-type semiconductors use nitrogen elements, while P-type semiconductors use boron elements. Annealing is added after ion implantation to make the ion implantation uniform, thereby reducing the gate resistance and increasing the speed of the component.

[0069] However, the annealing here actually brings disadvantages: 1. Due to the annealing process (>600℃), the gate silicon grains will grow again, and the grain boundary length will increase, and the degree will be difficult to control. The increase in grain boundary will cause subsequent ion implantation, such as lightly doped drain, to directly pass through the gate to the current channel, causing the gate to be inoperable and deriving leakage problems.

[0070] Therefore, the present invention makes the following improvements: after gate ion implantation and before annealing, additional carbon group element (carbon, silicon, germanium, etc.) ions are implanted to inhibit the slowdown of grain growth and expansion, and the grain boundary length is smaller than the reserved length after the annealing process, causing the current flow path to become longer, thereby preventing subsequent ion implantation from passing through the gate to the current channel, thereby preventing leakage problems.

[0071] Similarly, in this step, the annealing processes of the upper substrate 100 and the lower substrate 300 are also integrated, saving process.

[0072] S306, forming a gate, a source and a drain on the upper substrate 100 and the lower substrate 300 and the corresponding polysilicon layer 900, and forming an etching stop layer 702 on the outer surface. Specifically comprising: First, different thin films are deposited on one side of the wafer, and a certain thickness of SiN layer, oxide layer, amorphous carbon layer, SiON layer, oxide layer, and BARC layer are deposited in sequence. Then, photoresist 804 is coated to expose and develop the polysilicon. Then, the polysilicon etching process is performed, and a multi-step etching process + WET process is performed. Then, the polysilicon ROX (recessed oxidation) process is performed, and the side of the polysilicon is oxidized by the furnace tube process to grow an oxide layer of a certain thickness. Then, the SiN on the polysilicon head is removed using phosphoric acid to obtain the following. Fig.13 The structure of FIG. 1 is shown in FIG. 1 , that is, the gate 403 (ie, the original polysilicon layer 900 ) and the surrounding gate oxide layer 205 have been formed.

[0073] like Fig.14 As shown, the first sidewall process and LDD process are carried out: first, an oxide layer and a SiN layer of a certain thickness are deposited in sequence, and then the oxide layer and the SiN layer on the side of the polysilicon are generated by a self-alignment process, and then the NLDD mask is coated, and then exposed and developed, and then the LDD IMP ion implantation is carried out, and Ge, C, B, N, P, and As are implanted in sequence to a certain depth. The implantation of B here mainly plays a role in preventing the source and drain from being connected. The ion junction depth is deeper than the channel to prevent the source and drain from being connected.

[0074] like Fig.15 As shown, the photoresist 804 is first removed, and then the second sidewall process and the ion implantation process of the source / drain are entered. Specifically, an oxide layer and a SiN layer of a certain thickness are deposited in sequence, and then the second sidewall process is formed by a self-alignment process, that is, the oxide layer and the SiN layer on the side of the polysilicon, and then the NMOS S / D mask is coated, and then exposed and developed, and then ion implantation is performed. When performing ion implantation, P, Ge, P, AS and F need to be implanted in sequence to a certain depth, and the source / drain needs to be heavily doped, and its junction depth is almost the same as the depth of the channel.

[0075] like Fig.16As shown, the photoresist is removed first, and then the self-aligned silicide barrier layer process is entered: first, a certain thickness of oxide layer and SiN layer are deposited in sequence, and then the SAB layer mask is used for exposure and development, and then etching is performed to open the area where NiSi needs to be formed, and the area where NiSi does not need to be formed is covered. Then the Siconi process is used to pre-clean the oxide layer on the surface of the wafer, with a thickness of about 60A; then the NiPt alloy is deposited for about 120A, and then the covering layer TiN is deposited for 50A, and then the first RTP process is performed at a process temperature of 290°C for 30s to form a high-resistance metal silicide Ni2PtSi, and then the second RTP is performed to form a low-resistance NIPTSi2, and then the Ni in the area where NIPTSi2 is not formed is pulled out, which forms the following. Fig.16 The structure shown.

[0076] like Fig.17 As shown, a certain thickness of SiN, about 300A, is deposited as an etch stop layer 702, and then an ILD (Inter-Layer Dielectric, a dielectric layer located between different metal layers) oxide layer 4260A is deposited. After being polished by the CMP process, a thickness of 2100A remains, and then TEOS with a thickness of 600A is deposited. Finally, the ILD oxide layer 207 with a total thickness of 2700A is obtained.

[0077] Then the wafer is turned over and the process flow of S306 is repeated on the other side to obtain the following Fig.18 It should be noted that the process shown here is the same for the device on the back and the device on the front. If the device on the back is different, the process needs to be adjusted accordingly according to the specific device.

[0078] After completion, the ions injected in the previous process need to be heat treated at a certain temperature to activate the ions so that they are fixed and move within a certain depth.

[0079] At this point, the same devices are formed on both the front and back sides of the wafer.

[0080] S307 , forming metal contacts serving as connecting devices on the gate, source and drain respectively.

[0081] The metal layer is connected to the source, drain, and gate of the MOS device so that the front and back sides of the wafer are connected to each other, serving as metal contacts for connecting the devices. Since this is not the focus of the present invention, the specific process flow will not be listed in detail. The final structure is as follows: Fig.19 As shown, a source contact 501, a gate contact 502 and a drain contact 503 are obtained.

[0082] S4, etching a second through hole in the isolation region (ie, the fourth oxide layer 204) in the first through hole, and forming the conductive layer in the second through hole, for connecting the devices of the upper substrate and the lower substrate in series, specifically comprising: S401, forming a first metal from the ILD oxide layer on one side through the isolation region to the etch stop layer on the opposite side. Specifically, the ILD oxide layer on one side sequentially passes through the etch stop layer and the isolation region, and is etched all the way to the etch stop layer on the opposite side, and the first metal is formed in the etched hole. Similarly, it is necessary to coat various layers required for etching, and then expose, develop and etch.

[0083] Specifically, a TiN layer 805, a SiON layer 806, an oxide layer, and a BARC layer of a certain thickness are sequentially deposited, a through-hole photoresist is coated, exposed and developed, and then a through-hole trench hard mask is etched to obtain the following: Fig. 20 structure.

[0084] Then, an ODL layer, an SHB layer, and a photoresist of a certain thickness are sequentially coated, and then the through-hole channel is exposed and developed, and the through-hole and the channel are etched synchronously to obtain a second through-hole 2041. The specific structure is as follows: Fig.21 shown.

[0085] Next, a certain thickness of Ti / TiN is deposited by PVD process, and then the first metal 601 is deposited by CVD process. Fig. 22 As shown in FIG. Among them, W is used for the through hole and the channel, and other metals such as Al and Cu can also be used.

[0086] S402, forming a second metal connected to the first metal on the ILD oxide layer on the other side. Specifically, etching the ILD oxide layer on the opposite side until the first metal is exposed, and forming the second metal in the etched hole.

[0087] After depositing a layer of SiCN film 807, the wafer is flipped over to perform the through-hole process: a certain thickness of TiN layer 805, SiON layer, oxide layer, and BARC layer are deposited in sequence, and through-hole photoresist is applied, and then exposed and developed. Then, through-hole hard mask etching and ILD oxide layer etching are performed, and SiN is used as an etching stop layer. Here, in order to better connect the second metal and reduce the resistance value, the amount of etching OE needs to be increased to etch away all SiN. After etching, the WET process is performed to clean the through-hole, and the following is obtained. Fig.23 structure.

[0088] A certain thickness of TI / TIN is deposited by PVD process, and then the second metal is deposited by CVD process. A certain thickness of SiCN film 807 is deposited to obtain the final structure as shown in FIG. Fig.24 As shown, the conductive layer 600 is composed of a first metal 601 and a second metal. Fig.24 The figure shows a highly integrated double-layer integrated circuit structure provided by an embodiment of the present invention, including an upper substrate 100, an isolation layer 200 and a lower substrate 300 obtained by a bonding process; MOS transistors are formed on the upper substrate 100 and the lower substrate 300 respectively, and the positions of the MOS transistors on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer 200. The double-layer MOS transistor device also includes a conductive layer 600 that penetrates the upper substrate 100, the lower substrate 300 and the isolation layer 200, and is used to connect the MOS transistors formed in series on the upper substrate 100 and the lower substrate 300. The conductive layer 600 is formed by integrating the first metal 601 and the second metal. The SiCN film 807 serves as a dielectric barrier layer.

[0089] in, Fig.24 Only a partial cross-sectional view is given. Actually, there are several conductive layers 600 on the wafer, which are set according to the area of ​​the wafer and the size of the device. The conductive layers 600 are spaced apart at positions where electrical connectivity is required. It should be noted that the conductive layer 600 forms a structure that is wide at the top and narrow at the bottom, which is naturally caused by etching and does not require such a specific structure. Generally speaking, the conductive layer 600 does not require a specific structure, as long as it can play the role of electrical connectivity and facilitate process implementation. The structure of the MOS tube itself can be the same or different, and it only needs to be symmetrical in position on the upper substrate and the lower substrate. The same is true when the MOS tube is replaced with other devices.

[0090] In this embodiment, the MOS tube includes a well region 401 formed in an upper substrate or a lower substrate, a source 402 and a drain 404 are respectively formed in the well region 401, an isolation region and a gate 403 are formed on the outer surface of the well region 401, and the gate 403 is located between the source 402 and the drain 404, the source 402 and the drain 404 are connected by a channel, and the channel is isolated from the gate 502.

[0091] Furthermore, the source 402, the gate 403 and the drain 404 are respectively connected to a source contact 501, a gate contact 502 and a drain contact 503. The source contact 501, the gate contact 502 and the drain contact 503 are isolated by an ILD oxide layer, which is usually SiO2.

[0092] The above-mentioned back-to-back double-layer device structure can be formed through the above-mentioned process flow. The two-layer device can be connected in series through a through-hole structure, and then applied through the wiring process of the complex metal interconnect layer in the later stage. Since the metal interconnect layer is not the core technology of the present invention, the subsequent process will not be introduced here. The above-mentioned structure can adopt the traditional logic MOS process, and the number of MOS of the device can be doubled without changing the chip area size.

[0093] When the MOS tube is replaced with other devices, it is only necessary to adaptively adjust the above process according to the actual situation.

[0094] In summary, a highly integrated double-layer integrated circuit device and preparation method provided by the present invention firstly bonds two wafers to form upper and lower substrates, and then forms upper and lower symmetrical devices on the two bonded wafers, and connects the upper and lower devices in series by using a penetrating conductive layer. An unexpected effect is that double the devices can be integrated on a chip of the same area, greatly improving the chip integration, and can save part of the process flow (such as annealing), thereby improving the efficiency of the process.

[0095] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0096] The order of execution of each step in the above embodiment does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0097] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for preparing a highly integrated double-layer integrated circuit structure, characterized in that: The steps include: The first wafer includes an upper substrate and a first isolation layer, the second wafer includes a lower substrate and a second isolation layer, and the first isolation layer and the second isolation layer are bonded together to form an isolation layer; Forming a first through hole penetrating the upper substrate and the lower substrate, and forming an isolation region in the first through hole, on the surface of the upper substrate, and on the surface of the lower substrate; forming devices on the upper substrate and the lower substrate; A second through hole is formed in the isolation region within the first through hole, and a conductive layer is formed in the second through hole for connecting devices located on the upper substrate and the lower substrate in series.

2. The method for preparing a highly integrated double-layer integrated circuit structure according to claim 1, characterized in that: The formation of the isolation zone specifically includes: forming an oxide layer and an etching stop layer of a certain thickness on the surfaces of the upper substrate and the lower substrate respectively; Forming a layer required for exposure, development and etching on the etching stop layer on one side, etching a first through hole, the first through hole penetrating the upper substrate and the lower substrate and extending all the way to the etching stop layer on one side; Filling an insulating layer in the first through hole, wherein the insulating layer and the oxide layers on both sides together constitute the isolation region; Annealing makes the insulating layer more densely filled.

3. The method for preparing a highly integrated double-layer integrated circuit structure according to claim 1, characterized in that: When the device is a MOS tube, its formation includes: Performing ion implantation on the regions on the upper substrate and the lower substrate for forming the device, respectively, to form well regions; The first annealing activates ions in the well regions of the upper substrate and the lower substrate; Removing the isolation regions on the surfaces of the upper substrate and the lower substrate to expose the isolation regions and the well region in the first through hole, and then forming a gate oxide layer of a certain thickness on the surfaces of the upper substrate and the lower substrate; Forming a polysilicon layer used as a gate on the surfaces of the gate oxide layers of the upper substrate and the lower substrate respectively, and performing gate ion doping; The second annealing makes the gate ions in the upper and lower polysilicon layers implanted uniformly; A gate, a source and a drain are formed on the upper substrate, the lower substrate and the corresponding polysilicon layer respectively.

4. The method for preparing a highly integrated double-layer integrated circuit structure according to claim 3, characterized in that: When gate ion doping is performed on the upper and lower polysilicon layers respectively, carbon group element ions are also injected; the carbon group element ions in the upper and lower polysilicon layers are injected uniformly during the second annealing process.

5. The method for preparing a highly integrated double-layer integrated circuit structure according to claim 3, characterized in that: The formation of the conductive layer specifically includes: forming an etch stop layer and an ILD oxide layer on the outer surfaces of the gate, source and drain of the upper substrate and the lower substrate respectively; forming a first metal from the ILD oxide layer on one side through the isolation region to the etch stop layer on the opposite side; Forming a second metal connected to the first metal on the ILD oxide layer on the other side; The first metal and the second metal form a conductive layer.

6. The method for preparing a highly integrated double-layer integrated circuit structure according to claim 1 or 2, characterized in that: The device is a MOS tube, a diode, a triode, an IGBT or a thyristor.

7. A highly integrated double-layer integrated circuit structure, characterized in that: It comprises an upper substrate, an isolation layer and a lower substrate obtained by a bonding process; devices are formed on the upper substrate and the lower substrate respectively, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer; The double-layer integrated circuit structure also includes a conductive layer that penetrates the upper substrate, the lower substrate and the isolation layer and is used to connect devices formed on the upper substrate and the lower substrate in series.

8. The highly integrated double-layer integrated circuit structure according to claim 7, characterized in that: Also included is an isolation region penetrating the upper substrate and the lower substrate, wherein a conductive layer is formed in the isolation region and connected in series with the device; The device is provided with contacts, and the conductive layer is isolated from each contact by an ILD oxide layer.

9. The highly integrated double-layer integrated circuit structure according to claim 7, characterized in that: The device is a MOS tube, including a well region formed in an upper substrate or a lower substrate, a source and a drain are respectively formed in the well region, a gate is formed on the outer surface of the well region, and the gate is located between the source and the drain, the source and the drain are connected by a channel, and the channel is isolated from the gate.

10. The highly integrated double-layer integrated circuit structure according to claim 7 or 8, characterized in that: The outer surface of the device is provided with a dielectric barrier layer.

Images