Display panel and manufacturing method thereof

Abstract

A display panel and a method of manufacturing the same are disclosed. The display panel includes: a base layer; a pixel defining film disposed on the base layer and defining a light emitting opening portion; a partition wall disposed on the pixel defining film, having conductivity, and defining a partition wall opening portion corresponding to the light emitting opening portion; a light-emitting element disposed at the light-emitting opening and including an anode, an intermediate layer disposed on the anode, an electronic control layer disposed on the intermediate layer, and a cathode disposed on the electronic control layer and connected to the partition wall; a first pattern spaced apart from the electronic control layer and in contact with an upper surface of the partition wall, and including the same material as the electronic control layer; and a second pattern spaced apart from the cathode and disposed on the first pattern, and including the same material as the cathode.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display panel with improved display quality and a display device having the display panel. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablet computers that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern is separated in each light emitting region, and the cathode may provide a common voltage to each light emitting region. Summary of the invention

[0004] The present invention can provide a display panel with improved display quality when a display panel including a light-emitting element is formed without using a metal mask, and a method for manufacturing the display panel.

[0005] According to one embodiment of the present invention, there is provided a display panel, comprising: a base layer; a pixel defining film, arranged on the base layer and defining a light-emitting opening; a partition wall, arranged on the pixel defining film, having conductivity, and defining a partition wall opening corresponding to the light-emitting opening; a light-emitting element, arranged on the light-emitting opening and comprising an anode, an intermediate layer arranged on the anode, an electronic control layer arranged on the intermediate layer, and a cathode arranged on the electronic control layer and connected to the partition wall; a first pattern, separated from the electronic control layer and in contact with the upper surface of the partition wall, and comprising the same substance as the electronic control layer; and a second pattern, separated from the cathode and arranged on the first pattern, and comprising the same substance as the cathode.

[0006] A display panel may be provided, wherein the first pattern entirely covers the upper surface of the partition wall, and the second pattern entirely covers an upper surface of the first pattern.

[0007] A display panel may be provided, wherein the second pattern is in contact with an upper surface of the first pattern.

[0008] The following display panel may be provided, wherein the display panel further comprises: an encapsulation layer covering the light emitting element, wherein the encapsulation layer completely covers an upper surface of the second pattern.

[0009] A display panel may be provided, wherein the encapsulation layer fully covers the side surfaces of the first pattern and the second pattern.

[0010] A display panel may be provided, wherein the partition wall has an undercut shape in cross section.

[0011] The following display panel may be provided, wherein the intermediate layer includes: a hole control layer disposed on the anode; and a light emitting layer disposed on the hole control layer and including a light emitting substance.

[0012] According to one embodiment of the present invention, there is provided a display panel, comprising: a base layer; a pixel defining film, which is arranged on the base layer and defines a plurality of light-emitting openings separated from each other; a partition wall, which is arranged on the pixel defining film and defines a plurality of partition wall openings respectively overlapping with the plurality of light-emitting openings and has conductivity; a first light-emitting element, which is arranged in a first light-emitting opening among the light-emitting openings and comprises a first anode, a first intermediate layer, which is arranged on the first anode and comprises a first light-emitting substance that generates light of a first color, a first electronic control layer, which is arranged on the first intermediate layer, and a first cathode, which is arranged on the first electronic control layer and connected to the partition wall; a second light-emitting element, which is arranged on the A second light-emitting opening portion in the light-emitting opening portion, and includes a second anode, a second intermediate layer arranged on the second anode and including a second light-emitting material that generates light of a second color, a second electron control layer arranged on the second intermediate layer, and a second cathode arranged on the second electron control layer and connected to the partition wall; a first pattern, which is separated from the first electron control layer and the second electron control layer, contacts with the upper surface of the partition wall, and includes the same material as the first electron control layer and the second electron control layer; and a second pattern, which is separated from the first cathode and the second cathode, is arranged on the first pattern, and includes the same material as the first cathode and the second cathode.

[0013] The following display panel may be provided, the display panel further comprising: an encapsulation layer covering the first light emitting opening, the second light emitting opening and the partition wall, wherein the encapsulation layer completely covers an upper surface of the second pattern.

[0014] A display panel may be provided, wherein the first pattern entirely covers an upper surface of the partition wall, and the second pattern entirely covers an upper surface of the first pattern.

[0015] The following display panel can be provided, wherein the first intermediate layer includes: a first hole control layer, arranged on the first anode; and a first light-emitting layer, arranged on the first hole control layer and containing the first light-emitting substance, and the second intermediate layer includes: a second hole control layer, arranged on the second anode; and a second light-emitting layer, arranged on the second hole control layer and containing the second light-emitting substance.

[0016] According to one embodiment of the present invention, a method for manufacturing a display panel is provided, comprising the following steps: providing a preliminary display panel, the preliminary display panel comprising a base layer, an anode arranged on the base layer, and a preliminary pixel defining film arranged on the base layer and covering the anode; forming a partition wall arranged on the preliminary pixel defining film and formed with a plurality of partition wall openings; patterning the preliminary pixel defining film to form a plurality of light-emitting openings respectively overlapping with the plurality of partition wall openings and exposing at least a portion of the anode, thereby forming a pixel defining film; and forming a first intermediate layer, a second intermediate layer, a first electronic control layer, a second electronic control layer and a first pattern, the first intermediate layer and the second intermediate layer respectively comprising a first light-emitting substance and a second light-emitting substance respectively generating light of a first color and a second color different from each other in their respective partition wall openings, the first electronic control layer and the second electronic control layer respectively overlapping with the first intermediate layer and the second intermediate layer, the first pattern respectively separated from the first electronic control layer and the second electronic control layer and in contact with the upper surface of the partition wall, wherein the first pattern is formed simultaneously with the first electronic control layer, and the second intermediate layer is formed after the first intermediate layer is formed and before the first pattern is formed.

[0017] The following method for manufacturing a display panel can be provided, the method further comprising the following steps: forming a cathode arranged on the first intermediate layer and the second intermediate layer and in contact with the partition wall, and a second pattern separated from the cathode and arranged on the first pattern, wherein the second pattern is formed simultaneously with the cathode.

[0018] The following method for manufacturing a display panel can be provided, the method comprising the following steps: forming a first preliminary intermediate layer on the anode and the partition wall; forming a first protective layer on the first preliminary intermediate layer; forming a first photoresist pattern covering a first light-emitting opening portion among the plurality of light-emitting opening portions; removing the first protective layer to form a first protective pattern; and forming the first intermediate layer by removing the first preliminary intermediate layer and removing the first photoresist pattern.

[0019] The following method for manufacturing a display panel can be provided, the method comprising the following steps: forming a second preliminary intermediate layer on the anode, the first intermediate layer and the partition wall; forming a second protective layer on the second preliminary intermediate layer; forming a second photoresist pattern covering a second light-emitting opening portion among the multiple light-emitting opening portions; removing the second protective layer to form a second protective pattern; and forming the second intermediate layer by removing the second preliminary intermediate layer and removing the second photoresist pattern, wherein the first protective pattern and the second protective pattern are removed, and a second pattern, a first cathode arranged in the first light-emitting opening portion, and a second cathode arranged in the second light-emitting opening portion are formed.

[0020] The following method for manufacturing a display panel may be provided, wherein the first protective layer is formed by thermal evaporation.

[0021] The following method for manufacturing a display panel may be provided, wherein the first protective layer is removed by wet etching.

[0022] The following method for manufacturing a display panel can be provided, the method also comprising forming an encapsulation layer in a manner covering the plurality of partition wall openings, wherein the encapsulation layer simultaneously covers a first light-emitting opening and a second light-emitting opening separated from each other among the plurality of light-emitting openings.

[0023] The following method for manufacturing a display panel is provided, wherein the step of forming the partition wall includes the following steps: forming a first layer on the pixel defining film; forming a second layer on the first layer; a first etching to pattern the first layer and the second layer to form a partition wall pattern; and a second etching to pattern the partition wall pattern to form an undercut in the partition wall pattern.

[0024] According to a display panel and a method for manufacturing the display panel according to an embodiment of the present invention, a light emitting element can be formed without using a metal mask.

[0025] According to a display panel and a method for manufacturing the display panel according to an embodiment of the present invention, a light-emitting element with improved process reliability can be formed.

[0026] According to a display panel and a method for manufacturing the display panel according to an embodiment of the present invention, a light-emitting element with improved reliability of electrical connection can be formed.

[0027] According to a display panel and a method for manufacturing the display panel according to an embodiment of the present invention, a light-emitting element capable of preventing over-etching of a packaging layer can be formed.

[0028] According to a display panel and a method for manufacturing a display panel according to an embodiment of the present invention, a light-emitting element including an electron control layer and a cathode deposited simultaneously in a plurality of light-emitting openings can be formed.

[0029] According to the display panel and the method for manufacturing the display panel according to an embodiment of the present invention, the protection layer covering the intermediate layer can prevent the intermediate layer from being damaged.

[0030] According to a display panel and a method for manufacturing a display panel according to an embodiment of the present invention, the electron control layer and the cathode can be deposited in a plurality of light emitting openings at the same time by means of a protective layer covering the intermediate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a is a perspective view of a display device according to an embodiment of the present invention.

[0032] Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0033] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0034] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0035] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0036] Figure 5 is a plan view showing an enlarged portion of a display panel according to an embodiment of the present invention.

[0037] Figure 6 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention.

[0038] Figure 7 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention.

[0039] Figure 8a to Figure 8h is a cross-sectional view showing some steps in a method for manufacturing a display panel according to an embodiment of the present invention.

[0040] Figures 9a to 9f is a cross-sectional view showing some steps in a method for manufacturing a display panel according to an embodiment of the present invention.

[0041] Description of Reference Numerals DETAILED DESCRIPTION

[0042] In this specification, when a certain constituent element (or region, layer, part, etc.) is mentioned as being "on", "connected to" or "bound to" another constituent element (or region, layer, part, etc.), this means that it can be directly arranged on / connected to / bound to the other constituent element (or region, layer, part, etc.) or a third constituent element (or region, layer, part, etc.) can be arranged between them.

[0043] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated in order to effectively illustrate the technical content. The term "and / or" includes all combinations that can define more than one of the related components.

[0044] The terms "first", "second" and the like may be used when describing a variety of constituent elements, but the constituent elements are not limited to the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Unless otherwise clearly indicated in the context, a singular expression also includes a plural expression.

[0045] Furthermore, terms such as “below”, “below”, “above”, and “upper” are used to describe the relationship between components shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0046] The terms "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding the existence or additional possibilities of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof in advance.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the relevant technology, and in this case, unless clearly defined, should not be interpreted as overly ideal or overly formal meanings.

[0048] Hereinafter, a display panel and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0049] Figure 1a is a three-dimensional diagram of a display device according to an embodiment of the present invention, Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0050] In one embodiment of the present invention, the display device DD may be a large electronic device such as a television, a monitor, or an external advertising board. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, and a camera. However, this is only exemplary, and other display devices may also be used without departing from the concept of the present invention. Figure 1a and Figure 1b , a case where the display device DD is a smart phone is exemplarily illustrated.

[0051] Reference Figure 1a and Figure 1b , the display device DD can display an image IM on a display surface FS parallel to the first direction DR1 and the second direction DR2 toward the third direction DR3. The image IM may include not only dynamic images but also static images. Figure 1a , a clock window and an icon are shown as an example of the image IM. The display surface FS displaying the image IM may correspond to a front surface of the display device DD.

[0052] In this embodiment, the front surface (or upper surface) and the back surface (or lower surface) of each component are defined based on the direction in which the image IM is displayed. The front surface and the back surface may face each other in the third direction DR3, and the normal directions of the front surface and the back surface may be parallel to the third direction DR3. In addition, the directions indicated by the first direction DR1 to the third direction DR3 are relative concepts, which can be converted into other directions. In this specification, "on a plane" may refer to the situation when observed in the third direction DR3.

[0053] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to constitute the appearance of the display device DD.

[0054] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0055] The frame area BZA may be an area having a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. However, this is an exemplary case, and the frame area BZA of the window WP may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, but is not limited to a certain embodiment.

[0056] The display module DM may be disposed at the lower portion of the window WP. The display module DM may be a configuration that substantially generates an image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and is recognized by a user from the outside through the transmissive area TA.

[0057] The display module DM (or display surface IS) may include a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA, as an area covered by the frame area BZA, may not be recognizable from the outside.

[0058] The housing HAU may be combined with the window WP. The housing HAU may be combined with the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0059] The housing HAU may include a relatively high rigidity material. For example, the housing HAU may include a plurality of frames and / or plates formed of glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the display device DD contained in the internal space from external impact.

[0060] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0061] Reference Figure 2, the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present invention (refer to Figure 1a ) may further include a protection member arranged on the lower surface of the display panel DP or an anti-reflection member and / or a window member arranged on the upper surface of the input sensor INS.

[0062] The display panel DP may be a light-emitting display panel. However, this is merely exemplary and not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may contain an organic light-emitting substance. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0063] The display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly arranged on the thin film encapsulation layer TFE. In this specification, "A configuration is directly arranged on B configuration" means that no adhesive layer is arranged between A configuration and B configuration.

[0064] The base layer BL may include at least one plastic film. The base layer BL may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc., which is a flexible substrate. Figure 1b The display area DA and the non-display area NDA described in may be identically defined in the base layer BL.

[0065] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, and the like.

[0066] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0067] The thin film encapsulation layer TFE may include a plurality of thin films, a portion of which may be arranged to improve optical efficiency, and a portion of which may be arranged to protect the organic light emitting diode.

[0068] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. In addition, the input sensor INS may include a single-layer or multi-layer insulating layer. The input sensor INS may sense the external input in a capacitive manner. However, this is exemplary and not limited thereto. For example, in one embodiment, the input sensor INS may also sense the external input by electromagnetic induction or pressure sensing. In addition, in another embodiment of the present invention, the input sensor INS may be omitted.

[0069] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0070] Reference Figure 3 In the display panel DP, a display area DA and a non-display area NDA around the display area DA may be defined. The display area DA and the non-display area NDA may be divided by whether pixels PX are arranged. The pixels PX may be arranged in the display area DA. The scanning driving unit SDV, the data driving unit, and the light emitting driving unit EDV may be arranged in the non-display area NDA. The data driving unit may be a part of the circuit formed in the driving chip DIC.

[0071] The display panel DP includes pixels PX, initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, black scan lines GBL1-GBLm, light emission control lines ECL1-ECLm, data lines DL1-DLn, first and second control lines CSL1 and CSL2, driving voltage lines PL, and a plurality of pads PD, wherein m and n are natural numbers greater than or equal to 2.

[0072] The pixels PX may be connected to initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, black scan lines GBL1-GBLm, emission control lines ECL1-ECLm, and data lines DL1-DLn.

[0073] The initialization scan lines GIL1-GILm, the compensation scan lines GCL1-GCLm, the write scan lines GWL1-GWLm, and the black scan lines GBL1-GBLm may extend along the first direction DR1 and be electrically connected to the scan driving part SDV. The data lines DL1-DLn may extend along the second direction DR2 and be electrically connected to the driving chip DIC. The emission control lines ECL1-ECLm may extend along the first direction DR1 and be electrically connected to the emission driving part EDV.

[0074] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be arranged on different layers from each other. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0075] The first control line CSL1 may be connected to the scan driving part SDV, and the second control line CSL2 may be connected to the light emitting driving part EDV.

[0076] The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1, and the second control line CSL2.

[0077] In addition, the pad PD may also include an input pad. The input pad may be used to connect the flexible circuit film FCB to the input sensor INS (refer to Figure 2 However, not limited thereto, the input pad may be arranged at the input sensor INS and may be connected to a circuit board independent of the pad PD. Alternatively, the input sensor INS may be omitted or may not further include the input pad.

[0078] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0079] exist Figure 4 A plurality of pixels PX are exemplarily shown in FIG. Figure 3 ) is an equivalent circuit diagram of a pixel PXij in FIG. Each of the plurality of pixels PX has the same circuit structure, so the circuit structure of the pixel PXij will be described and detailed descriptions of the remaining pixels PX will be omitted.

[0080] Reference Figure 3 and Figure 4, the pixel PXij is connected to the i-th data line DLi among the data lines DL1-DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1-GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1-GCLm, the j-th write scan line GWLj among the write scan lines GWL1-GWLm, the j-th black scan line GBLj among the black scan lines GBL1-GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1-ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. i is an integer greater than 1 and less than n, and j is an integer greater than 1 and less than m.

[0081] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in response to the data signal Di. The light emitting element ED may emit light at a predetermined brightness in response to the amount of current provided from the pixel circuit PDC.

[0082] The pixel circuit PDC may include first to seventh transistors T1 to T7 and first, second, and third capacitors Cst, Cbst, and Nbst. According to the present invention, the pixel circuit PDC is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is only an example, and the configuration of the pixel circuit PDC may be modified and implemented.

[0083] At least one of the first transistor T1 to the seventh transistor T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1 to the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0084] Specifically, the first transistor T1 that directly affects the brightness of the light-emitting element ED can be configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby realizing a high-resolution display device. In addition, oxide semiconductors have high carrier mobility and low leakage current, so even if the driving time is long, the voltage drop is not large. That is, even when driven at a low frequency, the color change of the image caused by the voltage drop is not large, so low-frequency driving can be performed. As described above, oxide semiconductors have the advantage of less leakage current, so oxide semiconductors are used to form at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1, thereby preventing leakage current that may flow to the gate electrode while reducing power consumption.

[0085] A portion of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the remaining portion may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0086] The configuration of the pixel circuit PDC according to the present invention is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is only an example, and the composition of the pixel circuit PDC can be implemented in a modified manner. For example, all of the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be N-type transistors.

[0087] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj may respectively transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a voltage level corresponding to an image signal input to the display device DD (refer to FIG. 1 ).

[0088] The first driving voltage line VL1 and the second driving voltage line VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij, respectively.

[0089] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or, referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the first capacitor Cst (e.g., a first node N1). The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and provide a driving current to the light emitting element ED.

[0090] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on according to the write scan signal GWj received through the j-th write scan line GWLj, and transmits the i-th data signal Di received from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst can be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst can be connected to the first node N1.

[0091] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 is turned on according to the j-th compensation scan signal GCj received through the j-th compensation scan line GCLj, and connects the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other, thereby making the first transistor T1 diode-connected. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst may be connected to the first node N1.

[0092] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 that transmits the first initialization voltage VINT, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal GIj received through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0093] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (for example, a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element ED, and a third electrode (for example, a gate electrode) connected to the j-th light emission control line ECLj.

[0094] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the jth emission control signal EMj received through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED through the sixth transistor T6.

[0095] The seventh transistor T7 includes a first electrode connected to the second initialization voltage line VL4 transmitting the second initialization voltage VAINT, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (eg, a third electrode) connected to the black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the first initialization voltage VINT.

[0096] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0097] Figure 5 FIG. 1 is a plan view showing an enlarged portion of a display area of ​​a display panel according to an embodiment of the present invention. Figure 5A plane of the display module viewed from a display surface of the display module is shown, and an arrangement of light emitting areas is shown.

[0098] Reference Figure 5 , the display area DA may include first to third light emitting areas PXA-R, PXA-G, PXA-B and peripheral areas NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, PXA-B. The first to third light emitting areas PXA-R to PXA-B may correspond to areas where light provided from the light emitting element is emitted, respectively. The first to third light emitting areas PXA-R to PXA-B may be arranged according to the direction toward the display module DM (refer to Figure 2 ) is divided into the colors of the light emitted from the outside.

[0099] The first to third light emitting regions PXA-R to PXA-B may respectively provide first to third color lights having different colors from each other. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0100] Each of the first to third light emitting regions PXA-R to PXA-B may be defined as a region where the upper surface of the anode is exposed by a light emitting opening to be described later. The peripheral region NPXA may set a boundary between the first to third light emitting regions PXA-R to PXA-B and prevent color mixing between the first to third light emitting regions PXA-R to PXA-B.

[0101] The first to third light-emitting regions PXA-R to PXA-B may be respectively provided in a plurality and repeatedly arranged in a predetermined arrangement form in the display area DA. For example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the plurality of "second groups" may be respectively provided in a plurality, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0102] One second light emitting region PXA-G may be arranged to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0103] in addition, Figure 5The arrangement of the first light emitting region PXA-R to the third light emitting region PXA-B is shown as an example, but it is not limited thereto and can be arranged in various forms. In one embodiment, the first light emitting region PXA-R to the third light emitting region PXA-B can have the following configurations: Figure 5 PENTILE SHOWN ® Alternatively, the first light emitting area PXA-R to the third light emitting area PXA-B may have a stripe arrangement or a diamond pixel arrangement. ® Arrangement form.

[0104] The first to third light emitting regions PXA-R to PXA-B may have various shapes on a plane, for example, the first to third light emitting regions PXA-R to PXA-B may have a polygonal, circular, or elliptical shape. Figure 5 A case where the first and third light emitting regions PXA-R and PXA-B have a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G has an octagonal shape are exemplarily shown.

[0105] The first to third light emitting regions PXA-R to PXA-B may have the same shape as one another on a plane, or at least a portion may have a shape different from one another. Figure 5 The first and third light emitting regions PXA-R and PXA-B having the same shape as each other on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0106] At least a portion of the first to third light emitting regions PXA-R to PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light and smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship between the areas of the first to third light emitting regions PXA-R to PXA-B according to the light emitting color is not limited thereto, and may be different according to the display module DM (refer to Figure 2 ) design. Moreover, not limited thereto, the first to third light emitting regions PXA-R to PXA-B may also have the same area as each other on a plane.

[0107] In addition, the display module DM of the present invention (refer to Figure 2 The shapes, areas, and arrangements of the first to third light-emitting regions PXA-R to PXA-B can be determined based on the color of the emitted light or the display module DM (see Figure 2) are designed in various ways, not limited to Figure 5 The embodiment shown.

[0108] Figure 6 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Specifically, Figure 6 is along Figure 5 A cross-sectional view of a display panel according to an embodiment of the present invention taken along line II'. Figure 6 When, refer to Figure 5 The following description will be given, and descriptions of the same reference numerals will be omitted.

[0109] Figure 6 The display area DA is shown in an enlarged manner (see Figure 5 ) in a light emitting area PXA, and Figure 6 The light emitting area PXA may correspond to Figure 5 Any one of the first to third light emitting areas PXA-R to PXA-B.

[0110] Reference Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0111] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Then, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0112] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transfer area SCA, first to fifth insulating layers 10 to 50, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0113] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0114] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, not limited thereto, the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 6Only a portion of the semiconductor pattern is shown, and in the plurality of light emitting regions PXA-R, PXA-G, PXA-B (see Figure 5 ) may be additionally arranged with a semiconductor pattern. The semiconductor pattern may span across a plurality of light emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 5 ) are arranged in a specific rule. The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0115] The conductivity of the first region is greater than that of the second region, and the first region substantially functions as an electrode or a signal line. The second region may substantially be equivalent to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and another portion may be a conductive region.

[0116] The source S, the active region A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 6 A portion of a signal transfer area SCA formed of a semiconductor pattern is shown Although not separately shown, the signal transfer area SCA may be connected to the drain D of the transistor TR1 in a plane.

[0117] The first to fifth insulating layers 10 to 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10 to 50 may be inorganic layers or organic layers.

[0118] The first insulating layer 10 may be disposed on the buffer layer BFL. The gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0119] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transfer area SCA through a contact hole CNT-1 penetrating the first insulating layer 10 to the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0120] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0121] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a pixel defining layer PDL, a partition wall PW, and a dummy pattern DMP.

[0122] In the present invention, the light emitting element ED may include an anode AE ​​(or, a first electrode), a conductive pattern, an intermediate layer ITL, an electron control layer EL, and a cathode CE (or, a second electrode).

[0123] The anode AE ​​may be provided in plurality, and the anode AE ​​may be arranged on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may have conductivity. For example, the anode AE ​​may be formed of a variety of materials as long as it has conductivity such as metal, transparent conductive oxide (TCO: Transparent Conductive Oxide) or conductive polymer. The anode AE ​​may be configured as a single layer or as a multilayer.

[0124] In one embodiment, the anode AE ​​may be formed of three layers including indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO).

[0125] The anode AE ​​may be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transfer area SCA through the first connection electrode CNE1 and the second connection electrode CNE2, and may be electrically connected to a corresponding circuit element.

[0126] According to an embodiment of the present invention, the display panel DP may further include a sacrificial pattern SP. The sacrificial pattern SP may be arranged between the anode AE ​​and the pixel defining film PDL. A sacrificial opening portion OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening portion OP-S may overlap with the light emitting opening portion OP-E to be described later.

[0127] The pixel definition film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening portion OP-E may be defined in the pixel definition film PDL. The light emitting opening portion OP-E may correspond to the anode AE, and the pixel definition film PDL may expose at least a portion of the anode AE ​​through the light emitting opening portion OP-E.

[0128] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE ​​may be separated from the pixel defining film PDL in a cross section via the sacrificial pattern SP, thereby protecting the anode AE ​​from damage during the formation process of the light emitting opening OP-E.

[0129] The width of the light-emitting opening portion OP-E in one direction may be smaller than the width of the sacrificial opening portion OP-S in one direction. In the present specification, one direction may refer to a direction perpendicular to the thickness direction of the display panel DP (i.e., a first direction DR1). The inner surface of the pixel-defining film PDL defining the light-emitting opening portion OP-E is closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S. However, it is not limited to this, and the inner surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S may also be substantially aligned with the inner surface of the pixel-defining film PDL defining the corresponding light-emitting opening portion OP-E. In addition, in one embodiment of the present invention, the sacrificial pattern SP may also be omitted.

[0130] The pixel definition film PDL may include an inorganic insulating material. For example, the pixel definition film PDL may include silicon nitride (SiN x ). The pixel defining layer PDL may be disposed between the anode AE ​​and the partition wall PW so as to block the anode AE ​​and the partition wall PW from being electrically connected to each other.

[0131] The partition wall PW may be disposed on the pixel definition film PDL. A partition wall opening portion OP-P may be defined in the partition wall PW. The partition wall opening portion OP-P may overlap with the light emission opening portion OP-E and may expose at least a portion of the anode AE.

[0132] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of sequentially stacked layers, and at least one of the plurality of layers may be recessed compared to adjacent stacked layers. Accordingly, the partition wall PW may include a tip portion TP.

[0133] In this embodiment, the partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition layer PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 6As shown, the thickness of the first partition wall layer L1 can be greater than the thickness of the second partition wall layer L2, but is not limited thereto. Although the figure only shows the state in which the partition wall PW is arranged by the first partition wall layer L1 and the second partition wall layer L2, it is not limited thereto, and the third partition wall layer can be arranged on the second partition wall layer L2, not limited to a certain embodiment. In addition, the thickness of the third partition wall layer can be greater than the thickness of the second partition wall layer L2, but is not limited thereto.

[0134] The partition wall opening OP-P defined in the partition wall PW may include a first area A1 and a second area A2. The first partition wall layer L1 may include a first inner surface S-L1 defining the first area A1 of the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner surface S-L2 defining the second area A2. In cross section, the second inner surface S-L2 of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the first inner surface S-L1 of the first partition wall layer L1. The first inner surface S-L1 may be recessed in a direction away from the center of the anode AE ​​compared to the second inner surface S-L2.

[0135] The width of the first area A1 may be different from the width of the second area A2. The width of the first area A1 may be greater than the width of the second area A2. In this case, the second area A2 of the partition wall opening OP-P may be an area defining the tip portion TP. At this time, the light emitting area PXA may also be regarded as an area of ​​the anode AE ​​exposed by the second area A2 of the corresponding partition wall PW.

[0136] The first partition wall layer L1 may have conductivity. The first partition wall layer L1 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO: Transparent Conductive Oxide) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (IGZO: Induim Gallium Zinc Oxide) or aluminum zinc oxide (Aluminuin Zinc Oxide).

[0137] The second partition wall layer L2 is disposed on the first partition wall layer L1. The second partition wall layer L2 may include a material having an etching selectivity ratio with the first partition wall layer L1. As an example, the reactivity of the second partition wall layer L2 to the etchant may be lower than the reactivity of the first partition wall layer L1 to the etchant.

[0138] In the present embodiment, the first partition wall layer L1 may be relatively recessed with respect to the light emitting region PXA compared to the second partition wall layer L2. That is, the first partition wall layer L1 may be formed by undercutting the second partition wall layer L2. The portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1 toward the light emitting region PXA may define a tip portion TP within the partition wall PW.

[0139] The second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO: Transparent Conductive Oxide) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (IGZO: Induim Gallium Zinc Oxide) or aluminum zinc oxide (Aluminuin Zinc Oxide).

[0140] Alternatively, in another embodiment according to the present invention, the second partition wall layer L2 may include an insulating material. For example, the second partition wall layer L2 may include an inorganic insulating material, such as silicon nitride (SiN x ) or silicon oxide (SiO x ). In addition, this is only exemplarily shown, and in the partition wall PW according to an embodiment of the present invention, the second partition wall layer L2 may be omitted.

[0141] In the present embodiment, the second inner surface S-L2 of the second partition wall layer L2 is closer to the center of the anode AE ​​than the first inner surface S-L1 of the first partition wall layer L1. In other words, the first inner surface S-L1 of the first partition wall layer L1 may be recessed toward a direction away from the center of the anode AE ​​compared to the second inner surface S-L2 of the second partition wall layer L2. Accordingly, the second partition wall layer L2 may include a lower surface exposed from the first partition wall layer L1.

[0142] The partition wall PW may have an undercut shape in cross section. As described above, the undercut shape of the partition wall PW may be defined by the step difference between the first inner surface S-L1 of the first partition wall layer L1 and the second inner surface S-L2 of the second partition wall layer L2. In addition, the shape of the partition wall PW in cross section is not limited thereto, and it may have various shapes such as an inverted cone shape and an overhang shape, and is not limited to a certain embodiment.

[0143] although Figure 6 The case where the first inner side surface S-L1 of the first partition wall layer L1 and the second inner side surface S-L2 of the second partition wall layer L2 are respectively perpendicular to the upper surface of the fifth insulating layer 50 is exemplarily illustrated, but is not limited thereto.

[0144] The intermediate layer ITL may be arranged on the anode AE. The intermediate layer ITL may be patterned by each tip portion TP defined in the partition wall PW. At least a portion of the intermediate layer ITL may be arranged in the light emitting opening portion OP-E. The intermediate layer ITL may be entirely arranged in the light emitting opening portion OP-E, and the intermediate layer ITL may also be arranged not only in the respective light emitting opening portions OP-E but also in the partition wall opening portion OP-P. In an embodiment including a sacrificial pattern SP, the intermediate layer ITL may also be arranged in the sacrificial opening portion OP-S.

[0145] The intermediate layer ITL may include a light-emitting layer including a light-emitting substance, and may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the light-emitting layer.

[0146] The electron control layer EL may be arranged on the intermediate layer ITL. The electron control layer EL may also include an electron transport layer (ETL) and an electron injection layer (EIL) arranged between the light emitting layer and the cathode CE. The electron control layer EL may be patterned by defining each tip portion TP of the partition wall PW. At least a portion of the electron control layer EL may be arranged in the partition wall opening portion OP-P, or in the light emitting opening portion OP-E.

[0147] As described below, the first dummy pattern D1 including the same material as the electron control layer EL may be arranged on the upper surface of the partition wall PW. Specifically, the first dummy pattern D1 separated from the electron control layer EL may contact the upper surface of the partition wall PW. That is, no other layer may be arranged between the electron control layer EL and the upper surface of the partition wall PW.

[0148] The cathode CE may be arranged on the electron control layer EL. The cathode CE may be patterned by defining each tip portion TP of the partition wall PW. At least a portion of the cathode CE may be arranged in the partition wall opening OP-P. In one embodiment of the present invention, according to the thickness of the intermediate layer ITL and the electron control layer EL or the thickness of the pixel definition film PDL, a portion of the cathode CE may also be arranged in the light emitting opening OP-E.

[0149] The cathode CE may have electrical conductivity. For example, the cathode CE may be formed of various materials as long as it has electrical conductivity, such as metal, transparent conductive oxide (TCO) or conductive polymer.

[0150] like Figure 6 As shown, an end of the cathode CE may be in contact with the partition wall PW.

[0151] According to an embodiment of the present invention, the display panel DP may further include a capping pattern. The capping pattern may be arranged on the cathode CE. The capping pattern may be patterned by defining a tip portion TP of the partition wall PW. At least a portion of the capping pattern may be arranged in the partition wall opening portion OP-P.

[0152] The dummy pattern DMP may be arranged on the partition wall PW. The dummy pattern DMP may include a first dummy pattern D1 and a second dummy pattern D2. The first dummy pattern D1 and the second dummy pattern D2 may be sequentially stacked along the third direction DR3 on the upper surface of the second partition wall layer L2 of the partition wall PW. Specifically, the first dummy pattern D1 may contact the upper surface of the second partition wall layer L2, and the second dummy pattern D2 may be arranged on the first dummy pattern D1.

[0153] like Figure 6 and Figure 7 As shown, the first dummy pattern D1 may completely cover the upper surface of the second partition wall layer L2. The second dummy pattern D2 may completely cover the upper surface of the first dummy pattern D1. In addition, the second dummy pattern D2 may contact the upper surface of the first dummy pattern D1, but is not limited thereto. Other structures may be interposed between the first dummy pattern D1 and the second dummy pattern D2, but are not limited to a certain embodiment.

[0154] The first dummy pattern D1 may include an organic substance. For example, the first dummy pattern D1 may include the same substance as the electron control layer EL. The first dummy pattern D1 may be formed simultaneously with the electron control layer EL through one process, and may be formed to be separated from the electron control layer EL by the undercut shape of the partition wall PW.

[0155] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed simultaneously with the cathode CE through one process, and may be formed to be separated from the cathode CE by the undercut shape of the partition wall PW.

[0156] In the case where the display element layer DP-OLED also includes a capping pattern, the dummy pattern DMP may further include a third dummy pattern. The third dummy pattern may include a conductive material. For example, the third dummy pattern may include the same material as the capping pattern. The third dummy pattern may be formed simultaneously with the capping pattern through one process, and is formed to be separated from the capping pattern by the undercut shape of the partition wall PW.

[0157] A dummy opening OP-D may be defined in the dummy pattern DMP. The dummy opening OP-D may overlap with the light emitting opening OP-E. On a plane, the dummy pattern DMP may be in a closed line shape surrounding the light emitting region PXA.

[0158] although Figure 6 The situation in which the inner surfaces of the first dummy pattern D1 and the second dummy pattern D2 are aligned with the second inner surface S-L2 of the second partition wall layer L2 is exemplarily shown, but not limited to this, the first dummy pattern D1 and the second dummy pattern D2 may also cover the second inner surface S-L2 of the second partition wall layer L2.

[0159] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern (also referred to as a "lower encapsulation layer") LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0160] The lower encapsulation inorganic pattern LIL may be arranged on the cathode CE. The lower encapsulation inorganic pattern LIL may be formed to correspond to the light emitting opening portion OP-E. The lower encapsulation inorganic pattern LIL may be in direct contact with the cathode CE, the second dummy pattern D2, and the partition wall PW. For example, a portion of the lower encapsulation inorganic pattern LIL may cover the cathode CE and the partition wall PW in the partition wall opening portion OP-P, and another portion may cover the second dummy pattern D2 on the partition wall PW. As an example, the lower encapsulation inorganic pattern LIL may include silicon nitride (SiN x ), may also include other substances, but is not limited to a certain embodiment.

[0161] The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0162] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL can protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL can protect the display element layer DP-OLED from foreign matter such as dust particles.

[0163] Figure 7 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Specifically, Figure 7 is along Figure 5 A cross-sectional view of a display panel according to an embodiment of the present invention is shown taken along line II-II'.

[0164] Figure 7 The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B are shown in an enlarged manner. Figure 6 The description in the one light emitting region PXA is also applied to the first to third light emitting regions PXA-R to PXA-B, respectively.

[0165] Reference Figure 7 The display element layer DP-OLED may include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel defining layer PDL, a partition wall PW, and a dummy pattern DMP.

[0166] The light emitting elements ED1 , ED2 , ED3 may include a first light emitting element ED1 , a second light emitting element ED2 , and a third light emitting element ED3 .

[0167] The first light emitting element ED1 may include a first anode AE1, a first intermediate layer ITL1, a first electronic control layer EL1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second intermediate layer ITL2, a second electronic control layer EL2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third intermediate layer ITL3, a third electronic control layer EL3, and a third cathode CE3. The first anode AE1 to the third anode AE3 may be arranged in a plurality of patterns. In one embodiment, the first intermediate layer ITL1 may provide red light, the second intermediate layer ITL2 may provide green light, and the third intermediate layer ITL3 may provide blue light.

[0168] The pixel definition film PDL may be defined with first to third light emitting openings OP1-E to OP3-E. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0169] The sacrificial patterns SP1, SP2, SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1 to SP3 may be arranged on the upper surfaces of the first to third anodes AE1 to AE3, respectively. The first to third sacrificial openings OP1-S to OP3-S may be defined in the first to third sacrificial patterns SP1 to SP3, respectively overlapping the first to third light emitting openings OP1-E to OP3-E.

[0170] In the present embodiment, the partition wall PW may be defined with first to third partition wall openings OP1-P to OP3-P respectively overlapping with the first to third light emitting openings OP1-E to OP3-E. The first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first partition wall opening OP1-P. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second partition wall opening OP2-P. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third partition wall opening OP3-P.

[0171] Each of the first to third partition wall openings OP1 -P to OP3 -P may include the aforementioned Figure 6 The first area A1 (refer to Figure 6 ) and the second area A2 (refer to Figure 6 The first partition wall layer L1 may include a first inner side surface S-L1 (refer to FIG. 1 ) defining a first area A1 of the first partition wall opening OP1 -P to the third partition wall opening OP3 -P. Figure 6 The second partition wall layer L2 may include a second inner side surface SL2 (refer to FIG. 1 ) defining a second area A2 of the first to third partition wall openings OP1-P to OP3-P. Figure 6 ).

[0172] The first intermediate layer ITL1, the first electron control layer EL1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second intermediate layer ITL2, the second electron control layer EL2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third intermediate layer ITL3, the third electron control layer EL3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P.

[0173] In this embodiment, the first to third intermediate layers ITL1 to ITL3, the first to third electronic control layers EL1 to EL3, and the first to third cathodes CE1 to CE3 can be formed in the light emitting openings OP1-E, OP2-E, OP3-E and the partition wall openings OP1-P, OP2-P, OP3-P by being physically separated by the second partition wall layer L2 forming the tip portion TP. As shown in the figure, in the cross section, each of the first to third cathodes CE1 to CE3 can be in contact with the partition wall PW, and the first to third intermediate layers ITL1 to ITL3 can be in contact with the partition wall PW. In addition, as shown in the figure, each of the first to third electronic control layers EL1 to EL3 can be in contact with the partition wall PW. Although the figure exemplarily shows a situation in which each of the first to third intermediate layers ITL1 to ITL3 and the first to third electronic control layers EL1 to EL3 is in contact with the partition wall PW, each of the first to third intermediate layers ITL1 to ITL3 and the first to third electronic control layers EL1 to EL3 can be separated from the partition wall PW and prevent current leakage from occurring.

[0174] As described below, the first to third cathodes CE1 to CE3 may be formed by the same process and disposed in the first to third partition wall openings OP1 -P to OP3 -P, respectively.

[0175] According to the present invention, the first to third intermediate layers ITL1 to ITL3, the first to third electronic control layers EL1 to EL3, and the first to third cathodes CE1 to CE3 can be patterned and deposited in units of pixels by means of the tip portion TP defined in the partition wall PW. That is, although the first to third intermediate layers ITL1 to ITL3 are formed together using an open mask, they can be easily divided in units of pixels by means of the partition wall PW.

[0176] On the contrary, when the first to third intermediate layers ITL1 to ITL3 are patterned using a fine metal mask (FMM), a supporting spacer protruding from the conductive partition wall is required to support the fine metal mask. In addition, as the fine metal mask is separated from the base surface for patterning by a distance equivalent to the height of the partition wall and the spacer, there may be a limit to achieving high resolution. In addition, as the fine metal mask contacts the spacer, after the patterning process of the first to third intermediate layers ITL1 to ITL3, foreign matter may remain in the spacer, or the spacer may be damaged by the imprinting of the fine metal mask. As a result, a poor display panel may be formed.

[0177] According to the present embodiment, by including the partition wall PW, physical separation between the light emitting elements ED1, ED2, and ED3 can be easily achieved. Accordingly, current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B can be prevented, and each light emitting element ED1, ED2, and ED3 can be driven independently.

[0178] In particular, since the display area DA (refer to Figure 1b ) by patterning the plurality of first to third intermediate layers ITL1 to ITL3 in the absence of a mask that forms internal contacts within the display panel DP, thereby providing a display panel DP with reduced defective rate and improved process reliability. Since patterning can be achieved even without providing a separate supporting spacer protruding from the partition wall PW, the area of ​​the light-emitting regions PXA-R, PXA-G, and PXA-B can be miniaturized, thereby providing a display panel DP that can easily achieve high resolution.

[0179] In addition, when manufacturing a large-area display panel DP, by omitting the manufacture of a large-area mask, the process cost can be reduced, and the display panel DP with improved process reliability can be provided without being affected by defects that may occur in the large-area mask.

[0180] According to one embodiment of the present invention, the first to third electronic control layers EL1 to EL3 are formed in the same process. In addition, the first to third cathodes CE1 to CE3 are also formed in the same process, and the first to third cathodes CE1 to CE3 are formed after the first to third electronic control layers EL1 to EL3 are formed and arranged on the first to third electronic control layers EL1 to EL3.

[0181] That is, the present invention does not need to form an additional layer and remove the additional process in order to form an electronic control layer EL1, EL2, EL3 or cathode CE1, CE2, CE3 in one light-emitting opening OP1-E, OP2-E, OP3-E or partition wall opening OP1-P, OP2-P, OP3-P, and then form a different electronic control layer EL1, EL2, EL3 or cathode CE1, CE2, CE3 in a different light-emitting opening OP1-E, OP2-E, OP3-E or partition wall opening OP1-P, OP2-P, OP3-P. Thus, the intermediate layer ITL1, ITL2, ITL3, the electronic control layer EL1, EL2, EL3 and the cathode CE1, CE2, CE3 can be prevented from being damaged in the additional process of forming the additional layer and removing the additional layer, thereby ensuring the reliability of the electrical connection of the display panel DP. In addition, since the process can be simplified, the production cost and time can be reduced.

[0182] The dummy pattern DMP may include a plurality of first dummy patterns D1 and a plurality of second dummy patterns D2 .

[0183] The first dummy pattern D1 may include 1-1st to 1-3rd dummy patterns D11 to D13 respectively surrounding the first to third light emitting regions PXA-R to PXA-B on a plane. The 1-1st to 1-3rd dummy patterns D11 to D13 may include the same material as the first to third electronic control layers EL1 to EL3, respectively, and may be formed by the same process as the first to third electronic control layers EL1 to EL3.

[0184] The second dummy pattern D2 may include 2-1st to 2-3rd dummy patterns D21 to D23 respectively surrounding the first to third light emitting regions PXA-R to PXA-B on a plane. The 2-1st to 2-3rd dummy patterns D21 to D23 may include the same material as the first to third cathodes CE1 to CE3, respectively, and may be formed by the same process as the first to third cathodes CE1 to CE3.

[0185] The dummy pattern DMP may define first to third dummy openings OP1-D to OP3-D corresponding to the first to third light-emitting openings OP1-E to OP3-E, respectively. The first dummy opening OP1-D is defined by the inner surfaces of the 1-1st dummy pattern D11 and the 2-1st dummy pattern D21, the second dummy opening OP2-D is defined by the inner surfaces of the 1-2nd dummy pattern D12 and the 2-2nd dummy pattern D22, and the third dummy opening OP3-D may be defined by the inner surfaces of the 1-3rd dummy pattern D13 and the 2-3rd dummy pattern D23.

[0186] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1, LIL2, LIL3, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL. In the present embodiment, the lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. The first lower encapsulation inorganic pattern LIL1 to the third lower encapsulation inorganic pattern LIL3 may overlap with the first light emitting opening portion OP1-E to the third light emitting opening portion OP3-E, respectively.

[0187] The first lower package inorganic pattern LIL1 may cover the 1-1st dummy pattern D11 and the 2-1st dummy pattern D21, and a portion of the first lower package inorganic pattern LIL1 may be arranged inside the first partition wall opening OP1-P. The second lower package inorganic pattern LIL2 may cover the 1-2nd dummy pattern D12 and the 2-2nd dummy pattern D22, and a portion of the second lower package inorganic pattern LIL2 may be arranged inside the second partition wall opening OP2-P. The third lower package inorganic pattern LIL3 may cover the 1-3rd dummy pattern D13 and the 2-3rd dummy pattern D23, and a portion of the third lower package inorganic pattern LIL3 may be arranged inside the third partition wall opening OP3-P. The first to third lower package inorganic patterns LIL1 to LIL3 may be integrally arranged with each other.

[0188] As described below, the first to third lower encapsulation inorganic patterns LIL1 to LIL3 may be formed by the same process and may be provided as an integrated lower encapsulation layer LIL to cover the first to third light emitting openings OP1 -E to OP3 -E.

[0189] Figure 8a to Figure 8h as well as Figures 9a to 9f FIG. 1 is a cross-sectional view showing some steps in a method for manufacturing a display panel according to an embodiment of the present invention. Figure 8a to Figure 8h and Figures 9a to 9f 1 to Figure 7 The same / similar reference numerals will be used for the same / similar configurations, and repeated description will be omitted.

[0190] A method for manufacturing a display panel according to an embodiment of the present invention includes the following steps: providing a preliminary display panel, the preliminary display panel including a base layer, an anode arranged on the base layer, and a preliminary pixel defining film arranged on the base layer and covering the anode; forming a partition wall arranged on the preliminary pixel defining film and formed with a plurality of partition wall openings; forming a light-emitting opening portion that overlaps with the plurality of partition wall openings and exposes at least a portion of the anode by patterning the preliminary pixel defining film, and forming a pixel defining film; and forming a first intermediate layer, a second intermediate layer, a first electronic control layer, a second electronic control layer and a first pattern, the first intermediate layer and the second intermediate layer respectively including a first light-emitting substance and a second light-emitting substance that generate light of a first color and a second color different from each other in their respective partition wall openings, the first control layer and the second control layer respectively overlap with the first intermediate layer and the second intermediate layer, and the first pattern is respectively separated from the first electronic control layer and the second electronic control layer and contacts with the upper surface of the partition wall.

[0191] Furthermore, the steps of: forming a cathode disposed on the intermediate layer and in contact with the partition wall and a second pattern separated from the cathode and disposed on the first pattern; and forming an encapsulation layer covering the plurality of partition wall openings may be further included.

[0192] Below, through Figure 8a to Figure 8h as well as Figures 9a to 9f The method of forming two light emitting elements ED1, ED2 or three light emitting elements ED1, ED2, ED3 and a lower encapsulation layer LIL, an encapsulation organic film OL and an upper encapsulation inorganic film UIL covering the light emitting elements ED1, ED2, ED3 is described. Figure 8a to Figure 8h as well as Figures 9a to 9f The display panel DP formed exemplarily shows Figure 7 A portion of the display panel DP.

[0193] Below, in Figure 8a to Figure 8h In the figure, for the sake of convenience, only two light-emitting openings OP1-E and OP2-E are shown for illustration, but the same can be applied to the case where there are more than three light-emitting openings.

[0194] Reference Figure 8a The manufacturing method of the display panel according to the present embodiment may include the step of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in the present embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode AE1 and a second anode AE2, a first preliminary sacrificial pattern SP1-I and a second preliminary sacrificial pattern SP2-I, a pixel defining film PDL, a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0195] The circuit element layer DP-CL can be formed by a common circuit element manufacturing process that forms an insulating layer, a semiconductor layer and a conductive layer by coating, deposition, etc. and selectively patterns the insulating layer, the semiconductor layer and the conductive layer by photolithography and etching processes to form semiconductor patterns, conductive patterns and signal lines.

[0196] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by the same patterning process, and the second anode AE2 and the first preliminary sacrificial pattern SP2-I may be formed by the same patterning process. The pixel defining film PDL may be arranged on the base layer BL. The pixel defining film PDL may cover the first anode AE1 and the second anode AE2 and the first preliminary sacrificial pattern SP1-I and the second preliminary sacrificial pattern SP2-I.

[0197] The first preliminary partition wall layer L1-I may be arranged on the pixel definition film PDL. The first preliminary partition wall layer L1-I may be formed by a deposition process of a conductive material. The second preliminary partition wall layer L2-I may be arranged on the first preliminary partition wall layer L1-I. The second preliminary partition wall layer L2-I may also be formed by a deposition process of a conductive material. In this embodiment, the first preliminary partition wall layer L1-I may include aluminum (Al) or molybdenum (Mo), and the second preliminary partition wall layer L2-I may include titanium (Ti), but the materials included in the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are not limited thereto. The first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may form a preliminary partition wall PW-I.

[0198] Then, the manufacturing method of the display panel according to the present embodiment may include the following steps: forming a first photoresist layer PR1 on the preliminary partition wall PW-I. The first photoresist layer PR1 may be formed by patterning the preliminary photoresist layer using a photolithography mask after forming the preliminary photoresist layer on the preliminary partition wall PW-I. A first photolithography opening OP-PR1 and a second photolithography opening OP-PR2 may be formed in the first photoresist layer PR1 by a patterning process. The first photolithography opening OP-PR1 may overlap with the first anode AE1, and the second photolithography opening OP-PR2 may overlap with the second anode AE2.

[0199] Then, refer to Figure 8b and Figure 8c The manufacturing method of the display panel according to the present embodiment may include the following steps: forming a first partition wall layer L1 and a second partition wall layer L2 defining partition wall openings OP1-P and OP2-P by etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, so as to form a first partition wall layer L1 and a second partition wall layer L2 defining partition wall openings OP1-P and OP2-P from the preliminary partition wall PW-I (refer to Figure 8a ) forms a partition wall PW.

[0200] First, if Figure 8b As shown, the step of first etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include the following steps: using the first photoresist layer PR1 as a mask to perform dry etching on the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, thereby Figure 8a) to form preliminary partition wall openings OP1-PI and OP2-PI. The preliminary partition wall openings OP1-PI and OP2-PI may include a first preliminary partition wall opening OP1-PI and a second preliminary partition wall opening OP2-PI. The first preliminary partition wall opening OP1-PI may be formed to overlap with the first anode AE1, and the second preliminary partition wall opening OP2-PI may be formed to overlap with the second anode AE2.

[0201] In this embodiment, the first dry etching process can be performed in an etching environment in which the etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is substantially the same. Accordingly, the inner surface of the first preliminary partition wall layer L1-I and the inner surface of the second preliminary partition wall layer L2-I defining the preliminary partition wall openings OP1-PI and OP2-PI can be substantially aligned.

[0202] Then, if Figure 8c As shown, the first preliminary partition wall layer L1-I (refer to Figure 8b ) The step of performing a second etching may include the following steps: using the first photoresist layer PR1 as a mask to etch the first preliminary partition wall layer L1-I (refer to Figure 8b ) is wet-etched to form the partition wall openings OP1-PI and OP2-PI (see Figure 8b ) to form partition wall openings OP1-P and OP2-P. The partition wall openings OP1-P and OP2-P may include a first partition wall opening OP1-P and a second partition wall opening OP2-P. The first partition wall opening OP1-P may be formed to overlap with the first anode AE1, and the second partition wall opening OP2-P may be formed to overlap with the second anode AE2.

[0203] Each of the partition wall openings OP1-P and OP2-P may include a first area A1 and a second area A2 sequentially arranged in the thickness direction (i.e., the third direction DR3). The first partition wall layer L1 may include a first inner side surface S-L1 defining the first area A1 of the partition wall openings OP1-P and OP2-P, and the second partition wall layer L2 may include a second inner side surface S-L2 defining the second area A2.

[0204] Reference Figure 6 , Figure 7 and Figure 8c The step of forming the first partition wall layer L1 and the second partition wall layer L2 may include the following steps: forming a tip portion TP protruding from the first partition wall layer L1 toward the partition wall openings OP1-P and OP2-P in the second partition wall layer L2. The wet etching process in this embodiment may be performed on the first preliminary partition wall layer L1-I (refer to Figure 8b ) and the second preliminary partition wall layer L2-I (refer to Figure 8b ) in an environment where the etching selectivity ratio between the first and second partition wall layers OP1-P and OP2-P is large. Accordingly, the inner surface of the partition wall PW defining the partition wall openings OP1-P and OP2-P may have an undercut shape in cross section. Specifically, as the etching rate (etch rate) of the first partition wall layer L1 for the etching solution is greater than the etching rate of the second partition wall layer L2, the first partition wall layer L1 may be mainly etched. Accordingly, the first inner surface S-L1 of the first partition wall layer L1 may be formed to be further recessed inwardly than the second inner surface S-L2 of the second partition wall layer L2. The tip portion TP may be formed on the partition wall PW by a portion of the second partition wall layer L2 that protrudes more than the first partition wall layer L1.

[0205] Then, refer to Figure 8d The manufacturing method of the display panel according to the present embodiment may include the steps of etching the pixel definition film PDL and etching the preliminary sacrificial patterns SP1-I and SP2-I (refer to Figure 8c ). The etching process of the pixel defining film PDL can be performed by dry etching, and the first photoresist layer PR1 and the partition wall PW (for example, the second partition wall layer L2) can be used as a mask for etching. Light-emitting openings OP1-E and OP2-E corresponding to the partition wall openings OP1-P and OP2-P can be formed in the pixel defining film PDL. The light-emitting openings OP1-E and OP2-E can include a first light-emitting opening OP1-E and a second light-emitting opening OP2-E.

[0206] Prepare sacrificial patterns SP1-I, SP2-I (refer to Figure 8c ) can be performed by wet etching, and the first photoresist layer PR1 and the partition wall PW (for example, the second partition wall layer L2) can be used as masks for etching. Figure 8c ) in the sacrificial patterns SP1 and SP2 formed by the above-mentioned embodiment, sacrificial openings OP1-S and OP2-S overlapping with the light-emitting openings OP1-E and OP2-E may be formed.

[0207] The sacrificial patterns SP1 and SP2 may include a first sacrificial pattern SP1 and a second sacrificial pattern SP2. A first sacrificial opening portion OP1-S overlapping with the first light-emitting opening portion OP1-E may be formed in the first sacrificial pattern SP1, and a second sacrificial opening portion OP2-S overlapping with the second light-emitting opening portion OP2-E may be formed in the second sacrificial pattern SP2. At least a portion of the first anode AE1 may be exposed from the first sacrificial pattern SP1 and the pixel defining film PDL through the first sacrificial opening portion OP1-S and the first light-emitting opening portion OP1-E, and at least a portion of the second anode AE2 may be exposed from the second sacrificial pattern SP2 and the pixel defining film PDL through the second sacrificial opening portion OP2-S and the second light-emitting opening portion OP2-E.

[0208] The etching process of the sacrificial patterns SP1 and SP2 can be performed in an environment where the etching selectivity ratio between the sacrificial patterns SP1 and SP2 and the anodes AE1 and AE2 is large, thereby preventing the anodes AE1 and AE2 from being etched together. That is, by arranging the sacrificial patterns SP1 and SP2 having an etching rate higher than that of the anodes AE1 and AE2 between the pixel defining film PDL and the anodes AE1 and AE2, it is possible to prevent the anodes AE1 and AE2 from being etched together and damaged during the etching process.

[0209] Then, refer to Figure 8e to Figure 8h According to an embodiment of the present invention, a method for manufacturing a display panel comprises the following steps: removing the first photoresist layer PR1 (refer to Figure 8d ) Thereafter, a first preliminary intermediate layer ITL1-I and first protective layers SCL1-1 and SCL1-2 are formed in the partition wall openings OP1-P and OP2-P.

[0210] First refer to Figure 8e The step of forming the first preliminary intermediate layer ITL1 -I may include the step of depositing the first preliminary intermediate layer ITL1 -I. The process of depositing the first preliminary intermediate layer ITL1 -I may include a thermal evaporation process.

[0211] The first preliminary intermediate layer ITL1-I may include a hole control layer (hole injection layer or hole transport layer) and a light emitting layer including a light emitting substance. After the hole control layer is formed, the light emitting layer may be formed on the hole control layer.

[0212] The first preliminary intermediate layer ITL1-I may be formed on the anodes AE1 and AE2. The first preliminary intermediate layer ITL1-I may be separated and arranged in the light emitting openings OP1-E and OP2-E and the partition wall openings OP1-P and OP2-P by forming a tip portion TP of the partition wall PW. The first preliminary intermediate layer ITL1-I may be formed in the partition wall openings OP1-P and OP2-P to contact the first partition wall layer L1. In the step of forming the first preliminary intermediate layer ITL1-I, a first dummy layer D1-I separated from the first preliminary intermediate layer ITL1-I may be simultaneously formed on the partition wall PW.

[0213] The step of forming the first protective layers SCL1-1 and SCL1-2 may include the step of depositing the first protective layers SCL1-1 and SCL1-2. The process of depositing the first protective layers SCL1-1 and SCL1-2 may include a thermal evaporation process. The first protective layers SCL1-1 and SCL1-2 are deposited by thermal evaporation, so that the light emitting layer of the first preliminary intermediate layer ITL1-I can be prevented from being exposed to plasma.

[0214] The first protective layers SCL1-1 and SCL1-2 may be formed on the first preliminary intermediate layer ITL1-I. The first protective layers SCL1-1 and SCL1-2 may be separated by the tip portion TP formed on the partition wall PW and arranged in the partition wall openings OP1-P and OP2-P. In cross section, the first protective layers SCL1-1 and SCL1-2 may be formed in the partition wall openings OP1-P and OP2-P to be separated from the second partition wall layer L2. In the step of forming the first protective layers SCL1-1 and SCL1-2, a second dummy layer D2-I separated from the first protective layers SCL1-1 and SCL1-2 may be simultaneously formed on the partition wall PW.

[0215] Specifically, the 1-1st protection layer SCL1-1 may be formed on the first preliminary intermediate layer ITL1-I in the first partition wall opening OP1-P, and the 1-2nd protection layer SCL1-2 may be formed on the first preliminary intermediate layer ITL1-I in the second partition wall opening OP2-P.

[0216] According to an embodiment of the present invention, the 1-1 protective layer SCL1-1 and the 1-2 protective layer SCL1-2 may include a material having an etching selectivity ratio with the partition wall PW. As an example, the 1-1 protective layer SCL1-1 and the 1-2 protective layer SCL1-2 may include silver (Ag). However, this is not limited to this, and the 1-1 protective layer SCL1-1 and the 1-2 protective layer SCL1-2 may include other materials besides silver (Ag), and are not limited to a certain embodiment.

[0217] Reference Figure 8f , may include forming a first photoresist pattern PRP1 covering the first light emitting opening portion OP1-E and the first partition wall opening portion OP1-P. The first photoresist pattern PRP1 may not overlap with the second light emitting opening portion OP2-E.

[0218] The first photoresist pattern PRP1 may prevent the 1-1th protection layer SLCL1 - 1 from being etched in an etching step to be described later.

[0219] Reference Figure 8g , may include the step of removing a portion of the first protection layers SCL1 - 1 and SCL1 - 2 .

[0220] According to an embodiment of the present invention, the first protection layers SCL1-1 and SCL1-2 can be removed by wet etching (see Figure 8f ). At this time, the etchant used for wet etching may be an etchant that does not react with the partition wall PW but only reacts with the first protective layer SCL1-1, SCL1-2 (refer to Figure 8f As an example, when the first protective layers SCL1-1, SCL1-2 (refer to Figure 8f ) includes silver (Ag) and the partition wall PW includes aluminum (Al), the etchant may selectively etch only the silver (Ag) but not the aluminum (Al).

[0221] Referring to the drawings, the first photoresist pattern PRP1 prevents the 1-1 protection layer SCL1-1 from contacting the etchant by covering the 1-1 protection layer SCL1-1, so that the 1-1 protection layer SCL1-1 may not be removed. Figure 8f ) is not covered by the first photoresist pattern PRP1, so the 1-2 protection layer SCL1-2 (refer to Figure 8f ) may be removed by an etchant. At this time, the remaining 1-1 protection layer SCL1-1 may form a first protection pattern SCP1.

[0222] By removing the first protective layers SCL1-1, SCL1-2 (see Figure 8f ) to form a predetermined gap between the first photoresist pattern PRP1 and the first preliminary intermediate layer ITL1-I.

[0223] Not limited to the above, the first protection layers SCL1-1, SCL1-2 (refer to Figure 8f ) can be removed by dry etching, but is not limited to a certain etching method.

[0224] Reference Figure 8h , may include the step of removing the first preliminary intermediate layer ITL1-I and the first photoresist pattern PRP1. According to one embodiment of the present invention, the first preliminary intermediate layer ITL1-I and the first photoresist pattern PRP1 may be removed by stripping. However, it is not limited thereto, and may be removed by other methods, and is not limited to a certain embodiment.

[0225] The first preliminary intermediate layer ITL1-I and the first protection pattern SCP1 covered by the first photoresist pattern PRP1 may not be removed in this step. That is, the first preliminary intermediate layer ITL1-I formed in the second light-emitting opening portion OP2-E may be removed, while the first preliminary intermediate layer ITL1-I and the first protection pattern SCP1 formed in the first light-emitting opening portion OP1-E may not be removed. The remaining first preliminary intermediate layer ITL1-I may form the first intermediate layer ITL1.

[0226] Below, in Figures 9a to 9f In order to facilitate the description and present the light emitting elements ED1, ED2, ED3 (refer to Figure 7 ) are shown with three light-emitting openings OP1-E, OP2-E, and OP3-E, which can also be applied to situations with more than three light-emitting elements.

[0227] Reference Figure 9a and Figure 9b According to an embodiment of the present invention, a method for manufacturing a display panel may include the following steps: forming a second preliminary intermediate layer ITL2-I and second protective layers SCL2-1, SCL2-2, SCL2-3 in the partition wall openings OP1-P, OP2-P, OP3-P.

[0228] The step of forming the second preliminary intermediate layer ITL2 -I may include the step of depositing the second preliminary intermediate layer ITL2 -I, which may include a thermal deposition process.

[0229] The step of forming the second protective layers SCL2-1, SCL2-2, SCL2-3 may include the step of depositing the second protective layers SCL2-1, SCL2-2, SCL2-3. The process of depositing the second protective layers SCL2-1, SCL2-2, SCL2-3 may include a thermal evaporation process.

[0230] The second preliminary intermediate layer ITL2-I may be formed on the anodes AE1, AE2, and AE3. The second preliminary intermediate layer ITL2-I may be separated by a tip portion TP formed on the partition wall PW and arranged in the partition wall openings OP1-P, OP2-P, and OP3-P, and may overlap with the light-emitting openings OP1-E, OP2-E, and OP3-E. The second preliminary intermediate layer ITL2-I may be formed in the partition wall openings OP1-P, OP2-P, and OP3-P to contact the first partition wall layer L1. In the step of forming the second preliminary intermediate layer ITL2-I, a first dummy layer D1-I separated from the second preliminary intermediate layer ITL2-I may be simultaneously formed on the partition wall PW.

[0231] Specifically, the second preliminary intermediate layer ITL2-I may be formed on the first protection pattern SCP1 in the first partition wall opening OP1-P, may be formed on the second anode AE2 in the second partition wall opening OP2-P, and may be formed on the third anode AE3 in the third partition wall opening OP3-P.

[0232] The second protective layers SCL2-1, SCL2-2, SCL2-3 may be formed on the second preliminary intermediate layer ITL2-I. The second protective layers SCL2-1, SCL2-2, SCL2-3 may be separated by the tip portion TP formed on the partition wall PW, and may be arranged in the partition wall openings OP1-P, OP2-P, OP3-P. The second protective layers SCL2-1, SCL2-2, SCL2-3 may be formed in the partition wall openings OP1-P, OP2-P, OP3-P to be separated from the second partition wall layer L2 in cross section. In the step of forming the second protective layers SCL2-1, SCL2-2, SCL2-3, a second dummy layer D2-I separated from the second protective layers SCL2-1, SCL2-2, SCL2-3 may be simultaneously formed on the partition wall PW.

[0233] Specifically, the 2-1st protective layer SCL2-1 can be formed on the second preliminary intermediate layer ITL2-I in the first partition wall opening OP1-P, the 2-2nd protective layer SCL2-2 can be formed on the second preliminary intermediate layer ITL2-I in the second partition wall opening OP2-P, and the 2-3rd protective layer SCL2-3 can be formed on the second preliminary intermediate layer ITL2-I in the third partition wall opening OP3-P.

[0234] Reference Fig.9c , may include forming a second photoresist pattern PRP2 covering the second light emitting opening portion OP2-E and the second partition wall opening portion OP2-P. The second photoresist pattern PRP2 may not overlap with the first light emitting opening portion OP1-E and the third light emitting opening portion OP3-E.

[0235] The second photoresist pattern PRP2 may prevent the 2-2 protection layer SCL2 - 2 from being etched in an etching step to be described later.

[0236] Reference Figure 9d , which may include removing the second protective layers SCL2-1, SCL2-2, SCL2-3 (refer to Fig.9c ) is a part of the step. The second protective layer SCL2-1, SCL2-2, SCL2-3 (refer to Fig.9c ) may include the first protection layer SCL1-1, SCL1-2 (refer to Figure 8e ) and can be formed by the first protective layer SCL1-1, SCL1-2 (refer to Figure 8e ) are removed in the same way as the removal method of the second protective layers SCL2-1, SCL2-2, and SCL2-3.

[0237] Referring to the drawings, the second photoresist pattern PRP2 is formed by covering the second-2 protection layer SCL2-2 (refer to Fig.9c ) to prevent the 2-2 protection layer SCL2-2 (refer to Fig.9c ) is in contact with the etchant, so that the second protective layer SCL2-2 (refer to Fig.9c ) may not be removed. However, the 2-1st protection layer SCL2-1 (refer to Fig.9c ) and the 2nd-3rd protective layer SCL2-3 (refer to Fig.9c ) is not covered by the second photoresist pattern PRP2, so the 2-1st protection layer SCL2-1 (refer to Fig.9c ) and the 2nd-3rd protective layer SCL2-3 (refer to Fig.9c ) may be removed by the etchant. At this time, the remaining 2-2 protective layer SCL2-2 (refer to Fig.9c ) can form a second protection pattern SCP2.

[0238] Reference Fig.9e , which may include removing the second preliminary intermediate layer ITL2-I (refer to Figure 9d ) and the second photoresist pattern PRP2 (refer to Figure 9d According to one embodiment of the present invention, the second preliminary intermediate layer ITL2-I (refer to Figure 9d ) and a second photoresist pattern PRP2 (reference Figure 9d ) can be removed by stripping. However, it is not limited thereto and can be removed by other methods and is not limited to a certain embodiment.

[0239] The second photoresist pattern PRP2 (refer to Figure 9d ) covered by the second preliminary intermediate layer ITL2-I (refer to Figure 9d ) and the second protection pattern SCP2 may not be removed in this step. That is, the second preliminary intermediate layer ITL2-I (refer to Figure 9d ) can be removed, and the second preliminary intermediate layer ITL2-I (refer to Figure 9d ) and the second protection pattern SCP2 may not be removed. The remaining second preliminary intermediate layer ITL2-I (see Figure 9d ) may form a second intermediate layer ITL2.

[0240] Although not shown in the figure, the third intermediate layer ITL3 (refer to Figure 9f ) may be formed through a process in substantially the same manner as the case of forming the second intermediate layer ITL2 arranged in the second light emitting opening portion OP2-E. However, some steps may be performed differently and are not limited to a certain embodiment.

[0241] In the third intermediate layer ITL3 (ref. Figure 9f ) may be provided with a third protection pattern similar to the first protection pattern SCP1 provided on the first intermediate layer ITL1 and the second protection pattern SCP2 provided on the second intermediate layer ITL2. The first protection pattern SCP1, the second protection pattern SCP2, and the third protection pattern may prevent the first intermediate layer ITL1 to the third intermediate layer ITL3 (refer to Figure 9f ) in the subsequent formation of the first electronic control layer EL1 to the third electronic control layer EL3 (refer to Figure 9f ) due to previous exposure to external factors.

[0242] Reference Figure 9f, the manufacturing method of the display device according to one embodiment of the present invention may include the following steps after the step of forming the third intermediate layer ITL3 in the third light-emitting opening portion OP3-E: forming electronic control layers EL1, EL2, EL3, forming cathodes CE1, CE2, CE3, and forming a lower encapsulation inorganic pattern LIL.

[0243] According to an embodiment of the present invention, a first electronic control layer EL1, a second electronic control layer EL2, and a third electronic control layer EL3 may be formed on the first to third intermediate layers ITL1 to ITL3, respectively. Before forming the first to third electronic control layers EL1 to EL3, the first protective pattern SCP1 may be removed (see Fig.9e )、Second protection pattern SCP2 (refer to Fig.9e ) and the step of a third protection pattern.

[0244] The step of forming the first to third electron control layers EL1 to EL3 may include thermal evaporation.

[0245] In the step of forming the first to third electronic control layers EL1 to EL3, the first to third electronic control layers EL1 to EL3 may be separated by the tip portions TP formed in the partition wall PW, and may be arranged in respective partition wall openings OP1-P, OP2-P, OP3-P.

[0246] In the step of forming the first to third electron control layers EL1 to EL3 , first dummy patterns D1 spaced apart from the first to third electron control layers EL1 to EL3 may be simultaneously formed on the partition wall PW.

[0247] That is, in the present invention, the first to third electron control layers EL1 to EL3 respectively arranged in the partition wall openings OP1 -P, OP2 -P, and OP3 -P can be simultaneously formed by the same process.

[0248] According to an embodiment of the present invention, the first cathode CE1 to the third cathode CE3 may be formed on the first electronic control layer EL1, the second electronic control layer EL2 and the third electronic control layer EL3 respectively. The step of forming the first cathode CE1 to the third cathode CE3 may include thermal evapoation.

[0249] In the step of forming the first to third cathodes CE1 to CE3 , the first to third cathodes CE1 to CE3 may be separated by the tip portions TP formed in the partition wall PW, and may be arranged in the respective partition wall openings OP1 -P, OP2 -P, OP3 -P.

[0250] In the step of forming the first to third cathodes CE1 to CE3 , second dummy patterns D2 spaced apart from the cathodes CE1 , CE2 , and CE3 may be simultaneously formed on the partition wall PW.

[0251] That is, in the present invention, the first to third cathodes CE1 to CE3 respectively arranged in the respective partition wall openings OP1 -P, OP2 -P, and OP3 -P may be simultaneously formed by the same process.

[0252] According to one embodiment of the present invention, a lower encapsulation layer LIL covering the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may be formed. The lower encapsulation layer LIL may be formed by a chemical vapor deposition (CVD) process. The lower encapsulation layer LIL is formed on the partition wall PW and the second dummy pattern D2, and a portion of the lower encapsulation layer LIL may be formed on the inner side of the first partition wall opening OP1-P to the third partition wall opening OP3-P.

[0253] That is, the present invention can simultaneously form the first to third electronic control layers EL1 to EL3 respectively arranged in the first partition wall opening OP1-P to the third partition wall opening OP3-P by the same process. In addition, after forming the first to third electronic control layers EL1 to EL3, the first to third cathodes CE1 to CE3 arranged on the respective first to third electronic control layers EL1 to EL3 can be formed simultaneously. In addition, after forming the first to third cathodes CE1 to CE3, the lower encapsulation layer LIL covering the respective first to third cathodes CE1 to CE3 can be continuously formed.

[0254] According to an embodiment of the present invention, it is not necessary to form an additional layer and remove the additional process in order to form an electronic control layer EL1, EL2, EL3 or cathode CE1, CE2, CE3 in one light-emitting opening OP1-E, OP2-E, OP3-E or partition wall opening OP1-P, OP2-P, OP3-P, and then form a different electronic control layer EL1, EL2, EL3 or cathode CE1, CE2, CE3 in a different light-emitting opening OP1-E, OP2-E, OP3-E or partition wall opening OP1-P, OP2-P, OP3-P. Thus, it is possible to prevent the intermediate layers ITL1, ITL2, ITL3, the electronic control layers EL1, EL2, EL3 and the cathodes CE1, CE2, CE3 from being damaged in the additional process of forming the additional layer and removing the additional layer, thereby ensuring the reliability of the electrical connection of the display panel DP. In addition, since the process can be simplified, the production cost and time can be reduced.

[0255] Then, the following steps may be further included: forming an encapsulation organic film OL on the lower encapsulation layer LIL (refer to Figure 7 ); and in the encapsulation organic film OL (reference Figure 7 ) to form an upper encapsulation inorganic film UIL (refer to Figure 7 ).

[0256] Therefore, if Figure 7 As shown, a first dummy pattern D1, a second dummy pattern D2, a lower encapsulation layer LIL, and an encapsulation organic film OL (see Figure 7 ) and the upper encapsulation inorganic film UIL (see Figure 7 ). However, it is not limited to the situation shown in the drawings, and other layers except the second dummy pattern D2 may be interposed between the first dummy pattern D1 and the lower encapsulation layer LIL, and it is not limited to a certain embodiment.

[0257] The above description is made with reference to the preferred embodiments of the present invention, but it is understood by those skilled in the art or those with general knowledge in the art that various modifications and changes can be made to the present invention without departing from the concept and technical scope of the present invention as described in the claims. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the protection scope of the claims.

Claims

1. A display panel, comprising: Base layer; A pixel defining film is arranged on the base layer and defines a light-emitting opening; a partition wall disposed on the pixel definition film and having conductivity, and defining a partition wall opening portion corresponding to the light emitting opening portion; a light emitting element arranged in the light emitting opening and comprising an anode, an intermediate layer arranged on the anode, an electron control layer arranged on the intermediate layer, and a cathode arranged on the electron control layer and connected to the partition wall; a first pattern, which is separated from the electron control layer and contacts with the upper surface of the partition wall, and includes the same material as the electron control layer; as well as The second pattern is spaced apart from the cathode and disposed on the first pattern, and includes the same material as the cathode.

2. The display panel according to claim 1, wherein: The first pattern completely covers the upper surface of the partition wall, The second pattern completely covers the upper surface of the first pattern.

3. The display panel according to claim 1, wherein: The second pattern contacts an upper surface of the first pattern.

4. The display panel according to claim 1, further comprising: an encapsulation layer, covering the light emitting element, Wherein, the encapsulation layer completely covers the upper surface of the second pattern.

5. A display panel, comprising: Base layer; A pixel defining film, arranged on the base layer and defining a plurality of light-emitting openings separated from each other; a partition wall, arranged on the pixel definition film and defining a plurality of partition wall openings respectively overlapping the plurality of light emitting openings, and having conductivity; a first light-emitting element disposed in a first light-emitting opening of the light-emitting openings, and including a first anode, a first intermediate layer disposed on the first anode and including a first light-emitting substance that generates light of a first color, a first electron control layer disposed on the first intermediate layer, and a first cathode disposed on the first electron control layer and connected to the partition wall; a second light-emitting element disposed in a second light-emitting opening portion of the light-emitting opening portions, and including a second anode, a second intermediate layer disposed on the second anode and including a second light-emitting substance that generates light of a second color, a second electron control layer disposed on the second intermediate layer, and a second cathode disposed on the second electron control layer and connected to the partition wall; a first pattern, which is separated from the first electron control layer and the second electron control layer, contacts the upper surface of the partition wall, and includes the same material as the first electron control layer and the second electron control layer; as well as The second pattern is spaced apart from the first cathode and the second cathode, is disposed on the first pattern, and includes the same material as the first cathode and the second cathode.

6. A method for manufacturing a display panel, comprising the following steps: Providing a preliminary display panel, the preliminary display panel comprising a base layer, an anode disposed on the base layer, and a preliminary pixel defining film disposed on the base layer and covering the anode; forming a partition wall disposed on the preliminary pixel definition film and having a plurality of partition wall openings; Patterning the preliminary pixel defining film to form a plurality of light emitting openings respectively overlapping the plurality of partition wall openings and exposing at least a portion of the anode, thereby forming a pixel defining film; as well as A first intermediate layer, a second intermediate layer, a first electronic control layer, a second electronic control layer and a first pattern are formed, wherein the first intermediate layer and the second intermediate layer respectively include a first light-emitting substance and a second light-emitting substance that respectively generate light of a first color and a second color different from each other in the respective openings of the partition wall, the first electronic control layer and the second electronic control layer respectively overlap with the first intermediate layer and the second intermediate layer, and the first pattern is respectively separated from the first electronic control layer and the second electronic control layer and contacts with the upper surface of the partition wall, wherein the first pattern and the first electron control layer are formed simultaneously, The second intermediate layer is formed after forming the first intermediate layer and before forming the first pattern.

7. The method for manufacturing a display panel according to claim 6, further comprising the following steps: forming a cathode disposed on the first intermediate layer and the second intermediate layer and in contact with the partition wall, and a second pattern separated from the cathode and disposed on the first pattern, Wherein, the second pattern and the cathode are formed simultaneously.

8. The method for manufacturing a display panel according to claim 6, comprising the following steps: forming a first preliminary intermediate layer on the anode and the partition wall; forming a first protective layer on the first preliminary intermediate layer; forming a first photoresist pattern covering a first light-emitting opening portion among the plurality of light-emitting opening portions; removing the first protective layer to form a first protective pattern; as well as The first intermediate layer is formed by removing the first preliminary intermediate layer and removing the first photoresist pattern.

9. The method for manufacturing a display panel according to claim 8, comprising the following steps: forming a second preliminary intermediate layer on the anode, the first intermediate layer and the partition wall; forming a second protective layer on the second preliminary intermediate layer; forming a second photoresist pattern covering a second light-emitting opening portion among the plurality of light-emitting opening portions; removing the second protective layer to form a second protective pattern; as well as forming the second intermediate layer by removing the second preliminary intermediate layer and removing the second photoresist pattern, The first protection pattern and the second protection pattern are removed, and a second pattern, a first cathode arranged in the first light-emitting opening portion, and a second cathode arranged in the second light-emitting opening portion are formed.

10. The method for manufacturing a display panel according to claim 8, wherein: The first protective layer is formed by thermal deposition.

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