Self-rectification ferroelectric memristor based on ferroelectric out-of-plane polarization and preparation method of self-rectification ferroelectric memristor

Abstract

The invention discloses a self-rectification ferroelectric memristor based on ferroelectric surface external polarization and a preparation method thereof. The memristor is of a vertical structure comprising an upper electrode layer, a ferroelectric layer and a semiconductor layer from top to bottom, the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; the out-of-plane polarization direction of the ferroelectric layer is perpendicular to the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface at the same time, the two contact surfaces form an asymmetric barrier, and the out-of-plane polarization state of the ferroelectric layer can be changed through external voltage, so that the barrier height of the two contact surfaces is changed, meanwhile, the carrier transport characteristic of the semiconductor layer is changed, and the performance of the device is improved. And therefore, a function of regulating and controlling the conductivity state of the memristor is achieved. The conduction current of the memristor is measured through a peripheral circuit and is used as a storage value. High-resistance and low-resistance switching and rectification characteristics are realized by utilizing the change of the contact potential barrier of the ferroelectric layer and the silicon interface in the polarization overturning process. The memristor is simple in structure, easy to integrate and low in power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of ferroelectric storage, and in particular relates to a self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization and a preparation method thereof. Background Art

[0002] With the rapid development of new technologies such as artificial intelligence and big data, the market has higher and higher requirements for storage hardware performance. However, the huge demand for high-throughput data processing in new data-driven technologies and new scenarios has highlighted the shortcomings of silicon-based storage. Memristors are considered to be the fourth type of basic circuit elements. They store information by adjusting the resistance state, have nonlinear resistance characteristics, and can maintain information in the power-off state. Therefore, memristors can meet the needs of the next generation of high-density information storage and high-performance computing, while being able to realize non-volatile state logic operations and brain-like neural computing functions, integrating information storage and computing in a single device. Ferroelectric memristors use reversible ferroelectric domains in ferroelectric thin film layers to achieve storage. By applying an external electric field, the electric polarization of the ferroelectric domain can be flipped, thereby changing the state of the storage medium layer. Ferroelectric memory has the advantages of high speed, low power consumption and high storage density. These properties have made ferroelectric memory widely concerned and developed rapidly in recent years. One of the main obstacles in the development of memristor storage arrays is that the so-called sneak path current will cause crosstalk interference between adjacent storage cells, increase the overall circuit power consumption, and seriously affect the operation of the memristor crossbar array. The unique nonlinear and self-rectifying characteristics of self-rectifying devices have become one of the effective solutions because they do not require additional hardware overhead. Summary of the invention

[0003] In order to solve the leakage current phenomenon of memristors in larger-scale arrays, the present invention provides a self-rectifying ferroelectric memristor with high rectification ratio and high nonlinearity and a preparation method thereof.

[0004] The objective of the present invention is achieved through the following technical solutions:

[0005] In the first aspect, the present invention provides a self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization, which has a vertical structure of an upper electrode layer, a ferroelectric layer, and a semiconductor layer from top to bottom; a lower electrode layer is drawn out from the semiconductor layer; the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; and the contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer.

[0006] Furthermore, the out-of-plane polarization direction of the ferroelectric layer is perpendicular to both the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface. The two contact surfaces form an asymmetric potential barrier. The applied voltage will change the out-of-plane polarization state of the ferroelectric layer, thereby changing the barrier height of the two contact surfaces and changing the carrier transport characteristics of the semiconductor layer, thereby achieving the function of regulating the conductivity state of the memristor.

[0007] Furthermore, the self-rectifying ferroelectric memristor further includes an insulating layer for device isolation and / or substrate.

[0008] Furthermore, the electrode structure of the self-rectifying ferroelectric memristor is a sandwich structure, consisting of an upper electrode-ferroelectric layer and a semiconductor layer-lower electrode; the electrode material is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor or gallium indium alloy.

[0009] Furthermore, the material of the ferroelectric layer is two-dimensional CuInP2S6 or α-In2Se3.

[0010] Furthermore, the semiconductor layer is a doping material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium or tellurium crystals.

[0011] In a second aspect, the present invention provides a method for preparing a single device of a self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization, comprising preparing an interface structure between a ferroelectric layer and a semiconductor layer, and preparing electrodes respectively contacting the ferroelectric layer and the semiconductor layer; the specific steps are as follows:

[0012] S1, forming an insulating layer on the semiconductor layer, patterning the insulating layer and removing the insulating layer to prepare a contact window between the semiconductor layer and the ferroelectric layer;

[0013] S2, transferring the ferroelectric material to the contact window by a wet method or a dry method to form a ferroelectric layer;

[0014] S3, preparing an upper electrode layer on the ferroelectric layer by patterning and deposition processes;

[0015] S4, preparing a lower electrode layer on the semiconductor layer by using a patterning and deposition process or applying a gallium-indium alloy.

[0016] Furthermore, the semiconductor layer is silicon, the insulating layer is silicon oxide, the ferroelectric layer is copper indium phosphide, and the upper electrode layer is gold.

[0017] In a third aspect, the present invention provides a method for preparing an array of self-rectifying ferroelectric memristors based on ferroelectric out-of-plane polarization, comprising the following steps:

[0018] S1, fabricating discrete semiconductor layers on semiconductor / insulator using patterning and deep silicon etching techniques;

[0019] S2, filling insulating materials between discrete semiconductor layers using a patterning process and a deposition process to form an inert insulating layer;

[0020] S3, transferring ferroelectric layer materials on the insulating layer / semiconductor surface or preparing the ferroelectric layer by deposition method;

[0021] S4, preparing an upper electrode layer on the ferroelectric layer by patterning and deposition processes;

[0022] S5, leading out a lower electrode layer in a non-overlapping region of the semiconductor layer to form a device array.

[0023] Furthermore, the semiconductor in S1 is silicon, the insulator is silicon oxide, and the semiconductor / insulator is implemented using SOI silicon wafer; the inert insulating layer is aluminum oxide, the ferroelectric layer is copper indium phosphorus sulfide, and the upper electrode layer is gold.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization provided by the present invention has a high rectification ratio, which means that it can effectively prevent reverse current, thereby reducing energy consumption and improving calculation accuracy. Secondly, its high nonlinearity ensures significant differences in conductivity changes within different voltage ranges, which helps to achieve low-power storage and calculation. In addition, the vector matrix multiplication achieved by utilizing its high nonlinearity characteristics has the characteristics of high quantization bits, which is very critical to the multi-bit precision requirements in vector matrix multiplication, and can significantly improve the calculation accuracy and model performance of neural networks. Therefore, this device has unique advantages in hardware implementation of deep learning and AI computing tasks, and is an important candidate for building efficient and low-power computing accelerators. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 An implementation scheme of the self-rectifying ferroelectric memristor provided in Embodiment 1 of the present invention;

[0028] Figure 2 An implementation scheme of the self-rectifying ferroelectric memristor provided in Embodiment 2 of the present invention;

[0029] Figure 3 A schematic diagram of a 9*9 array structure of a self-rectifying ferroelectric memristor provided in Example 2 of the present invention;

[0030] Figure 4 A cyclic voltammetry curve of a self-rectifying ferroelectric memristor based on gold / copper indium phosphide / silicon provided in an embodiment of the present invention;

[0031] Figure 5 A current holding characteristic duration curve diagram of a self-rectifying ferroelectric memristor based on gold / copper indium phosphorus sulfide / silicon / gallium indium alloy / copper provided in an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of a memristor array with matrix multiplication acceleration function provided by an embodiment of the present invention;

[0033] In the figure: 1. Semiconductor layer; 2. Insulating layer; 3. Inert insulating layer; 4. Ferroelectric layer; 5. Upper electrode layer. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0036] The present invention provides a self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization. The self-rectifying ferroelectric memristor has a vertical structure of an upper electrode layer, a ferroelectric layer, and a semiconductor layer from top to bottom. A lower electrode layer is drawn out from the semiconductor layer. The ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization. The contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer.

[0037] The out-of-plane polarization direction of the ferroelectric layer is perpendicular to the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface at the same time. The upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface form an asymmetric potential barrier. The out-of-plane polarization state of the ferroelectric layer is changed by applying an external voltage, thereby changing the barrier height of the two contact surfaces and changing the carrier transport characteristics of the semiconductor layer, thereby achieving the regulation function of the conductance state of the memristor. The self-rectifying ferroelectric memristor provided by the present invention has a high rectification ratio, high nonlinearity and low power consumption, has large-scale scalability, and can be used for the hardware implementation of the storage unit of the storage array and the in-memory computing acceleration unit.

[0038] Furthermore, the material of the ferroelectric layer is a two-dimensional ferroelectric semiconductor with out-of-plane ferroelectric polarization, such as CuInP2S6 and α-In2Se3.

[0039] Furthermore, the semiconductor layer is a doping material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium or tellurium crystals.

[0040] Furthermore, the electrode structure of the self-rectifying ferroelectric memristor is a sandwich structure, consisting of an upper electrode-ferroelectric layer and a semiconductor layer-lower electrode; the material of the electrode is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor or gallium indium alloy.

[0041] Furthermore, the self-rectifying ferroelectric memristor further includes an insulating layer for device isolation and / or substrate.

[0042] Further, the material of the insulating layer is any one of silicon dioxide, aluminum oxide, zirconium oxide, hafnium silicon oxide, titanium oxide, silicon nitride or aluminum nitride.

[0043] Example 1

[0044] The structure of the self-rectifying ferroelectric memristor in this embodiment is as follows Figure 1 The semiconductor layer 1 is silicon, the insulating layer 2 is silicon oxide, the ferroelectric layer 4 is copper indium phosphide (CIPS), and the upper electrode layer 5 is gold.

[0045] The preparation of a single device of the self-rectifying ferroelectric memristor includes preparing an interface structure between a ferroelectric layer and a semiconductor layer, and preparing electrodes that are in contact with the ferroelectric layer and the semiconductor layer respectively; the specific steps are as follows:

[0046] (1) An insulating layer 2 with a thickness of 100 nm is formed on the semiconductor layer 1, a window pattern is produced on the insulating layer 2 using ultraviolet photolithography technology, and the insulating layer 2 is etched cleanly using a BOE solution to expose the silicon in the window pattern;

[0047] (2) Using PDMS to transfer CIPS to the edge area of ​​the window pattern to form a ferroelectric layer 4;

[0048] (3) using photolithography technology to produce the upper electrode pattern, using electron beam evaporation or thermal evaporation technology to first grow a chromium adhesion layer with a thickness of about 5 to 10 nm, and then grow a gold layer with a thickness of about 40 to 80 nm as the upper electrode layer 5;

[0049] (4) After the bottom of the semiconductor layer 1 is cleaned with a BOE solution, a lower electrode layer is formed, thereby completing the preparation of a single self-rectifying ferroelectric memristor in this embodiment.

[0050] Furthermore, in step (1), the semiconductor layer 1 is n-type lightly doped silicon, preferably with a resistivity of 2-4 Ω·cm.

[0051] Furthermore, the window sizes formed by the photolithography technology in step (1) are 3um, 5um, and 10um, corresponding to the lateral sizes of the subsequent devices.

[0052] Furthermore, the thickness of the copper indium phosphide transferred in step (2) is between 10 nm and 100 nm.

[0053] Furthermore, in step (4), the lower electrode layer is prepared by sputtering, atomic layer deposition or evaporation; the thickness of the lower electrode layer is tens to hundreds of nanometers. Alternatively, a gallium-indium alloy is evenly coated on the bottom of the semiconductor layer 1 as the lower electrode layer.

[0054] Example 2

[0055] The structure of the self-rectifying ferroelectric memristor in this embodiment is as follows Figure 2 As shown. The semiconductor layer 1 is silicon, the insulating layer 2 is silicon oxide, and the semiconductor layer 1 and the insulating layer 2 are implemented by SOI silicon wafers. The inert insulating layer 3 is aluminum oxide, the ferroelectric layer 4 is copper indium phosphorus sulfur (represented by CIPS), and the upper electrode layer 5 is gold.

[0056] The array preparation process of the self-rectifying ferroelectric memristor is as follows:

[0057] (1) An array pattern of a semiconductor layer is produced on an SOI silicon wafer using ultraviolet lithography technology, and etching is performed using deep silicon etching technology; in this embodiment, the array pattern of the semiconductor layer is a bit line pattern in a crossbar structure;

[0058] (2) using atomic layer deposition technology to deposit aluminum oxide between the array patterns, and using an aluminum oxide etching solution to completely etch away excess aluminum oxide on the surface of the silicon material to form an inert insulating layer 3;

[0059] (3) growing CIPS as the ferroelectric layer 4 on the silicon surface by a vacuum chemical vapor transport system;

[0060] (4) using photolithography technology to produce an array pattern of the upper electrode layer; in this embodiment, the array pattern of the upper electrode layer is a word line pattern in the crossbar structure; using electron beam evaporation or thermal evaporation technology, firstly growing a chromium adhesion layer with a thickness of about 5 to 10 nm, and then growing a gold layer with a thickness of about 40 to 80 nm as the upper electrode layer 5;

[0061] (5) A lower electrode layer is drawn out in the non-overlapping region of the semiconductor layer 1 to complete the preparation of the device array in this embodiment. Figure 3 Schematic diagram of the 9*9 array structure of self-rectifying ferroelectric memristors.

[0062] Furthermore, the etching depth of the deep silicon etching in step (1) needs to reach the insulating layer 2 to achieve electrical isolation between subsequent devices.

[0063] In the present invention, the electrode patterning process includes masking, photolithography, laser direct writing, electron beam exposure and nanoimprinting; the electrode deposition process adopts vacuum resistance thermal evaporation deposition, electron beam deposition or magnetron sputtering; the ferroelectric preparation process adopts physical vapor deposition, chemical vapor deposition, epitaxial growth, solution method or sol-gel method; the ferroelectric transfer process adopts wet transfer or dry transfer; the semiconductor preparation process adopts physical vapor deposition, chemical vapor deposition or epitaxial growth.

[0064] The method for using the self-rectifying ferroelectric memristor proposed by the present invention is specifically as follows:

[0065] A read / write voltage is applied to the upper electrode, and the lower electrode is grounded.

[0066] In one embodiment of the present invention, Figure 4 This is a cyclic voltammogram of a self-rectifying ferroelectric memristor based on gold / copper indium phosphide / silicon, where the horizontal axis is voltage and the vertical axis is current. The voltage scans from 0V to 4V. Before the voltage scan reaches 4V, at about 2.7V, the self-rectifying ferroelectric memristor based on gold / copper indium phosphide / silicon obtains a stable low-resistance state through the SET process. During the voltage scan from 0V to -3V, it returns to a high-resistance state through the RESET process and can maintain a stable resistance value. And by comparing the current at 2V, 1V, and -2V, it can be found that the memristor has a resistance of about 10 2 The nonlinearity and 10 3 The SET voltage of the present invention is stable within 2V, and the RESET voltage is stable within -3V. The self-rectifying ferroelectric memristor of the present invention has high stability, and each IV curve has a high overlap.

[0067] like Figure 5 This is a graph of the current retention characteristics of a self-rectifying ferroelectric memristor based on gold / copper indium phosphide / silicon / gallium indium alloy / copper, where the horizontal axis is time and the vertical axis is current. The switching ratio between the high-resistance state and the low-resistance state is 10 3 , and the maintenance time is relatively long. When the ferroelectric memristor is under the action of the read voltage, the low resistance state current (about 10 -10 A) can last for more than 1000s, high resistance current (about 10 -13 A) can also last for more than 1000s, and the duration can be further extended, which shows that the self-rectifying ferroelectric memristor of the present invention has good switching characteristics and holding characteristics.

[0068] The embodiment of the present invention further provides a memristor array with matrix multiplication acceleration function. The memristor realizes matrix-vector multiplication by utilizing Kirchhoff's law. , where N is the number of rows, such as Figure 6 As shown, there is a memristor at each node of the interconnection line, V iis the voltage applied to the i-th row, G ij is the conductance value of the memristor in the i-th row and j-th column, I j It is the product of the conductivity matrix and the voltage vector. This value is converted into voltage by the transimpedance amplifier and becomes the result of a calculation. In particular, the use of self-rectifying memristors for matrix-vector multiplication requires preprocessing of the input. V i It needs to be quantized once to x[i-1], and then input voltage according to each bit of data, input 1 / 2 times the read voltage for 0, and input 1 times the read voltage for 1. This calculation method makes full use of the high nonlinearity of the memristor and can achieve high-precision matrix-vector multiplication.

[0069] The above description is merely a preferred embodiment of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present specification shall be included in the scope of protection of one or more embodiments of the present specification.

Claims

1. A self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization, characterized in that: The self-rectifying ferroelectric memristor is a vertical structure of an upper electrode layer, a ferroelectric layer, and a semiconductor layer from top to bottom; a lower electrode layer is drawn out from the semiconductor layer; the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; and the contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer.

2. The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that: The out-of-plane polarization direction of the ferroelectric layer is perpendicular to both the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface. The two contact surfaces form an asymmetric potential barrier. The applied voltage can change the out-of-plane polarization state of the ferroelectric layer, thereby changing the barrier height of the two contact surfaces and changing the carrier transport characteristics of the semiconductor layer, thereby achieving the function of regulating the conductivity state of the memristor.

3. The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that: The self-rectifying ferroelectric memristor further includes an insulating layer for device isolation and / or substrate.

4. The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that: The electrode structure of the self-rectifying ferroelectric memristor is a sandwich structure, consisting of an upper electrode-ferroelectric layer and a semiconductor layer-lower electrode; the electrode material is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor or gallium indium alloy.

5. The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that: The material of the ferroelectric layer is two-dimensional CuInP2S6 or α-In2Se3.

6. The self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that: The semiconductor layer is a doping material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium or tellurium crystal.

7. A method for preparing a single device of the self-rectifying ferroelectric memristor according to any one of claims 1 to 6, characterized in that: The method includes preparing the interface structure between the ferroelectric layer and the semiconductor layer, and preparing electrodes respectively contacting the ferroelectric layer and the semiconductor layer. The specific steps are as follows: S1, forming an insulating layer on the semiconductor layer, patterning the insulating layer and removing the insulating layer to prepare a contact window between the semiconductor layer and the ferroelectric layer; S2, transferring the ferroelectric material to the contact window by a wet method or a dry method to form a ferroelectric layer; S3, preparing an upper electrode layer on the ferroelectric layer by patterning and deposition processes; S4, preparing a lower electrode layer on the semiconductor layer by using a patterning and deposition process or applying a gallium-indium alloy.

8. The preparation method according to claim 7, characterized in that: The semiconductor layer is silicon, the insulating layer is silicon oxide, the ferroelectric layer is copper indium phosphide, and the upper electrode layer is gold.

9. A method for preparing an array of the self-rectifying ferroelectric memristor according to any one of claims 1 to 6, characterized in that: The steps include: S1, fabricating discrete semiconductor layers on semiconductor / insulator using patterning and deep silicon etching techniques; S2, filling insulating materials between discrete semiconductor layers using a patterning process and a deposition process to form an inert insulating layer; S3, transferring ferroelectric layer materials on the insulating layer / semiconductor surface or preparing the ferroelectric layer by deposition method; S4, preparing an upper electrode layer on the ferroelectric layer by patterning and deposition processes; S5, leading out a lower electrode layer in a non-overlapping region of the semiconductor layer to form a device array.

10. The preparation method according to claim 9, characterized in that: The semiconductor in S1 is silicon, the insulator is silicon oxide, and the semiconductor / insulator is implemented by SOI silicon wafer; the inert insulating layer is aluminum oxide, the ferroelectric layer is copper indium phosphorus sulfur, and the upper electrode layer is gold.

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