In situ adsorbate formation for dielectric etch

Abstract

A method of processing a substrate, the method comprising: flowing an etch gas, O2, and an adsorbate precursor into a plasma processing chamber configured to hold the substrate comprising a silicon-containing dielectric layer and a patterned mask layer, the etch gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning the silicon-containing dielectric layer on the substrate with the plasma, wherein the adsorbate forms a sidewall passivation layer.

Description

[0001] Cross-references to related patents and applications

[0002] This application claims priority to and the benefit of the filing date of U.S. non-provisional patent application No. 17 / 937,179, filed on September 30, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates generally to methods of processing substrates and, in particular embodiments, to neutral adsorption enhancement via in-situ adsorbate formation for dielectric etching. Background Art

[0004] Typically, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning dielectric material layers, conductive material layers, and semiconductor material layers on a substrate to form a network of electronic components and interconnecting elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated into a monolithic structure. Many of the processing steps used to form the component structures of semiconductor devices are performed using plasma processes.

[0005] The semiconductor industry has repeatedly reduced the minimum feature size in semiconductor devices to a few nanometers to increase the packing density of components. As a result, the semiconductor industry increasingly requires plasma processing technology to provide a process for patterning features with accuracy, precision, and profile control, often at atomic-level dimensions. Facing this challenge and the consistency and repeatability required for high-volume IC manufacturing, further innovation in plasma processing technology is needed. Summary of the invention

[0006] According to an embodiment of the present invention, a method for processing a substrate includes: flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber, the plasma processing chamber being configured to fix the substrate including a silicon-containing dielectric layer and a patterned mask layer, the etching gas containing hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning the silicon-containing dielectric layer on the substrate with the plasma, wherein the adsorbate forms a sidewall passivation layer.

[0007] According to an embodiment of the present invention, a method for processing a substrate includes: flowing an etchant containing hydrogen and fluorine, O2, and an adsorbate precursor into a plasma processing chamber, the adsorbate precursor including PH3, B2H6, SixHy, H2S, or NH3; generating plasma in the plasma processing chamber while flowing the etchant, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate containing P, B, Si, S, or N; and forming a recess in a silicon-containing dielectric layer of the substrate by exposing the substrate to the plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess.

[0008] According to an embodiment of the present invention, a method for processing a substrate includes: depositing an organic layer on a silicon-containing dielectric layer of the substrate; patterning the organic layer by a halogen-free plasma etching process; and using the patterned organic layer as an etching mask to pattern the silicon-containing dielectric layer by a halogen-based plasma etching process, wherein the halogen-based plasma etching process includes generating a halogen-containing plasma from a gas mixture containing a halogen-containing etching gas in a plasma processing chamber, flowing O2 and an adsorbate precursor into the plasma processing chamber, wherein the adsorbate precursor includes PH3, B2H6, Si x H y , H2S or NH3, wherein the adsorbate precursor is oxidized under the halogen-containing plasma to form an adsorbate comprising P, B, Si, S or N, and a recess is formed in the silicon-containing dielectric layer of the substrate by exposing the substrate to the halogen-containing plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A-1C A cross-sectional view of a substrate during an example semiconductor manufacturing process including a plasma etching process for forming high aspect ratio (HAR) features on the substrate is shown according to various embodiments. Figure 1A An incoming substrate including a dielectric layer and a patterned hard mask layer is shown, Figure 1B shows a substrate during formation of HAR features by a plasma etching process, and Figure 1C shows the substrate after completing the plasma etching process;

[0011] Figure 2A-2B A cross-sectional view of a substrate during a plasma etching process is shown, wherein Figure 2AA substrate is shown wherein the etchant species causes lateral etching, and Figure 2B A substrate is shown in which a passivation layer prevents lateral etching;

[0012] Figures 3A-3C Schematic surface structures with various adsorbates on silicon oxide are shown. Figure 3A Demonstrated H3PO4 adsorption, Figure 3B exhibited HF adsorption, and Figure 3C HF-H3PO4 co-adsorption was demonstrated;

[0013] Figures 4A-4C A process flow chart of a semiconductor manufacturing method according to various embodiments is shown, the semiconductor manufacturing method including a plasma etching process for forming a HAR feature, wherein Figure 4A Demonstrates embodiments, Figure 4B Alternative embodiments are presented, and Figure 4C Yet another embodiment is presented; and

[0014] Figure 5 A plasma system for performing a semiconductor manufacturing process according to various embodiments is presented. DETAILED DESCRIPTION

[0015] The present application relates to the manufacture of semiconductor devices (e.g., integrated circuits including semiconductor devices), and more particularly to high-capacity three-dimensional (3D) memory devices, such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices. The manufacture of such devices may generally require conformal high aspect ratio (HAR) features (e.g., contact holes) to form circuit elements. Features with an aspect ratio (the ratio of the height of a feature to the width of a feature) higher than 50:1 are generally considered to be high aspect ratio features, and in some cases, manufacturing higher aspect ratios such as 100:1 may be desired for advanced 3D semiconductor devices. In such applications, HAR features can be formed in a dielectric layer (e.g., silicon oxide, silicon nitride, or oxide / nitride layer stack) with high fidelity by a highly anisotropic plasma etching process. However, conventional HAR etching methods can generally include dozens and sometimes hundreds of processing steps, which complicates process optimization and etching throughput. Therefore, a simple but effective HAR process may be desired. Embodiments of the present application disclose methods for manufacturing HAR features by plasma etching processes based on a combination of halogen-based etching chemistry and in-situ neutral adsorbate formation. These methods can advantageously enhance the etching rate by increasing the amount of neutrals in the plasma. In addition, the neutral adsorbate can also provide sidewall passivation, which improves the anisotropy of the plasma etching process. The inventors of the present disclosure also found that the co-adsorption of two types of adsorbates (e.g., HF and H3PO4) may be thermodynamically favorable, which can advantageously benefit the effects of neutrals on etching rate and sidewall passivation. Although some adsorbate materials (e.g., H2O) may require low temperatures (e.g., below -50°C) for effective sidewall passivation, these methods in various embodiments can be advantageously applied to in-situ adsorbate formation of materials (e.g., H3PO4) that do not require such low temperatures. Therefore, the methods disclosed in the present application can achieve new cost-effective HAR dielectric etching processes. In various embodiments, these methods achieve in-situ formation of non-volatile adsorbate species by flowing an adsorbate precursor (e.g., PH3) and an oxidant (e.g., O2) into a plasma processing chamber. In certain embodiments, other types of adsorbates containing other elements (e.g., B, S, Si, and / or N) may also be used.

[0016] In the following, reference Figures 1A-1C An exemplary plasma etch process for forming high aspect ratio (HAR) features is described according to various embodiments. Figure 2A-2B The effect of sidewall passivation by a passivation layer is described. Figures 3A-3C In the simulation, different adsorption modes are compared in terms of adsorption energies. Figures 4A-4C An example process flow diagram is shown in . Figure 5An example capacitively coupled plasma (CCP) system for performing semiconductor manufacturing processes according to various embodiments is provided. All drawings are for illustration purposes only and are not drawn to scale, including aspect ratios of features.

[0017] Figures 1A-1C A cross-sectional view of a substrate 100 is shown during an example semiconductor manufacturing process including a plasma etching process for forming HAR features on the substrate, according to various embodiments.

[0018] Figure 1A An incoming substrate 100 is shown, which includes a dielectric layer 110 and a patterned hard mask layer 120 .

[0019] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon on insulator (SOI) wafer. In some embodiments, the substrate may include a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate includes a heterogeneous layer, such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, and multilayer silicon on silicon or SOI substrate.

[0020] In various embodiments, substrate 100 is part of a semiconductor device and may have undergone multiple processing steps, such as following conventional processes. For example, a semiconductor structure may include substrate 100 in which various device regions are formed. At this stage, substrate 100 may include isolation regions such as shallow trench isolation (STI) regions and other regions formed therein.

[0021] A dielectric layer 110 may be formed on the substrate 100. In various embodiments, the dielectric layer 110 is a target layer to be patterned into one or more high aspect ratio (HAR) features. In some embodiments, the HAR features etched into the dielectric layer 110 may be contact holes, slits, or other suitable structures including grooves. In some embodiments, the dielectric layer 110 may be a silicon oxide layer. In alternative embodiments, the dielectric layer 110 may include silicon nitride, silicon oxynitride, or an O / N / O / N layer stack (a stack of oxides and nitrides). The dielectric layer 110 may be deposited using appropriate techniques such as vapor deposition (including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD)) and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. In one embodiment, the dielectric layer 110 has a thickness between 1 μm and 10 μm. In another embodiment, the dielectric layer 110 may include a layer stack, wherein each layer of the stack has a thickness between 50 nm and 2.5 μm.

[0022] Still reference Figure 1A, forming a patterned hard mask layer 120 on the dielectric layer 110. In various embodiments, the patterned hard mask layer 120 may include an amorphous carbon layer (ACL). In one or more embodiments, the patterned hard mask layer 120 may include spin-on carbon, tungsten carbide, boron carbide, or other suitable carbon-containing mask materials. The patterned hard mask layer 120 may be formed by first depositing a hard mask layer using, for example, an appropriate spin coating technique or vapor deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. The deposited hard mask layer may then be patterned using a photolithography process and an anisotropic etching process (e.g., using an oxygen-based etching chemistry). The relative thicknesses of the patterned hard mask layer 120 and the dielectric layer 110 may have any suitable relationship. For example, the patterned hard mask layer 120 can be thicker than the dielectric layer 110, thinner than the dielectric layer 110, or the same thickness as the dielectric layer 110. In some embodiments, the patterned hard mask layer 120 has a thickness between 1 μm and 4 μm. In one embodiment, the patterned hard mask layer 120 includes an amorphous carbon layer (ACL) and has a thickness of 2.5 μm and a critical dimension (CD) of 75 nm, but in other embodiments, the thickness and CD of the patterned hard mask layer 120 can each have any suitable value.

[0023] The patterned hard mask layer 120 and / or the dielectric layer 110 may be considered together as part of the substrate 100. In addition, the substrate 100 may further include other layers. For example, for the purpose of patterning the hard mask layer, there may be a three-layer structure including a photoresist layer, a SiON layer, and an optical planarization layer (OPL).

[0024] According to various embodiments, fabricating HAR features in the dielectric layer 110 may be performed by a plasma etching process using a gas combination. The process gas may include a halogen-containing etching gas, an oxidant (eg, O2), and an adsorbate precursor.

[0025] In various embodiments, the etching gas may contain hydrogen and fluorine, such as hydrogen fluoride (HF). HF species and / or other fluorine-containing species may serve as etchant species for etching the dielectric layer 110 .

[0026] In some embodiments, the HF in the process gas can be less than 70vol% of the total gas flow. In one or more embodiments, the HF in the process gas can be less than 50vol%, or less than 10% in another embodiment. Alternatively, the process gas may not contain HF. In some embodiments, the process gas may contain little or no HF, but HF may be formed in situ by the reaction between the fluorine-containing gas and the hydrogen-containing gas in the etching gas in the presence of plasma. In one embodiment, the process gas may include fluorocarbons and hydrogen-containing gases (e.g., CF4 and H2). In another embodiment, the process gas may include non-carbon fluorine-containing gases and hydrogen-containing gases (e.g., NF3 and H2, SF6 and H2, PF3 and H2, or PF5 and H2).

[0027] In various embodiments, the etching gas may include a combination of hydrofluorocarbons, hydrocarbons and fluorine-containing gases, or a combination of fluorocarbons and hydrogen-containing gases. In some embodiments, one or more fluorocarbons may be used as the main etching gas. For example, a saturated fluorocarbon, an unsaturated fluorocarbon, or a combination thereof may be included in the process gas. In the present disclosure, an unsaturated fluorocarbon refers to any compound containing carbon and fluorine having at least one carbon-carbon double bond (C=C bond) or triple bond (C≡C bond), and a saturated fluorocarbon refers to any compound containing carbon and fluorine without any C=C bond or C≡C bond. In some embodiments, the unsaturated fluorocarbon may include hexafluorobutadiene (C4F6), hexafluoro-2-butyne (C4F6), or hexafluorocyclobutene (C4F6), and the saturated fluorocarbon may include octafluoropropane (C3F8), perfluorobutane (C4F 10 ) or perfluoropentane (C5F 12 ). In various embodiments, other gases such as rare gases and / or balancers may also be added. For example, in some embodiments, argon (Ar) and molecular oxygen (O2) may be included as rare gases and balancers, respectively. In alternative embodiments, the gas combination may further include a third carbon fluoro compound. In one embodiment, the third carbon fluoro compound may be octafluorocyclobutane (C4F8), octafluoro-2-butene (C4F8), hexafluoropropylene (C3F6), carbon tetrafluoride (CF4) or trifluoromethane (CHF3). Although the above examples are mainly fluorine-based etching gases, other halogen-containing gases (e.g., BCl3, Cl2, and HBr) may also be used.

[0028] An adsorbate precursor and an oxidant (e.g., O2) may be included in the process gas so that under plasma conditions, an adsorbate may be formed in the plasma processing chamber via oxidation. In various embodiments, the adsorbate may include phosphorus. In one or more embodiments, the adsorbate formed in the plasma processing chamber may include phosphoric acid (H3PO4). The inventors of the present disclosure have found that H3PO4 can be an effective adsorbate for providing sidewall passivation. However, H3PO4 is non-volatile, and therefore it is not practical to transport it directly to the plasma processing chamber in the gas phase. In various embodiments, these methods transport adsorbate precursors to achieve in-situ formation of adsorbates in the plasma processing chamber. In-situ formation of adsorbates such as H3PO4 can overcome the problem of non-volatility. Therefore, the adsorbate precursor may include phosphorus. Examples of P-containing adsorbate precursors include PH3 and PCl3.

[0029] In other embodiments, the adsorbate may contain other elements such as B, S, Si and / or N, and the adsorbate precursor may contain these elements accordingly. In certain embodiments, the adsorbate precursor may include B2H6, Si x H y , H2S or NH3. Thus, the adsorbate formed in the plasma processing chamber may contain boric acid, silicic acid, sulfuric acid, nitric acid or similar acidic molecules containing B, S, Si and / or N. These acidic molecules may be exposed to to exhibit similar behavior to phosphoric acid (H3PO4) and thereby function as an effective adsorbate for sidewall passivation.

[0030] Furthermore, in various embodiments, these adsorbates can be primarily neutral species in the plasma system and are effective in surface modification / activation during plasma etching processes such as reactive ion etching (RIE). By increasing the amount of neutrals in the plasma, these methods can advantageously enhance the etch rate.

[0031] The inventors of the present disclosure have discovered that a specific additive gas combination of an oxidant (e.g., O2) and an adsorbate precursor that can be oxidized (e.g., PH3) may be critical to achieving in-situ adsorbate formation and thereby achieving effective sidewall passivation and etch rate enhancement. The presence of oxygen species in the presence of plasma enables and promotes the oxidation reaction of the adsorbate precursor. In certain embodiments, the plasma etching process may use a gas combination including an etching gas and an additive gas mixture including O2 and PH3. In addition, the inclusion of a hydrogen-containing gas (e.g., H2) may be beneficial in generating reactive ionic species in the plasma by promoting the dissociation of molecules (which can enhance the etching rate). Therefore, in another embodiment, the additive gas mixture may include O2, H2, and PH3. In yet another embodiment, the additive gas mixture may include O2, H2, and B2H6, O2, H2, and Si x H y , O2, H2 and H2S, O2, H2 and NH3, O2, H2 and CO2, or O2, H2 and CO. In certain embodiments, more than one type of adsorbate may be used. In one or more embodiments, in addition to adsorbates containing P, B, S, Si and / or N, additional adsorbates (e.g., H2O) may be formed in the plasma processing chamber.

[0032] All gases may flow continuously at a steady flow rate, or in certain embodiments, their flow rates may be individually varied during the plasma etching process. In addition, various gas pulsing schemes may be applied to these methods. For example, a portion of the process gas (e.g., O2 and adsorbate precursors) may be intermittently flowed into the plasma processing chamber with gas pulsing. Such gas pulsing may allow fine tuning of the adsorbate concentration in the plasma processing chamber and thereby the degree of passivation.

[0033] In some embodiments, the ratio of the flow rate of the halogen-containing etching gas (e.g., CF4) to the flow rate of the adsorbate precursor (e.g., PH3) can be between 100: 1 and 1: 1. In one or more embodiments, the ratio of the flow rates can be between 100: 1 and 10: 1, and in another embodiment between 100: 1 and 20: 1.

[0034] In certain embodiments, the ratio of the flow rate of the oxidant (e.g., O2) to the flow rate of the adsorbate precursor (e.g., PH3) can be between 100: 1 and 1: 1. In one or more embodiments, the ratio of the flow rates can be between 100: 1 and 10: 1, and in another embodiment between 100: 1 and 20: 1.

[0035] In some embodiments, the ratio of the flow rate of the halogen-containing etching gas to the flow rate of the oxidant (e.g., O2) can be between 100: 1 and 1: 1. In one or more embodiments, the ratio of the flow rates can be between 100: 1 and 10: 1, and in another embodiment between 100: 1 and 20: 1.

[0036] In various embodiments, the substrate temperature can be maintained above 0°C, such as between 0°C and 50°C, during the plasma etching process. In most methods using HF as the primary etching gas and / or using certain adsorbate species (e.g., HO), low temperature conditions (e.g., <0°C) may be required for sufficient etching performance, primarily because physical adsorption of HF may occur only at very low temperatures. Using novel adsorbate species instead of or in addition to HF, these methods can advantageously remove the low temperature requirement from the plasma etching process for HAR features in dielectric materials. Therefore, the etching rate can be improved by controlling the temperature over a wider range according to these methods.

[0037] Figure 1B The substrate 100 is shown during the formation of HAR features by a plasma etching process.

[0038] exist Figure 1B In the embodiment, a high aspect ratio (HAR) feature is formed as a recess 125 in the dielectric layer 110 by a plasma etching process. Figure 1B As shown, by the plasma etching process, the groove 125 can be formed straight and uniformly on the substrate 100 with almost no curvature. Curvature refers to the deviation of a completely straight groove from a purely anisotropic profile to a groove with an outward curvature. Curvature can generally occur near the top of the sidewall of the etching target (e.g., the dielectric layer 110) and may be caused by the turn of the incident ion trajectory of the ions used during the plasma etching process. The curvature can be eliminated or minimized by sidewall passivation in the groove 125. Such passivation can be achieved by a passivation layer 130 of an adsorbate substance. In one or more embodiments, the passivation layer 130 may also include a deposit of a polymer substance derived from a carbon-containing gas (e.g., a saturated and / or unsaturated fluorocarbon) in the etching gas.

[0039] Also in Figure 1BIn the example of , a sufficient etching rate enables the recess 125 to have a high aspect ratio in a short processing time compared to conventional HAR etching methods. Although not wishing to be bound by any theory, the presence of adsorbates at the etching front (e.g., the exposed top surface of the dielectric layer 110) can catalyze the reaction of the etchant (e.g., the F-containing species) with the dielectric layer 110, which thus increases the etching rate. At the same time, due to the good selectivity to the hard mask during the etching process, only a small portion of the hard mask may be consumed.

[0040] The groove 125 can be in any shape and structure, including a contact hole, a slit, or other suitable structures containing grooves that can be used for semiconductor device manufacturing. In various embodiments, the feature defined by the groove 125 has a critical dimension (CD) of 200nm or less. In some embodiments, the CD can be between 50nm and 200nm. For example, the feature can include a slit with a CD of about 150nm. In an alternative embodiment, the groove 125 can include a hole with a top opening having a diameter of 80nm or less.

[0041] Figure 1C The substrate 100 is shown after the plasma etching process is completed.

[0042] The plasma etching process is continued by etching through the entire thickness of the dielectric layer 110. Figure 1B The groove 125 shown in FIG. 1 may further expand and reach the top surface of the substrate 100, as shown in FIG. Figure 1C In addition to the hard mask, the plasma etching process according to various embodiments may provide good selectivity to silicon (Si). Therefore, the plasma etching may be selective to the substrate 100 including silicon, and the formation of the groove 125 may advantageously stop at the top surface of the substrate 100.

[0043] In various embodiments, RF pulses in the kHz range may be used to power the plasma. Using RF pulses can help produce high energy ions (>keV) in the plasma used for the plasma etching process while reducing the charging effect. The charging effect during the process is a phenomenon in which electrons accumulate charge on the insulating material (e.g., silicon oxide of the dielectric layer 110), generating a local electric field that may direct positive ions to the sidewalls and cause lateral etching. Therefore, fine-tuning the power conditions of the plasma etching process may also be important for minimizing the widening of the critical dimension (CD) of high aspect ratio (HAR) features. In some embodiments, a moderate duty cycle between 40% and 80% may be used. In one embodiment, a bias power of 18kW may be pulsed at a frequency of 5kHz with a duty cycle of 60%.

[0044] In some embodiments, the plasma etching process can be advantageously performed as a continuous process with a processing time of 60 min or less to form high aspect ratio (HAR) features with aspect ratios of 100: 1 or higher. In other embodiments, the plasma etching process can be applied as part of a cyclic plasma process including various steps (e.g., an etching step, a deposition step, a flash step, and a byproduct control step).

[0045] In various embodiments, process parameters may be selected to optimize the characteristics of high aspect ratio (HAR) features taking into account various factors including controlled deposition levels, selectivity to hard mask, sidewall passivation in HAR features, and good critical dimension uniformity (CDU). The process parameters may include gas selection, gas flow rate, pressure, temperature, processing time, and plasma conditions such as source power, bias power, RF pulse conditions.

[0046] Conventional processing may be followed by further processing, for example, by removing the patterned hard mask layer 120, followed by filling the recesses 125 with a conductive material to form HAR conductive features (e.g., contact plugs for a memory array). For example, the conductive material may be copper formed using electroplating. However, any suitable conductive material and deposition method may be used. A planarization process (e.g., chemical-mechanical planarization) may then be used to remove excess conductive material from the top surface of the dielectric layer 110.

[0047] Figure 2A-2B A cross-sectional view of the substrate 100 during a plasma etching process is shown. Figure 2A A substrate 100 is shown in which an etchant species causes lateral etching, and Figure 2B The substrate 100 is shown in which the passivation layer 130 prevents lateral etching. The structure of the substrate 100 can be similar to Figures 1A-1C are the same as those shown in , and therefore are not repeated.

[0048] exist Figure 2A , the substrate 100 is shown after a plasma etching process without passivation of the sidewalls of the groove 125. In this example, when the etchants 210 (e.g., F-containing species) in the plasma impinge on the sidewalls of the groove 125, they may cause lateral etching, which may then cause widening / bending of the groove 125. Since the extent of the lateral etching may vary at different depths of the groove 125, the sidewall of the groove 125 may not be straight. It may be tapered (e.g., Figure 2A As a result, the HAR features of the dielectric layer 110 may suffer from line twisting and / or pattern collapse. To avoid such problems, in various embodiments, sidewall passivation can be achieved and improved by adding a hydrogen-containing gas to the process gas.

[0049] exist Figure 2B , substrate 100 is shown after a plasma etching process with sidewall passivation of recess 125. Sidewall passivation can be achieved by forming a passivation layer 130 containing an adsorbate (e.g., H3PO4). Passivation layer 130 protects the sidewalls of recess 135 from etchant 210.

[0050] Figures 3A-3C Schematic surface structures with various adsorbates on silicon oxide are shown.

[0051] The inventors of the present disclosure have found through quasi-continuous density functional theory (QC-DFT) simulations that P-containing adsorbates may be advantageous in providing sidewall passivation in the absence of cryogenic conditions. In addition, a synergistic enhancement of adsorption energy is demonstrated for HF-H3PO4 co-adsorption. Figure 3A In this paper, the adsorption of H3PO4 on the hydrophilic surface of SiO2 is demonstrated, and the simulated adsorption energy (E ads ) is -0.8837eV. Figure 3B In this paper, the adsorption of HF onto the hydrophilic surface of SiO2 is demonstrated, and the simulated E 吸附 is -0.4920eV. Figure 3C In this paper, the adsorption of HF and H3PO4 onto the hydrophilic surface of SiO2 is demonstrated, and the simulated E 吸附 is -1.4519 eV. The results are summarized in Table 1. The E of the co-adsorbed simulation 吸附 (-1.4519 eV) is larger than the E of the two simulations of HF and H3PO4 吸附 The sum of HF and H3PO4 is -1.3757 eV, indicating a synergistic enhancement of the adsorption energy. This result demonstrates that the presence of HF or H3PO4 during the plasma etching process can advantageously enhance the adsorption of the second adsorbate type (H3PO4 or HF), respectively. Therefore, these methods can benefit from including both types of adsorbates to obtain better adsorbate effects (e.g., etch rate and / or sidewall passivation).

[0052] Table 1. Simulated adsorption energies on SiO2

[0053]

[0054] Figures 4A-4C Process flow diagrams of semiconductor manufacturing methods according to various embodiments are shown, which include a plasma etching process for forming HAR features on a substrate including a material layer. The process flow can follow the above-discussed figures (e.g., Figures 1A-1C ) and therefore will not be described again.

[0055] exist Figure 4AIn some embodiments, process flow 40 may begin by flowing an etching gas, molecular oxygen (O2), and an adsorbate precursor (e.g., PH3) into a plasma processing chamber (block 410). Next, a plasma may be generated in the plasma processing chamber (block 420), wherein the adsorbate precursor is oxidized to form an adsorbate (e.g., H3PO4). The plasma may then be used to perform a plasma etching process to pattern a silicon-containing dielectric layer of a substrate provided in the plasma processing chamber with the plasma (block 430, Figures 1A-1C ), where the adsorbate forms a sidewall passivation layer.

[0056] exist Figure 4B According to an alternative embodiment, process flow 42 may begin by making an etchant containing hydrogen and fluorine, molecular oxygen (O2), and a etchant containing PH3, B2H6, Si x H y , H2S, or NH3 (block 412). Next, a plasma may be generated in a plasma processing chamber while flowing an etchant, O2, and the adsorbate precursor, wherein the adsorbate precursor is oxidized to form an adsorbate containing P, B, Si, S, or N (block 422). Subsequently, the substrate may be exposed to the plasma to form a recess in the silicon-containing dielectric layer of the substrate, wherein the adsorbate forms a sidewall passivation layer in the recess (block 432, Figures 1A-1C ).

[0057] exist Figure 4C According to yet other embodiments, process flow 44 may begin by depositing an organic layer on a silicon-containing dielectric layer of a substrate (block 404), followed by patterning the organic layer using a halogen-free plasma etching process (block 406, Figure 1A Next, a halogen-based plasma etching process may be performed to pattern the silicon-containing dielectric layer using the patterned organic layer as an etching mask (block 424, Figure 1B-1C The halogen-based plasma etching process may begin by generating a halogen-containing plasma from a gas mixture containing a halogen-containing etching gas in a plasma processing chamber (block 426), followed by ionizing molecular oxygen (O2) and a gas mixture containing PH3, B2H6, Si x H y An adsorbate precursor of 200 Å, 100 Å, 200 Å, 100 Å, 200 Å, or 300 Å is flowed into a plasma processing chamber (block 428), wherein the adsorbate precursor is oxidized under a halogen-containing plasma to form an adsorbate containing P, B, Si, S, or N. Subsequently, the substrate may be exposed to the halogen-containing plasma in the plasma processing chamber to form a high aspect ratio (HAR) recess in the silicon-containing dielectric layer of the substrate (block 434), wherein the adsorbate forms a sidewall passivation layer in the recess.

[0058] Figure 5A plasma processing system 50 for performing a semiconductor manufacturing process is shown in accordance with various embodiments.

[0059] For demonstration purposes, Figure 5 The substrate 100 is shown placed on a substrate holder 554 (e.g., a circular electrostatic chuck (ESC)) near the bottom inside the plasma processing chamber 510. A heater / cooler 556 surrounding the substrate holder 554 may optionally be used to maintain the substrate 100 at a desired temperature. The temperature of the substrate 100 may be maintained by a temperature controller 540 connected to the substrate holder 554 and the heater / cooler 556. The ESC may be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that electrical connections can be made to the substrate holder 554.

[0060] like Figure 5 As shown, substrate support 554 can be a bottom electrode of plasma processing chamber 510. Figure 5 In the illustrative example in FIG. 5 , the substrate support 554 is connected to two RF bias power sources 570 and 580 through DC blocking capacitors 590 and 591. In some embodiments, the conductive circular plate near the top inside the plasma processing chamber 510 is the top electrode 552. Figure 5 , the top electrode 552 is connected to a DC power source 550 of the plasma processing system 50.

[0061] Gases may be introduced into the plasma processing chamber 510 via a gas delivery system 520. The gas delivery system 520 includes a plurality of gas flow controllers to control the flow of the plurality of gases into the chamber. Each of the gas flow controllers of the gas delivery system 520 may be assigned for each of the fluorocarbon, the noble gas, and / or the balance agent. In some embodiments, an optional center / edge distributor may be used to independently adjust the gas flow rates at the center and edge of the substrate 100.

[0062] RF bias power sources 570 and 580 may be used to supply continuous wave (CW) or pulsed RF power to sustain a plasma, such as plasma 560. Plasma 560, shown between top electrode 552 and bottom electrode (also substrate support 554), illustrates direct plasma generated near substrate 100 in plasma processing chamber 510 of plasma processing system 50. Etching may be performed by exposing substrate 100 to plasma 560 while powering substrate support 554 with RF bias power sources 570, 580 and optionally powering top electrode 552 with DC power source 550.

[0063] The configuration of the plasma processing system 50 described above is merely exemplary. In alternative embodiments, various alternative configurations may be used for the plasma processing system 50. For example, an inductively coupled plasma (ICP) may be used, wherein the RF source power is coupled to a planar coil on a top dielectric cover, a gas inlet and / or a gas outlet may be coupled to an upper wall, etc. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rate, and other plasma process parameters may be selected according to a corresponding process recipe. In some embodiments, the plasma processing system 50 may be a resonator such as a spiral resonator.

[0064] Although not described herein, embodiments of the present invention may also be applied to remote plasma systems as well as batch systems.For example, a substrate holder may be capable of supporting multiple wafers that rotate about a central axis as the multiple wafers pass through different plasma zones.

[0065] Example embodiments of the invention are summarized herein. Other embodiments are also apparent from the overall description and claims presented herein.

[0066] Example 1. A method for processing a substrate, the method comprising: flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber, the plasma processing chamber being configured to hold the substrate including a silicon-containing dielectric layer and a patterned mask layer, the etching gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning the silicon-containing dielectric layer on the substrate with the plasma, wherein the adsorbate forms a sidewall passivation layer.

[0067] Example 2. A method as described in Example 1, wherein the adsorbate comprises H3PO4, and wherein the adsorbate precursor comprises PH3.

[0068] Example 3. The method of one of examples 1 or 2, wherein the adsorbate comprises boron.

[0069] Example 4. The method of any one of examples 1 to 3, wherein the adsorbate comprises silicon.

[0070] Example 5. The method of any one of Examples 1 to 4, wherein the adsorbate comprises sulfur.

[0071] Example 6. The method of any one of Examples 1 to 5, wherein the adsorbate comprises nitrogen.

[0072] Example 7. The method of any one of Examples 1 to 6, wherein the etching gas does not contain HF.

[0073] Example 8. The method of any one of Examples 1 to 7, wherein the etching gas is a gas mixture comprising molecular hydrogen (H2) and a fluorocarbon.

[0074] Example 9. The method of any one of Examples 1 to 8, wherein the etching gas is a gas mixture comprising molecular hydrogen (H2) and NF3, H2 and SF6, H2 and PF3, or H2 and PF5.

[0075] Example 10. The method of any one of Examples 1 to 9, wherein the silicon-containing dielectric layer comprises silicon oxide or silicon nitride.

[0076] Example 11. The method of any one of Examples 1 to 10, wherein the ratio of the gas flow rate of O2 to the gas flow rate of the adsorbate precursor is between 100:1 and 1:1.

[0077] Example 12. The method of any one of Examples 1 to 11, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

[0078] Example 13. A method of processing a substrate, the method comprising: flowing an etchant comprising hydrogen and fluorine, O2, and an adsorbate precursor into a plasma processing chamber, the adsorbate precursor comprising PH3, B2H6, SixHy, H2S, or NH3; generating a plasma in the plasma processing chamber while flowing the etchant, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate comprising P, B, Si, S, or N; and forming a recess in a silicon-containing dielectric layer of the substrate by exposing the substrate to the plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess.

[0079] Example 14. The method of Example 13, wherein the substrate further comprises a patterned amorphous carbon layer (ACL) on the silicon-containing dielectric layer, the patterned ACL being an etch mask during the formation of the recess.

[0080] Example 15. The method of either of Examples 13 or 14, wherein the recess defines features having a critical dimension between 50 nm and 200 nm.

[0081] Example 16. The method of any one of Examples 13 to 15, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

[0082] Example 17. A method of processing a substrate, the method comprising: depositing an organic layer on a silicon-containing dielectric layer of the substrate; patterning the organic layer by a halogen-free plasma etching process; and patterning the silicon-containing dielectric layer by a halogen-based plasma etching process using the patterned organic layer as an etching mask, the halogen-based plasma etching process comprising generating a halogen-containing plasma from a gas mixture comprising a halogen-containing etching gas in a plasma processing chamber, flowing O2 and an adsorbate precursor into the plasma processing chamber, the adsorbate precursor comprising PH3, B2H6, Si x H y , H2S or NH3, wherein the adsorbate precursor is oxidized under the halogen-containing plasma to form an adsorbate comprising P, B, Si, S or N, and a recess is formed in the silicon-containing dielectric layer of the substrate by exposing the substrate to the halogen-containing plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess.

[0083] Example 18. The method of Example 17, wherein the halogen-containing plasma is a capacitively coupled plasma (CCP).

[0084] Example 19. The method of one of Examples 17 or 18, wherein flowing O2 and the adsorbate precursor comprises flowing O2 and the adsorbate precursor intermittently.

[0085] Example 20. The method of any one of Examples 17 to 19, further comprising maintaining the temperature of the substrate between 0° C. and 50° C. during the halogen-based plasma etching process.

[0086] Although the present invention has been described with reference to illustrative embodiments, it is not intended that this description be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art by reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, the method comprising: flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber configured to hold the substrate including the silicon-containing dielectric layer and the patterned mask layer, the etching gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and The silicon-containing dielectric layer on the substrate is patterned with the plasma, wherein the adsorbate forms a sidewall passivation layer.

2. The method of claim 1, wherein: The adsorbate comprises H3PO4, and wherein the adsorbate precursor comprises PH3.

3. The method of claim 1, wherein: The adsorbate comprises boron.

4. The method of claim 1, wherein: The adsorbate comprises silicon.

5. The method of claim 1, wherein: The adsorbate comprises sulfur.

6. The method of claim 1, wherein: The adsorbate comprises nitrogen.

7. The method of claim 1, wherein: The etching gas does not contain HF.

8. The method of claim 7, wherein: The etching gas is a gas mixture containing molecular hydrogen (H2) and fluorocarbons.

9. The method of claim 7, wherein: The etching gas is a gas mixture containing molecular hydrogen (H2) and NF3, H2 and SF6, H2 and PF3, or H2 and PF5.

10. The method of claim 1, wherein: The silicon-containing dielectric layer includes silicon oxide or silicon nitride.

11. The method of claim 1, wherein: The ratio of the gas flow rate of O2 to the gas flow rate of the adsorbate precursor is between 100:1 and 1:

1.

12. The method of claim 1, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

13. A method for processing a substrate, the method comprising: An etchant containing hydrogen and fluorine, O2, and an adsorbate precursor containing PH3, B2H6, Si x H y , H2S or NH3; generating a plasma in the plasma processing chamber while flowing the etchant, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate comprising P, B, Si, S, or N; and A recess is formed in a silicon-containing dielectric layer of the substrate by exposing the substrate to the plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess.

14. The method of claim 13, wherein: The substrate further includes a patterned amorphous carbon layer (ACL) on the silicon-containing dielectric layer, the patterned ACL being an etch mask during formation of the recess.

15. The method of claim 13, wherein: The recesses define features having critical dimensions between 50 nm and 200 nm.

16. The method of claim 13, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

17. A method for processing a substrate, the method comprising: depositing an organic layer on the silicon-containing dielectric layer of the substrate; patterning the organic layer by a halogen-free plasma etching process; and The silicon-containing dielectric layer is patterned using the patterned organic layer as an etch mask by a halogen-based plasma etch process, the halogen-based plasma etch process comprising generating a halogen-containing plasma from a gas mixture comprising a halogen-containing etch gas in a plasma processing chamber, O2 and an adsorbate precursor are flowed into the plasma processing chamber, wherein the adsorbate precursor comprises PH3, B2H6, Si x H y , H2S or NH3, wherein the adsorbate precursor is oxidized under the halogen-containing plasma to form an adsorbate comprising P, B, Si, S or N, and A recess is formed in the silicon-containing dielectric layer of the substrate by exposing the substrate to the halogen-containing plasma in the plasma processing chamber, the recess having an aspect ratio of at least 50:1, wherein the adsorbate forms a sidewall passivation layer in the recess.

18. The method of claim 17, wherein: The halogen-containing plasma is a capacitively coupled plasma (CCP).

19. The method of claim 17, wherein: Flowing O2 and the adsorbate precursor includes flowing O2 and the adsorbate precursor intermittently.

20. The method of claim 17, further comprising maintaining the temperature of the substrate between 0°C and 50°C during the halogen-based plasma etching process.

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