Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a substrate and a reinforcement pattern disposed on the substrate, in which the reinforcement pattern includes a first reinforcement portion extending on the substrate in a first horizontal direction, and a second reinforcement portion extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, the width of the first reinforcing portion is different from that of the second reinforcing portion.

Description

Technical Field

[0001] The present invention relates to a circuit board, and more particularly, to a circuit board having improved warpage characteristics and a semiconductor package including the same. Background Art

[0002] As the performance of electrical / electronic products advances, technologies for arranging a greater number of semiconductor devices on a semiconductor package substrate of limited size are being proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in achieving desired performance.

[0003] Therefore, a semiconductor package for mounting a plurality of semiconductor devices using a plurality of circuit boards has recently been provided. The semiconductor package has a structure in which a plurality of semiconductor devices are connected to each other in a horizontal direction and / or a vertical direction on a circuit board. Therefore, the semiconductor package has the advantages of effectively utilizing the mounting area of ​​the semiconductor device and transmitting a high-speed signal through a short signal transmission path between the semiconductor devices.

[0004] Due to these advantages, the semiconductor package as described above is widely used in mobile devices and the like.

[0005] In addition, as the number of semiconductor devices and / or the size of each semiconductor device increases with the trend toward high integration, or as functional portions of semiconductor devices are divided, semiconductor packaging applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers expands the concept to semiconductor chiplets.

[0006] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets becomes important, and thus, there is a trend to dispose an interposer between a circuit board of a semiconductor package and the semiconductor device.

[0007] The interposer may be used as a redistribution layer that gradually increases the width or depth of a circuit pattern from the semiconductor device to the semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chips or to interconnect the semiconductor device and the semiconductor package substrate, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package substrate, the semiconductor package substrate having a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.

[0008] The interposer may have an area greater than the total area of ​​the plurality of semiconductor devices and / or semiconductor chips to mount the plurality of semiconductor devices and / or semiconductor chips as a whole, or may be provided only in a portion for interconnection between the semiconductor devices and / or semiconductor chips. That is, the area of ​​the interposer may increase as the number of semiconductor devices and / or semiconductor chips increases, or the area of ​​the interposer may not increase. However, as the number of semiconductor devices and / or semiconductor chips increases, the area of ​​the circuit board of the semiconductor package tends to increase.

[0009] Therefore, as the area of ​​the semiconductor package increases, there is a problem that the semiconductor package warps more. In addition, as the number of semiconductor devices and / or semiconductor chips increases, heat generation becomes more serious, so there is a problem that heat dissipation characteristics must be further improved.

[0010] (Patent Document 1) KR 10-2016-0116838 A Summary of the invention

[0011] [Technical issues]

[0012] The embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board having improved warpage characteristics and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board having improved heat dissipation characteristics and a semiconductor package including the same.

[0015] In addition, the embodiment provides a semiconductor package having improved adhesion between a circuit board and a connection member.

[0016] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and those skilled in the art to which the proposed embodiments belong can clearly understand other technical problems not mentioned from the following description.

[0017] [Technical solution]

[0018] According to an embodiment, a circuit board includes a substrate and a reinforcement pattern arranged on the substrate, wherein the reinforcement pattern includes: a first reinforcement portion extending on the substrate in a first horizontal direction, and a second reinforcement portion extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, wherein a width of the first reinforcement portion is different from a width of the second reinforcement portion.

[0019] In addition, the width of the first reinforcement portion is the width of the first reinforcement portion in the second horizontal direction, and the width of the second reinforcement portion is the width of the second reinforcement portion in the first horizontal direction.

[0020] In addition, a width of the substrate in the first horizontal direction is different from a width of the substrate in the second horizontal direction.

[0021] In addition, a width of the substrate in the first horizontal direction is greater than a width of the substrate in the second horizontal direction.

[0022] In addition, the width of the first reinforcing portion in the second horizontal direction is in the range of 1.3 to 5 times the width of the second reinforcing portion in the first horizontal direction.

[0023] In addition, the width of the first reinforcing portion in the second horizontal direction is in the range of 50 μm to 90 μm.

[0024] In addition, the reinforcement pattern is provided on the substrate in a closed loop shape, and the first reinforcement portion is connected to the second reinforcement portion.

[0025] Meanwhile, a semiconductor package according to an embodiment includes a circuit board and a connection member disposed on the circuit board, wherein the circuit board includes an electrode layer connected to the connection member.

[0026] In addition, the electrode layer includes: a reinforcement electrode corresponding to the reinforcement pattern; and a signal electrode separated from the reinforcement electrode and electrically connected to the connection member.

[0027] In addition, the reinforcing electrode is a power line for supplying power to the connecting member.

[0028] In addition, the reinforcing electrode includes a plurality of reinforcing electrodes disposed in different layers, and the circuit board includes a through portion connecting the plurality of reinforcing electrodes.

[0029] In addition, the through portion includes: a first through portion vertically overlapping the first reinforcing portion; and a second through portion vertically overlapping the second reinforcing portion.

[0030] In addition, a width of the first through portion in the first horizontal direction is greater than a width of the first through portion in the second horizontal direction.

[0031] In addition, a width of the second through portion in the first horizontal direction is smaller than a width of the second through portion in the second horizontal direction.

[0032] In addition, the circuit board includes a first reinforcing electrode, the connection member includes a second reinforcing electrode, and the first reinforcing electrode and the second reinforcing electrode do not overlap in a vertical direction.

[0033] In addition, the circuit board includes a first reinforcing electrode and a first signal electrode, the connecting member includes a second reinforcing electrode and a second signal electrode, and the first reinforcing electrode and the second reinforcing electrode overlap in the vertical direction.

[0034] In addition, the semiconductor package includes: a first connection portion provided between the first reinforcement electrode and the second reinforcement electrode; and a second connection portion provided between the first signal electrode and the second signal electrode.

[0035] [Beneficial Effects]

[0036] The circuit board of the embodiment includes a substrate and a reinforcement pattern arranged on the substrate. The reinforcement pattern includes a first part arranged on the substrate in a first horizontal direction and a second part arranged in a second horizontal direction different from the first horizontal direction. At this time, the first part is arranged on the substrate to extend in the first horizontal direction. In addition, the second part is arranged on the substrate to extend in the second horizontal direction. At this time, the width of the first part in the second horizontal direction is different from the width of the second part in the first horizontal direction. That is, the embodiment allows the width of the first part arranged in the direction where a relatively large bend occurs in the circuit board to be greater than the width of the second part. For example, the width of the substrate in the first horizontal direction is greater than the width of the substrate in the second horizontal direction. In addition, the width of the first part of the reinforcement pattern is greater than the width of the second part. Therefore, the embodiment can more effectively prevent the bending of the circuit board by controlling the width of the reinforcement pattern. Therefore, the embodiment can improve the bending characteristics of the circuit board. In addition, the embodiment can improve the warping bending characteristics by controlling the width while minimizing the area of ​​the reinforcement pattern on the substrate. Therefore, the embodiment can minimize the circuit board area increased due to the reinforcement pattern.

[0037] In addition, the embodiment can improve the bonding characteristics between the circuit board and the connection member. Here, the connection member may be a separate external substrate bonded to the circuit board, or may be a semiconductor device.

[0038] Specifically, the connection portion is disposed between the circuit board and the connection member. At this time, when the circuit board is bent, there may be a problem that the connection portion is separated from the circuit board and / or the connection member. In addition, when the circuit board is bent, the position alignment between the circuit board and the connection member may deteriorate.

[0039] Different from this, the embodiment can improve the bonding force between the circuit board and the connecting member by improving the warpage characteristics of the circuit board. In addition, the embodiment can improve the alignment of the bonding position between the circuit board and the connecting member. Therefore, the embodiment can improve the physical characteristics and / or electrical characteristics of the semiconductor package.

[0040] Meanwhile, the reinforcing patterns of the embodiment are respectively arranged on different layers of the circuit board. In addition, the circuit board includes a reinforcing through portion connected between the reinforcing patterns arranged on different layers. The embodiment can further improve the warpage characteristics of the circuit board and the warpage characteristics of the semiconductor package by further arranging the reinforcing through portion.

[0041] Meanwhile, the reinforcing pattern is a reinforcing electrode, which is a part of an electrode layer provided on the circuit board. In addition, the reinforcing electrode may include a metal material. Thus, the embodiment can improve the warping characteristics of the circuit board by using the reinforcing pattern, while dissipating the heat generated in the circuit board to the outside. Thus, the embodiment can further improve the heat dissipation characteristics of the circuit board.

[0042] Furthermore, the semiconductor package of the embodiment includes a circuit board having a first reinforcement pattern and a connection member having a second reinforcement pattern.

[0043] At this time, the embodiment allows the first reinforcement pattern and the second reinforcement pattern to overlap in the vertical direction. Specifically, the semiconductor package includes a connecting portion arranged between the circuit board and the connecting member. In addition, the connecting portion includes a first connecting portion arranged between the first reinforcement pattern of the circuit board and the second reinforcement pattern of the connecting member. At this time, the embodiment uses the first connecting portion to connect the first reinforcement pattern of the circuit board and the second reinforcement pattern of the second circuit board. Therefore, the embodiment can further improve the bonding strength between the circuit board and the connecting member. In addition, the embodiment can transfer the heat generated from the circuit board to the connecting member or transfer the heat generated from the connecting member to the circuit board through the first connecting portion. Therefore, the embodiment can further improve the heat dissipation characteristics of the semiconductor package.

[0044] In addition, the first reinforcement pattern may be used as a power terminal to supply power from the circuit board to the connection member. Therefore, the embodiment may stably supply power to the connection member, thereby enabling the connection member to operate stably.

[0045] Specifically, the circuit board can provide sufficient power required to drive the connection member by providing a power signal to the connection member using a reinforcement pattern. Therefore, the embodiment can improve the driving characteristics of the connection member. That is, the embodiment can solve the problem of insufficient power provided to the connection member. That is, recently, the functions provided by the connection member have increased or the performance of the connection member has improved, so the driving power required for the connection member may increase. Therefore, the embodiment can provide a power signal to the connection member through the reinforcement pattern, thereby, the embodiment can further improve the electrical reliability of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a diagram showing a semiconductor package according to a comparative example.

[0047] Figure 2a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0048] Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0049] Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0050] Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0051] Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0052] Figure 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

[0053] Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0054] Figure 3 is a cross-sectional view showing a circuit board according to the first embodiment.

[0055] Figure 4 is a perspective view schematically showing a circuit board according to an embodiment.

[0056] Figure 5 is a plan view showing a reinforcement pattern according to an embodiment.

[0057] Figure 6 is a diagram showing a circuit board according to a second embodiment.

[0058] Figure 7 is a diagram showing a circuit board according to a third embodiment.

[0059] Figure 8 It is shown Figure 7 A plan view of a reinforcing electrode and a reinforcing through portion of a circuit board.

[0060] Figure 9a is a diagram illustrating a semiconductor package including a plurality of circuit boards according to an embodiment.

[0061] Figure 9b is a diagram illustrating a semiconductor package including a plurality of circuit boards according to another embodiment.

[0062] Fig.10 is a cross-sectional view showing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0063] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0064] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments, but may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and replaced within the spirit and scope of the present disclosure.

[0065] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure may be interpreted as having the same meaning as that generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and such terms as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0066] In the present specification, a singular form may also include a plural form unless specifically stated in a phrase, and when described in "at least one (or more) of A (and), B, and C", at least one of all combinations that can be combined in A, B, and C may be included. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0067] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "contacting" another element, it may include not only that the element is directly "connected", "coupled" or "contacting" the other element, but also that the element is "connected", "coupled" or "contacting" another element between the element and the other element.

[0068] In addition, when described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only two elements being directly connected to each other but also one or more other elements being formed or disposed between the two elements. In addition, when expressed as “on (above)” or “under (below)”, it may include not only an upper direction based on one element but also a lower direction.

[0069] Comparative example (structure and problems of prior art)

[0070] Figure 1 is a diagram showing a semiconductor package according to a comparative example.

[0071] refer to Figure 1 , the semiconductor package includes a plurality of components 10 and 20 which are electrically connected to each other via a connection portion 30 interposed therebetween.

[0072] In one embodiment, the plurality of components 10 and 20 may be a first circuit board and a second circuit board. In another embodiment, the plurality of components 10 and 20 may be a circuit board and a semiconductor device.

[0073] At this time, as the demand for high-performance semiconductor devices applied to semiconductor packages increases, the plane areas of the plurality of components 10 and 20 increase. In addition, there is a problem that the plurality of components 10 and 20 bend more as the plane areas increase.

[0074] For example, the semiconductor package includes a first component 10 and a second component 20 .

[0075] At this time, the first component 10 includes a plurality of first insulating layers and first electrode layers. At this time, there is a problem that the first component 10 bends in a specific direction depending on the type of insulating material forming the first insulating layer and the wiring density occupied by the electrode layer on the first insulating layer.

[0076] The semiconductor package electrically connects the second component 20 with the connection portion 30 provided on the first component 10 .

[0077] At this time, there is a problem that the first member 10 bends in a specific direction. In addition, there is a problem that the second member 20 bends in a specific direction.

[0078] Therefore, when the first member 10 and the second member 20 are each bent in a specific direction, there is a problem that at least a portion of the connection portion 30 is separated from the first member 10 or the second member 20 .

[0079] For example, Figure 1As shown, when at least one of the first component 10 and the second component 20 is bent in a specific direction, the connecting portion 30 includes a first connecting portion 31 normally connected between the first component 10 and the second component 20 and a second connecting portion 32 separated from at least one of the first component 10 and the second component 20.

[0080] In addition, when the connection portion 30 includes the second connection portion 32 , an electrical reliability problem may occur because the first component 10 and the second component 20 are not electrically connected to each other.

[0081] Furthermore, in the semiconductor package of the comparative example, as the plane area of ​​the first member 10 or the second member 20 increases, the heat generation of the first member 10 or the second member 20 becomes more serious.

[0082] That is, as the plane area of ​​the semiconductor package increases, there is a problem of more bending and a problem of requiring greater improvement in heat dissipation characteristics.

[0083] Therefore, the embodiment improves the warpage characteristics and heat dissipation characteristics of the semiconductor package, thereby further improving the product reliability of the semiconductor package.

[0084] Electronic devices

[0085] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0086] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor devices in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one semiconductor device. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), and the like, or a chipset including a specific combination of those listed so far.

[0087] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, and the like.

[0088] On the other hand, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0089] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0090] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various packaging structures including a circuit board described later. In addition, the circuit board in one embodiment may be a packaging substrate described below, and the circuit board in another embodiment may be an interposer described below.

[0091] Figure 2a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0092] refer to Figure 2a The semiconductor package according to the first embodiment may include a first circuit board 1100, a second circuit board 1200, and a semiconductor device 1300. At this time, one of the first circuit board 1100 and the second circuit board 1200 may be a main circuit board, and the other may be referred to as a connection member together with the semiconductor device 1300.

[0093] The first circuit board 1100 represents a package substrate.

[0094] For example, the first circuit board 1100 may provide a space coupled to at least one external circuit board. The external circuit board may refer to the second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board included in the electronic device coupled to the lower portion of the first circuit board 1100.

[0095] In addition, although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0096] The first circuit board 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a through portion passing through the at least one insulating layer.

[0097] The second circuit board 1200 is disposed on the first circuit board 1100 .

[0098] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is installed. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are installed. The second circuit board 1200 may electrically connect the first semiconductor device 1310, the second semiconductor device 1320 to the first circuit board 1100, and electrically connect the first semiconductor device 1310 to the second semiconductor device 1320. That is, the second circuit board 1200 may perform a horizontal connection function between a plurality of semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0099] Figure 2a It is shown that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0100] The second circuit board 1200 may be disposed between the at least one semiconductor device 1300 and the first circuit board 1100 .

[0101] In one embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 1100, and may have the functions of multiple logic chips. Having the function of a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of the current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. In addition, the active interposer may perform the functions of the corresponding logic chip while performing the signal transmission function between the second logic chip disposed thereon and the first circuit board 1100.

[0102] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may be used as a signal relay between the semiconductor device 1300 and the first circuit board 1100, and may have a passive device function such as a resistor, a capacitor, or an inductor. For example, due to 5G, the Internet of Things (IOT), the improvement of image quality, and the improvement of communication speed, the number of terminals of the semiconductor device 1300 is gradually increasing. That is, the number of terminals provided in the semiconductor device 1300 increases, thereby reducing the width of the terminal or the interval between the plurality of terminals. In this case, the first circuit board 1100 is connected to the main board of the electronic device. There is a problem that in order to make the electrodes provided on the first circuit board 1100 have a certain width and interval to be connected to the semiconductor device 1300 and the main board respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complicated. Therefore, in the first embodiment, the second circuit board 1200 is provided between the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having a fine width and interval corresponding to the terminals of the semiconductor device 1300.

[0103] The semiconductor device 1300 may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0104] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0105] For example, the semiconductor package includes a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 electrically connects the second circuit board 1200 to the first circuit board 1100 while coupling them.

[0106] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while coupling them.

[0107] The semiconductor package includes a third connection portion 1430 disposed on a lower surface of the first circuit board 1100. The third connection portion 1430 may electrically connect the first circuit board 1100 to the main board while coupling them.

[0108] At this time, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 may be electrically connected between the plurality of components by using at least one bonding method of wire bonding, solder bonding, and metal-to-metal direct bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 have a function of electrically connecting the plurality of components, when metal-to-metal direct bonding is used, the connection portion of the semiconductor package may be understood as an electrical connection portion, rather than solder or a wire.

[0109] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using a material containing at least one of Sn, Ag, and Cu. In addition, the metal-to-metal direct bonding method may refer to recrystallization by applying heat and pressure between multiple components in the absence of solder, wires, conductive adhesives, etc., and may refer to direct bonding between multiple components. In addition, the metal-to-metal direct bonding method may refer to a bonding method through the second connection portion 1420. In this case, the second connection portion 1420 may represent a metal layer formed between multiple components by recrystallization.

[0110] Specifically, the first connection part 1410, the second connection part 1420, and the third connection part 1430 may couple the plurality of components to each other by a thermocompression (TC) bonding method. TC bonding may refer to a method of directly coupling a plurality of components by applying heat and pressure to the first connection part 1410, the second connection part 1420, and the third connection part 1430.

[0111] In this case, at least one of the first circuit board 1100 and the second circuit board 1200 may include a protruding portion provided on the electrode on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are provided. The protruding portion may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0112] The protruding portion may be referred to as a bump. The protruding portion may also be referred to as a post. The protruding portion may also be referred to as a pillar. Preferably, the protruding portion may refer to an electrode on which a second connection portion 1420 for coupling with the semiconductor device 1300 is disposed among the electrodes of the second circuit board 1200. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between a plurality of second connection portions 1420 respectively connected to a plurality of terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermocompression bonding may be performed to reduce the volume of the second connection portion 1420, and in order to ensure diffusion prevention and alignment that can prevent the diffusion of an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protruding portion into the interposer and / or the circuit board, the protruding portion may be included in the electrode on which the second connection portion 1420 is placed of the second circuit board 1200.

[0113] At the same time, reference Figure 2b , the semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that a connecting member 1210 is disposed on a second circuit board 1200. The connecting member 1210 may be referred to as a bridging substrate. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may perform a function of electrically connecting a plurality of semiconductor devices horizontally to each other. For example, since the area of ​​a semiconductor device is generally too large, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device differ greatly in terms of the width or spacing of the circuit pattern, a buffering effect of the circuit pattern is required for electrical connection. The buffering effect may refer to a size between the width or spacing of the circuit pattern of the semiconductor package and the width or spacing of the circuit pattern of the semiconductor device, and the redistribution layer may include a function of performing a buffering effect.

[0114] In one embodiment, the connection member 1210 may be a silicon bridge. That is, the connection member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0115] In another embodiment, the connection member 1210 may be an organic bridge. For example, the connection member 1210 may include an organic material. For example, the connection member 1210 includes an organic substrate including an organic material instead of a silicon substrate.

[0116] The connection member 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connection member 1210 may be provided on the second circuit board 1200 to have a protruding structure.

[0117] In addition, the second circuit board 1200 may include a cavity, and the connection member 1210 may be disposed in the cavity of the second circuit board 1200 .

[0118] The connection member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200. In addition, in another sense, the connection member may represent a plurality of semiconductor devices, and may also refer to one of the first circuit board and the second circuit board.

[0119] refer to Figure 2c , the semiconductor package according to the third embodiment includes a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment has a structure in which the first circuit board 1100 is removed, compared with the semiconductor package of the second embodiment.

[0120] That is, the second circuit board 1200 of the third embodiment may be used as a package substrate while performing the interposer function.

[0121] The first connection portion 1410 disposed on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to a main board of the electronic device.

[0122] refer to Figure 2d , the semiconductor package according to the fourth embodiment includes a first circuit board 1100 and a semiconductor device 1300 .

[0123] In this case, the semiconductor package of the fourth embodiment has a structure in which the second circuit board 1200 is removed, compared with the semiconductor package of the second embodiment.

[0124] That is, the first circuit board 1100 of the fourth embodiment can be used as a packaging substrate, while also performing the function of connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 may include a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 may be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0125] refer to Figure 2e Compared with the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment further includes a third semiconductor device 1330 .

[0126] To this end, the fourth connection portion 1440 is provided at the lower surface of the first circuit board 1100 .

[0127] In addition, the third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.

[0128] In this case, the third semiconductor device 1330 may have a configuration in which Figure 2c The structure of the lower surface of the second circuit board 1200 in the semiconductor package.

[0129] refer to Figure 2f , the semiconductor package according to the sixth embodiment includes a first circuit board 1100 .

[0130] The first semiconductor device 1310 may be disposed on the first circuit board 1100 . To this end, the first connection portion 1410 is disposed between the first circuit board 1100 and the first semiconductor device 1310 .

[0131] In addition, the first circuit board 1100 includes a conductive coupling portion 1450. The conductive coupling portion 1450 may also protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump, or alternatively, may also be referred to as a column. The conductive coupling portion 1450 may be configured to have a structure protruding on an electrode disposed on the uppermost side of the first circuit board 1100.

[0132] The second semiconductor device 1320 may be disposed on the conductive coupling portion 1450. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450. In addition, the second connection portion 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0133] Therefore, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0134] That is, the second semiconductor device 1320 is connected to the first circuit board 1100 through the conductive coupling portion 1450 , and is also connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0135] In this case, the second semiconductor device 1320 may receive a power signal and / or electric power through the conductive coupling portion 1450. In addition, the second semiconductor device 1320 may transmit and receive communication signals to and from the first semiconductor device 1310 through the second connection portion 1420.

[0136] The semiconductor package according to the sixth embodiment provides a power signal and / or electric power to the second semiconductor device 1320 through the conductive coupling portion 1450 , thereby providing sufficient power to drive the second semiconductor device 1320 or being able to smoothly control power operation.

[0137] Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 1320. In addition, in the embodiment, at least one of the power signal, the electric power and the communication signal of the second semiconductor device 1320 is provided by different paths passing through the conductive coupling portion 1450 and the second connection portion 1420. Thus, the embodiment can solve the problem that the communication signal is lost due to the power signal. For example, the embodiment can minimize the mutual interference between the communication signal and the power signal.

[0138] Meanwhile, the second semiconductor device 1320 in the sixth embodiment may have a POP (Package on Package) structure in which a plurality of package substrates are stacked, and may be provided on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. In addition, the memory package may be coupled to the conductive coupling portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0139] refer to Figure 2g , the semiconductor package according to the seventh embodiment includes a first circuit board 1100 , a first connection portion 1410 , a first connection portion 1410 , a semiconductor device 1300 , and a third connection portion 1430 .

[0140] In this case, the semiconductor package of the seventh embodiment is different from the semiconductor package of the fourth embodiment in that the first circuit board 1100 includes a plurality of substrate layers, while the connection member 1110 is removed.

[0141] The first circuit board 1100 includes a plurality of circuit board layers. For example, the first circuit board 1100 may include a first circuit board layer 1100A corresponding to a package substrate and a second circuit board layer 1100B corresponding to a redistribution layer of a connection member.

[0142] That is, the semiconductor package of the seventh embodiment includes Figure 2aThe first circuit board (package substrate 1100) and the second circuit board (interposer 1200) disclosed in the seventh embodiment are formed integrally with the first circuit board layer 1100A and the second circuit board layer 1100B. The material of the insulating layer of the second circuit board layer 1100B may be different from the material of the insulating layer of the first circuit board layer 1100A. For example, the material of the insulating layer of the second circuit board layer 1100B may include a photocurable material. For example, the second circuit board layer 1100B may be a photoimageable dielectric (PID). In addition, since the second circuit board layer 1100B includes a photocurable material, the electrode can be miniaturized. Therefore, in the seventh embodiment, the second circuit board layer 1100B can be formed by sequentially stacking insulating layers of photocurable materials on the first circuit board layer 1100A and forming miniaturized electrodes on the insulating layers of photocurable materials. Therefore, the second circuit board layer 1100B may include a redistribution layer function including microelectrodes, and may include a function of horizontally connecting a plurality of semiconductor devices 1310 and 1320.

[0143] Before describing a circuit board of an embodiment, a circuit board described below may represent any one of a plurality of circuit boards included in a previous semiconductor package.

[0144] For example, in an embodiment, the circuit board described below may refer to Figure 2a to Figure 2g At least one of the first circuit board 1100 , the second circuit board 1200 , and the connecting member (or the bridge substrates 1110 and 1210 ) shown in any one of .

[0145] Figure 3 is a cross-sectional view showing a circuit board according to the first embodiment.

[0146] refer to Figure 3 , the circuit board 100 according to the first embodiment includes a first insulating layer 110 , a second insulating layer 150 , a third insulating layer 160 , an electrode layer 120 , a through portion 130 , and an insulating member 140 .

[0147] The first insulating layer 110 of the circuit board 100 may have a layer structure of at least one layer. Preferably, the first insulating layer 110 of the circuit board 100 may have a plurality of laminated structures. The laminated structures may be distinguished by the through-portion 130, and may be distinguished by the width difference between the through-portion 130 and the electrode layer 120. That is, the width of the lower surface of the electrode layer 120 may be greater than the width of the upper surface of the through-portion 130, and the laminated structures may be distinguished thereby. Through the above-mentioned laminated structure, the circuit board 100 of the embodiment may effectively electrically connect at least one semiconductor device and / or the second circuit board to the mainboard.

[0148] at this time, Figure 3The first insulating layer 110 of the circuit board 100 is shown as having a five-layer structure, but is not limited thereto. For example, the first insulating layer 110 of the circuit board 100 may have four or fewer layers, or may have six or more layers. The first insulating layer 110 may be referred to as a supporting substrate that supports the circuit board 100, and thus may be referred to as a "substrate".

[0149] In the case where the first insulating layer 110 of the circuit board 100 has a multi-layer structure, the plurality of first insulating layers of the circuit board 100 may include the same insulating material, but is not limited thereto. For example, at least one of the plurality of first insulating layers of the circuit board 100 may include an insulating material different from the insulating material of another first insulating layer.

[0150] The first insulating layer 110 of the circuit board 100 may be rigid or flexible. For example, the first insulating layer 110 of the circuit board 100 may include glass or plastic. For example, the first insulating layer 110 of the circuit board 100 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the first insulating layer 110 of the circuit board 100 may include strengthened or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the first insulating layer 110 of the circuit board 100 may include sapphire. For example, the first insulating layer 110 of the circuit board 100 may include an optically isotropic film. For example, the first insulating layer 110 of the circuit board 100 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the first insulating layer 110 of the circuit board 100 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 110 of the circuit board 100 may have a structure in which an inorganic filler of silicon oxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin.

[0151] The first insulating layer 110 may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0152] In one embodiment, the first insulating layer 110 may include a first layer corresponding to a core layer including a reinforcing member. In addition, the first insulating layer 110 may include a plurality of second layers respectively disposed at the upper and lower portions of the core layer and not including a reinforcing member. In this case, the circuit board 100 may be a core substrate. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0153] The reinforcing member may refer to a glass fiber material extending in the horizontal direction of the first insulating layer 110, and may have a different meaning from the inorganic fillers spaced apart from each other. That is, the reinforcing member of the first layer may have a different length or width from the filler of the second layer in the horizontal direction. For example, the glass fiber may extend to have a width greater than the width of the first layer. Here, the meaning of having a width greater than the width of the first layer may mean that the glass fiber may be arranged in a curved shape in the horizontal direction. In addition, even if the second layer includes a filler, the effect of preventing problems such as bending is not as great as that of the glass fiber of the first layer, so the reinforcing member is described separately from the filler of the second layer.

[0154] In another embodiment, the first insulating layer 110 of the circuit board 100 may be a coreless substrate that does not include a core. For example, the first insulating layer 110 of the circuit board 100 may include an organic material that does not include a reinforcing member, has excellent processability, can make the circuit board 100 thinner, and can miniaturize the electrode layer 120 of the circuit board 100. For example, the first insulating layer 110 of the circuit board 100 may use ABF (Ajinomoto stacked film) (a product issued by Ajinomoto Co., Ltd.) as an example, and the first insulating layer 110 of the circuit board 100 may use FR-4, BT (bismaleimide triazine), PID (photosensitive imageable dielectric resin), BT, etc. For example, the first insulating layer 110 may include a plurality of layers composed of ABF.

[0155] At this time, if the first insulating layer 110 of the circuit board 100 is composed only of ABF that does not include a reinforcing member, the warpage characteristics of the circuit board 100 may be deteriorated. Therefore, if the first insulating layer 110 of the circuit board 100 is composed of ABF (Ajinomoto deposited film), at least one ABF of the ABFs constituting the plurality of insulating layers of the circuit board 100 may include a reinforcing member that can improve the warpage characteristics.

[0156] For example, the first insulating layer 110 of the circuit board 100 includes a first layer composed of a first ABF including a resin and a filler. In addition, the first insulating layer 110 of the circuit board 100 includes a layer composed of a second ABF including a reinforcing member. At this time, the reinforcing member included in the second ABF may include a GCP (glass core primer) material, but is not limited thereto.

[0157] The layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member may have a thickness in the range of 10 μm to 40 μm. Preferably, the layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member may have a thickness in the range of 15 μm to 35 μm. More preferably, the layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member may have a thickness in the range of 18 μm to 32 μm. If the thickness of the layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member is less than 10 μm, the warpage characteristics of the circuit board 100 may be deteriorated. In addition, if the thickness of the layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member is less than 10 μm, the electrode layer 120 of the circuit board 100 cannot be stably protected, and thus electrical reliability may be reduced. In addition, if the thickness of the layer of the first insulating layer 110 of the circuit board 100 that does not include a reinforcement member exceeds 40 μm, the total thickness of the circuit board 100 increases, and thus, the thickness of the semiconductor package may increase. In addition, if the thickness of the layer of the first insulating layer 110 of the circuit board 100 excluding the reinforcement member exceeds 40 μm, it may be difficult to miniaturize the electrode layer 120 of the circuit board 100 .

[0158] The thickness may correspond to the vertical distance between electrode layers disposed on different layers. That is, the thickness may represent the length in the direction from the upper surface to the lower surface or from the lower surface to the upper surface of the circuit board 100, and may represent the length in the vertical direction. Here, the upper surface may represent the highest position in the vertical direction in each component, and the lower surface may represent the lowest position in the vertical direction in each component. In addition, the positions of the upper surface and the lower surface may be referred to as being relative to each other.

[0159] Meanwhile, the semiconductor package of the embodiment may include a second insulating layer 150 disposed on the upper surface of the circuit board 100. In addition, the semiconductor package may include a third insulating layer 160 disposed on the lower surface of the circuit board 100.

[0160] At this time, the upper surface of the circuit board 100 may refer to the upper surface of the first insulating layer 110, and more specifically, the upper surface of the circuit board 100 may refer to the upper surface of the first insulating layer disposed at the uppermost side among the plurality of first insulating layers. The lower surface of the circuit board 100 may refer to the lower surface of the first insulating layer 110, and more specifically, the lower surface of the circuit board 100 may refer to the lower surface of the first insulating layer disposed at the lowermost side among the plurality of first insulating layers.

[0161] The second insulating layer 150 and the third insulating layer 160 may have a function of protecting the upper and lower surfaces of the circuit board 100. Therefore, the second insulating layer 150 and the third insulating layer 160 may be functionally referred to as a first protective layer and a second protective layer, respectively.

[0162] The second insulating layer 150 and the third insulating layer 160 may be a resist layer. Preferably, the second insulating layer 150 and the third insulating layer 160 may be a solder resist layer including an organic polymer material. For example, the second insulating layer 150 and the third insulating layer 160 may include an epoxy acrylate resin. In detail, the second insulating layer 150 and the third insulating layer 160 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the second insulating layer 150 and the third insulating layer 160 may be any one of a photosensitive solder resist layer, a cover layer, and a polymer material.

[0163] For example, when the protrusion 123 and the semiconductor device are joined by solder, the solder and the solder resist layer do not have good mutual wettability, and thus, a problem of electrical short circuit between two adjacent protrusions among the plurality of protrusions 123 due to the solder can be prevented.

[0164] The thickness of each of the second insulating layer 150 and the third insulating layer 160 may be 1 μm to 20 μm. The thickness of each of the second insulating layer 150 and the third insulating layer 160 may be 1 μm to 15 μm. For example, the thickness of each of the second insulating layer 150 and the third insulating layer 160 may be 5 μm to 20 μm. In this case, the thickness of the second insulating layer 150 may represent a vertical distance from the upper surface of the electrode layer disposed at the uppermost side to the upper surface of the second insulating layer 150. In addition, the thickness of the third insulating layer 160 may represent a vertical distance from the lower surface of the electrode layer disposed at the lowermost side to the lower surface of the third insulating layer 160.

[0165] If the thickness of each of the second insulating layer 150 and the third insulating layer 160 exceeds 20 μm, it may be difficult to thin the semiconductor package due to an increase in the thickness of the semiconductor package, or stress applied to the insulating layer 110 disposed between the second insulating layer 150 and the third insulating layer 160 may increase. That is, stress may be applied to the circuit board 100. If the thickness of each of the second insulating layer 150 and the third insulating layer 160 is less than 1 μm, it may be difficult to stably protect the electrode layer 120 included in the circuit board 100, and thus electrical reliability or physical reliability may be deteriorated.

[0166] The circuit board 100 may include an electrode layer 120. The electrode layer 120 may be disposed on a surface of the first insulating layer 110 of the circuit board 100. For example, when the first insulating layer 110 of the circuit board 100 has a five-layer structure, the electrode layer 120 may be disposed on a surface of each of the five insulating layers.

[0167] At this time, one of the electrode layers 120 of the circuit board 100 may have an ETS (embedded trace substrate) structure. For example, the electrode layer disposed on the upper surface of the circuit board 100 may have an ETS structure. For example, the electrode layer disposed on the upper surface of the circuit board 100 may be disposed in a recessed portion of the upper surface of the first insulating layer 110 located at the top. The ETS structure may also be referred to as an embedded structure. Compared with an electrode layer having a general protruding structure, the ETS structure is conducive to miniaturization. Therefore, the embodiment enables the formation of electrodes corresponding to the size and pitch of the terminals disposed in the semiconductor device. Thus, the embodiment can improve the circuit integration. In addition, the embodiment can minimize the transmission distance of the signal transmitted through the semiconductor device, thereby minimizing the signal transmission loss.

[0168] The electrode layer 120 may include a reinforcing electrode 122 that is electrically and / or physically separated from the signal electrode 121. The reinforcing electrode 122 may represent a dummy electrode that is physically and / or electrically separated from the signal electrode 121. However, the embodiment is not limited thereto. The reinforcing electrode 122 may be electrically connected to the signal electrode 121, for example, may be connected to a ground electrode included in the signal electrode 121. In addition, the reinforcing electrode 122 may be used as a power supply electrode for supplying power to a connecting member connected to a circuit board. Thus, the embodiment may stably supply power to the connecting member, thereby allowing the connecting member to operate stably. Specifically, the circuit board may provide sufficient power required to drive the connecting member by providing a power signal to the connecting member using the reinforcing electrode 122. Therefore, the embodiment may improve the driving characteristics of the connecting member. That is, the embodiment may solve the problem of insufficient power provided to the connecting member. That is, recently, the functions provided by the connecting member have increased or the performance of the connecting member has improved, so the driving power required for the connecting member may increase. Therefore, the embodiment may provide a power signal to the connecting member through a reinforcing pattern, thereby, the embodiment may further improve the electrical reliability of the semiconductor package.

[0169] In addition, the reinforcing electrode 122 can transfer the heat generated from the circuit board 100 to the outside. Thus, the embodiment can improve the heat dissipation characteristics of the circuit board 100. For example, when the reinforcing electrode 122 is connected to the signal electrode 121, the heat can be transferred to the outside through the ground electrode. However, even if the reinforcing electrode 122 is physically and / or electrically separated from the signal electrode 121, the heat generated from the circuit board 100 can be transferred to the outside through the reinforcing electrode.

[0170] The reinforcing electrode 122 of the embodiment may be provided on the circuit board 100 to prevent physical deformation, such as bending, of the circuit board 100. The reinforcing electrode 122 may have a function of preventing the circuit board 100 from bending in a specific direction. In addition, the reinforcing electrode 122 may be used as a power line, so that power can be stably supplied to the connection member provided on the circuit board 100.

[0171] The specific structure of the reinforcing electrode 122 will be described in more detail below.

[0172] The circuit board of the embodiment includes a reinforcing electrode 122. This may also be referred to as a reinforcing member, which is used to prevent physical deformation of the circuit board. The reason why the reinforcing member is referred to as the reinforcing electrode 122 is because the reinforcing member is part of the electrode layer 120. However, the embodiment is not limited thereto. For example, the reinforcing member may include a material different from the electrode layer. For example, the reinforcing member may include an insulating material such as silicon or ceramic.

[0173] Meanwhile, the electrode layer 120 may include a protruding portion 123. The protruding portion 123 may protrude on the circuit board 100 in a direction away from the circuit board 100. The protruding portion 123 may be disposed on the signal electrode 121 of the electrode layer 120. The protruding portion 123 may be disposed to protrude upward on the signal electrode disposed at the uppermost side in the electrode layer 120. However, the embodiment is not limited thereto. For example, the protruding portion 123 may be disposed to protrude downward on the lower surface of the signal electrode disposed at the lowermost side in the electrode layer 120.

[0174] The protruding portion 123 may be referred to as a bump. The protruding portion 123 may also be referred to as a post. The protruding portion 123 may be referred to as a pillar. The semiconductor device may be disposed on the signal electrode 121 of the circuit board 100. In contrast, the interposer coupled to the semiconductor device may be bonded to the signal electrode 121 of the circuit board 100. At this time, as the pitch of the terminal of the semiconductor device or the electrode of the interposer becomes finer, the problem of short circuit of the conductive connection portion disposed on a plurality of terminals or electrodes may occur. Therefore, in order to reduce the volume of the conductive connection portion disposed on each of the plurality of terminals or electrodes, the signal electrode 121 may include a protruding portion 123. In addition, when using a TC (thermocompression) bonding that applies heat and pressure to the conductive connection portion disposed between the circuit board 100 and the semiconductor device or the interposer to bond them, the protruding portion 123 may have a function of improving the alignment between the signal electrode 121 and the terminal of the semiconductor device or the electrode of the interposer. In addition, the protruding portion 123 may have a function of preventing the conductive connection portion from spreading.

[0175] The electrode layer 120 of the circuit board 100 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the electrode layer 120 of the circuit board 100 may be formed of a paste or solder paste including at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the electrode layer 120 of the circuit board 100 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0176] The signal electrode 121 and the reinforcement electrode 122 of the electrode layer 120 may include the same metal material, but are not limited thereto. However, in order to simplify the manufacturing process of the circuit board 100, the signal electrode 121 and the reinforcement electrode 122 may include the same metal material.

[0177] The electrode layer 120 of the circuit board 100 may have a thickness in the range of 7 μm to 20 μm. For example, the electrode layer 120 of the circuit board 100 may have a thickness in the range of 9 μm to 17 μm. The electrode layer 120 of the circuit board 100 may have a thickness in the range of 10 μm to 13 μm. If the thickness of the electrode layer 120 of the circuit board 100 is less than 7 μm, the resistance of the electrode layer 120 may increase, and the allowable current of the transmittable signal may decrease. In addition, if the thickness of the electrode layer 120 of the circuit board 100 exceeds 20 μm, it may be difficult to miniaturize the electrode layer 120 and thin the circuit board 100.

[0178] The electrode layer 120 of the circuit board 100 may include a through pad connected to the through portion 130 of the circuit board 100 and at least one electrode pattern connected to an external circuit board or a semiconductor device. In addition, the electrode layer 120 of the circuit board 100 may include a trace of a signal transmission line connected to the through pad or the electrode pattern. The through pad or electrode pattern of the electrode layer 120 of the circuit board 100 may have a width in the range of 15 μm to 90 μm. The through pad or electrode pattern of the electrode layer 120 of the circuit board 100 may have a width in the range of 20 μm to 85 μm. The through pad or electrode pattern of the electrode layer 120 of the circuit board 100 may have a width in the range of 25 μm to 80 μm.

[0179] At this time, the through pads or electrode patterns of the electrode layer 120 of the circuit board 100 can have different widths within the above range according to the function. In addition, the electrodes of the electrode layer 120 of the circuit board 100 can have different widths corresponding to the size of the terminals of the connected semiconductor device or the size of the pads of the external circuit board.

[0180] Meanwhile, when the signal electrode 121 includes the protrusion 123, the width of the protrusion 123 may have a range of 40 μm to 70 μm. If the width of the protrusion 123 is less than 40 μm, the width of the protrusion 123 is too small and may cause a collapse problem during TC bonding. In addition, if the width of the protrusion 123 is greater than 70 μm, there may be a problem that it is difficult to correspond to the fine pitch of the terminal of the semiconductor device or the electrode of the interposer.

[0181] The electrode layer 120 may include a through portion 130. That is, the electrode layer includes the electrode layer 120 and the through portion 130, and the electrode layer 120 may have an electrode pattern. The width of the through portion 130 may be narrower than the width of a through pad having the same width as the through portion, and the lower surface of the through pad may be on the same plane as the lower surface of the electrode pattern.

[0182] The through portion 130 may pass through the first insulating layer 110 of the circuit board 100. The through portion 130 of the circuit board 100 may connect between electrode layers disposed on different insulating layers of the circuit board 100. The through portion 130 may have a function of vertically connecting between electrode layers disposed on different layers.

[0183] The thickness of the through portion 130 in the vertical direction may be greater than the thickness of the electrode layer 120 in the vertical direction. When the electrode layer 120 is embedded in the first insulating layer 110, the through portion 130 may pass through a region between electrode layers disposed in the first insulating layer. In addition, when the electrode layer protrudes from the upper and lower surfaces of the first insulating layer, the through portion 130 may pass through the insulating layer as a whole.

[0184] The through portion 130 of the circuit board 100 may be formed by filling the inside of a through hole passing through the first insulating layer 110 of the circuit board 100 with a conductive material.

[0185] The through hole can be formed by any of mechanical, laser and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling and routing can be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method can be used. In addition, when the through hole is formed by chemical processing, chemicals containing aminosilane, ketone, etc. can be used.

[0186] When forming the through hole, the inside of the through hole can be filled with a conductive material to form the through portion 130 of the circuit board 100. The metal material forming the through portion can be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd). In addition, the conductive material filling can utilize any one or a combination of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing.

[0187] Meanwhile, when the first insulating layer 110 includes a core layer, the through portion 130 passing through the core layer may include an insulating member 140. The insulating member 140 may be provided to fill a portion of the through hole passing through the core layer. The insulating member 140 may also be referred to as a hole blocking member. The insulating member 140 may include an insulating material disposed in the through hole of the core layer. For example, the insulating member 140 may include a paste of an insulating ink material. For example, the insulating member 140 may include blocking ink. However, embodiments are not limited thereto. For example, the insulating member 140 may include a conductive material. Specifically, the insulating member 140 may include a conductive paste containing a conductive metal powder.

[0188] Hereinafter, the reinforcement electrode 122 of the electrode layer 120 according to the first embodiment will be described in detail.

[0189] Figure 4 is a perspective view schematically showing a circuit board according to an embodiment, Figure 5 is a plan view showing a reinforcement pattern according to an embodiment.

[0190] refer to Figure 4 , the circuit board 100 may have a hexahedral shape. Therefore, the planar shape of the circuit board 100 may have a square shape. However, the embodiment is not limited thereto. For example, the planar shape of the circuit board 100 may have one of a circular shape, an elliptical shape, a triangular shape, and a polygonal shape. However, for ease of explanation, the planar shape of the circuit board 100 is described as having a square shape.

[0191] The planar shape of the circuit board 100 may be a rectangle. For example, a width W1 of the circuit board 100 in the first horizontal direction HD1 may be different from a width W2 of the circuit board 100 in the second horizontal direction HD2.

[0192] The first horizontal direction HD1 may indicate a width direction or an x-axis direction. Preferably, the first horizontal direction HD1 may indicate a long-axis direction having a relatively larger width than the second horizontal direction HD2 in the plane of the circuit board 100 .

[0193] The second horizontal direction HD2 may indicate a length direction or a y-axis direction. Preferably, the second horizontal direction HD2 may indicate a short-axis direction having a relatively smaller width than the first horizontal direction HD1 in the plane of the circuit board 100. The second horizontal direction HD2 may indicate a direction perpendicular to the first horizontal direction HD1.

[0194] The width W1 of the circuit board 100 in the first horizontal direction HD1 may be greater than the width W2 in the second horizontal direction HD2. The width W1 of the circuit board 100 in the first horizontal direction HD1 may be 1.3 times or more of the width W2 in the second horizontal direction HD2. Preferably, the width W1 of the circuit board 100 in the first horizontal direction HD1 may be 1.5 times or more of the width W2 in the second horizontal direction HD2. More preferably, the width W1 of the circuit board 100 in the first horizontal direction HD1 may be 1.8 times or more of the width W2 in the second horizontal direction HD2. For example, a plurality of semiconductor devices may be provided on the circuit board 100. For example, the semiconductor package may include two semiconductor devices arranged on the circuit board 100. At this time, the first horizontal direction HD1 may indicate a direction in which the two semiconductor devices are spaced apart. In addition, if the width W1 of the circuit board 100 in the first horizontal direction HD1 is less than 1.3 times of the width W2 in the second horizontal direction HD2, the space wasted meaninglessly in the structure provided with a plurality of semiconductor devices may increase, and thus the total area of ​​the circuit board 100 may increase. In addition, if the width W1 of the circuit board 100 in the first horizontal direction HD1 exceeds 5 times the width W2 in the second horizontal direction HD2, the spacing distance between the terminals of the plurality of semiconductor devices or between the electrodes of the interposer provided on the circuit board 100 may increase. In addition, if the spacing distance increases, the signal transmission distance may increase, and thus the signal transmission loss may increase. Therefore, the width W1 of the circuit board 100 in the first horizontal direction HD1 is set to have a range of 1.3 to 5 times the width W2 in the second horizontal direction HD2.

[0195] At the same time, reference Figure 5 , the electrode layer 120 may be disposed on the circuit board 100. Preferably, the signal electrode 121 and the reinforcement electrode 122 may be disposed on the first insulating layer 110 of the circuit board 100.

[0196] At this time, the reinforcing electrode 122 may be disposed in a peripheral region adjacent to the side surface of the circuit board 100 on the plane of the circuit board 100. For example, the reinforcing electrode 122 may be disposed along an outer region or edge region of the upper surface of the circuit board 100 adjacent to the side surface of the circuit board 100.

[0197] For example, the reinforcing electrode 122 may be disposed on the circuit board 100 in a closed loop shape along the peripheral direction of the circuit board 100. Thus, the embodiment may more effectively prevent the circuit board 100 from bending. Therefore, the embodiment may improve the electrical reliability and / or physical reliability of the circuit board 100.

[0198] However, the embodiment is not limited thereto. The reinforcement electrode 122 may have an open loop shape along the peripheral direction on the circuit board 100. In one embodiment, when the reinforcement electrode 122 has an open loop shape, the reinforcement electrode 122 may have an electrode pattern in which an open area is formed between one end and the other end. In another embodiment, when the reinforcement electrode 122 has an open loop shape, the reinforcement electrode 122 may include a plurality of electrode patterns spaced apart from each other.

[0199] The reinforcing electrode 122 may include a first electrode portion 122-1 disposed on the circuit board 100 in the first horizontal direction HD1. The first electrode portion 122-1 may be disposed on the circuit board 100 to extend in the first horizontal direction HD1. For example, the first electrode portion 122-1 of the reinforcing electrode 122 may be disposed on the circuit board 100 along the long axis direction of the circuit board 100.

[0200] The reinforcing electrode 122 may include a second electrode portion 122-2 disposed on the circuit board 100 in a second horizontal direction HD2 different from the first horizontal direction HD1. As described above, the second horizontal direction HD2 may be a direction perpendicular to the first horizontal direction HD1, but is not limited thereto. The second electrode portion 122-2 may be disposed on the circuit board 100 to extend in the second horizontal direction HD2. For example, the second electrode portion 122-2 of the reinforcing electrode 122 may be disposed on the circuit board 100 along the short axis direction of the circuit board 100.

[0201] The first electrode portion 122-1 and the second electrode portion 122-2 of the reinforcing electrode 122 may have an integral structure connected to each other, but are not limited thereto. For example, at least one opening region may be provided between the first electrode portion 122-1 and the second electrode portion 122-2. Therefore, a separation portion may be provided between the first electrode portion 122-1 and the second electrode portion 122-2.

[0202] A width W3 of the first electrode portion 122 - 1 of the reinforcement electrode 122 may be different from a width W4 of the second electrode portion 122 - 2 of the reinforcement electrode 122 .

[0203] When the width W1 of the first horizontal direction HD1 and the width W2 of the second horizontal direction HD2 of the circuit board 100 are different from each other, the stresses applied in the first horizontal direction HD1 and the second horizontal direction HD2 may be different from each other. Therefore, based on the magnitude of the applied stress, the width W3 of the first electrode portion 122-1 of the reinforcement electrode 122 and the width W4 of the second electrode portion 122-2 may be set differently. In the above embodiment, the width W1 of the first horizontal direction HD1 is greater than the width W2 of the second horizontal direction HD2, and therefore, the magnitude of the stress applied along the first horizontal direction HD1 is greater than the magnitude of the stress applied along the second horizontal direction HD2, and therefore, the width W3 of the first electrode portion 122-1 is set to be greater than the width W4 of the second electrode portion 122-2 of the reinforcement electrode 122. However, if the stress applied in the second horizontal direction is greater than the stress applied in the first horizontal direction, the width W3 of the first electrode portion 122-1 may be set to be smaller than the width W4 of the second electrode portion 122-2 of the reinforcement electrode 122 according to the magnitude of the stress.

[0204] In the present embodiment, preferably, the width W3 of the first electrode portion 122 - 1 may be greater than the width W4 of the second electrode portion 122 - 2 .

[0205] At this time, the width W3 of the first electrode portion 122-1 may represent the width of the first electrode portion 122-1 in the second horizontal direction HD2. In addition, the width W4 of the second electrode portion 122-2 may represent the width of the second electrode portion 122-2 in the first horizontal direction HD1.

[0206] At this time, the difference between the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 and the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1 may be determined based on the difference between the width W1 in the first horizontal direction HD1 and the width W2 in the second horizontal direction HD2 of the circuit board 100. For example, the difference between the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 and the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1 may be determined based on a stress difference applied in the first horizontal direction HD1 and the second horizontal direction HD2, which is changed due to the difference between the width W1 in the first horizontal direction HD1 and the width W2 in the second horizontal direction HD2.

[0207] At this time, the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 may have a range of 1.3 to 5 times the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1. Preferably, the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 may have a range of 1.5 to 4 times the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1. More preferably, the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 may have a range of 1.8 to 4 times the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1.

[0208] If the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 is less than 1.3 times the width W2 of the second electrode portion 122-2 in the first horizontal direction HD1, the effect of improving the warpage characteristics of the circuit board 100 caused by the reinforcement electrode 122 may not be significant. Specifically, the circuit board 100 may experience bending concentrated in a portion having a relatively large width in the first horizontal direction HD1 and the second horizontal direction HD2. Therefore, the embodiment allows the width W3 of the first electrode portion 122-1 of the reinforcement electrode 122 disposed in the first horizontal direction HD1 of the circuit board 100 to be greater than the width W4 of the second electrode portion 122-2. Therefore, the embodiment can further improve the warpage characteristics of the circuit board 100 while minimizing the area occupied by the reinforcement electrode 122 on the circuit board 100. In addition, if the width W3 of the first electrode portion 122-1 in the second horizontal direction HD2 exceeds 5 times the width W4 of the second electrode portion 122-2 in the first horizontal direction HD1, a problem that the area of ​​the circuit board 100 becomes larger due to the arrangement of the reinforcement electrode 122 may occur.

[0209] Specifically, the width W3 of the first electrode portion 122-1 may be in the range of 50 μm to 90 μm. Preferably, the width W3 of the first electrode portion 122-1 may be in the range of 55 μm to 85 μm. More preferably, the width W3 of the first electrode portion 122-1 may be in the range of 60 μm to 80 μm. If the width W3 of the first electrode portion 122-1 is less than 50 μm, the effect of improving the warpage characteristics of the circuit board 100 by the first electrode portion 122-1 may not be significant. If the width W3 of the first electrode portion 122-1 exceeds 90 μm, the area occupied by the reinforcing electrode 122 on the circuit board increases, which may increase stress, and the unnecessary area where the semiconductor device is not installed may increase, which may waste cost and material.

[0210] Figure 6 is a diagram showing a circuit board according to a second embodiment, Figure 7 is a diagram showing a circuit board according to a third embodiment, Figure 8It is shown Figure 7 A plan view of a reinforcing electrode and a reinforcing through portion of a circuit board.

[0211] refer to Figure 6 , the circuit board according to the second embodiment may include a first insulating layer 110, an electrode layer 120, a through portion 130, an insulating member 140, a second insulating layer 150, and a third insulating layer 160. At this time, the electrode layer 120 may include a signal electrode 121 and a reinforcing electrode 122. In addition, the reinforcing electrode 122 may be provided on at least two layers of the plurality of layers constituting the first insulating layer 110. Thus, the embodiment can further prevent the circuit board 100 from bending in a specific direction.

[0212] Although not shown, the reinforcing electrodes 122 disposed on the plurality of layers may overlap each other vertically and may include non-overlapping portions. Depending on the magnitude of the stress and the direction in which the stress is applied, the reinforcing electrodes 122 disposed in each of the plurality of layers may have a structure that overlaps in the vertical direction, thereby having the effect of an overall thicker structure. In addition, in the case of having non-overlapping portions, the reinforcing electrodes 122 may be arranged to have an opening that is wider in width toward the circuit board 100. By arranging a wider reinforcing electrode 122 toward the circuit board 100, the effect of gradually reducing the magnitude of the stress applied in the direction toward the semiconductor device may be provided, so that the stress applied to the semiconductor package gradually decreases toward the semiconductor device. Therefore, the difference in stress applied to each of the plurality of layers constituting the first insulating layer 110 may be controlled not to become too large, thereby improving the electrical reliability and physical reliability of the semiconductor device package.

[0213] The reinforcing electrode 122 may have the same thickness as the signal electrode 121, and when the stress is large, the thickness of the reinforcing electrode 122 may be thicker than that of the signal electrode 121. That is, it may be freely set according to the size of the circuit board and the magnitude of the stress.

[0214] refer to Figure 7 and Figure 8 , the circuit board according to the third embodiment is different from the circuit board of the second embodiment in that it further includes a reinforcing through portion.

[0215] For example, the circuit board according to the first and second embodiments includes the through portion 130. At this time, the through portion 130 includes only the signal through portion of the signal electrode 121 connected to the electrode layer 120 in the circuit board.

[0216] Different from this, the circuit board of the third embodiment includes a through electrode 130. The through electrode 130 includes a first through portion 131 connected to the signal electrode 121. In addition, the through electrode 130 of the circuit board of the third embodiment may include a second through portion 132.

[0217] The first through-portion 131 may be connected to the signal electrode 121 of the electrode layer 120 .

[0218] In addition, the second through-portion 132 may be connected to the reinforcing electrode 122. For example, the second through-portion 132 may be connected between a plurality of reinforcing electrodes 122 disposed in different layers of the circuit board 100.

[0219] The second through-portion 132 can more effectively prevent the circuit board 100 from bending by passing through the first insulating layer 110. In addition, the second through-portion 132 can transfer heat between the reinforcing electrodes 122 by connecting between the plurality of reinforcing electrodes 122. Thus, the embodiment can dissipate the heat generated in the circuit board 100 by using the second through-portion 132, thereby improving the heat dissipation characteristics of the circuit board 100. In addition, the reinforcing electrode 122 can be used as a power supply electrode for supplying power to the connecting member connected to the circuit board. Thus, the embodiment can stably supply power to the connecting member, so that the connecting member can operate stably. Specifically, the circuit board can provide sufficient power required to drive the connecting member by providing a power signal to the connecting member using the reinforcing electrode 122. Therefore, the embodiment can improve the driving characteristics of the connecting member. That is, the embodiment can solve the problem of insufficient power provided to the connecting member. That is, recently, the functions provided by the connecting member have been increased or the performance of the connecting member has been improved, so that the driving power required for the connecting member may increase. Therefore, the embodiment can provide a power signal to the connecting member through the reinforcing pattern, thereby further improving the electrical reliability of the semiconductor package.

[0220] Meanwhile, the second through portion 132 may be divided into a plurality of parts.

[0221] For example, the second through-portion 132 may include a first through-portion 132 - 1 .

[0222] The first through portion 132-1 may vertically overlap a portion of the reinforcing electrode 122. Preferably, the first through portion 132-1 may vertically overlap a first electrode portion 122-1 of the reinforcing electrode 122. More preferably, the first through portion 132-1 may be connected to the first electrode portion 122-1 of the reinforcing electrode 122.

[0223] The width W5 of the first through portion 132-1 in the second horizontal direction HD2 may be different from the width W6 of the first through portion 132-1 in the first horizontal direction HD1. For example, the planar shape of the first through portion 132-1 may have an elliptical shape or a rectangular shape, in which the width W5 in the second horizontal direction HD2 is greater than the width W6 in the first horizontal direction HD1. Therefore, the embodiment can prevent the bending of the first circuit board 100 having a relatively large width in the first horizontal direction HD1 by the first through portion 132-1.

[0224] The second through portion 132-2 may vertically overlap a portion of the reinforcement electrode 122. Preferably, the second through portion 132-2 may vertically overlap a second electrode portion 122-2 of the reinforcement electrode 122. More preferably, the second through portion 132-2 may be connected to the second electrode portion 122-2 of the reinforcement electrode 122.

[0225] The width W7 of the second through portion 132-2 in the second horizontal direction HD2 may be different from the width W8 of the second through portion 132-2 in the first horizontal direction HD1. For example, the planar shape of the second through portion 132-2 may have an elliptical shape or a rectangular shape, wherein the width W7 of the second horizontal direction HD2 is smaller than the width W8 of the first horizontal direction HD1.

[0226] Figure 9a is a diagram showing a semiconductor package including a plurality of circuit boards according to an embodiment, Figure 9b is a diagram showing a semiconductor package including a plurality of circuit boards according to another embodiment, Fig.10 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0227] refer to Figure 9a According to an embodiment of the present invention, a semiconductor package may include a first circuit board 100A and a second circuit board 100B. The first circuit board 100A and the second circuit board 100B may represent Figure 2a The first circuit board 1100 and the second circuit board 1200 are shown, but are not limited thereto.

[0228] At this time, the first circuit board 100A and the second circuit board 100B may each have a structure corresponding to the circuit board 100 described in the previous drawings.

[0229] However, the first circuit board 100A may represent a package substrate. In addition, the second circuit board 100B may represent an interposer disposed on the package substrate. Therefore, the total plane area of ​​the first circuit board 100A may be greater than the total plane area of ​​the second circuit board 100B. At this time, the first circuit board 100A may be referred to as a main circuit board of the semiconductor package, and for the convenience of explaining the second circuit board 100B, it may be referred to as a connecting member connected to the first circuit board.

[0230] The first circuit board 100A includes a first reinforcing electrode 122A. In addition, the second circuit board 100B includes a second reinforcing electrode 122B.

[0231] In one embodiment, the first reinforcing electrode 122A of the first circuit board 100A and the second reinforcing electrode 122B of the second circuit board 100B may not overlap each other in the vertical direction. Therefore, in the above exemplary embodiment, the first reinforcing electrode 122A of the first circuit board 100A and the second reinforcing electrode 122B of the second circuit board 100B are prevented from overlapping each other vertically, so that the area occupied by the first reinforcing electrode 122A and the second reinforcing electrode 122B is minimized, and the warpage characteristics of the semiconductor package including the first circuit board 100A and the second circuit board 100B are improved as a whole. In addition, the reinforcing electrodes 122A and 122B can be used as power supply electrodes for supplying power to the connecting member connected to the circuit board. Thus, the embodiment can stably supply power to the connecting member, thereby allowing the connecting member to operate stably. Specifically, the circuit board can provide sufficient power required to drive the connecting member by providing a power signal to the connecting member using the reinforcing electrode 122. Therefore, the embodiment can improve the driving characteristics of the connecting member. That is, the embodiment can solve the problem of insufficient power provided to the connecting member. That is, recently, the functions provided by the connecting member have increased or the performance of the connecting member has improved, so the driving power required for the connecting member may increase. Therefore, embodiments may provide a power signal to a connection member through a reinforcement pattern, whereby embodiments may further improve electrical reliability of a semiconductor package.

[0232] refer to Figure 9b In another embodiment, the first circuit board 100A1 may include a plurality of reinforcing electrodes. For example, the first circuit board 100A1 may include a first reinforcing electrode 122A1 disposed above the first circuit board 100A1 and a second reinforcing electrode 122A2 disposed below the first circuit board 100A1.

[0233] The second circuit board 100B1 may include a plurality of reinforcing electrodes. For example, the second circuit board 100B1 may include a first reinforcing electrode 122B1 disposed above the second circuit board 100B1 and a second reinforcing electrode 122B2 disposed below the second circuit board 100B1. Thus, the embodiment can minimize the physical deformation of the circuit board and further minimize the physical deformation of the semiconductor package.

[0234] At the same time, reference Fig.10 , the first reinforcing electrode 122A of the first circuit board 100A and the second reinforcing electrode 122B of the second circuit board 100B may overlap each other in the vertical direction. In this case, the first reinforcing electrode 122A of the first circuit board 100A may be connected to the second reinforcing electrode 122B of the second circuit board 100B. The connection between the first reinforcing electrode 122A and the second reinforcing electrode 122B may include an electrical connection or a physical connection between the first reinforcing electrode 122A and the second reinforcing electrode 122B.

[0235] The first reinforcing electrode 122A may be disposed on the upper surface of the first circuit board 100A. At this time, the first reinforcing electrode 122A may include a portion embedded in the first circuit board 100A and a portion protruding from the embedded portion toward the second circuit board 100B.

[0236] In addition, the first circuit board 100A may include a first signal electrode 121A spaced apart from the first reinforcement electrode 122A. The first signal electrode 121A may also include an embedded portion and a protruding portion corresponding to the first reinforcement electrode 122A.

[0237] In addition, the second reinforcement electrode 122B may be provided on the lower surface of the second circuit board 100B. At this time, the second reinforcement electrode 122B may include a portion embedded in the lower surface of the second circuit board 100B and a portion protruding from the embedded portion toward the first circuit board 100A. In addition, the second circuit board 100B may include a second signal electrode 121B spaced apart from the second reinforcement electrode 122B. The second signal electrode 121B may also include an embedded portion and a protruding portion corresponding to the second reinforcement electrode 122B.

[0238] At this time, the connection portion may be provided between the first circuit board 100A and the second circuit board 100B.

[0239] The connection portion may include a first connection portion 300A disposed between the first signal electrode 121A of the first circuit board 100A and the second signal electrode 121B of the second circuit board 100B. The first connection portion 300A may electrically connect the first signal electrode 121A of the first circuit board 100A and the second signal electrode 121B of the second circuit board 100B.

[0240] In addition, the connection portion may include a second connection portion 300B disposed between the first reinforcement electrode 122A of the first circuit board 100A and the second reinforcement electrode 122B of the second circuit board 100B. The second connection portion 300B may couple the first reinforcement electrode 122A of the first circuit board 100A and the second reinforcement electrode 122B of the second circuit board 100B to each other. Thus, the embodiment may further enhance the bonding force between the first circuit board 100A and the second circuit board 100B by arranging the second connection portion 300B coupling the first reinforcement electrode 122A and the second reinforcement electrode 122B. Thus, the embodiment may further enhance the physical reliability and / or electrical reliability of the semiconductor package.

[0241] In addition, the embodiment can dissipate heat generated in the first circuit board 100A through the second circuit board 100B via the second connection portion 300B, or can dissipate heat generated in the second circuit board 100B through the first circuit board 100A. Thus, the embodiment can further improve the heat dissipation characteristics of the semiconductor package.

[0242] On the other hand, when the semiconductor package having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, the semiconductor package having the features of the present invention can be used to safely protect the semiconductor device from external moisture or contaminants, or alternatively, the problems of leakage current, electrical short circuit and electrical open circuit of the terminals provided to the semiconductor device can be solved. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the semiconductor package having the above-mentioned features of the present invention can maintain the stable function of the IT equipment or household appliances, so that the entire product and the semiconductor package to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0243] When the semiconductor package having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by safely protecting the semiconductor device controlling the transportation device from the outside and solving the problem of leakage current or electrical short circuit between terminals provided to the semiconductor device or electrical open circuit of the terminals. Therefore, the transportation device and the semiconductor package to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0244] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combination and such modification are included within the scope of the embodiments.

[0245] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: substrate; as well as a reinforcement pattern, the reinforcement pattern being arranged on the substrate, Wherein, the reinforcement pattern comprises: a first reinforcing portion extending on the substrate in a first horizontal direction, and a second reinforcing portion, the second reinforcing portion extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, Wherein, a width of the first reinforcement portion is different from a width of the second reinforcement portion.

2. The circuit board according to claim 1, wherein: The width of the first reinforcement portion is the width of the first reinforcement portion in the second horizontal direction, The width of the second reinforcement portion is the width of the second reinforcement portion in the first horizontal direction.

3. The circuit board according to claim 1 or 2, wherein: A width of the substrate in the first horizontal direction is different from a width of the substrate in the second horizontal direction.

4. The circuit board according to claim 3, wherein: A width of the substrate in the first horizontal direction is greater than a width of the substrate in the second horizontal direction.

5. The circuit board according to claim 3, wherein: The width of the first reinforcing portion in the second horizontal direction is in the range of 1.3 to 5 times the width of the second reinforcing portion in the first horizontal direction.

6. The circuit board according to claim 5, wherein: The width of the first reinforcing portion in the second horizontal direction is in the range of 50 μm to 90 μm.

7. The circuit board according to claim 3, wherein: The reinforcing pattern is disposed on the substrate in a closed loop shape, Wherein, the first reinforcement portion is connected to the second reinforcement portion.

8. A semiconductor package, comprising: The circuit board according to any one of claims 1 to 7; as well as a connecting member, the connecting member being arranged on the circuit board, Wherein, the circuit board includes an electrode layer connected to the connecting member.

9. The semiconductor package according to claim 8, wherein: The electrode layer comprises: a reinforcement electrode, the reinforcement electrode corresponding to the reinforcement pattern; and A signal electrode is separated from the reinforcing electrode and is electrically connected to the connection member.

10. The semiconductor package according to claim 9, wherein The reinforcing electrode is a power line for supplying power to the connecting member.

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