Communication device and signal sampling method

Abstract

The invention discloses a communication device and a signal sampling method. The communication device comprises a clock control circuit, a data sampling circuit and a clock recovery circuit. Wherein the clock control circuit is used for determining the sampling clock deviation of the data sampling circuit and generating a first clock control signal according to the sampling clock deviation, and the first clock control signal is used for adjusting the sampling clock of the data sampling circuit. The clock recovery circuit is used for adjusting a sampling clock of the data sampling circuit according to the first clock control signal and sending a clock signal to the data sampling circuit. The data sampling circuit is used for sampling an input analog signal according to a clock signal. Through the communication device, the sampling clock of the data sampling circuit can be locked at the optimal sampling time, and the sampled digital signal can keep useful information of the original analog signal without oversampling the original analog signal. In addition, the complexity of the data sampling circuit is not increased even in a large-bandwidth scene.

Description

Communication device and signal sampling method Technical Field

[0001] The present application relates to the field of clock synchronization technology, and in particular to a communication device and a signal sampling method. Background Art

[0002] In digital communications, analog signals are converted to digital signals for processing using an analog-to-digital converter (ADC). In order for the digital signal to retain all the information in the original analog signal, the ADC's sampling frequency must theoretically be greater than or equal to twice the bandwidth occupied by the original analog signal. Sampling clock recovery is then performed in the digital domain to determine the optimal sampling time. Channel transmission delays and clock skew between the transmitter and receiver can prevent the ADC from sampling at the optimal time, resulting in deviations between the collected data and the original data. Therefore, clock synchronization is necessary.

[0003] Currently, commonly used clock synchronization methods include the Gardner algorithm and overhead-assisted synchronization methods. The Gardner algorithm essentially interpolates the original sampled sequence, expanding the original sequence in the time domain. When the sampling clock is recovered, the interpolated original sequence is decimated (also known as downsampling) to determine the optimal sampling time. However, the Gardner algorithm requires oversampling, which limits its application in large-bandwidth scenarios. The overhead-assisted synchronization method involves inserting a low-speed overhead signal into the data signal and performing narrowband filtering at the receiving end to recover the sampling clock. However, the overhead-assisted synchronization method introduces additional spectral overhead and requires the filter bandwidth of the receiving end to be narrow. In large-bandwidth systems, the filter design is relatively difficult.

[0004] It can be seen that how to achieve clock synchronization in a large bandwidth scenario is an urgent problem that needs to be solved.

[0005] Summary of the Invention

[0006] The present application provides a communication device and a signal sampling method for achieving sampling clock synchronization.

[0007] In a first aspect, embodiments of the present application provide a communication device, which can be used in a receiver. The communication device includes a clock control circuit, a data sampling circuit, and a clock recovery circuit. The clock control circuit is configured to determine a sampling clock deviation of the data sampling circuit and generate a first clock control signal based on the sampling clock deviation. The first clock control signal is configured to adjust the sampling clock of the data sampling circuit. The clock recovery circuit is configured to adjust the sampling clock of the data sampling circuit based on the first clock control signal and transmit a clock signal to the data sampling circuit. The data sampling circuit is configured to sample an input analog signal based on the clock signal.

[0008] The data sampling circuit is, for example, an ADC module. In an embodiment of the present application, the clock control circuit can generate a corresponding first clock control signal based on the sampling clock deviation of the data sampling circuit and feed it back to the clock recovery circuit. The clock recovery circuit can adjust the sampling clock of the data sampling circuit based on the first clock control signal and feed back a clock signal obtained from the adjusted sampling clock to the data sampling circuit, so that the data sampling circuit performs sampling based on the adjusted sampling clock. The data sampling circuit can feed back the signal sampled based on the adjusted sampling clock to the clock control circuit. The clock control circuit can again determine the sampling clock deviation of the data sampling circuit and generate a corresponding clock control signal to feed back to the clock recovery circuit. The clock recovery circuit can further adjust the sampling clock of the data sampling circuit based on the received clock control signal and feed back a clock signal obtained from the adjusted sampling clock to the data sampling circuit. Because the clock control circuit and the clock recovery circuit can cooperate to adjust the sampling clock of the data sampling circuit multiple times, the sampling clock of the data sampling circuit can be locked to an optimal sampling time. This eliminates the need to oversample the original analog signal and enables the sampled digital signal to retain useful information from the original analog signal. Since there is no need to oversample the original analog signal, the complexity of the ADC and the complexity of the filter in the receiver will not be increased even in large bandwidth scenarios.

[0009] [Corrected 18.10.2022 in accordance with Rule 91] In one possible design, when the first clock control signal indicates that the sampling clock deviation of the data sampling circuit is below a first threshold, the clock signal is a target clock signal, which is capable of generating the desired sampling clock of the data sampling circuit. The desired sampling clock of the data sampling circuit can be considered the optimal sampling clock of the data sampling circuit. After multiple adjustments by the clock recovery circuit, the actual sampling clock of the data sampling circuit gradually decreases from the optimal sampling clock until the actual sampling clock of the data sampling circuit approaches or even equals the optimal sampling clock. At this point, the clock signal generated by the clock recovery circuit is called the target clock signal, i.e., the clock signal that enables the data sampling circuit to achieve the optimal sampling clock.

[0010] In one possible design, the clock recovery circuit includes a splitter, a first delayer, a second delayer, and a multiplier, wherein the splitter is connected to the input end of the first delayer and the input end of the second delayer, and the multiplier is connected to the output end of the first delayer and the output end of the second delayer. The output end of the first delayer and the output end of the second delayer are also connected to the input end of the clock control circuit. The splitter is used to split the input analog signal into a first analog sub-signal and a second analog sub-signal. The first delayer is used to delay the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and output the first delayed signal to the multiplication circuit and the clock control circuit. The second delayer is used to delay the second analog word signal according to the first clock control signal to obtain a second delayed signal, and output the second delayed signal to the multiplication circuit and the clock control circuit. The multiplication circuit is used to multiply the first delayed signal and the second delayed signal to obtain a first signal, and output the first signal to the data sampling circuit.

[0011] In an embodiment of the present application, the analog signal input to the clock recovery circuit and the analog signal input to the data sampling circuit are identical. Therefore, the clock recovery circuit processes the input analog signal to adjust the sampling clock of the data sampling circuit. For example, the clock recovery circuit adjusts the sampling clock of the data sampling circuit by splitting the input analog signal into two paths and controlling the delay between the two paths, thereby achieving an optimal sampling clock for the data sampling circuit.

[0012] In one possible design, a clock control circuit includes a processor and a determinator. The processor is configured to determine a sampling clock deviation based on a first digital signal and a second digital signal output by a data sampling circuit, and generate a first clock control signal based on the sampling clock deviation. The first digital signal is a real component obtained by the data sampling circuit sampling an input analog signal, and the second digital signal is an imaginary component obtained by the data sampling circuit sampling the analog signal. The determinator is configured to determine, based on the first delay signal and the second delay signal, that a clock recovery circuit cannot generate a target clock signal, and output a second clock control signal to the clock recovery circuit.

[0013] In the embodiment of the present application, the clock recovery circuit can gradually reduce the clock deviation of the data sampling circuit until the sampling clock of the data sampling circuit reaches the optimal sampling clock. Otherwise, the clock recovery circuit needs to continue to adjust the sampling clock of the data sampling circuit. Therefore, if the clock control circuit determines that the clock signal generated by the clock recovery circuit is not the target clock signal, it will continue to output the clock control signal to the clock recovery circuit.

[0014] In a possible design, the determiner is further configured to: determine, based on the first delay signal and the second delay signal, that the clock recovery circuit is capable of generating the target clock signal, and output an indication signal to the clock recovery circuit. The indication information indicates that there is no need to adjust the sampling clock of the data sampling circuit. When the clock control circuit determines that the clock signal generated by the clock recovery circuit is the target clock signal, the determiner outputs an indication signal to the clock recovery circuit, indicating that the clock recovery circuit does not need to further adjust the sampling clock of the data sampling circuit.

[0015] In a possible design, the determiner is specifically configured to: determine a first delay duration of the first analog sub-signal based on the first delay signal, and determine a second delay duration of the second analog sub-signal based on the second delay signal. When the difference between the first delay duration and the second delay duration deviates from a sampling clock expected by the data sampling circuit by more than a first threshold, it is determined that the clock recovery circuit cannot generate a target clock signal.

[0016] In a possible design, a first delayer delays a first analog sub-signal according to a first clock control signal, including: when the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the first delayer delays the first analog sub-signal according to a first delay step size; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the first delayer delays the first analog sub-signal according to a second delay step size, wherein the first delay step size is greater than the second delay step size. A second delayer delays a second analog sub-signal according to the first clock control signal, including: when the first clock control signal indicates that the sampling clock deviation is greater than or equal to the first value, the second delayer delays the second analog sub-signal according to a third delay step size; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delayer delays the second analog sub-signal according to a fourth delay step size, wherein the third delay step size is greater than the fourth delay step size.

[0017] In an embodiment of the present application, multiple delay steps can be predefined for the first delayer and the second delayer respectively. When the data sampling clock deviation is large, the first delayer and the second delayer delay the input analog signal according to the longer delay step; when the data sampling clock deviation is small, the first delayer and the second delayer delay the input analog signal according to the shorter delay step, so as to improve the sampling clock adjustment efficiency and accuracy.

[0018] In a possible design, the clock recovery circuit further includes: a first low-pass filter connected to the multiplier, configured to filter out high-frequency components in the first signal, thereby reducing interference caused by the high-frequency components.

[0019] In a possible design, the clock recovery circuit further includes: a limiting amplifier connected to the first low-pass filter, configured to filter out components with amplitudes higher than the first amplitude in the signal output by the first low-pass filter, so as to reduce the probability of signal saturation.

[0020] In a possible design, the clock recovery circuit further includes: a phase-locked loop connected to the limiting amplifier, for making the frequency of the target clock signal consistent with the frequency of the first signal to improve phase stability.

[0021] In a possible design, the communication device further includes a phase locking module, which is connected to the clock control circuit and the data sampling circuit respectively. The phase locking circuit is configured to determine a sampling phase deviation of the data sampling circuit based on an error signal, generate a third control signal based on the sampling phase deviation, and output the third control signal to the data sampling circuit. The error signal is the error signal between the first digital signal and the second digital signal output by the data acquisition circuit. The third control signal is used to instruct the data sampling circuit to adjust the sampling phase.

[0022] In the embodiments of the present application, a phase-locking circuit is provided to take into account the phase deviation of the sampling clock. The clock control circuit calculates the phase deviation of the sampling clock of the data sampling circuit and feeds it back to the phase-locking circuit. The phase-locking circuit then feeds back the phase deviation to the data sampling circuit to adjust the phase of the sampling clock.

[0023] In a possible design, the phase locking module includes: a phase detector, a voltage-controlled oscillator, and a second low-pass filter connected in sequence to the clock control circuit. The second low-pass filter has an input connected to the voltage-controlled oscillator and an output connected to the data sampling circuit.

[0024] In a second aspect, embodiments of the present application provide a signal sampling method that can be performed by a communication device comprising a clock control circuit, a data sampling circuit, and a clock recovery circuit. The clock control circuit determines a sampling clock deviation of the data sampling circuit and generates a first clock control signal based on the sampling clock deviation. The first clock control signal is used to adjust the sampling clock of the data sampling circuit. The clock recovery circuit adjusts the sampling clock of the data sampling circuit based on the first clock control signal and sends a clock signal to the data sampling circuit. The data sampling circuit samples an input analog signal based on the clock signal.

[0025] [Corrected 18.10.2022 according to Rule 91] In one possible implementation, the first clock control signal indicates that a sampling clock deviation of the data sampling circuit is lower than a first threshold, and the clock signal is a target clock signal that can generate a desired sampling clock of the data sampling circuit.

[0026] In one possible implementation, a clock recovery circuit includes a splitter, a first delayer, a second delayer, and a multiplier. The first delayer is connected to the splitter and the clock control circuit, and the second delayer is connected to the splitter and the clock control circuit. The splitter divides the input analog signal into a first analog sub-signal and a second analog sub-signal. The first delayer delays the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and outputs the first delayed signal to the multiplication circuit and the clock control circuit. The second delayer delays the second analog word signal according to the first clock control signal to obtain a second delayed signal, and outputs the second delayed signal to the multiplication circuit and the clock control circuit. The multiplication circuit multiplies the first delayed signal and the second delayed signal to obtain a first signal, and outputs the first signal to the data sampling circuit.

[0027] In one possible implementation, a clock control circuit includes a processor and a delay device. The processor determines a sampling clock deviation based on a first digital signal and a second digital signal output by a data sampling circuit, and generates a first clock control signal based on the sampling clock deviation. The first digital signal is the real component of an analog signal sampled by the data sampling circuit, and the second digital signal is the imaginary component of the analog signal sampled by the data sampling circuit. A decision device determines, based on the first and second delay signals, that a clock recovery circuit cannot generate a target clock signal and outputs a second clock control signal to the clock recovery circuit.

[0028] In one possible implementation, the determiner further determines, based on the first delay signal and the second delay signal, that the clock recovery circuit can generate the target clock signal, and outputs an indication signal to the clock recovery circuit, indicating that the sampling clock of the data sampling circuit does not need to be adjusted.

[0029] In one possible implementation, the determiner is specifically used to: determine a first duration of delay of the first analog sub-signal based on a first delay signal, determine a second duration of delay of the second analog sub-signal based on a second delay signal, and when the difference between the first duration and the second duration deviates from the sampling clock expected by the data sampling circuit by more than a first threshold, determine that the clock recovery circuit cannot generate the target clock signal.

[0030] In one possible implementation, when the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the first delay device delays the first analog sub-signal according to a first delay step size. When the first clock control signal indicates that the sampling clock deviation is less than the first value, the first delay device delays the first analog sub-signal according to a second delay step size, wherein the first delay step size is greater than the second delay step size. When the first clock control signal indicates that the sampling clock deviation is greater than or equal to the first value, the second delay device delays the second analog sub-signal according to a third delay step size. When the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delay device delays the second analog sub-signal according to a fourth delay step size, wherein the third delay step size is greater than the fourth delay step size.

[0031] [Corrected 18.10.2022 according to Rule 91] In one possible implementation, the clock recovery circuit further includes a first low-pass filter connected to the multiplication circuit, and the first low-pass filter is used to filter out high-frequency components in the first signal.

[0032] In a possible implementation, the clock recovery circuit further includes a limiting amplifier connected to the first low-pass filter, and the limiting amplifier is configured to filter out a component with an amplitude higher than the first amplitude in a signal output by the first low-pass filter.

[0033] In a possible implementation, the clock recovery circuit further includes a phase-locked loop connected to the limiting amplifier, where the phase-locked loop is configured to make the frequency of the target clock signal consistent with the frequency of the first signal.

[0034] In one possible implementation, the communication device further includes a phase locking module, the phase locking module being connected to the clock control circuit and the data sampling circuit, respectively. The method further includes: determining, by the phase locking circuit, a sampling phase deviation of the data sampling circuit based on an error signal, generating a third control signal based on the sampling phase deviation, and outputting the third control signal to the data sampling circuit. The error signal is an error signal between the first digital signal and the second digital signal output by the data acquisition circuit. The third control signal is used to instruct the data sampling circuit to adjust the sampling phase.

[0035] In one possible implementation, the phase locking module includes a phase detector, a voltage-controlled oscillator, and a second low-pass filter connected in sequence to the clock control circuit, wherein the input end of the second low-pass filter is connected to the voltage-controlled oscillator, and the output end is connected to the data sampling circuit.

[0036] In a third aspect, an embodiment of the present application provides a receiver, which includes the communication device described in the first aspect and any possible implementation of the first aspect.

[0037] In a fourth aspect, an embodiment of the present application provides a receiver, comprising an input / output interface and a logic circuit. The input / output interface is used to input and / or output information. The logic circuit is used to execute the method described in the second aspect.

[0038] In a fifth aspect, embodiments of the present application provide a chip system comprising a communication interface and a processor, enabling a device equipped with a system-on-chip to execute the method described in the second aspect or any possible implementation of the second aspect. In one possible implementation, the chip system further comprises a memory for storing a computer program. The chip system may be composed of a chip alone, or may include a chip and other discrete components.

[0039] In a sixth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, it implements the method described in the second aspect or any possible implementation of the second aspect.

[0040] In a seventh aspect, a computer program product is provided, comprising: a computer program code, wherein when the computer program code is run, the method described in the second aspect or any possible implementation of the second aspect is executed.

[0041] The beneficial effects of the above-mentioned second to seventh aspects and their implementation methods can refer to the description of the beneficial effects of the first aspect and its possible design methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of the architecture of a communication system applicable to an embodiment of the present application;

[0043] FIG2 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0044] FIG3 is a schematic diagram of conditions that need to be met for an optimal sampling clock of a data sampling circuit provided by an embodiment of the present application;

[0045] FIG4 is another schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0046] FIG5 is another structural diagram of a communication device provided in an embodiment of the present application;

[0047] FIG6 is a schematic diagram showing a deviation between an actual sampling clock and an expected sampling clock of a data sampling circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The technical solutions provided by the embodiments of the present application can be applied to devices requiring ADC, such as receivers. The receiver can communicate with a transmitter via a wireless channel or a wired cable. As an example, see Figure 1, which is a schematic diagram of the network architecture of a communication system applicable to the embodiments of the present application. The communication system may include a transmitter and a receiver. Figure 1 takes the example of a transmitter and a receiver communicating via a wired cable. The transmitter includes a baseband chip, a digital-to-analog converter (DAC), a radio frequency chip, and a power amplifier. The base station chip is used to process the signal to be transmitted and send the processed digital signal to the DAC for digital-to-analog conversion, that is, converting the digital signal into an analog signal. The analog signal is converted into a radio frequency signal by the radio frequency chip, and then transmitted to the radio frequency chip in the receiver via a wireless channel or a wired cable through the power amplifier. The radio frequency chip in the receiver down-converts the received radio frequency information and then converts it into a digital signal through the ADC. The digital signal can be used to restore the information carried by the signal sent by the transmitter. The baseband processing chip in the receiver processes the digital signal to obtain the original information sent by the transmitter. It should be noted that the components included in the transmitter and receiver in FIG1 are only examples, and other possible components may also be included, such as filters, mixers, etc., which are not listed here one by one.

[0049] In order for the digital signal to retain all the information contained in the analog signal sent by the transmitter, the ADC sampling frequency theoretically must be greater than or equal to twice the bandwidth occupied by the original analog signal. However, due to various factors, a precise sampling frequency cannot be guaranteed, and the ADC is often required to sample at a higher sampling frequency (also known as oversampling). ADC oversampling requires sampling clock recovery in the digital domain to determine the optimal sampling moment. Channel transmission delays and clock skew between the transmitter and receiver prevent the ADC from sampling at the optimal moment, resulting in deviations between the collected data and the original data. Therefore, clock synchronization is necessary, as shown in Figure 1. Sampling clock synchronization ensures that the ADC samples at the optimal moment.

[0050] Currently, commonly used clock synchronization methods include the Gardner algorithm and overhead-assisted synchronization methods. The Gardner algorithm essentially interpolates the original sampled sequence, expanding the original sequence in the time domain. When the sampling clock is recovered, the interpolated original sequence is decimated (also known as downsampling) to determine the optimal sampling time. However, the Gardner algorithm requires oversampling, which limits its application in large-bandwidth scenarios. The overhead-assisted synchronization method involves inserting a low-speed overhead signal into the data signal and performing narrowband filtering at the receiving end to recover the sampling clock. However, the overhead-assisted synchronization method introduces additional spectral overhead and requires the filter bandwidth of the receiving end to be narrow. In large-bandwidth systems, the filter design is relatively difficult.

[0051] In an embodiment of the present application, the ADC sampling clock can be locked to a desired sampling clock (optimal sampling clock). Since the ADC is locked to operate at the optimal sampling clock, there is no need to oversample the original analog signal, and the sampled digital signal can retain the useful information of the original analog signal. Since the ADC does not need to oversample the original analog signal, that is, the ADC sampling frequency is independent of the bandwidth of the original analog signal, the solution provided by the embodiment of the present application does not increase the complexity of the ADC or the complexity of the filter in the receiver even in large bandwidth scenarios.

[0052] The following describes the technical solutions provided by the embodiments of this application in conjunction with the accompanying drawings. In the embodiments of this application, high frequency and low frequency are relative terms. For example, the frequency range of high frequency can be [1.5×Fs, ~], and the frequency range of low frequency can be [0, 1.5×Fs], where Fs is the bandwidth of the first signal. A delay device is also called a time delay device.

[0053] Please refer to Figure 2, which is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. The communication device can be applied to a receiver. As shown in Figure 2, the communication device includes a clock control circuit 201, a clock recovery circuit 202 and a data sampling circuit 203. The clock control circuit 201 is connected to the data sampling circuit 203 and the clock recovery circuit respectively, and the clock recovery circuit 202 is also connected to the data sampling circuit 203. The data sampling circuit 203 is, for example, an ADC module. It should be noted that the clock control circuit 201 and the clock recovery circuit 202 can be two independent circuits or physical devices (this article takes this as an example), or they can be integrated together. In other words, the clock control circuit 201 and the clock recovery circuit 202 can be an integrated device, such as a carrier data recovery (CDR) module.

[0054] The clock control circuit 201 can determine the sampling clock deviation of the data sampling circuit 203 based on the signal collected by the data sampling circuit 203 and feed it back to the clock recovery circuit 202. The clock recovery circuit 202 can adjust the sampling clock of the data sampling circuit 203 based on the sampling clock deviation fed back by the clock control circuit 201 and feed the adjusted sampling clock back to the data sampling circuit 203. The data sampling circuit 203 samples according to the sampling clock fed back by the clock recovery circuit 202 and outputs the sampled signal to the clock control circuit 201. The adjustment by the clock recovery circuit 202 can reduce the sampling clock deviation of the data sampling circuit 203. If the sampling clock of the data sampling circuit 203 still deviates from the optimal sampling clock after the first adjustment by the clock recovery circuit 202, the sampling clock of the data sampling circuit 203 can be adjusted again. For example, the data sampling circuit 203 can feed back the signal sampled according to the adjusted sampling clock to the clock control circuit 201. The clock control circuit 201 can then again determine the sampling clock deviation of the data sampling circuit and generate a corresponding clock control signal to feed back to the clock recovery circuit 202. The clock recovery circuit 202 can again adjust the sampling clock of the data sampling circuit 203 according to the received clock control signal and feed back the clock signal obtained from the adjusted sampling clock to the data sampling circuit 203. Similarly, the sampling clock of the data sampling circuit 203 is adjusted multiple times by the clock control circuit 201 and the clock recovery circuit 202 until the actual sampling clock of the data sampling circuit 203 reaches the optimal sampling clock.

[0055] The actual sampling clock of the data sampling circuit 203 reaches the optimal sampling clock, which can also be understood as the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold. The first threshold can be preset or preconfigured, and the embodiment of the present application does not limit the size of the first threshold. For example, the first threshold can be a possible value obtained from experimental testing. Depending on the sampling accuracy, the size of the first threshold can also be different. For example, the first threshold can be a normalized clock deviation, such as 10 -6It can be understood that when the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold, the clock control signal generated by the clock control circuit is used to adjust the sampling clock of the data sampling circuit 203. When the sampling clock deviation of the data sampling circuit 203 is greater than or equal to the first threshold, the clock control circuit 201 can generate an indication signal, which indicates that the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold. The clock recovery circuit 202 can determine that there is no need to further adjust the sampling clock of the data sampling circuit 203 based on the indication signal fed back by the clock control circuit 201. In this case, the clock recovery circuit 202 does not adjust the sampling clock of the data sampling circuit 203, but directly outputs the final clock signal (referred to as the target clock signal herein) to the data sampling circuit 203. This target clock signal can enable the sampling clock of the data sampling circuit 203 to reach the desired sampling clock.

[0056] For ease of understanding, the following example uses a receiver receiving a first analog signal from a transmitter. The first analog signal is divided into two signals, which are respectively referred to as an I signal and a Q signal. The I signal is the real component of the first analog signal, and the Q signal is the imaginary component of the first analog signal.

[0057] Continuing with FIG2 , the I signal and the local oscillator signal pass through the mixer and then the low-pass filter before being input into the data sampling circuit 203. Similarly, the Q signal and the local oscillator signal pass through the mixer and then the low-pass filter before being input into the data sampling circuit 203. The I signal is sampled by the data acquisition circuit 203 to obtain a first digital signal, and the Q signal is sampled by the data acquisition circuit 203 to obtain a second digital signal. The data sampling circuit 203 outputs the first digital signal and the second digital signal to the clock control circuit 201. For example, the first digital signal I′[k] and the second digital signal Q′[k] respectively satisfy the following formulas:

[0058]

[0059]

[0060] Among them, I k +jQ k is a digital signal obtained by sampling the first analog signal by the data sampling circuit 203, Ts is a sampling clock of the data sampling circuit 203, θ o is the sampling phase deviation of the data sampling circuit 203, Δf is the sampling frequency deviation of the data sampling circuit 203, and k is an index.

[0061] The clock control circuit 201 can determine the sampling clock deviation of the data sampling circuit 203 according to the first digital signal and the second digital signal, and can determine the sampling clock deviation of the data sampling circuit 203 according to the sampling clock deviation.k The first deviation signal between For example, the clock control circuit 201 is based on Q′[k] and Q k The second deviation signal between Wherein, m is a preset integer.

[0062] After determining the first and second error signals, the clock control circuit 201 can determine the sampling clock deviation err_clock = error_s_I + j × error_s_Q based on the first and second error signals. Furthermore, the clock control signal err_clock is generated based on the sampling clock deviation. The clock control signal err_clock can be a linear function of the error signal err_clock, for example, error_s = k × (err_clock), where k is greater than 0. It is understood that when error_s is minimized, err_clock is also minimized. Therefore, the magnitude and direction of err_clock can be adjusted based on error_s.

[0063] It can be understood that after multiple adjustments by the clock recovery circuit 202, the sampling clock deviation of the data sampling circuit 203 can be gradually reduced, that is, error_s gradually decreases. Accordingly, the amount of sampling clock adjustment indicated by the clock recovery circuit 202, as indicated by the clock control signal, also decreases. That is, the clock control signal generated by the clock recovery circuit 202 varies with the number of adjustments. For ease of description, the clock control signal initially determined by the clock control circuit 201 may be referred to as the first clock control signal. The following describes how the clock recovery circuit 202 adjusts the sampling clock of the data sampling circuit 203 based on the clock control signal fed back by the clock control circuit 201, using the clock control signal generated by the clock control circuit 201 as the first clock control signal.

[0064] In the embodiment of the present application, the sampling clock of the data sampling circuit 203 can be locked to an optimal sampling clock. For example, the sampling clock of the analog signal input to the data sampling circuit 203 is processed by the clock recovery circuit 202, and a determination is made based on the processing result as to whether the sampling clock of the data sampling circuit 203 is the optimal sampling clock. For example, the clock recovery circuit adjusts the sampling clock of the data sampling circuit by dividing the input analog signal into two paths and controlling the delay between the two paths.

[0065] In a possible design, the clock recovery circuit 202 may include a splitter 2021, a first delay 2022, a second delay 2023, and a multiplier 2024. The splitter 2021 is used to split the first analog signal into the first analog sub-signal r IF (t) and the second simulated sub-signal r IF (t). IF(t) satisfies: r IF (t) = real(A(t)×exp(j×2×π×f0×t)). Where A(t) is the first analog signal, f0 is the carrier frequency, t is time, real represents the real part of the complex number, and exp is the exponential function. The first analog sub-signal r IF (t) is output to the first delay 2022, and the second analog sub-signal r IF (t) is output to the second delay 2023. The first clock control signal is fed back to the input terminals of the first delay 2022 and the second delay 2023, respectively. It should be noted that the splitter 2021 may also be a power splitter, as long as it can split one signal into two signals. For example, the splitter 2021 may be a two-power splitter.

[0066] The first delayer 2022 can delay the first analog sub-signal r according to the first clock control signal. IF (t), the second delayer 2023 can delay the second analog sub-signal r according to the first clock control signal IF (t). Assume that the first analog sub-signal r IF (t) delay time τ1, the second analog sub-signal r IF (t) delay time τ2, the first analog sub-signal r after delay IF (t) is denoted as r IF (t-τ1), the delayed second analog sub-signal r IF (t) is denoted as r IF (t-τ2). r IF (t-τ1) and r IF (t-τ2) passes through the multiplier 2024 to obtain the first signal S1(t)=r IF (t-τ1)×r IF (t-τ2). The first signal S1(t) is filtered through a low-pass filter to remove high-frequency components and obtain:

[0067]

[0068] Wherein, Ts is the sampling clock expected by the data sampling circuit 203, A n Where A is the amplitude of the signal, n is the series, and the value of n ranges from a very small negative number to a large positive integer. Function g represents an integer function, function g′ represents an equivalent integer function, t represents time, τ represents π, and f IF Indicates the carrier frequency.

[0069] The power spectrum S2(f) of S2(t) satisfies:

[0070] in, is the noise power, G is the frequency domain expression of function g′, and m is an integer.

[0071] Wherein, Ts is the optimal sampling clock of the data sampling circuit 203. Please refer to FIG3, which shows the power spectrum S2(f). The vertical axis in FIG3 is S2(f). As can be seen from FIG3, when (τ2-τ1)=T s hour, Maximum, therefore, when τ2-τ1=T s , it can be determined that the clock recovery circuit 202 has adjusted the sampling clock of the data sampling circuit 203 to the desired sampling clock. s When the sampling clock adjustment of the data sampling circuit 203 has not reached the expected sampling clock, the clock recovery circuit 202 needs to continue to adjust the sampling clock of the data sampling circuit 203, that is, the clock recovery circuit 202 needs to continue to delay the received signal through the first delay 2022 and the second delay 2023.

[0072] It should be understood that the delay of the received signal by the first delay 2022 and the second delay 2023 is actually a time-domain shift of the received signal. In the embodiment of the present application, the time-domain shifts of the received signal by the first delay 2022 and the second delay 2023 are opposite: that is, when τ1 is positive, τ2 is negative; and when τ1 is negative, τ2 is positive. After multiple adjustments, the clock recovery circuit 202 can gradually reduce the sampling clock deviation of the data sampling circuit 203 until the sampling clock of the data sampling circuit 203 is adjusted to the desired sampling clock. Since the sampling clock deviation of the data sampling circuit 203 gradually decreases during these multiple adjustments, the clock recovery circuit 202 should also adaptively reduce the delay duration of the received signal via the first delay 2022. Similarly, the delay duration of the received signal by the second delay 2023 should also be adaptively reduced.

[0073] In a possible design, multiple delay steps can be predefined for the first delayer 2022 and the second delayer 2023 respectively. The clock recovery circuit 202 receives a clock control signal from the clock control circuit 201, and can select a delay step that matches the first delayer 2022 and a delay step that matches the second delayer 2023 according to the size of the sampling clock deviation indicated by the clock control signal. Taking the first delayer 2022 as an example, a first delay step, a second delay step and a third delay step can be predefined. Among them, the first delay step is greater than the second delay step, and the second delay step is greater than the third delay step. If the clock control signal received by the first delayer 2022 from the clock control circuit 201 indicates that the sampling clock deviation is greater than or equal to the first value, the first delayer 2022 is set to the first delay step τ. 11Delay the first analog sub-signal to obtain a delayed signal, denoted as r IF (t-τ 11 If the clock control signal received by the first delayer 2022 from the clock control circuit 201 indicates that the sampling clock deviation is greater than or equal to the second value, the first delayer 2022 delays the sampling clock according to the second delay step τ. 12 Delay the first analog sub-signal to obtain a delayed signal, denoted as r IF (t-τ 12 ). The first value is greater than the second value.

[0074] Similarly, a fourth delay step, a fifth delay step, and a sixth delay step may also be predefined for the second delayer 2023. The fourth delay step is greater than the fifth delay step, and the fifth delay step is greater than the sixth delay step. If the clock control signal received by the second delayer 2023 from the clock control circuit 201 indicates that the sampling clock deviation is greater than or equal to the first value, the second delayer 2023 is set to the fourth delay step τ. 21 Delay the first analog sub-signal to obtain a delayed signal, denoted as r IF (t-τ 21 If the clock control signal received by the second delayer 2023 from the clock control circuit 201 indicates that the sampling clock deviation is greater than or equal to the second value, the second delayer 2023 delays the sampling clock according to the fifth delay step τ 22 Delay the first analog sub-signal to obtain a delayed signal, denoted as r IF (t-τ 22 ). It can be understood that the first delay step, the second delay step, and the third delay step are positive numbers, and the fourth delay step, the fifth delay step, and the sixth delay step are negative numbers; or, the first delay step, the second delay step, and the third delay step are negative numbers, and the fourth delay step, the fifth delay step, and the sixth delay step are positive numbers. The embodiment of the present application does not limit the size of the first delay step, the second delay step, and the third delay step, and does not limit the size of the fourth delay step, the fifth delay step, and the sixth delay step.

[0075] It should be noted that some or all of the components in the splitter 2021, the first delay 2022, the second delay 2023, and the multiplier 2024 may be integrated together. For example, the first delay 2022 and the second delay 2023 may be integrated together as one component.

[0076] The first delay 2022 and the second delay 2023 feed back the generated signals to the clock control circuit 201. The clock control circuit 201 determines whether the first delay 2022 and the second delay 2023 have adjusted the current sampling clock of the data sampling circuit 203 to the desired sampling clock. For ease of description, the signal generated by the first delay 2022 is referred to as the first delayed signal, and the signal generated by the second delay 2023 is referred to as the second delayed signal.

[0077] The clock control circuit 201 receives a first delayed signal from the first delay unit 2022 and a second delayed signal from the second delay unit 2023, and determines whether the clock recovery circuit 202 has adjusted the current sampling clock of the data sampling circuit 203 to the desired sampling clock. For example, the clock control circuit 201 includes a decision unit 2012, which determines a first delay duration for the first analog sub-signal based on the first delayed signal, and a second delay duration for the second analog sub-signal based on the second delayed signal. If the difference between the first delay duration and the second delay duration and the desired sampling clock Ts of the data sampling circuit 203 is greater than a first threshold, the multiplier 2024 multiplies the first delayed signal and the second delayed signal to obtain a first signal, i.e., the clock signal generated by the clock recovery circuit 202, is not the target clock signal, meaning that the clock recovery circuit 202 is unable to generate the target clock signal.

[0078] In this case, the clock control circuit 201 continues to calculate the sampling clock deviation based on the I and Q signals received from the data sampling circuit 203 and generates a new clock control signal, such as a second clock control signal, based on the sampling clock deviation. For example, the processor 2011 in the clock control circuit 201 calculates the sampling clock deviation based on the I and Q signals received from the data sampling circuit 203 and generates a second clock control signal based on the sampling clock deviation. This second clock control signal may indicate that the sampling clock deviation of the data sampling circuit 203 is below a second threshold. This second clock control signal is fed back to the first delay 2022 and the second delay 2023. The first delay 2022 and the second delay 2023 each delay the received signals based on the second clock control signal and feed the generated delayed signals back to the clock control circuit 201, and so on. This continues until the clock control circuit 201 determines that the difference between the delay duration corresponding to the first delayed signal and the delay duration corresponding to the second delayed signal is less than or equal to the deviation between the sampling clock Ts expected by the data sampling circuit 203 and the first threshold. At this point, the clock control circuit 201 feeds back an indication signal to the first delay 2022 and the second delay 2023, indicating that the sampling clock deviation of the data sampling circuit 203 is below a first threshold. The multiplier 2024 multiplies the first delayed signal and the second delayed signal to obtain a first signal, which is the target clock signal. It should be understood that the indication signal is a special case of a clock control signal, and its specific implementation is also a clock control signal. It is understood that if the sampling clock of the data sampling circuit 203 is adjusted to the desired sampling clock, but the actual sampling clock of the data sampling circuit 203 deviates from the desired sampling clock during subsequent use, the aforementioned method can be continued to adjust the sampling clock of the data sampling circuit 203 to maximize the actual sampling clock of the data sampling circuit 203 to the desired sampling clock.

[0079] Considering that the high-frequency components contained in the first signal output by multiplier 2024 may cause interference, in a possible design, clock recovery circuit 202 may also include a functional module for filtering out the high-frequency components of the first signal. For example, referring to FIG4 , clock recovery circuit 202 may include, in addition to multiplier 2024, a low-pass filter 2025 connected to multiplier 2024. Low-pass filter 2025 can filter out the high-frequency components in the first signal, thereby reducing the interference that the first signal may cause.

[0080] If the amplitude of the first signal is too large, saturation may cause inaccuracy in the target clock signal. To this end, the clock recovery circuit 202 may further include a limiting amplifier 2026 connected to the low-pass filter 2025. For example, the clock recovery circuit 202 may include a multiplier 2024, a low-pass filter 2025, and a limiting amplifier 2026, as shown in Figure 4. The limiting amplifier 2026 can filter out components of the signal output by the low-pass filter 2025 that have an amplitude greater than a preset amplitude, thereby reducing the probability of the first signal causing amplitude saturation.

[0081] If the frequency of the signal output by limiting amplifier 2026 cannot be fixed, the sampling clock may fail to converge, i.e., the sampling clock may become unstable. To this end, clock recovery circuit 202 may further include a phase-locked loop 2027 connected to limiting amplifier 2026. For example, clock recovery circuit 202 may include a multiplication circuit 2024, a low-pass filter 2025, a limiting amplifier 2026, and a phase-locked loop 2027, as shown in FIG4 . The phase-locked loop 2027 can ensure that the frequency of the target clock signal is consistent with the frequency of the first signal output by multiplication circuit 2024, thereby reducing the probability of sampling clock instability caused by phase instability.

[0082] Referring to FIG. 5 , the communication device provided in an embodiment of the present application may further include a phase locking module 204. For example, the communication device includes a clock control circuit 201, a clock recovery circuit 202, a data sampling circuit 203, and a phase locking module 204. The clock control circuit 201 may be used to eliminate sampling phase deviations of the data sampling circuit 203. Specifically, the phase locking module 204 may include a phase detector 2041, a voltage-controlled oscillator 2042, and a low-pass filter 2043. The input of the phase detector 2041 is connected to the clock control circuit 201, and the output of the phase detector 2041 is connected to the input of the voltage-controlled oscillator 2042. The output of the voltage-controlled oscillator 2042 is connected to the input of the low-pass filter 2043, and the output of the low-pass filter 2043 is connected to the data sampling circuit.

[0083] The processor 2011 in the clock control circuit 201 can determine the sampling phase deviation of the data sampling circuit based on the first digital signal and the second digital signal received from the data sampling circuit 203. For ease of description, the first digital signal is denoted as I'(k) and the second digital signal is denoted as Q'(k). Assuming that there is no sampling phase deviation, the signal output by the digital sampling circuit 203 is I k +jQ k .have:

[0084]

[0085]

[0086] Where Δf is the frequency deviation, and θ0 is the sampling phase deviation, that is, the deviation between the desired sampling clock and the actual sampling clock, as shown in Figure 6.

[0087] The processor 2011 in the clock control circuit 201 can extract I k +jQ k The error signal between I′(k)+Q′(k) is: Processor 2011 feeds this deviation signal back to phase detector 2041, which then determines the sampling phase deviation via voltage-controlled oscillator 2042. Voltage-controlled oscillator 2042 generates a third control signal based on the sampling phase deviation. Low-pass filter 2043 filters out high-frequency components from the third control signal before outputting it to data sampling circuit 203. To conserve resources, this third control signal can indicate whether to adjust the sampling phase up or down, thereby ensuring a stable sampling phase for data sampling circuit 203.

[0088] By using the communication device provided in the embodiment of the present application, the sampling clock of the data sampling circuit 203 (i.e., ADC) can be locked to the desired sampling clock (optimal sampling clock). Since the ADC is locked to operate at the optimal sampling clock, there is no need to oversample the original analog signal, and the sampled digital signal can retain the useful information of the original analog signal. Since the sampling frequency of the ADC is independent of the bandwidth of the original analog signal, it is possible to sample analog signals at various bandwidths. And since the ADC does not need to oversample the original analog signal, even in a large bandwidth scenario, the complexity of the ADC and the complexity of the filter in the receiver will not be increased.

[0089] In the embodiment provided by the present application, the communication device provided by the embodiment of the present application is introduced from the processing of signals between the various circuits (or devices or functional modules) included in the communication device and the transmission path. The various functional modules included in the communication device can be hardware structures and / or software modules, which implement the above-mentioned functions in the form of hardware structures, software modules, or hardware structures plus software modules. A certain function in the above-mentioned functions is performed in the form of hardware structures, software modules, or hardware structures plus software modules, depending on the specific application and design constraints of the technical solution.

[0090] For example, the various circuits (or devices or functional modules) included in the communication device may be independent, integrated, or coupled to each other. For example, the communication device may be a chip system. In the embodiment of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices. For specific functions, please refer to the description in the above embodiment.

[0091] For another example, the processor 2011 and the decision device 2012 can be independent or coupled together. The coupled processor 2011 and decision device 2012 can also be referred to as a processor, and the processor can also be referred to as a processing unit or a processing module, which can implement certain control functions. The processor can be a general-purpose processor or a dedicated processor, etc. For example, it includes: a central processing unit, an application processor, a modem processor, a graphics processor, an image signal processor, a digital signal processor, a video codec processor, a controller, a memory, and / or a neural network processor, etc. The central processing unit can be used to control the communication device, execute software programs and / or process data. Different processors can be independent devices or integrated into one or more processors, for example, integrated into one or more dedicated integrated circuits.

[0092] The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, for information exchange between devices, units or modules. Multiple coupled modules can operate in a coordinated manner.

[0093] It should be noted that the communication device in the above embodiment may also be a circuit, or a chip used in a device, or other combined devices, components, etc. having the functions of the above communication device.

[0094] The present application also provides a receiver comprising the communication device of the aforementioned embodiment. The receiver also includes other necessary functional components, such as a transceiver and an antenna. The transceiver may be referred to as a transceiver unit, transceiver module, transceiver, transceiver circuit, transceiver, input / output interface, etc., and is used to implement the transceiver function of the receiver via the antenna.

[0095] The communication device described in this article can be an independent device (for example, an independent integrated circuit, a mobile phone, etc.), or it can be a part of a larger device (for example, a module that can be embedded in other devices). For details, please refer to the aforementioned description of terminal devices and network devices, which will not be repeated here.

[0096] Optionally, the communication device may further include one or more of the following components: a wireless communication module, an audio module, an external memory interface, an internal memory, a universal serial bus (USB) interface, a power management module, an antenna, a speaker, a microphone, an input / output module, a sensor module, a motor, a camera, or a display screen, etc. It will be appreciated that in some embodiments, the communication device may include more or fewer components, or some components may be integrated or some components may be separated. These components may be implemented in hardware, software, or a combination of software and hardware.

[0097] Based on the same inventive concept as described above, an embodiment of the present application further provides a signal sampling method, applied to a receiver, comprising a communication device including a clock control circuit 201, a clock recovery circuit 202, and a data sampling circuit 203. The method comprises: determining, by the clock control circuit 201, a sampling clock deviation of the data sampling circuit 203, generating a first clock control signal based on the sampling clock deviation, the first clock control signal being used to adjust the sampling clock of the data sampling circuit 203; adjusting, by the clock recovery circuit 202, the sampling clock of the data sampling circuit 203 based on the first clock control signal, and sending a clock signal to the data sampling circuit 203; and sampling, by the data sampling circuit 203, an input analog signal based on the clock signal.

[0098] In a possible implementation, the first clock control signal indicates that the sampling clock deviation of the data sampling circuit 203 is lower than a first threshold, and the clock signal is a target clock signal that can generate a sampling clock expected by the data sampling circuit 203 .

[0099] In one possible implementation, the clock recovery circuit 202 includes a splitter 2021, a first delay 2022, a second delay 2023, and a multiplication circuit 2024. The first delay 2022 is connected to the splitter 2021 and the clock control circuit 201, and the second delay 2023 is connected to the splitter 2021 and the clock control circuit 201. The splitter 2021 splits the input analog signal into a first analog sub-signal and a second analog sub-signal. The first delay 2022 delays the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and outputs the first delayed signal to the multiplication circuit 2024 and the clock control circuit 201. The second delay 2023 delays the second analog word signal according to the first clock control signal to obtain a second delayed signal, and outputs the second delayed signal to the multiplication circuit 2024 and the clock control circuit 201. The multiplication circuit 2024 multiplies the first delayed signal and the second delayed signal to obtain a first signal, and outputs the first signal to the data sampling circuit 203.

[0100] In one possible implementation, the clock control circuit 201 includes a processor 2011 and a delayer 2012. The processor 2011 determines a sampling clock deviation based on a first digital signal and a second digital signal output by the data sampling circuit 203, and generates a first clock control signal based on the sampling clock deviation. The first digital signal is the real component of the analog signal sampled by the data sampling circuit 203, and the second digital signal is the imaginary component of the analog signal sampled by the data sampling circuit 203. The determiner 2012 determines, based on the first and second delayed signals, that the clock recovery circuit 202 cannot generate the target clock signal and outputs a second clock control signal to the clock recovery circuit 202.

[0101] In one possible implementation, the determiner 2012 further determines, based on the first delay signal and the second delay signal, that the clock recovery circuit 202 is capable of generating the target clock signal, and outputs an indication signal to the clock recovery circuit 202. The indication signal indicates that the sampling clock of the data sampling circuit 203 does not need to be adjusted.

[0102] In one possible implementation, the determiner 2012 is specifically used to: determine a first duration for which the first analog sub-signal is delayed based on the first delay signal, determine a second duration for which the second analog sub-signal is delayed based on the second delay signal, and determine that the clock recovery circuit 202 cannot generate the target clock signal when the difference between the first duration and the second duration deviates from the sampling clock expected by the data sampling circuit 203 by more than a first threshold.

[0103] In one possible implementation, when the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the first delayer 2022 delays the first analog sub-signal according to a first delay step size. When the first clock control signal indicates that the sampling clock deviation is less than the first value, the first delayer 2022 delays the first analog sub-signal according to a second delay step size, wherein the first delay step size is greater than the second delay step size. When the first clock control signal indicates that the sampling clock deviation is greater than or equal to the first value, the second delayer 2023 delays the second analog sub-signal according to a third delay step size. When the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delayer 2023 delays the second analog sub-signal according to a fourth delay step size, wherein the third delay step size is greater than the fourth delay step size.

[0104] In a possible implementation, the clock recovery circuit 202 further includes a first low-pass filter 2025 connected to the multiplication circuit 2024 . The first low-pass filter 2025 is configured to filter out high-frequency components in the first signal.

[0105] In a possible implementation, the clock recovery circuit 202 further includes a limiting amplifier 2026 connected to the first low-pass filter 2025 . The limiting amplifier 2026 is configured to filter out a component with an amplitude higher than the first amplitude in the signal output by the first low-pass filter 2025 .

[0106] In a possible implementation, the clock recovery circuit 202 further includes a phase-locked loop 2027 connected to the limiting amplifier 2026 , and the phase-locked loop 2027 is configured to make the frequency of the target clock signal consistent with the frequency of the first signal.

[0107] In one possible implementation, the communication device further includes a phase locking module 204, which is connected to the clock control circuit 201 and the data sampling circuit 203, respectively. The method further includes: determining, by the phase locking circuit 204, a sampling phase deviation of the data sampling circuit 203 based on the error signal, generating a third control signal based on the sampling phase deviation, and outputting the third control signal to the data sampling circuit 203. The error signal is an error signal between the first digital signal and the second digital signal output by the data sampling circuit 203. The third control signal is used to instruct the data sampling circuit 203 to adjust the sampling phase.

[0108] In one possible implementation, the phase locking module includes a phase detector 2041, a voltage-controlled oscillator 2042, and a second low-pass filter 2043, which are sequentially connected to the clock control circuit 201. The input end of the second low-pass filter 2043 is connected to the voltage-controlled oscillator 2042, and the output end is connected to the data sampling circuit 203.

[0109] The present application also provides a communication system. Specifically, the communication system includes the communication device and the sending device described in any one of Figures 2 to 5. For details, please refer to the relevant description in the above method embodiment, which will not be repeated here.

[0110] An embodiment of the present application also provides a computer-readable storage medium, including instructions, which, when executed on a computer, enables the computer to implement the functions of the communication device as described in any one of Figures 2 to 5.

[0111] An embodiment of the present application also provides a computer program product, including instructions, which, when executed on a computer, enables the computer to implement the functions of the communication device as described in any one of Figures 2 to 5.

[0112] The present invention provides a chip system that includes a processor and may also include a memory, so that a device equipped with the chip system can implement the functions of the communication device described in any one of Figures 2 to 5. The chip system can be composed of a chip or include a chip and other discrete devices.

[0113] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0114] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0115] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0118] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the part that essentially contributes to the technical solution of the present application or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0119] It should be noted that the connection involved in this application, which describes the connection relationship between two objects, can represent two types of connection relationships. For example, the connection between A and B can represent two situations: A is directly connected to B, and A is connected to B through C. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the system structure and business scenarios provided in the embodiments of the present application are mainly for explaining some possible implementation methods of the technical solution of the present application, and should not be interpreted as a unique limitation on the technical solution of the present application. Those of ordinary skill in the art will know that with the evolution of the system and the emergence of newer business scenarios, the technical solution provided in this application can still be applicable to the same or similar technical problems.

[0120] Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of protection of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A communication device, characterized in that: It includes a clock control circuit, a data sampling circuit and a clock recovery circuit; wherein, The clock control circuit is configured to determine a sampling clock deviation of the data sampling circuit and generate a first clock control signal according to the sampling clock deviation, wherein the first clock control signal is configured to adjust the sampling clock of the data sampling circuit; The clock recovery circuit is configured to adjust the sampling clock of the data sampling circuit according to the first clock control signal and send a clock signal to the data sampling circuit; The data sampling circuit is used to sample the input analog signal according to the clock signal.

2. [Corrected 18.10.2022 according to Rule 91] The device according to claim 1, characterized in that When the first clock control signal indicates that the sampling clock deviation of the data sampling circuit is lower than a first threshold, the clock signal is a target clock signal, and the target clock signal can generate a sampling clock expected by the data sampling circuit.

3. The device according to claim 1 or 2, characterized in that The clock recovery circuit comprises: A splitter, configured to split an input analog signal into a first analog sub-signal and a second analog sub-signal; a first delayer, connected to the splitter and the clock control circuit, configured to delay the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and output the first delayed signal to the multiplication circuit and the clock control circuit; a second delayer, connected to the splitter and the clock control circuit, configured to delay the second analog word signal according to the first clock control signal to obtain a second delayed signal, and output the second delayed signal to the multiplication circuit and the clock control circuit; The multiplication circuit is used to multiply the first delayed signal and the second delayed signal to obtain a first signal, and output the first signal to the data sampling circuit.

4. The device according to any one of claims 2 to 3, characterized in that The clock control circuit comprises: a processor, configured to determine the sampling clock deviation based on a first digital signal and a second digital signal output by the data sampling circuit, and generate the first clock control signal based on the sampling clock deviation; wherein the first digital signal is a real component obtained by the data sampling circuit sampling an input analog signal, and the second digital signal is an imaginary component obtained by the data sampling circuit sampling the analog signal; A decider is configured to determine, based on the first delayed signal and the second delayed signal, that the clock recovery circuit cannot generate the target clock signal, and output a second clock control signal to the clock recovery circuit.

5. The device according to claim 4, characterized in that The arbiter is also used to: Determine, based on the first delay signal and the second delay signal, that the clock recovery circuit is capable of generating the target clock signal, and output an indication signal to the clock recovery circuit, wherein the indication information indicates that the sampling clock of the data sampling circuit does not need to be adjusted.

6. The device according to claim 4, characterized in that The decision device is specifically used for: determining a first time duration for which the first analog sub-signal is delayed according to the first delay signal; determining a second time length during which the second analog sub-signal is delayed according to the second delayed signal; When the deviation between the difference between the first time length and the second time length and the sampling clock expected by the data sampling circuit is greater than the first threshold, it is determined that the clock recovery circuit cannot generate the target clock signal.

7. The device according to claim 3, wherein The first delayer delays the first analog sub-signal according to the first clock control signal, comprising: When the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the first delayer delays the first analog sub-signal according to a first delay step length; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the first delayer delays the first analog sub-signal according to a second delay step length, wherein the first delay step length is greater than the second delay step length; The second delayer delays the second analog sub-signal according to the first clock control signal, comprising: When the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the second delayer delays the second analog sub-signal according to a third delay step; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delayer delays the second analog sub-signal according to a fourth delay step, wherein the third delay step is greater than the fourth delay step.

8. [Corrected 18.10.2022 in accordance with Rule 91] The device according to any one of claims 2 to 7, characterized in that The clock recovery circuit further includes: A first low-pass filter is connected to the multiplication circuit and is used to filter out high-frequency components in the first signal.

9. The device according to claim 8, wherein The clock recovery circuit further includes: A limiting amplifier is connected to the first low-pass filter and is used to filter out a component with an amplitude higher than the first amplitude in the signal output by the first low-pass filter.

10. The device according to claim 9, wherein The clock recovery circuit further includes: A phase-locked loop is connected to the limiting amplifier and is used to make the frequency of the target clock signal consistent with the frequency of the first signal.

11. [Corrected 18.10.2022 in accordance with Rule 91] The device according to any one of claims 1 to 10, characterized in that The device further includes a phase locking module, which is connected to the clock control circuit and the data sampling circuit respectively; wherein the phase locking circuit is used to: determining a sampling phase deviation of the data sampling circuit according to an error signal, and generating a third control signal according to the sampling phase deviation, wherein the error signal is an error signal between a first digital signal and a second digital signal output by the data sampling circuit; The third control signal is output to the data sampling circuit, where the third control signal is used to instruct the data sampling circuit to adjust a sampling phase.

12. The device according to claim 11, wherein The phase locking module comprises: a phase detector connected to the clock control circuit; a voltage-controlled oscillator connected to the phase detector; The second low-pass filter has an input end connected to the voltage-controlled oscillator and an output end connected to the data sampling circuit.

13. A signal sampling method, characterized in that: Applied to a communication device, the communication device includes a clock control circuit, a data sampling circuit and a clock recovery circuit; The clock control circuit determines a sampling clock deviation of the data sampling circuit, and generates a first clock control signal according to the sampling clock deviation, wherein the first clock control signal is used to adjust the sampling clock of the data sampling circuit; The clock recovery circuit adjusts the sampling clock of the data sampling circuit according to the first clock control signal and sends a clock signal to the data sampling circuit; The data sampling circuit samples the input analog signal according to the clock signal.

14. [Corrected 18.10.2022 under Rule 91] The method according to claim 13, characterized in that When the first clock control signal indicates that the sampling clock deviation of the data sampling circuit is lower than a first threshold, the clock signal is a target clock signal, and the target clock signal can generate a sampling clock expected by the data sampling circuit.

15. [Corrected 18.10.2022 in accordance with Rule 91] The method according to claim 13 or 14, characterized in that The clock recovery circuit includes a splitter, a first delayer, a second delayer and a multiplication circuit, wherein the first delayer is connected to the splitter and the clock control circuit, and the second delayer is connected to the splitter and the clock control circuit; Wherein, the splitter divides the input analog signal into a first analog sub-signal and a second analog sub-signal; The first delayer delays the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and outputs the first delayed signal to the multiplication circuit and the clock control circuit; The second delayer delays the second analog word signal according to the first clock control signal to obtain a second delayed signal, and outputs the second delayed signal to the multiplication circuit and the clock control circuit; The multiplication circuit multiplies the first delayed signal and the second delayed signal to obtain a first signal, and outputs the first signal to the data sampling circuit.

16. The method according to any one of claims 14 to 15, wherein: The clock control circuit includes a processor and a delay device, wherein the processor determines the sampling clock deviation based on the first digital signal and the second digital signal output by the data sampling circuit, and generates the first clock control signal based on the sampling clock deviation; wherein the first digital signal is the real component obtained by the data sampling circuit sampling the input analog signal, and the second digital signal is the imaginary component obtained by the data sampling circuit sampling the analog signal; The determiner determines, based on the first delay signal and the second delay signal, that the clock recovery circuit cannot generate the target clock signal, and outputs a second clock control signal to the clock recovery circuit.

17. The method according to claim 16, wherein The decider also determines, based on the first delay signal and the second delay signal, that the clock recovery circuit is capable of generating the target clock signal, and outputs an indication signal to the clock recovery circuit, wherein the indication information indicates that the sampling clock of the data sampling circuit does not need to be adjusted.

18. The method according to claim 16, wherein The decision device is specifically used for: determining a first time duration for which the first analog sub-signal is delayed according to the first delay signal; determining a second time length during which the second analog sub-signal is delayed according to the second delayed signal; When the deviation between the difference between the first time length and the second time length and the sampling clock expected by the data sampling circuit is greater than the first threshold, it is determined that the clock recovery circuit cannot generate the target clock signal.

19. The method according to claim 15, wherein When the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the first delayer delays the first analog sub-signal according to a first delay step length; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the first delayer delays the first analog sub-signal according to a second delay step length, wherein the first delay step length is greater than the second delay step length; When the first clock control signal indicates that the sampling clock deviation is greater than or equal to a first value, the second delayer delays the second analog sub-signal according to a third delay step; when the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delayer delays the second analog sub-signal according to a fourth delay step, wherein the third delay step is greater than the fourth delay step.

20. [Corrected 18.10.2022 under Rule 91] A method according to any one of claims 14 to 19, characterized in that The clock recovery circuit further includes a first low-pass filter connected to the multiplication circuit, and the first low-pass filter is used to filter out high-frequency components in the first signal.

21. The method according to claim 20, wherein The clock recovery circuit further includes a limiting amplifier connected to the first low-pass filter, and the limiting amplifier is used to filter out a component with an amplitude higher than a first amplitude in a signal output by the first low-pass filter.

22. The method according to claim 21, wherein The clock recovery circuit further includes a phase-locked loop connected to the limiting amplifier, and the phase-locked loop is used to make the frequency of the target clock signal consistent with the frequency of the first signal.

23. [Corrected 18.10.2022 in accordance with Rule 91] The method according to any one of claims 13 to 22, wherein: The communication device further includes a phase locking module, wherein the phase locking module is connected to the clock control circuit and the data sampling circuit respectively. The method further includes: The phase locking circuit determines a sampling phase deviation of the data sampling circuit based on an error signal, generates a third control signal based on the sampling phase deviation, and outputs the third control signal to the data sampling circuit; wherein the error signal is an error signal between a first digital signal and a second digital signal output by the data sampling circuit, and the third control signal is used to instruct the data sampling circuit to adjust the sampling phase.

24. The method according to claim 23, wherein The phase locking module comprises: a phase detector connected to the clock control circuit; a voltage-controlled oscillator connected to the phase detector; The second low-pass filter has an input end connected to the voltage-controlled oscillator and an output end connected to the data sampling circuit.

25. A chip system, characterized in that: include: a communication interface for inputting and / or outputting information; A processor, configured to execute a computer program so that a device equipped with the chip system executes the method according to any one of claims 13 to 24.

26. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction, and when the computer program or instruction is executed, the method according to any one of claims 13 to 24 is implemented.

27. A transmitter, characterized in that: include: The communication device according to any one of claims 1 to 12.

28. A base station, characterized in that: include: The communication device according to any one of claims 1 to 12.

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