Test fixture

Abstract

The invention provides a test fixture which can be applied to the technical field of testing. The test fixture comprises a fixture body; the serial bus interface is arranged on the first surface of the jig body, and the serial bus interface is connected to a circuit to be tested; the first test interface and the second test interface are arranged on the second surface of the jig body, the first test interface receives a test signal, and the second test interface is connected to first test equipment; wherein the test signal is transmitted to the to-be-tested circuit through the first test interface and the serial bus interface, and the to-be-tested circuit generates an output signal based on the test signal and outputs the output signal to the serial bus interface, so that the output signal is transmitted to the first test device through the serial bus interface and the second test interface. And the first test device determines a first test result of the to-be-tested circuit based on the output signal.

Description

Technical Field

[0001] The present disclosure relates to the field of testing technology, and in particular to a testing fixture. Background Art

[0002] In order to meet the development needs of artificial intelligence technology, relevant personnel have defined an OCP accelerator module (OpenCompute Project Accelerator Module, OAM) to standardize the interface standard and appearance of the graphics processing unit (GPU) through the accelerator module. During the research and development process, it is necessary to perform multiple tests on the accelerator module and the universal baseboard (UBB). However, it is difficult to perform consistency tests on the accelerator module and the universal baseboard in related technologies. Summary of the invention

[0003] In view of the above problems, the present disclosure provides a test fixture.

[0004] According to one aspect of the present disclosure, a test fixture is provided, comprising: a fixture body; a serial bus interface, which is arranged on the first surface of the fixture body, and the serial bus interface is connected to a circuit to be tested; and a first test interface and a second test interface, which are arranged on the second surface of the fixture body, the first test interface receives a test signal, and the second test interface is connected to a first test device; wherein the test signal is transmitted to the circuit to be tested via the first test interface and the serial bus interface, the circuit to be tested generates an output signal based on the test signal, and outputs the output signal to the serial bus interface, so that the output signal is transmitted to the first test device via the serial bus interface and the second test interface, and the first test device determines a first test result of the circuit to be tested based on the output signal.

[0005] According to an embodiment of the present disclosure, the above-mentioned serial bus interface includes multiple pins; a first pin among the above-mentioned multiple pins is connected to the above-mentioned first test interface via the wiring inside the above-mentioned controller body, and the above-mentioned first pin is used to transmit the test signal transmitted via the above-mentioned first test interface to the above-mentioned circuit to be tested; and a second pin among the above-mentioned multiple pins is connected to the above-mentioned second test interface via the wiring inside the above-mentioned controller body, and the above-mentioned second pin is used to transmit the output signal from the above-mentioned circuit to be tested to the above-mentioned first test device.

[0006] According to an embodiment of the present disclosure, the first surface and the second surface are relative surfaces of the treatment body, the first test interface and the second test interface are arranged in a test interface area of ​​the second surface, and a projection of the serial bus interface on the second surface at least partially overlaps with the test interface area.

[0007] According to an embodiment of the present disclosure, the serial bus interface of the above-mentioned test fixture includes a first serial bus interface and a second serial bus interface; wherein, the projection of the above-mentioned first serial bus interface on the above-mentioned second surface is within the above-mentioned test interface area, and the projection of the above-mentioned second serial bus interface on the above-mentioned second surface is outside the above-mentioned test interface area.

[0008] According to an embodiment of the present disclosure, the above-mentioned test interface area includes a first sub-area and a second sub-area, the above-mentioned first test interface is arranged in the above-mentioned first sub-area, the above-mentioned second test interface is arranged in the above-mentioned second sub-area, and the projection of the above-mentioned first serial bus interface on the above-mentioned second surface does not overlap with the above-mentioned first sub-area, and at least partially overlaps with the above-mentioned second sub-area; wherein, the projection of the above-mentioned first serial bus interface on the above-mentioned second sub-area does not overlap with the above-mentioned second test interface.

[0009] According to an embodiment of the present disclosure, the first surface and the second surface are located in the same plane, and the first test interface and the second test interface are arranged adjacent to the serial bus interface.

[0010] According to an embodiment of the present disclosure, the test fixture further includes a power supply module, which is disposed on the second surface of the fixture body; the serial bus interface includes a plurality of pins, a third pin among the plurality of pins is connected to the power supply module via a wiring inside the fixture body, and the third pin is used to transmit the power supply voltage from the power supply module to the circuit to be tested, so as to power the circuit to be tested.

[0011] According to an embodiment of the present disclosure, the above-mentioned first test device includes an oscilloscope, and the above-mentioned test fixture also includes a pulse output interface; wherein the above-mentioned pulse output interface is connected to the above-mentioned first test interface to use the pulse signal output by the above-mentioned pulse output interface as the above-mentioned test signal.

[0012] According to an embodiment of the present disclosure, the above-mentioned first test equipment includes a bit error meter, and the above-mentioned test fixture also includes a clock signal interface; wherein, the clock input terminal of the above-mentioned bit error meter is connected to the above-mentioned clock signal interface, the data output terminal of the above-mentioned bit error meter is connected to the above-mentioned first test interface, and the data input terminal of the above-mentioned bit error meter is connected to the above-mentioned second test interface; the above-mentioned bit error meter is configured to: generate the above-mentioned test signal based on the clock signal from the above-mentioned clock signal interface; output the above-mentioned test signal via the above-mentioned data output terminal; receive the above-mentioned output signal via the above-mentioned data input terminal; and generate the above-mentioned first test result based on the above-mentioned test signal and the above-mentioned output signal.

[0013] According to an embodiment of the present disclosure, the test fixture further includes a first differential line and a second differential line; the first differential line and the second differential line are connected to a second test device, so that the second test device determines the loss information between the serial bus interface and the test interface based on the differential signal received via the first differential line and the second differential line, and the second test device sends the loss information to the first test device, so that the first test device compensates for the first test result based on the loss information to obtain a second test result.

[0014] According to an embodiment of the present disclosure, the serial bus interface of the test fixture is electrically connected to the circuit to be tested, and the first test interface of the test fixture receives a test signal, so that the test signal can be transmitted to the circuit to be tested via the first test interface and the serial bus interface. The circuit to be tested generates an output signal based on the test signal and outputs the output signal to the serial bus interface, so as to transmit the output signal to the first test device via the serial bus interface and the second test interface, thereby obtaining a first test result and realizing the test of the circuit to be tested. As an instrument electrically connected to the circuit to be tested during the operation of the circuit to be tested, the test fixture can test the circuit to be tested during the operation of the circuit to be tested, thereby ensuring the test effect of the circuit to be tested, and making the circuit to be tested that passes the test stably adapt to various devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0016] Figure 1A A schematic diagram of a test fixture according to an embodiment of the present disclosure is schematically shown.

[0017] Figure 1B A schematic diagram of a first pin and a second pin according to an embodiment of the present disclosure is schematically shown.

[0018] Figure 2AThe diagram schematically shows a first surface of a test fixture according to an embodiment of the present disclosure.

[0019] Figure 2B The diagram schematically shows a second surface of a test fixture according to an embodiment of the present disclosure.

[0020] Figure 3A The diagram schematically shows a second surface of a test fixture according to another embodiment of the present disclosure.

[0021] Figure 3B A schematic diagram of a universal substrate according to an embodiment of the present disclosure is schematically shown.

[0022] Figure 3C The figure schematically shows the connection between the universal substrate and the test fixture according to the embodiment of the present disclosure.

[0023] Figure 4A The figure schematically shows a connection diagram of a TX consistency test according to an embodiment of the present disclosure.

[0024] Figure 4B The figure schematically shows a connection diagram of an RX consistency test according to an embodiment of the present disclosure.

[0025] Figure 5A A schematic diagram of a test fixture according to another embodiment of the present disclosure is schematically shown.

[0026] Figure 5B A schematic diagram of a first surface of an OAM module according to an embodiment of the present disclosure is schematically shown.

[0027] Figure 5C A schematic diagram of the second surface of the OAM module according to an embodiment of the present disclosure is schematically shown.

[0028] Fig. 6A A connection diagram of a TX consistency test according to another embodiment of the present disclosure is schematically shown.

[0029] Figure 6B A connection diagram of an RX consistency test according to another embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0031] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0032] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0033] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0034] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0035] During the R&D process, if the designed universal baseboard passes the consistency test, the universal baseboard can be adapted to a variety of OCP accelerator modules. If the designed OCP accelerator module passes the consistency test, the OCP accelerator module can be used on a variety of universal baseboards. The consistency test can include TX (transmit) consistency test and RX (receive) consistency test.

[0036] In view of this, the present invention provides a test fixture that can implement consistency testing of an OCP accelerator module and a universal substrate. By performing consistency testing on the OCP accelerator module and the universal substrate, the signal quality of the OCP accelerator module and the universal substrate can be guaranteed.

[0037] like Figure 1A As shown, the test fixture 100 of this embodiment includes: a fixture body 110, a serial bus interface S, a first test interface T1 and a second test interface T2.

[0038] In the embodiments of the present disclosure, the serial bus interface S may be a high-speed differential signal interface. The present disclosure may use a Mirror Mezz connector, i.e., a mirror-type mezzanine connector, as the serial bus interface S. However, it should be understood that the Mirror Mezz connector here is only an example and does not necessarily mean that the present disclosure will use a Mirror Mezz connector during implementation. The present disclosure may also use a connector with similar functions to the Mirror Mezz connector as the serial bus interface S.

[0039] The serial bus interface S is disposed on the first surface 111 of the body 110 and is connected to the circuit under test on the first surface 111. The circuit under test may be the above-mentioned OCP accelerator module or the above-mentioned universal substrate. The signal may be a PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) signal.

[0040] The first test interface T1 and the second test interface T2 may be RF coaxial interfaces. The present disclosure may use an MMPX connector as the first test interface T1 and the second test interface T2. However, it should be understood that the MMPX connector here is only an example and does not necessarily mean that the present disclosure uses an MMPX connector during implementation. The present disclosure may also use a connector with a function similar to that of the MMPX connector as the first test interface T1 and the second test interface T2.

[0041] The first test interface T1 and the second test interface T2 are arranged on the second surface 112 of the treatment body 110. The second surface 112 and the first surface 111 may be located in the same plane or in different planes, which is not limited in the present disclosure. The first test interface T1 may be electrically connected to the first test device TM or other interface on the second surface 112 to receive a test signal from the first test device TM or other interface. The second test interface T2 may be electrically connected to the first test device TM on the second surface 112.

[0042] Through the above connection mode, the test signal can be transmitted to the circuit under test via the first test interface T1 and the serial bus interface S. The circuit under test generates an output signal based on the test signal, and outputs the output signal to the serial bus interface S, so that the output signal is transmitted to the first test device TM via the serial bus interface S and the second test interface T2. The first test device TM determines a first test result of the circuit under test based on the output signal.

[0043] In the embodiment of the present disclosure, the serial bus interface S of the test fixture 100 is electrically connected to the circuit to be tested, and the first test interface T1 of the test fixture 100 receives the test signal, so that the test signal can be transmitted to the circuit to be tested via the first test interface T1 and the serial bus interface S, and the circuit to be tested generates an output signal based on the test signal and outputs the output signal to the serial bus interface S, so as to transmit the output signal to the first test device TM via the serial bus interface S and the second test interface T2, thereby obtaining a first test result, and realizing the test of the circuit to be tested. The test fixture 100 is an apparatus electrically connected to the circuit to be tested during the operation of the circuit to be tested, and can test the circuit to be tested during the operation of the circuit to be tested, thereby ensuring the test effect of the circuit to be tested, so that the circuit to be tested that passes the test is stably adapted to various devices. For example, the test fixture of the present disclosure can be used as an OCP accelerator module to perform consistency testing on a universal substrate without interfering with other OCP accelerator modules. Alternatively, the test fixture provided by the present disclosure can be used as a universal substrate to perform consistency testing on an OCP accelerator module without interfering with other universal substrates. Therefore, a universal substrate that passes the consistency test can be stably adapted to a variety of OCP accelerator modules, or an OCP accelerator module that passes the consistency test can be stably adapted to a variety of universal substrates.

[0044] like Figure 1B As shown, the serial bus interface S may include a plurality of pins, for example, may include a first pin P1 and a second pin P2. The first pin P1 is connected to the first test interface T1 via a wiring inside the controller body 110. The first pin P1 is used to transmit a test signal transmitted via the first test interface T1 to the circuit to be tested. For example, the wiring inside the controller body 110 is a PCB (Printed Circuit Board) wiring. The second pin P2 is connected to the second test interface T2 via a wiring inside the controller body 110. The second pin P2 is used to transmit an output signal from the circuit to be tested to the first test device TM.

[0045] In the embodiment of the present disclosure, there may be multiple serial bus interfaces S. Figure 2A As shown, in the first surface 210 of this embodiment, a first serial bus interface S1 and a second serial bus interface S2 are provided. The first serial bus interface S1 and the second serial bus interface S2 are electrically connected to the circuit under test on the first surface 210 .

[0046] like Figure 2B As shown, in this embodiment, the first test interface T1 and the second test interface T2 can be arranged in the test interface area located on the second surface 220. The test interface area includes a first sub-area 221 and a second sub-area 222. The first test interface T1 is in the first sub-area 221, and the second test interface T2 is in the second sub-area 222.

[0047] On this basis, the test fixtures in the two embodiments of the present disclosure can test the OCP accelerator module and the universal substrate respectively. For example, the test fixture used as the compliance load board (CLB) in the present disclosure can be used to test the universal substrate. Figure 3A to Figure 4B Provide explanation.

[0048] Figure 3A The second surface 310 shown includes a first sub-area 311 provided with a first test interface T1 and a second sub-area 312 provided with a second test interface T2. In addition, the second surface 310 also includes a pulse output interface TC, a clock signal interface CLK, a first differential line TR1 and a second differential line TR2 of a pulse output module. The pulse output module can be implemented based on the Toggle Clock standard, and it should be understood that this is only an example. The pulse output module can be used to generate a pulse signal. The frequency of the pulse signal can be and is not limited to 100MHz. The first differential line TR1 and the second differential line TR2 are electrically connected to the second test device so that the second test device determines the loss information between the serial bus interface and the test interface (i.e., the first test interface T1 or the second test interface T2 mentioned above) based on the differential signal received via the first differential line TR1 and the second differential line TR2. The loss information characterizes the signal transmission loss between the serial bus interface and the test interface.

[0049] For example, the second test device may be a vector network analyzer (VNA). The first differential line TR1 and the second differential line TR2 are passive lines of different lengths. The first differential line TR1 may include a differential line for input signals and a differential line for output signals. By electrically connecting the above two differential lines of the first differential line TR1 to the vector network analyzer, the signal parameters of the first differential line TR1 may be measured. Similarly, the signal parameters of the second differential line TR2 may be obtained in the same manner. The difference between the signal parameters of the first differential line TR1 and the signal parameters of the second differential line TR2 is determined by using a predetermined algorithm. The difference may be determined as the above loss information. The second test device may be electrically connected to the second test device, and the second test device sends the loss information to the first test device TM, so that the first test device TM compensates for the first test result based on the loss information to obtain the second test result, thereby improving the accuracy of the test.

[0050] like Figure 3B and Figure 3CAs shown, the universal substrate 320 to be tested includes multiple areas, each area includes two interfaces. The first serial bus interface S1 and the second serial bus interface S2 of the test fixture can be connected to two interfaces in any area of ​​the multiple areas. In the embodiment of the present disclosure, the first surface and the second surface of the fixture are relative surfaces of the fixture. In addition, there is a predetermined interval between the first serial bus interface S1 and the second serial bus interface S2 of the first surface of the test fixture, and the predetermined interval can be determined based on the interval between the two interfaces in the same area on the surface of the universal substrate 320. The test fixture can be inserted into the interface of any area of ​​the universal substrate 320 through the first serial bus interface S1 and the second serial bus interface S2, so that the test fixture and the universal substrate 320 are electrically connected. Since the predetermined interval between the first serial bus interface S1 and the second serial bus interface S2 is determined based on the interval between the two interfaces in the same area on the surface of the universal substrate 320, the test fixture can be fixed on the surface of the universal substrate 320. When the test fixture and the universal substrate 320 are electrically connected, the first surface of the test fixture faces the universal substrate 320, thereby being covered by the surface of the universal substrate 320. The second surface 310 of the test fixture is not covered by the surface of the universal substrate 320 , and the interface on the second surface 310 of the test fixture can be electrically connected to the first test equipment TM or other interfaces through a cable.

[0051] Optionally, the first test interface T1 and the second test interface T2 are arranged in a test interface area of ​​the second surface, and a projection of the serial bus interface S on the second surface 310 at least partially overlaps with the test interface area.

[0052] For example, the projections of the first serial bus interface S1 and the second serial bus interface S2 on the second surface 310 are both within the test interface area. However, the embodiments of the present disclosure are not limited thereto. For the test scenario of the PCIe signal of the universal substrate 320, only the positional relationship between the projection of one of the first serial bus interface S1 and the second serial bus interface S2 on the second surface 310 and the test interface area is concerned. For example, the projection of the first serial bus interface S1 on the second surface 310 is within the test interface area, and the projection of the second serial bus interface S2 on the second surface 310 is outside the test interface area. Thus, the PCIe signal is mainly transmitted through the first serial bus interface S1, the first test interface T1, and the second test interface T2. The second serial bus interface S2 is not connected to the first test interface T1 and the second test interface T2. For example, the projection of the first serial bus interface S1 on the second surface 310 does not overlap with the first sub-area 311, and at least partially overlaps with the second sub-area 312. The projection of the first serial bus interface S1 in the second sub-area 312 does not overlap with the second test interface T2, so that the wiring between the first serial bus interface S1 and the second test interface T2 can be arranged inside the fixture, so that the space inside the fixture can be fully utilized to lay out the wiring, and the size of the test fixture can be made as small as possible, reducing the loss of signals transmitted through the wiring. Based on this, the consumption of production resources of the test fixture can be reduced, which is suitable for batch production of test fixtures.

[0053] like Figure 4A As shown, the first test device TM includes an oscilloscope Scope. The circuit to be tested is a universal substrate. When the oscilloscope Scope is used to perform a TX consistency test on the universal substrate, the pulse output interface TC is connected to the first test interface T1 in the first sub-area 411, so that the pulse signal output by the pulse output interface TC is used as a test signal. The pulse output module can realize the function of switching Preset during the TX consistency test. For example, the test fixture can also be provided with a trigger corresponding to the trigger pulse module, and when the trigger is triggered, the pulse output module outputs a pulse signal. The pulse signal is transmitted to the first test interface T1 via the pulse output interface TC, and is transmitted to the universal substrate via the first test interface T1 and the serial bus interface S. The universal substrate generates an output signal based on the initial signal (for example, a PCIe signal) and the test signal generated by itself during the working process, and outputs the output signal to the serial bus interface S, so as to transmit the output signal to the oscilloscope Scope via the serial bus interface S and the second test interface T2 in the second sub-area 412. The oscilloscope Scope calls a preset program to process the output signal, thereby obtaining a first test result.

[0054] like Figure 4BAs shown, the first test device TM includes a bit error meter BERT. In the case of using the bit error meter BERT to perform an RX consistency test on the universal substrate, the clock input terminal RC of the bit error meter BERT is connected to the clock signal interface CLK, the data output terminal PPG of the bit error meter BERT is connected to the first test interface T1 in the first sub-area 411, and the data input terminal ED of the bit error meter BERT is connected to the second test interface T2 in the second sub-area 412. The bit error meter BERT generates a test signal based on the clock signal from the clock signal interface CLK, outputs the test signal via the data output terminal PPG, receives the output signal via the data input terminal ED, and generates a first test result based on the test signal and the output signal. For example, the test signal can be a PPG (Pulse Position Generator) signal. The test signal is transmitted to the universal substrate via the first test interface T1 and the serial bus interface S. The universal substrate generates an output signal based on the initial signal and the test signal generated by itself during the working process, and outputs the output signal to the serial bus interface S, so as to transmit the output signal to the bit error meter BERT via the serial bus interface S and the second test interface T2. The bit error detector BERT can call a preset program to analyze the output test signal and the received output signal to obtain a first test result.

[0055] For example, the test fixture used as the compliance base board (CBB) in the present disclosure can be used to test the OCP accelerator module. Figure 5A to Figure 6B Provide explanation.

[0056] exist Figure 5A In the test fixture 510 shown, the first surface and the second surface are located in the same plane, and the first test interface T1 and the second test interface T2 are arranged adjacent to the serial bus interface S. In addition to the first test interface T1, the second test interface T2 and the serial bus interface S, the test fixture 510 also includes a clock signal interface CLK, a pulse output module, a first differential circuit TR1, a second differential circuit TR2 and a power module VDD. Among them, the functions of the clock signal interface CLK, the pulse output module, the first differential circuit TR1 and the second differential circuit TR2 can refer to the previous description, and will not be repeated here. Since the OCP accelerator module itself is not provided with a power supply, the test fixture can use the power module provided by itself to power the OCO accelerator module. For example, the power module VDD is arranged on the second surface of the fixture. The multiple pins of the serial bus interface S may also include a third pin, and the third pin may be connected to the power module VDD via the wiring inside the fixture. The third pin is used to transmit the power supply voltage from the power module VDD to the circuit to be tested to power the circuit to be tested.

[0057] like Figure 5A , Figure 5B , Figure 5C and Fig. 6A As shown, the OCP accelerator module is provided with an interface facing the test fixture 510, so that the interface of the accelerator module is inserted into the serial bus interface S of the test fixture 510, so that the interface of the accelerator module is electrically connected to the serial bus interface S of the test fixture 510. In the case of performing a TX consistency test on the accelerator module, the pulse output interface TC is connected to the first test interface in the first sub-area 511, so as to use the pulse signal output by the pulse output interface as a test signal. The pulse signal is transmitted to the first test interface T1 via the clock signal interface CLK, and is transmitted to the OCP accelerator module via the first test interface T1 and the serial bus interface S. The OCP accelerator module generates an output signal based on the initial signal and the test signal generated by itself during the working process, and outputs the output signal to the serial bus interface S, so as to transmit the output signal to the oscilloscope Scope via the serial bus interface S and the second test interface T2 in the second sub-area 512. The oscilloscope Scope calls a preset program to process the output signal, thereby obtaining a first test result.

[0058] like Figure 6B As shown, the first test device TM includes a bit error meter BERT. When the bit error meter BERT is used to perform an RX consistency test on the accelerator module, the clock input terminal RC of the bit error meter BERT is connected to the clock signal interface CLK, the data output terminal PPG of the bit error meter BERT is connected to the first test interface T1 in the first sub-area 511, and the data input terminal ED of the bit error meter BERT is connected to the second test interface T2 in the second sub-area 512. The bit error meter BERT generates a test signal based on the clock signal from the clock signal interface CLK, outputs the test signal via the data output terminal PPG, receives the output signal via the data input terminal ED, and generates a first test result based on the test signal and the output signal. For example, the test signal can be a PPG (Pulse Position Generator) signal. The test signal is transmitted to the OCP accelerator module via the first test interface T1 and the serial bus interface S. The OCP accelerator module generates an output signal based on the initial signal and the test signal generated by itself during the working process, and outputs the output signal to the serial bus interface S, so as to transmit the output signal to the bit error detector BERT via the serial bus interface S and the second test interface T2. The bit error detector BERT can call a preset program to analyze the test signal output by the data output terminal PPG and the output signal received by the data input terminal ED, so as to obtain a first test result.

[0059] In the embodiments of the present disclosure, based on the small size and cable connection method of the test fixture of the present disclosure, when the OCP accelerator module or the universal substrate is tested using the test fixture, no structural interference with other modules or devices occurs, and the connection relationship between the OCP accelerator module or the universal substrate to be tested and other devices or modules can be ensured.

[0060] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0061] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A test fixture, characterized in that: The test fixture includes: Treat specific; A serial bus interface, disposed on the first surface of the treatment body, the serial bus interface being connected to the circuit to be tested; and A first test interface and a second test interface are arranged on the second surface of the treatment body, the first test interface receives a test signal, and the second test interface is connected to a first test device; The test signal is transmitted to the circuit under test via the first test interface and the serial bus interface, the circuit under test generates an output signal based on the test signal, and outputs the output signal to the serial bus interface, so that the output signal is transmitted to the first test device via the serial bus interface and the second test interface, and the first test device determines a first test result of the circuit under test based on the output signal.

2. The test fixture according to claim 1, characterized in that: The serial bus interface includes a plurality of pins; A first pin among the plurality of pins is connected to the first test interface via a wiring inside the controller, and the first pin is used to transmit a test signal transmitted via the first test interface to the circuit under test; and A second pin among the plurality of pins is connected to the second test interface via a wiring inside the controller, and the second pin is used to transmit an output signal from the circuit under test to the first test device.

3. The test fixture according to claim 1 or 2, characterized in that: The first surface and the second surface are opposite surfaces of the treatment body, the first test interface and the second test interface are arranged in a test interface area of ​​the second surface, and a projection of the serial bus interface on the second surface at least partially overlaps with the test interface area.

4. The test fixture according to claim 3, characterized in that: The serial bus interface of the test fixture includes a first serial bus interface and a second serial bus interface; The projection of the first serial bus interface on the second surface is within the test interface area, and the projection of the second serial bus interface on the second surface is outside the test interface area.

5. The test fixture according to claim 4, characterized in that: The test interface area includes a first sub-area and a second sub-area, the first test interface is arranged in the first sub-area, the second test interface is arranged in the second sub-area, and a projection of the first serial bus interface on the second surface does not overlap with the first sub-area, and at least partially overlaps with the second sub-area; The projection of the first serial bus interface in the second sub-area does not overlap with the second test interface.

6. The test fixture according to claim 1 or 2, characterized in that: The first surface and the second surface are located in the same plane, and the first test interface and the second test interface are arranged adjacent to the serial bus interface.

7. The test fixture according to claim 6, characterized in that: The test fixture further comprises a power supply module, and the power supply module is arranged on the second surface of the fixture body; The serial bus interface includes multiple pins, a third pin among the multiple pins is connected to the power module via a wiring inside the controller, and the third pin is used to transmit the power supply voltage from the power module to the circuit under test to power the circuit under test.

8. The test fixture according to claim 1 or 2, characterized in that: The first test equipment includes an oscilloscope, and the test fixture also includes a pulse output interface; The pulse output interface is connected to the first test interface so that the pulse signal output by the pulse output interface is used as the test signal.

9. The test fixture according to claim 1 or 2, characterized in that: The first test equipment includes a bit error meter, and the test fixture also includes a clock signal interface; Wherein, the clock input end of the bit error meter is connected to the clock signal interface, the data output end of the bit error meter is connected to the first test interface, and the data input end of the bit error meter is connected to the second test interface; The BERT configuration is: generating the test signal based on the clock signal from the clock signal interface; outputting the test signal via the data output terminal; receiving the output signal via the data input terminal; and The first test result is generated based on the test signal and the output signal.

10. The test fixture according to claim 1 or 2, characterized in that: The test fixture further includes a first differential circuit and a second differential circuit; The first differential line and the second differential line are connected to a second test device so that the second test device determines loss information between the serial bus interface and the test interface based on differential signals received via the first differential line and the second differential line, and the second test device sends the loss information to the first test device so that the first test device compensates for the first test result based on the loss information to obtain a second test result.

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