Detection method and detection system for chip early failure

Abstract

The invention provides a detection method, a detection system, a detection device and a computer readable storage medium for chip failure in the early period, and the detection method comprises the following steps: firstly, carrying out chip testing on a plurality of chips in at least one test wafer, according to a chip testing result, judging the chip with the chip testing result conforming to a test specification as a good chip, and according to the chip testing result, judging the chip with the chip testing result conforming to the test specification as a non-defective chip; judging the chips of which the chip test results do not conform to the test specifications as invalid chips; and carrying out after-test detection and analysis on the qualified chips and the invalid chips after the chip test, and determining potential early-stage invalid chips from the qualified chips. Compared with the prior art, the method and the device have the advantages that the good chips and the failure chips can be detected and analyzed after the chips are tested, the potential failure conditions of the good chips are fully considered, the potential early failure chips are determined from the good chips through certain analysis, quality accidents caused by failure at a client can be avoided, and the detection efficiency is improved. The method has the advantages of simple detection, rapidness, high efficiency, reliability and the like.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip premature failure detection method, detection system, detection equipment, and computer-readable storage medium. Background Art

[0002] In order to verify the performance and reliability of each die (i.e. chip) on the wafer, the chip needs to be tested. The failure rate of integrated circuit (IC) chips and electronic devices containing these IC chips usually takes the shape of the so-called bathtub curve. For example, the early failure of a chip refers to the period when many chip products have a relatively high failure rate at the beginning of their use, and the failure rate has the characteristic of rapidly decreasing. Early failure has a great impact on user experience, manufacturer's profits and reputation, so the testing and screening of early failure chips is crucial to product quality.

[0003] Early failure test of chips is a type of chip test, which is used to screen defective chips with early failure. At present, the industry can use aging test (Burn-in Test), early failure rate (EFR), high voltage stress test (HVS), dynamic part average test (DPAT), etc. However, in related technologies, the detection accuracy is not high, and the potential quality risks of chips cannot always be effectively detected. Taking the DPAT test of chips on wafers as an example, it is to sample and test the chips on the wafers by batch and perform data statistics to determine the specification threshold applicable to the current batch of chips. The specification threshold is used as a criterion to screen the abnormal products of the current batch of chips, and the test item values ​​in a batch that seriously deviate from the overall distribution are defined as abnormal products, and the chips that meet the requirements are defined as good products. However, in actual applications, the test results of chips often differ due to the drift of related process parameters, resulting in changes in data distribution. The simple and general use of the existing DPAT test method will inevitably result in missed judgments or misjudgments, resulting in the outflow of abnormal products or defective products, bringing uncontrollable risks. If good products are tested a second or third time, the testing process becomes complicated, increasing testing time and cost, and may damage the chip. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the related art, the purpose of the present disclosure is to provide a chip premature failure detection method, detection system, detection equipment, and computer-readable storage medium to solve various problems in the related art.

[0005] The first aspect of the present disclosure provides a method for detecting premature failure of a chip, comprising the following steps:

[0006] Performing chip testing on a plurality of chips in at least one test wafer, and obtaining chip test results of the plurality of chips based on a chip test determination means;

[0007] According to the chip test results, the chips whose chip test results meet the test specifications are determined as good chips, and the chips whose chip test results do not meet the test specifications are determined as failed chips; and

[0008] Post-test detection and analysis are performed on good chips and failed chips, and potential premature failed chips are identified from the good chips.

[0009] In certain examples of the first aspect, the chip testing of multiple chips in at least one test wafer includes the following steps: providing at least one test wafer, each test wafer having multiple chips; selecting test items, executing the test program corresponding to the selected test items to perform chip testing on the multiple chips in at least one test wafer, and obtaining test data for each chip based on chip test judgment means.

[0010] In certain examples of the first aspect, the chip test results that meet the test specifications are determined as good chips, and the chips that do not meet the test specifications are determined as failed chips, according to the chip test results, including the following steps: for each chip, comparing the test data of the chip in the test item with the test specification of the test item; if the test data of the chip in the test item is within the allowable range of the test specification of the test item, it indicates that the chip has passed the test of the test item, and the chip is determined to be a good chip; if the test data of the chip in the test item exceeds the allowable range of the test specification of the test item, it indicates that the chip has not passed the test of the test item, and the chip is determined to be a failed chip.

[0011] In some examples of the first aspect, when a chip test includes multiple test items, currently, the chip can be determined as a good chip only if the chip passes the tests of all the test items.

[0012] In some examples of the first aspect, the test items include: one or more of a high voltage stress test, an aging test, and an early failure rate test.

[0013] In some examples of the first aspect, the chip test determination means includes one or more of a dynamic upper and lower limit test, a dynamic component average test, and a parameter difference comparison test.

[0014] In certain examples of the first aspect, the post-test inspection and analysis of good chips and failed chips to determine potential prematurely failed chips from the good chips includes the following steps: collecting information related to chip testing, the information including: position information of at least one test wafer and position information of good chips and failed chips on each test wafer; selecting a post-test inspection and analysis means and executing the selected post-test inspection and analysis means to determine potential prematurely failed chips based on the collected information related to chip testing.

[0015] In certain examples of the first aspect, the post-test inspection and analysis of good chips and failed chips to determine potential prematurely failed chips from the good chips includes the following steps: selecting a post-test inspection and analysis means; collecting information related to the chip test according to the selected post-test inspection and analysis means, the information including: one or more of position information of at least one test wafer, position information of good chips on each test wafer, and position information of failed chips on each test wafer; executing the post-test inspection and analysis means to determine potential prematurely failed chips from the good chips according to the collected information related to the chip test.

[0016] In some examples of the first aspect, the post-test detection and analysis means include: Z-yield detection and analysis and / or clustering fault detection and analysis.

[0017] A second aspect of the present disclosure provides a chip premature failure detection system, comprising:

[0018] a chip testing module, configured to perform chip testing on a plurality of chips in at least one test wafer, obtain chip testing results of the plurality of chips based on a chip testing determination means, and, based on the chip testing results, determine a chip whose chip testing results meet the test specifications as a good chip and determine a chip whose chip testing results do not meet the test specifications as a failed chip; and

[0019] The post-test detection and analysis module is used to perform post-test detection and analysis on good chips and failed chips after chip testing, and to determine potential prematurely failed chips from the good chips.

[0020] A third aspect of the present disclosure provides a chip premature failure detection device, comprising: a processor; a memory storing a test program; wherein the test program is executed by the processor to execute the chip premature failure detection method as described above.

[0021] A fourth aspect of the present disclosure provides a computer-readable storage medium, characterized in that a computer program is stored therein, and when the computer program is executed, the method for detecting premature chip failure as described above is executed.

[0022] As described above, the present disclosure provides a method, system, device, and computer-readable storage medium for detecting premature failure of chips, which are used to detect premature failure of chips. The detection method includes: firstly performing chip testing on multiple chips in at least one test wafer, and judging the chips whose chip test results meet the test specifications as good chips, and judging the chips whose chip test results do not meet the test specifications as failed chips according to the chip test results; then performing post-test detection and analysis on the good chips and failed chips after the chip test, and determining potential premature failure chips from the good chips. Compared with the related art, the present disclosure can perform post-test detection and analysis on good chips and failed chips after chip testing, fully considering the potential failure of good chips, and through certain analysis, determining potential premature failure chips from the good chips, which can avoid quality accidents caused by failure on the client side, and has the advantages of simple, fast, efficient, and reliable detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a principle block diagram of an embodiment of the chip premature failure detection technology disclosed in the present invention.

[0024] Figure 2 It is a schematic diagram showing the flow of a method for detecting premature failure of a chip disclosed in one embodiment.

[0025] Figure 3 It is a functional schematic diagram of an embodiment of a chip premature failure detection system disclosed in the present invention.

[0026] Figure 4 It is a schematic diagram showing the structure of a chip premature failure detection device in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0028] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0031] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0032] Throughout the specification, unless otherwise clearly specified and limited, the terms "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Furthermore, when a certain device is said to “include” a certain component, unless otherwise stated, it does not exclude other components but means that other components may be included.

[0034] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0035] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0036] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0037] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0038] The manufacturing process of chips is complex and involves many steps. Therefore, defective chips are inevitably produced during the manufacturing process. Some defective chips perform normally during initial use, but after a period of use, defects will be stimulated, causing the chip to fail. This phenomenon of failure in the early stage of use is called early failure or premature failure of the chip. This type of defective chip appears to be a good product during factory inspection, but fails prematurely when it is put on the market and used, affecting customers. In order to solve the problem of early failure of chips, early failure tests of chips can be performed to screen out defective chips.

[0039] Early failure tests of chips are usually completed before they leave the factory. In the related technologies involving early failure tests of chips, the test results of chips often differ due to the drift of related process parameters, resulting in changes in data distribution, which inevitably lead to missed judgments or misjudgments, resulting in the outflow of abnormal or defective products, bringing uncontrollable risks. If the chip is tested repeatedly, the test process will be complicated, increasing the test time and test costs, and may damage the chip.

[0040] In view of this, the embodiments of the present disclosure provide a chip premature failure detection method, detection system, detection equipment, and computer-readable storage medium, which, compared with related chip early failure tests, have the advantages of simple detection, rapidity, efficiency, and reliability.

[0041] The embodiments of the present disclosure provide a method and system for detecting premature failure of a chip.

[0042] See also Figure 1 , which is a principle block diagram of an embodiment of the chip premature failure detection technology disclosed in the present invention.

[0043] like Figure 1 As shown, in the embodiment of the present disclosure, chip testing is first performed on each chip of the wafer, and after the chip testing, post-test detection and analysis are performed, so that potential premature failure chips can be identified from good chips.

[0044] The following is a detailed description of a chip premature failure detection method and a detection system provided in accordance with an embodiment of the present disclosure.

[0045] See also Figure 2 , which is a schematic diagram of the flow chart of a method for detecting premature failure of a chip disclosed in one embodiment.

[0046] like Figure 2 As shown, the method for detecting premature failure of a chip disclosed in the present invention comprises the following steps:

[0047] Step S201 , performing chip testing on multiple chips in at least one test wafer, and obtaining chip test results of the multiple chips based on a chip test determination means.

[0048] In step S201, chip testing is performed on multiple chips on a wafer to be tested to detect corresponding performances of the chips.

[0049] In some embodiments, performing chip testing on a plurality of chips in at least one test wafer in step S201 may further include the following steps:

[0050] First, at least one test wafer is provided, each test wafer having a plurality of chips.

[0051] There may be multiple test wafers, each of which includes multiple chips. The number of test wafers and the number of chips can at least reflect the statistical law of failed chips. Therefore, the number of test wafers and the number of chips must meet certain requirements. Exemplarily, a batch of test wafers is selected, and the number of test wafers in the batch is at least one box. The number of test wafers in each box of wafers may be, for example, 25 (pieces). The number of chips arranged on each wafer may be greater than or equal to 100 or more (for example, 200, 300, 400, 500, 600, 700, 800, 900, 1000, etc.).

[0052] Next, a test item is selected, and a test program corresponding to the selected test item is executed to perform chip testing on a plurality of chips in at least one test wafer.

[0053] As mentioned above, the chip to be tested is a chip located on a wafer. Therefore, the test items used for the chip test on the wafer include but are not limited to: one or more of: High Voltage Stress (HVS), Burn-in Test, Early Failure Rate (EFR), etc.

[0054] Take the high voltage stress test HVS as an example. The HVS test gives the chip an operating voltage that exceeds the chip specification in a very short time, and at the same time gives some basic signals required by the chip, so that the chip can operate under the excessively high operating voltage. When the chip operates under an excessively high operating voltage, the defects of the chip can be deteriorated in a very short time, thereby finding the defective chip.

[0055] Burn-in Test uses high-temperature aging to stimulate potential defects hidden in chips, accelerate their exposure, and eliminate those chips that fail early before use to improve the reliability level of the batch of chips.

[0056] A certain test item is selected to perform chip testing, and based on the chip testing determination means, chip testing results of the plurality of chips are obtained.

[0057] In some implementations, the chip test determination means include, but are not limited to: one or more of: dynamic upper and lower limit testing, dynamic part average testing (Dynamic Part Average Testing, DPAT), and parameter difference comparison testing.

[0058] Taking the dynamic upper and lower limit test as an example, the dynamic upper and lower limit test is to perform sampling test and data statistics on the chips on the wafers in the same batch, and dynamically adjust the specification threshold of the current batch during the test. For example, before testing the chips in a batch of wafers, the specification threshold used is V0. As the chips on the wafers in the batch are tested, the specification threshold will be dynamically adjusted. For example, when testing the chips on a part of the wafers in the batch, the specification threshold will be dynamically adjusted to V1. As the chips on other wafers in the batch are tested, the specification threshold will be dynamically adjusted to V2.

[0059] Taking the dynamic part average test DPAT as an example, the DPAT test is to sample and test the chips on the wafer by batch and perform data statistics to determine the specification threshold applicable to the current batch of chips, that is, each chip in all wafers in the batch uses the same specification threshold when performing chip testing. For example, each chip on the first batch of wafers uses the first specification threshold when performing chip testing, and each chip on the second batch of wafers uses the second specification threshold when performing chip testing. The first specification threshold may be the same as or different from the second specification threshold. In this way, the specification threshold can be used as a criterion to screen the current batch of chips for abnormal products, and the test item values ​​within a batch that seriously deviate from the overall distribution are defined as abnormal products, and the chips that meet the requirements are defined as good products.

[0060] Step S203 , based on the chip test results, determining the chips whose chip test results meet the test specifications as good chips, and determining the chips whose chip test results do not meet the test specifications as failed chips.

[0061] In step S203, after chip testing is performed on multiple chips in each test wafer by executing the test program corresponding to the selected test item, test data of each chip can be obtained.

[0062] The test data of each chip obtained from the test is compared with the corresponding test specification of the chip. If the test data of the chip meets the corresponding test specification, that is, the test data of the chip is within the allowable range of the corresponding test specification, it indicates that the chip has passed the test of the test item, and the chip is determined to be a good chip. If the test data of the chip does not meet the corresponding test specification, that is, the test data of the chip exceeds the allowable range of the corresponding test specification, it indicates that the chip has not passed the test of the test item, and the chip is determined to be a failed chip.

[0063] In some embodiments, the determination results of each chip may be recorded.

[0064] When the chip test includes multiple test items, taking two test items as an example, the chip test of the first test item can be performed first, and each chip can be judged as a good chip or a failed chip based on the test result of the first test item, and then the chip test of the second test item can be performed, and each chip can be judged as a good chip or a failed chip based on the test result of the second test item.

[0065] In order to avoid quality accidents caused by chips that should be failed chips being judged as good chips due to missed judgments or misjudgments during the testing process, in some embodiments, we can make the following settings: when the chip test includes multiple test items, the chip can only be judged as a good chip if it passes the tests of all the test items. That is, as long as a chip fails the test in any test item, the chip is a failed chip.

[0066] Of course, the above is only an exemplary description and is not limited to this. In some embodiments, for example, when there are two test items, different weights can be assigned to the two test items, and the following settings can be made: when a chip passes the test item with a smaller weight but fails the test item with a larger weight, the chip is judged as a failed chip, and when a chip fails the test item with a smaller weight but passes the test item with a larger weight, the chip is judged as a good chip. In some embodiments, for example, when there are three test items, it can be set that as long as a chip passes at least two of the three test items, the chip can be judged as a good chip, otherwise, the chip is judged as a failed chip.

[0067] Step S205 , performing post-test inspection and analysis on good chips and failed chips, and determining potential prematurely failed chips from the good chips.

[0068] In some embodiments, performing post-test detection and analysis on good chips and failed chips, and determining potential premature failed chips from good chips, may further include the following steps:

[0069] First, information related to chip testing is collected, wherein the information includes: location information of at least one test wafer and location information of good chips and location information of failed chips on each test wafer.

[0070] The position information of the test wafer includes one or more of the batch of the test wafer, the position of the material box under the batch, and the position in the material box. The batch of the test wafer can be obtained by the batch number. The material box position under the batch can be, for example, the sequential position under the corresponding batch, which can be obtained by the material box number. The position in the material box refers to the position of the wafer slot storing the wafer.

[0071] The position information of the good chip refers to the position on the corresponding wafer, and the position information can be calibrated by, for example, two-dimensional coordinates.

[0072] The position information of the failed chip refers to the position on the corresponding wafer, and the position information can be calibrated by, for example, two-dimensional coordinates.

[0073] Next, a post-test detection and analysis method is selected and executed, and potential premature failure chips are determined from good chips based on the collected information related to chip testing.

[0074] In the aforementioned embodiment, the location information related to the chip test is first collected, and then a post-test detection and analysis method is selected to be executed to identify potential premature failure chips from good chips.

[0075] In some embodiments, performing post-test detection and analysis on good chips and failed chips, and determining potential premature failed chips from good chips, may further include the following steps:

[0076] First, choose a post-test detection and analysis method.

[0077] Next, according to the selected post-test detection and analysis means, information related to the chip test is collected, the information including: one or more of the position information of at least one test wafer, the position information of good chips on each test wafer, and the position information of failed chips on each test wafer.

[0078] The position information of the test wafer includes one or more of the batch of the test wafer, the position of the material box under the batch, and the position in the material box. The batch of the test wafer can be obtained by the batch number. The material box position under the batch can be, for example, the sequential position under the corresponding batch, which can be obtained by the material box number. The position in the material box refers to the position of the wafer slot storing the wafer.

[0079] The position information of the good chip refers to the position on the corresponding wafer, and the position information can be calibrated by, for example, two-dimensional coordinates.

[0080] The position information of the failed chip refers to the position on the corresponding wafer, and the position information can be calibrated by, for example, two-dimensional coordinates.

[0081] Next, the post-test detection and analysis means are performed to identify potential premature failure chips from good chips based on the collected information related to the chip test.

[0082] In the aforementioned embodiment, a post-test detection and analysis method is selected, and then the position information related to the chip test is first collected according to the selected post-test detection and analysis method, and the selected post-test detection and analysis method is executed to determine potential premature failure chips from good chips.

[0083] Regarding post-test detection and analysis means, in some embodiments, the post-test detection and analysis means may include: Z-yield detection and analysis, cluster fault detection and analysis, etc. In some optional embodiments, the cluster fault detection and analysis may further include, for example, GDBC (Good Die in a Bad Cluster), KBC (Kernal Based Cluster), NNR (Nearest Neighborhood Residual), etc. The above post-test detection and analysis means may be used alone or in combination with multiple means.

[0084] Taking Z-yield detection and analysis as an example, the Z-yield detection and analysis refers to the detection and analysis of each chip at the same position. In practical applications, the chip is detected and analyzed in the Z direction, that is, the chips at the same (consistent two-dimensional coordinates) position in different wafers are detected and analyzed. Generally, when the wafer is undergoing a process, if a large number of chips at a certain position fail, then the probability of failure of the chip at that position is high. Even if a chip is determined to be a good chip after chip detection, it still has a high risk of failure. Therefore, in some embodiments, by using Z-yield detection and analysis, the same failure position risk threshold (or good position risk threshold) can be set for the wafer, or a corresponding failure position risk threshold (or good position risk threshold) can be set for each position in the wafer. When the number of chips at the same position in different wafers in the same batch or the same material box that fail to pass the chip test and are determined to be failed chips is greater than or equal to the corresponding failure position risk threshold, or the number of chips that pass the chip test and are determined to be good chips is less than or equal to the corresponding good position risk threshold, the good chips at the position can be determined as potential premature failure chips. Exemplarily, for a box of 25 wafers, the failure position risk threshold is set to 6, then chip tests are performed on each chip on these 25 wafers, and the number of chips determined to be failed and the number of chips determined to be good are counted according to the chip test results. If, after chip testing, 25 chips at a certain position are judged to be 2 failed chips, and 23 are judged to be good chips, the number of chips judged to be 2 failed chips is less than the set failure position risk threshold of 6, and therefore, the good chips are still valid. If, after chip testing, 25 chips at a certain position are judged to be 6 failed chips, and 19 good chips are judged to be good chips, the number of chips judged to be 6 failed chips is greater than or equal to the set failure position risk threshold of 6, and therefore, the good chips at this position are determined to be potential premature failure chips. Or, illustratively, for a box of 25 wafers, the set good position risk threshold is 20, then, chip testing is performed on each chip on these 25 wafers, and according to the chip test results, the number of chips judged to be failed and the number of chips judged to be good are counted. If 25 chips at a certain position are tested and the number of chips determined to be good is 23 and the number of chips determined to be failed is 2, the number of chips determined to be good 23 is greater than the set good position point risk threshold of 20, therefore, the good chips are still valid.If, after chip testing, 25 chips at a certain position point are judged to be 6 failed chips and 19 good chips, the number of good chips 19 is less than or equal to the set good position point risk threshold of 20. Therefore, the good chips at this position point are determined to be potential premature failure chips.

[0085] Take GDBC cluster fault detection and analysis as an example, that is, the impact of surrounding failed chips on the good chips in the middle. Exemplarily, a good chip is surrounded by clusters of failed chips, that is, there are a certain number of failed chips in the vicinity of a good chip at a certain position, and a certain number of failed chips in the vicinity will have an adverse effect on the good chip at that position. The good chip at that position will receive the superposition of the adverse effects of a certain number of failed chips in the vicinity. If the superposition of adverse effects exceeds the set failure risk threshold (or the number of failed chips in the vicinity within a certain distance exceeds the set failure number threshold), it can be considered that the good chip at that position has a higher failure risk, and the good chip can be determined as a potential premature failure chip. Of course, in practical applications, the failure risk threshold can be gradually adjusted in an iterative manner to obtain a better abnormality detection effect.

[0086] Take KBC cluster fault detection and analysis as an example, that is, the impact of failed chips on surrounding good chips. For example, a failed chip at a certain location has an adverse impact on the surrounding good chips. Correspondingly, a good chip will also be affected by the superposition of adverse effects of multiple failed chips. If the superposition of adverse effects exceeds the set failure risk threshold, it can be considered that the good chip at this location has a higher failure risk, and the good chip can be determined as a potential premature failure chip. Of course, in actual applications, the failure risk threshold can be gradually adjusted in an iterative manner to obtain better abnormality detection effects.

[0087] Taking NNR cluster fault detection and analysis as an example, the position relationship is combined with the test results. For example, the difference between a good chip and other adjacent chips is calculated. When the calculated difference is greater than or equal to the set failure risk threshold, the good chip is determined as a potential premature failure chip. Of course, in actual applications, the failure risk threshold can be gradually adjusted in an iterative manner to obtain better anomaly detection results.

[0088] As can be seen from the above, in step S205, by performing post-test inspection and analysis on good chips and failed chips after chip testing, the failure risks associated with good chips can be activated according to corresponding post-test inspection and analysis means, and when the failure risk is greater than or equal to the set failure risk threshold, the corresponding good chip can be determined as a potential premature failure chip for further screening to avoid uncontrollable risks caused by the outflow of abnormal or defective products.

[0089] The method for detecting premature chip failure provided by the embodiment of the present disclosure first performs chip testing on multiple chips in at least one test wafer, determines the chips after the chip testing as good chips and failed chips, and then performs post-test detection and analysis on the good chips and failed chips after the chip testing, and determines the potential premature failure chips from the good chips. Compared with the related art, the present disclosure can perform post-test detection and analysis on good chips and failed chips after chip testing, fully consider the potential failure of good chips, and determine the potential premature failure chips from the good chips through certain analysis, which can avoid quality accidents caused by failure on the client side, and has the advantages of simple detection, rapidity, high efficiency, and reliability.

[0090] The disclosed embodiment provides a chip premature failure detection system.

[0091] See also Figure 3 , which is a functional schematic diagram of a chip premature failure detection system disclosed in one embodiment.

[0092] like Figure 3 As shown, the chip premature failure detection system includes: a chip testing module 31 and a post-test detection and analysis module 33.

[0093] The chip testing module 31 is used to perform chip testing on a plurality of chips in at least one test wafer, and obtain chip testing results of the plurality of chips based on chip testing determination means.

[0094] In some embodiments, the chip testing module 31 may execute a test program corresponding to a selected test item to perform chip testing on a plurality of chips in at least one test wafer.

[0095] The test items used for chip testing on the chip on the wafer include but are not limited to: one or more of a high voltage stress test (High Voltage Stress, HVS), an aging test (Burn-in Test), an early failure rate test (Early Failure Rate, EFR), etc.

[0096] When executing the test items, the method further includes obtaining chip test results of the plurality of chips based on a chip test determination means.

[0097] In some implementations, the chip test determination means include, but are not limited to: one or more of: dynamic upper and lower limit testing, dynamic part average testing (Dynamic Part Average Testing, DPAT), and parameter difference comparison testing.

[0098] The chip testing module 31 is also used to determine, based on the chip testing results, a chip whose chip testing results meet the testing specifications as a good chip, and a chip whose chip testing results do not meet the testing specifications as a failed chip.

[0099] In some embodiments, the test data of each chip obtained after the chip test is compared with the corresponding test specification of the chip. If the test data of the chip meets the corresponding test specification, that is, the test data of the chip is within the allowable range of the corresponding test specification, it indicates that the chip has passed the test of the test item, and the chip is determined to be a good chip. If the test data of the chip does not meet the corresponding test specification, that is, the test data of the chip exceeds the allowable range of the corresponding test specification, it indicates that the chip has not passed the test of the test item, and the chip is determined to be a failed chip.

[0100] The post-test detection and analysis module 33 is used to perform post-test detection and analysis on the good chips and failed chips after the chip test, and to determine potential prematurely failed chips from the good chips.

[0101] In certain embodiments, when performing post-test inspection and analysis on good chips and failed chips after chip testing, it is achieved by performing post-test inspection and analysis based on information related to chip testing (the information includes but is not limited to the position information of the test wafer, the position information of the good chips on each test wafer, the position information of the failed chips on each test wafer, etc.).

[0102] By performing post-test inspection and analysis on good chips and failed chips after chip testing, the failure risks associated with good chips can be activated according to the corresponding post-test inspection and analysis methods, and when the failure risk is greater than or equal to the set failure risk threshold, the corresponding good chip can be identified as a potential premature failure chip for further screening to avoid uncontrollable risks caused by the outflow of abnormal or defective products.

[0103] It should be noted that the chip premature failure detection system provided in the above embodiment and the chip premature failure detection method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment and will not be repeated here. In actual applications, the chip premature failure detection system provided in the above embodiment can distribute the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0104] Based on the above embodiments, the present invention also discloses a chip premature failure detection device. Figure 4, which is a schematic diagram of the structure of a chip premature failure detection device in one embodiment of the present invention. The chip premature failure detection device 4 comprises: a processor 41, a memory 43, and a computer program 45 stored in the memory 43 and executable on the processor 41. When the processor 41 executes the computer program 45, the steps in the above chip premature failure detection method embodiment are implemented.

[0105] The processor 41 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0106] The memory 43 may be an internal storage unit of the electronic device 4, such as a hard disk or memory of the chip premature failure detection device 4. The memory 43 may also be an external storage device of the chip premature failure detection device 4, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the chip premature failure detection device 4. Further, the memory 43 may also include both an internal storage unit and an external storage device of the chip premature failure detection device 4. The memory 43 is used to store computer programs and other programs and data required by the electronic device. The memory 43 may also be used to temporarily store data that has been output or is to be output.

[0107] The computer program 45 may be divided into one or more modules / units. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program 45 in the electronic device 7.

[0108] In addition to the above structure, those skilled in the art can understand that Figure 4 This is merely an example of a chip premature failure detection device and does not constitute a limitation of the chip premature failure detection device. The chip premature failure detection device may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0109] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0110] Based on the above embodiments, the embodiments of the present disclosure further provide a computer-readable storage medium having at least one computer program stored thereon, and when the computer program is executed by a processor, the method for detecting premature chip failure in the above embodiments is implemented.

[0111] A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium, an optical medium, or a semiconductor medium, wherein the magnetic medium can be, for example, a floppy disk, a hard disk, or a tape, etc., the optical medium can be, for example, a digital video disc (DVD), etc., and the semiconductor medium can be, for example, a solid-state hard disk (SSD), etc.

[0112] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0113] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A method for detecting premature failure of a chip, characterized in that: The steps include: Performing chip testing on a plurality of chips in at least one test wafer, and obtaining chip test results of the plurality of chips based on a chip test determination means; According to the chip test results, the chips whose chip test results meet the test specifications are determined as good chips, and the chips whose chip test results do not meet the test specifications are determined as failed chips; as well as Post-test detection and analysis are performed on good chips and failed chips, and potential premature failed chips are identified from the good chips.

2. The method for detecting premature chip failure according to claim 1, characterized in that: The chip testing of multiple chips in at least one test wafer comprises the following steps: Providing at least one test wafer, each test wafer having a plurality of chips; and A test item is selected, and a test program corresponding to the selected test item is executed to perform chip testing on multiple chips in at least one test wafer, and test data of each chip is obtained based on a chip test determination method.

3. The method for detecting premature chip failure according to claim 2, characterized in that: According to the chip test results, the chip whose chip test results meet the test specifications is determined as a good chip, and the chip whose chip test results do not meet the test specifications is determined as a failed chip, including the following steps: For each chip, comparing the test data of the chip in the test item with the test specification of the test item; If the test data of the chip in the test item is within the allowable range of the test specification of the test item, it indicates that the chip has passed the test of the test item and the chip is determined to be a good chip; if the test data of the chip in the test item exceeds the allowable range of the test specification of the test item, it indicates that the chip has failed the test of the test item and the chip is determined to be a failed chip.

4. The method for detecting premature chip failure according to claim 3, characterized in that: When a chip test includes multiple test items, currently the chip can be determined as a good chip only if the chip passes the tests of all the test items.

5. The method for detecting premature chip failure according to claim 1, characterized in that: The test items include: one or more of a high voltage stress test, an aging test, and an early failure rate test.

6. The method for detecting premature chip failure according to claim 1, characterized in that: The chip test determination means include one or more of dynamic upper and lower limit tests, dynamic component average tests, and parameter difference comparison tests.

7. The method for detecting premature chip failure according to claim 1, characterized in that: The post-testing and analyzing of good chips and failed chips to determine potential premature failed chips from the good chips includes the following steps: Collecting information related to chip testing, the information including: location information of at least one test wafer and location information of good chips and failed chips on each test wafer; A post-test detection and analysis method is selected and executed to determine potential premature failure chips based on the collected information related to the chip test.

8. The method for detecting premature chip failure according to claim 1, characterized in that: The post-testing and analyzing of good chips and failed chips to determine potential premature failed chips from the good chips includes the following steps: Choose a post-test detection and analysis method; According to the selected post-test detection and analysis means, collecting information related to the chip test, the information including: one or more of the position information of at least one test wafer, the position information of the good chips on each test wafer, and the position information of the failed chips on each test wafer; The post-test detection and analysis means are executed to determine potential premature failure chips from the good chips based on the collected information related to the chip test.

9. The method for detecting premature chip failure according to claim 1, characterized in that: The post-test detection and analysis means include: Z-yield detection and analysis and / or cluster fault detection and analysis.

10. A chip premature failure detection system, characterized in that: include: A chip testing module, used to perform chip testing on multiple chips in at least one test wafer, obtain chip test results of the multiple chips based on chip test determination means, and, based on the chip test results, determine chips whose chip test results meet the test specifications as good chips and determine chips whose chip test results do not meet the test specifications as failed chips; as well as The post-test detection and analysis module is used to perform post-test detection and analysis on good chips and failed chips after chip testing, and to determine potential prematurely failed chips from the good chips.

11. A chip premature failure detection device, characterized in that: include: processor; A memory storing a test program; Wherein, when the test program is executed by the processor, the method for detecting premature chip failure as claimed in any one of claims 1 to 9 is executed.

12. A computer-readable storage medium, characterized in that: A computer program is stored, and when the computer program is executed, the method for detecting premature chip failure according to any one of claims 1 to 9 is executed.

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